JP7247892B2 - Silicon carbide semiconductor device - Google Patents

Description

The present disclosure relates to silicon carbide semiconductor devices. This application claims priority based on Japanese Patent Application No. 2017-240856 filed on December 15, 2017. All the contents described in the Japanese patent application are incorporated herein by reference.

International Publication No. 2013/035818 (Patent Document 1) describes a trench gate type IGBT (Insulated Gate Bipolar Transistor). The IGBT is provided with a gate runner electrically connected to the gate electrode for the trench gate.

WO2013/035818

A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a gate insulating film, a first gate electrode, a first electrode, a second electrode, and gate runners. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. and a third impurity region having the first conductivity type provided on the second impurity region such that the third impurity region has the first conductivity type. A gate electrode trench and a gate runner trench are provided on the first main surface. The gate electrode trench is defined by side surfaces and a bottom surface continuous with the side surfaces. The side surface is composed of a first impurity region, a second impurity region, and a third impurity region. The bottom surface is composed of the first impurity region. The gate insulating film contacts both the side surfaces and the bottom surface. The first gate electrode is provided on the gate insulating film. A second gate electrode is provided in the gate runner trench and electrically connected to the first gate electrode. The first electrode is in contact with the third impurity region on the first main surface. The second electrode contacts the second main surface. A gate runner is provided on the second gate electrode.

A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a gate insulating film, a first gate electrode, a first electrode, a second electrode, and gate runners. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. and a third impurity region having the first conductivity type provided on the second impurity region such that the third impurity region has the first conductivity type. A gate electrode trench and a gate runner trench are provided on the first main surface. The gate electrode trench is defined by side surfaces and a bottom surface continuous with the side surfaces. The side surface is composed of a first impurity region, a second impurity region, and a third impurity region. The bottom surface is composed of the first impurity region. The gate insulating film contacts both the side surfaces and the bottom surface. The first gate electrode is provided on the gate insulating film. A second gate electrode is provided in the gate runner trench and electrically connected to the first gate electrode. The first electrode is in contact with the third impurity region on the first main surface. The second electrode contacts the second main surface. A gate runner is provided on the second gate electrode. The silicon carbide substrate is between the gate runner trench and the second main surface and includes a fourth impurity region having the second conductivity type and being in contact with the gate runner trench.

A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a gate insulating film, a first gate electrode, a first electrode, a second electrode, and gate runners. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. and a third impurity region having the first conductivity type provided on the second impurity region such that the third impurity region has the second conductivity type and is higher than the second impurity region. and a fifth impurity region having an impurity concentration. A gate electrode trench and a gate runner trench are provided on the first main surface. The gate electrode trench is defined by side surfaces and a bottom surface continuous with the side surfaces. The side surface is composed of a first impurity region, a second impurity region, and a third impurity region. The bottom surface is composed of the first impurity region. The gate insulating film contacts both the side surfaces and the bottom surface. The first gate electrode is provided on the gate insulating film. A second gate electrode is provided in the gate runner trench and electrically connected to the first gate electrode. The first electrode is in contact with the third impurity region on the first main surface. The second electrode contacts the second main surface. A gate runner is provided on the second gate electrode.

FIG. 1 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment, and corresponds to the schematic cross-sectional view taken along line II in FIG. FIG. 2 is a schematic plan view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. 3 is a schematic plan view showing the configuration of the gate electrode trenches and the gate runner trenches in region III of FIG. 2. FIG. 4 is a schematic cross-sectional view taken along line IV-IV of FIG. 3. FIG. 5 is a schematic cross-sectional view taken along line VV in FIG. 2. FIG. FIG. 6 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment. FIG. 7 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the third embodiment.

[Outline of Embodiment of Present Disclosure]
First, an outline of an embodiment of the present disclosure will be described.

A gate runner mainly plays a role of transmitting a gate signal to a gate electrode. A gate runner is usually arranged over a gate electrode provided on a silicon carbide substrate with a gate oxide film interposed therebetween. On the other hand, the source pad is arranged on the surface of the silicon carbide substrate without the insulating layer interposed therebetween. Therefore, the position of the surface of the gate runner is higher than the position of the surface of the source pad by the amount of the gate oxide film and the gate electrode. For example, when performing wire bonding to the source pad, the wire may come into contact with the gate runner protruding from the source pad. When the wire contacts the gate runner, an impact is applied to the gate runner and the gate runner may crack.

(1) Silicon carbide semiconductor device 100 according to the present disclosure includes silicon carbide substrate 10 , gate insulating film 51 , first gate electrode 41 , first electrode 26 , second electrode 60 , and gate runner 53 . I have. Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide substrate 10 includes first impurity region 11 having a first conductivity type, second impurity region 12 provided on first impurity region 11 and having a second conductivity type different from the first conductivity type, and first impurity region 12 having a second conductivity type different from the first conductivity type. A third impurity region 13 having the first conductivity type is provided on the second impurity region 12 so as to be separated from the impurity region 11 . A gate electrode trench 23 and a gate runner trench 33 are provided in the first main surface 1 . The gate electrode trench 23 is defined by side surfaces and a bottom surface continuous with the side surfaces. Side surface 21 is composed of first impurity region 11 , second impurity region 12 , and third impurity region 13 . The bottom surface 22 is composed of the first impurity region 11 . Gate insulating film 51 is in contact with both side surface 21 and bottom surface 22 . The first gate electrode 41 is provided on the gate insulating film 51 . The second gate electrode 42 is provided inside the gate runner trench 33 and electrically connected to the first gate electrode 41 . First electrode 26 is in contact with third impurity region 13 on first main surface 1 . The second electrode 60 contacts the second main surface 2 . A gate runner 53 is provided on the second gate electrode 42 .

In silicon carbide semiconductor device 100 according to (1) above, first main surface 1 is provided with gate electrode trench 23 and gate runner trench 33 . The gate electrode trench 23 is defined by a side surface 21 and a bottom surface 22 continuous with the side surface 21 . Gate insulating film 51 is in contact with both side surface 21 and bottom surface 22 . The first gate electrode 41 is provided on the gate insulating film 51 . The second gate electrode 42 is provided inside the gate runner trench 33 and electrically connected to the first gate electrode 41 . A gate runner 53 is provided on the second gate electrode 42 . Thereby, the height of the gate runners 53 can be reduced compared to the case where the gate runner trenches 33 are not provided in the first main surface 1 . Therefore, when an external wiring such as a wire is connected to the source pad, the possibility that the external wiring contacts gate runner 53 and impacts gate runner 53 can be reduced. As a result, cracks in the gate runners 53 can be suppressed.

(2) According to silicon carbide semiconductor device 100 according to (1) above, in the direction perpendicular to second main surface 2 , the boundary between second gate electrode 42 and gate runner 53 is located at first main surface 1 and the second main surface 2 . Thereby, the height of the gate runner 53 can be further reduced. Therefore, cracks in the gate runners 53 can be further suppressed.

(3) In silicon carbide semiconductor device 100 according to (1) or (2) above, the depth of gate runner trench 33 may be greater than the depth of gate electrode trench 23 .

(4) In silicon carbide semiconductor device 100 according to any one of (1) to (3) above, silicon carbide substrate 10 is between gate runner trench 33 and second main surface 2 and is of the second conductivity type. may include a fourth impurity region 14 having Thereby, concentration of an electric field on the gate runner insulating film 52 can be suppressed. Therefore, breakage of the gate runner insulating film 52 can be suppressed.

(5) In silicon carbide semiconductor device 100 according to (4) above, fourth impurity region 14 may be in contact with gate runner trench 33 . As a result, concentration of the electric field on the gate runner insulating film 52 can be further suppressed. Therefore, breakage of the gate runner insulating film 52 can be further suppressed.

(6) In silicon carbide semiconductor device 100 according to any one of (1) to (5) above, third impurity region 13 may be spaced from gate runner trench 33 .

(7) In silicon carbide semiconductor device 100 according to any one of (1) to (6) above, width W2 of gate runner trench 33 in a cross section perpendicular to the extending direction of gate runner trench 33 is equal to the gate electrode trench It may be larger than the width W1 of the gate electrode trench 23 in the cross section perpendicular to the extending direction of 23 .

(8) In silicon carbide semiconductor device 100 according to any one of (1) to (7) above, width W3 of second gate electrode 42 in a cross section perpendicular to the extending direction of second gate electrode 42 is It may be larger than the width W4 of the gate runner 53 in the cross section perpendicular to the extending direction of the runner 53 . If the width W3 of the second gate electrode 42 is the same as the width W4 of the gate runner 53, the gate runner 53 may protrude outside the gate runner trench 33 and ride on the first main surface 1 if the positioning error is large. By making the width W3 of the second gate electrode 42 larger than the width W4 of the gate runner 53, the gate runner 53 can be arranged inside the gate runner trench 33 even if the positioning error is large to some extent. Runners 53 can be prevented from running on first main surface 1 . As a result, even if the positioning error is large to some extent, the height of the gate runner 53 can be reduced.

(9) Silicon carbide semiconductor device 100 according to any one of (1) to (8) above may further include source pad 25 electrically connected to second impurity region 13 . The gate runner 53 may include a third major surface 7 facing the second major surface 2 and a fourth major surface 5 opposite the third major surface 7 . The source pad 25 may include a fifth major surface 6 facing the second major surface 2 and a sixth major surface 4 opposite to the fifth major surface 6 . In the direction perpendicular to the second principal surface 2, the distance H4 between the fourth principal surface 5 and the second principal surface 2 may be shorter than the distance H5 between the sixth principal surface 4 and the second principal surface 2. good. This allows the gate runner 53 to be lower than the source pad 25 . Therefore, when an external wiring such as a wire is connected to source pad 25 , the possibility that the external wiring contacts gate runner 53 and impacts gate runner 53 can be further reduced. As a result, cracks in the gate runners 53 can be further suppressed.

(10) According to silicon carbide semiconductor device 100 according to (1) above, in the direction perpendicular to second main surface 2 , the boundary between second gate electrode 42 and gate runner 53 is located at first main surface 1 and the second main surface 2 . Silicon carbide substrate 10 may include a fourth impurity region 14 that is between gate runner trench 33 and second main surface 2 and has the second conductivity type. A width W3 of the second gate electrode 42 in a cross section perpendicular to the extending direction of the second gate electrode 42 is larger than a width W4 of the gate runner 53 in a cross section perpendicular to the extending direction of the gate runner 53. good too. Silicon carbide semiconductor device 100 may further include a source pad 25 electrically connected to second impurity region 13 . The gate runner 53 may include a third major surface 7 facing the second major surface 2 and a fourth major surface 5 opposite the third major surface 7 . The source pad 25 may include a fifth major surface 6 facing the second major surface 2 and a sixth major surface 4 opposite to the fifth major surface 6 . In the direction perpendicular to the second principal surface 2, the distance H4 between the fourth principal surface 5 and the second principal surface 2 may be shorter than the distance H5 between the sixth principal surface 4 and the second principal surface 2. good.

(11) Silicon carbide semiconductor device 100 according to the present disclosure includes silicon carbide substrate 10, gate insulating film 51, first gate electrode 41, first electrode 26, second electrode 60, and gate runner 53. I have. Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide substrate 10 includes first impurity region 11 having a first conductivity type, second impurity region 12 provided on first impurity region 11 and having a second conductivity type different from the first conductivity type, and first impurity region 12 having a second conductivity type different from the first conductivity type. A third impurity region 13 having the first conductivity type is provided on the second impurity region 12 so as to be separated from the impurity region 11 . A gate electrode trench 23 and a gate runner trench 33 are provided in the first main surface 1 . The gate electrode trench 23 is defined by side surfaces and a bottom surface continuous with the side surfaces. Side surface 21 is composed of first impurity region 11 , second impurity region 12 , and third impurity region 13 . The bottom surface 22 is composed of the first impurity region 11 . Gate insulating film 51 is in contact with both side surface 21 and bottom surface 22 . The first gate electrode 41 is provided on the gate insulating film 51 . The second gate electrode 42 is provided inside the gate runner trench 33 and electrically connected to the first gate electrode 41 . First electrode 26 is in contact with third impurity region 13 on first main surface 1 . The second electrode 60 contacts the second main surface 2 . A gate runner 53 is provided on the second gate electrode 42 . Silicon carbide substrate 10 is between gate runner trench 33 and second main surface 2 , has the second conductivity type, and includes fourth impurity region 14 in contact with gate runner trench 33 .

(12) Silicon carbide semiconductor device 100 according to the present disclosure includes silicon carbide substrate 10, gate insulating film 51, first gate electrode 41, first electrode 26, second electrode 60, and gate runner 53. I have. Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide substrate 10 includes first impurity region 11 having a first conductivity type, second impurity region 12 provided on first impurity region 11 and having a second conductivity type different from the first conductivity type, and first impurity region 12 having a second conductivity type different from the first conductivity type. a third impurity region 13 having the first conductivity type provided on the second impurity region 12 so as to be separated from the impurity region 11, and a third impurity region 13 having the second conductivity type provided on the second impurity region 12; and a fifth impurity region 18 having an impurity concentration higher than that of the second impurity region 12 . A gate electrode trench 23 and a gate runner trench 33 are provided in the first main surface 1 . The gate electrode trench 23 is defined by side surfaces and a bottom surface continuous with the side surfaces. Side surface 21 is composed of first impurity region 11 , second impurity region 12 , and third impurity region 13 . The bottom surface 22 is composed of the first impurity region 11 . Gate insulating film 51 is in contact with both side surface 21 and bottom surface 22 . The first gate electrode 41 is provided on the gate insulating film 51 . The second gate electrode 42 is provided inside the gate runner trench 33 and electrically connected to the first gate electrode 41 . First electrode 26 is in contact with third impurity region 13 on first main surface 1 . The second electrode 60 contacts the second main surface 2 . A gate runner 53 is provided on the second gate electrode 42 .

[Details of the embodiment of the present disclosure]
Embodiments will be described below with reference to the drawings. In the drawings below, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], aggregated orientations by <>, individual planes by ( ), and aggregated planes by { }. In addition, the fact that the crystallographic index is negative is usually expressed by attaching a "-" (bar) above the number, but in this specification, a negative sign is attached before the number. there is

(First embodiment)
First, the configuration of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of silicon carbide semiconductor device 100 according to the first embodiment will be described.

As shown in FIG. 1, the MOSFET 100 according to the present embodiment includes a silicon carbide substrate 10, a gate insulating film 51, a first gate electrode 41, a source electrode 26 (first electrode 26), and a drain electrode 60 ( second electrode 60), second gate electrode 42, gate runner 53, gate pad 80 (see FIG. 2), first interlayer insulating film 36, second interlayer insulating film 38, and passivation layer 34. mainly have Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 16 and a silicon carbide epitaxial layer 17 on silicon carbide single crystal substrate 16 .

Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide epitaxial layer 17 forms first main surface 1 . Silicon carbide single crystal substrate 16 forms second main surface 2 . Silicon carbide single crystal substrate 16 and silicon carbide epitaxial layer 17 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 16 contains an n-type impurity such as nitrogen (N) and has n-type (first conductivity type).

The first main surface 1 is a {0001} plane or a plane in which the {0001} plane is inclined in the off direction by an off angle of 8° or less. Preferably, the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or may be 2° or more. The off angle may be 6° or less, or may be 4° or less.

Silicon carbide epitaxial layer 17 includes drift region 11 (first impurity region 11), body region 12 (second impurity region 12), source region 13 (third impurity region 13), fourth impurity region 14, It mainly has a contact region 15 . Drift region 11 contains an n-type impurity such as nitrogen and has n-type conductivity. The concentration of n-type impurities in drift region 11 may be lower than the concentration of n-type impurities in silicon carbide single crystal substrate 16 . Drift region 11 has an n-type impurity concentration of, for example, 1×10 ¹⁴ cm ⁻³ or more and 5×10 ¹⁶ cm ^{−3 or} less.

Body region 12 is provided on drift region 11 . Body region 12 contains a p-type impurity such as aluminum (Al) and has p-type (second conductivity type) conductivity. The concentration of p-type impurities in body region 12 is higher than the concentration of n-type impurities in drift region 11, for example. The p-type impurity concentration in body region 12 is, for example, 1×10 ¹⁶ cm ⁻³ or more and 5×10 ¹⁸ cm ^{−3 or} less.

Source region 13 is provided on body region 12 so as to be separated from drift region 11 by body region 12 . Source region 13 contains an n-type impurity such as nitrogen or phosphorus (P), and has n-type conductivity. Source region 13 forms part of first main surface 1 . The concentration of n-type impurities in source region 13 is higher than the concentration of p-type impurities in body region 12, for example. The n-type impurity concentration of source region 13 is, for example, about 1×10 ¹⁹ cm ⁻³ .

Contact region 15 contains a p-type impurity such as aluminum, and has p-type conductivity. The p-type impurity concentration of contact region 15 is higher than the p-type impurity concentration of body region 12, for example. Contact region 15 penetrates source region 13 and contacts body region 12 . Contact region 15 forms part of first main surface 1 . The p-type impurity concentration of contact region 15 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less.

A gate electrode trench 23 is provided in the first main surface 1 . Gate electrode trench 23 is defined by first side surface 21 and first bottom surface 22 . First side surface 21 extends through source region 13 and body region 12 to drift region 11 . The first bottom surface 22 is continuous with the first side surface 21 . First bottom surface 22 is located in drift region 11 . First side surface 21 is composed of drift region 11 , body region 12 , and source region 13 . The first bottom surface 22 is configured by the drift region 11 .

The first bottom surface 22 is, for example, a plane parallel to the second main surface 2 . The first side surface 21 extends in a direction substantially perpendicular to the first bottom surface 22, for example. First side surface 21 may be inclined with respect to first bottom surface 22 such that the width of gate electrode trench 23 expands from first bottom surface 22 toward first main surface 1 . Gate electrode trench 23 extends, for example, in a stripe shape along a direction parallel to second main surface 2 . The gate electrode trenches 23 may extend in a honeycomb shape, or may be scattered like islands.

Gate insulating film 51 is, for example, an oxide film. Gate insulating film 51 is made of a material containing, for example, silicon dioxide. Gate insulating film 51 contacts both first side surface 21 and first bottom surface 22 . Gate insulating film 51 is in contact with drift region 11 at first bottom surface 22 . Gate insulating film 51 is in contact with each of source region 13 , body region 12 and drift region 11 at first side surface 21 .

The first gate electrode 41 is provided on the gate insulating film 51 . First gate electrode 41 is made of, for example, polysilicon containing conductive impurities. First gate electrode 41 is arranged, for example, inside gate electrode trench 23 . Gate insulating film 51 is provided between each of source region 13 , body region 12 and drift region 11 and first gate electrode 41 .

A gate runner trench 33 is provided in the first main surface 1 . Gate runner trench 33 is defined by second side surface 31 and second bottom surface 32 . Second side surface 31 penetrates contact region 15 and body region 12 to reach drift region 11 . The second bottom surface 32 continues to the second side surface 31 . Second bottom surface 32 is located in drift region 11 . Second side surface 31 is composed of drift region 11 , body region 12 , and contact region 15 . The second bottom surface 32 is composed of the drift region 11 . The second bottom surface 32 is, for example, a plane parallel to the second main surface 2 . The second side surface 31 extends, for example, in a direction substantially perpendicular to the second bottom surface 32 . The second side surface 31 may be inclined with respect to the second bottom surface 32 so that the width of the gate runner trench 33 expands from the second bottom surface 32 toward the first main surface 1 . Gate runner trenches 33 extend, for example, in stripes along a direction parallel to second main surface 2 .

Gate runner insulating film 52 is, for example, an oxide film. Gate runner insulating film 52 is made of a material containing, for example, silicon dioxide. The gate runner insulating film 52 contacts both the second side surface 31 and the second bottom surface 32 . Gate runner insulating film 52 contacts drift region 11 at second bottom surface 32 . Gate runner insulating film 52 is in contact with each of contact region 15 , body region 12 and drift region 11 on second side surface 31 . From another point of view, source region 13 is spaced from gate runner trench 33 .

The second gate electrode 42 is provided on the gate runner insulating film 52 . The second gate electrode 42 is made of polysilicon containing conductive impurities, for example. The second gate electrode 42 is provided inside the gate runner trench 33 . The material forming the second gate electrode 42 is the same as the material forming the first gate electrode 41, for example. The second gate electrode 42 is electrically connected to the first gate electrode 41 . The second gate electrode 42 and the first gate electrode 41 may be formed integrally or may be formed separately. The second gate electrode 42 may be directly connected to the first gate electrode 41 or may be electrically connected to the first gate electrode 41 via another conductor.

A gate runner 53 is provided on the second gate electrode 42 . The material forming gate runner 53 is different from the material forming each of first gate electrode 41 and second gate electrode 42 . The electrical conductivity of the material forming gate runner 53 may be higher than the electrical conductivity of the material forming each of first gate electrode 41 and second gate electrode 42 . Gate runner 53 is made of a material containing, for example, aluminum.

A portion of gate runner 53 may be disposed within gate runner trench 33 . The gate runner 53 is provided facing the second bottom surface 32, for example. A portion of the gate runner 53 may face the second side surface 31 . Depth H3 at which gate runner 53 enters gate runner trench 33 is, for example, 0.1 μm or more and 2 μm or less. The depth H3 is the distance between the first principal surface 1 and the boundary in the direction perpendicular to the second principal surface 2 .

The boundary 3 between the second gate electrode 42 and the gate runner 53 may be between the first main surface 1 and the second main surface 2 in the direction perpendicular to the second main surface 2 . Specifically, the boundary 3 is between the first main surface 1 and the second bottom surface 32 in a direction perpendicular to the second main surface 2 . The boundary 3 is located on the second bottom surface 32 side with respect to the first main surface 1 . Gate runner 53 has a fourth major surface 5 opposite boundary 3 .

Depth H2 of gate runner trench 33 may be greater than depth H1 of gate electrode trench 23 . Depth H1 of gate electrode trench 23 is, for example, 0.5 μm or more and 2.5 μm or less. Depth H2 of gate runner trench 33 is, for example, 0.5 μm or more and 3.0 μm or less.

Width W2 of gate runner trench 33 in a cross section perpendicular to the extending direction of gate runner trench 33 is larger than width W1 of gate electrode trench 23 in a cross section perpendicular to the extending direction of gate electrode trench 23. good too. Width W1 of gate electrode trench 23 is, for example, 0.25 μm or more and 3.0 μm or less. Width W2 of gate runner trench 33 is, for example, 0.30 μm or more and 1000 μm or less. The extending direction of the trench is the direction parallel to the bottom surface of the trench and the side surface of the trench.

A width W3 of the second gate electrode 42 in a cross section perpendicular to the extending direction of the second gate electrode 42 is larger than a width W4 of the gate runner 53 in a cross section perpendicular to the extending direction of the gate runner 53. good too. A width W3 of the second gate electrode 42 is, for example, 0.30 μm or more and 1000 μm or less. Width W4 of gate runner 53 is, for example, 0.4 μm or more and 995 μm or less. The extending direction of the second gate electrode 42 is the longitudinal direction of the second gate electrode 42 . The same applies to the extending method of the gate runners 53 .

Fourth impurity region 14 is, for example, between gate runner trench 33 and second main surface 2 . Specifically, the fourth impurity region 14 is between the second bottom surface 32 and the second main surface 2 . Fourth impurity region 14 contains a p-type impurity such as aluminum (Al), and has p-type (second conductivity type) conductivity. The p-type impurity concentration of fourth impurity region 14 is, for example, 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁹ cm ^{−3 or} less. In a cross section perpendicular to the extending direction of gate runner trench 33 , the width of fourth impurity region 14 may be larger than width W<b>2 of second bottom surface 32 .

The fourth impurity region 14 does not have to be arranged directly under the gate electrode trench 23 . Specifically, fourth impurity region 14 is not arranged in a region between first bottom surface 22 and second main surface 2 . For example, drift region 11 is arranged in a region between first bottom surface 22 and second main surface 2 . Drift region 11 is sandwiched between, for example, fourth impurity regions 14 . The fourth impurity region 14 may be electrically connected to the source electrode 26 or may be floating.

Source electrode 26 is in contact with source region 13 and contact region 15 on, for example, first main surface 1 . Source electrode 26 has contact electrode 24 and source pad 25 . Source electrode 26 is provided in a source trench (not shown) provided in first main surface 1 and may be in contact with source region 13 on the wall surface of the source trench. A source pad 25 is on the contact electrode 24 . Source pad 25 is electrically connected to source region 13 . Contact electrode 24 may be in contact with source region 13 and contact region 15 on first main surface 1 . Contact electrode 24 is made of a material containing Ti, Al, and Si, for example. Contact electrode 24 is in ohmic contact with source region 13 . The contact electrode 24 may be in ohmic contact with the contact region 15 .

As shown in FIG. 1, the gate runner 53 includes a third major surface 7 facing the second major surface 2 and a fourth major surface 5 opposite the third major surface 7 . Source pad 25 includes a fifth main surface 6 facing second main surface 2 and a sixth main surface 4 opposite to fifth main surface 6 . In the direction perpendicular to the second principal surface 2, the distance H4 between the fourth principal surface 5 and the second principal surface 2 may be shorter than the distance H5 between the sixth principal surface 4 and the second principal surface 2. good. From another point of view, gate runner 53 may be lower than source pad 25 .

Drain electrode 60 is in contact with second main surface 2 . Drain electrode 60 is in contact with silicon carbide single-crystal substrate 16 at second main surface 2 . Drain electrode 60 is electrically connected to drift region 11 . Drain electrode 60 is made of a material containing NiSi or TiAlSi, for example.

First interlayer insulating film 36 is provided, for example, on each of first gate electrode 41 and gate insulating film 51 . For example, first interlayer insulating film 36 is in contact with each of first gate electrode 41 and gate insulating film 51 . First interlayer insulating film 36 is made of, for example, a material containing silicon dioxide. The first interlayer insulating film 36 electrically insulates the first gate electrode 41 and the source electrode 26, for example. The first interlayer insulating film 36 is covered with the source electrode 26, for example. The upper surface of first interlayer insulating film 36 is in contact with source pad 25, for example. The side surface of first interlayer insulating film 36 is in contact with each of source pad 25 and contact electrode 24, for example.

Second interlayer insulating film 38 is provided, for example, on contact region 15 . Second interlayer insulating film 38 is in contact with contact region 15 on first main surface 1, for example. Second interlayer insulating film 38 is made of, for example, a material containing silicon dioxide. The second interlayer insulating film 38 electrically insulates the gate runner 53 and the source electrode 26, for example. A portion of the second interlayer insulating film 38 may enter a portion of the gate runner trench 33 and be in contact with the upper surface of the second gate electrode 42 . The second interlayer insulating film 38 is in contact with the gate runner 53 and the gate runner insulating film 52, for example. A portion of the second interlayer insulating film 38 may be arranged, for example, between the gate runner 53 and the gate runner insulating film 52 .

Passivation layer 34 is provided to cover source electrode 26 , gate runner 53 , and second interlayer insulating film 38 . Passivation layer 34 is in contact with each of source electrode 26 , gate runner 53 and second interlayer insulating film 38 . Passivation layer 34 is made of a material such as silicon nitride (SiN), silicon dioxide, or polyimide.

As shown in FIG. 2, gate pad 80 has, for example, a rectangular shape when viewed in a direction perpendicular to second main surface 2 . The gate runner 53 has, for example, a first gate runner portion 81 , a second gate runner portion 82 and a third gate runner portion 83 . As shown in FIG. 2, each of first gate runner portion 81 and second gate runner portion 82 has, for example, an L shape. The first gate runner portion 81 extends from one end of the gate pad 80 in a direction parallel to the first direction 101 and away from the gate pad 80 . The first gate runner portion 81 is bent at approximately 90° halfway and extends in a direction parallel to the second direction 102 . The first direction 101 is, for example, the <11-20> direction. The second direction 102 is, for example, a direction perpendicular to the first direction 101 and parallel to the second main surface 2 . The second direction 102 is, for example, the <1-100> direction.

The second gate runner portion 82 extends from the other end of the gate pad 80 in a direction parallel to the first direction 101 and away from the gate pad 80 . The second gate runner portion 82 is bent at approximately 90° halfway and extends in a direction parallel to the second direction 102 . When viewed in a direction perpendicular to the second main surface 2, the third gate runner portion 83 has an elongated rectangular shape. The third gate runner portion 83 is positioned between the first gate runner portion 81 and the second gate runner portion 82 . The third gate runner portion 83 extends, for example, in a direction parallel to the second direction 102 .

FIG. 3 is a schematic plan view showing the configuration of the gate electrode trenches and gate runner trenches in region III of FIG. As shown in FIG. 3, gate runner trenches 33 extend in a direction parallel to second direction 102, for example. Gate electrode trench 23 extends, for example, in a direction parallel to first direction 101 . The gate electrode trenches 23 may be positioned on both sides of the gate runner trenches 33 . The gate electrode trench 23 continues to the gate runner trench 33 .

As shown in FIG. 4 , the first bottom surface 22 of the gate electrode trench 23 may continue to the second side surface 31 of the gate runner trench 33 . The gate insulating film 51 continues to the gate runner insulating film 52 . The first gate electrode 41 may be continuous with the second gate electrode 42 at the boundary between the first bottom surface 22 and the second side surface 31 . A gate runner 53 is arranged on the second gate electrode 42 . A portion of gate runner 53 is in contact with, for example, first gate electrode 41 . A portion of the gate runner 53 may run over the first gate electrode 41 .

As shown in FIG. 4, a portion of the gate runners 53 may be arranged to face the first bottom surface 22 . The gate runner 53 may be arranged on the boundary between the first bottom surface 22 and the second side surface 31 . The gate runner 53 may be in contact with the first interlayer insulating film 36 . A portion of the gate runner 53 may be sandwiched between the first gate electrode 41 and the passivation layer 34 .

As shown in FIG. 5, the MOSFET 100 according to this embodiment may further include a first insulating layer 39, a second insulating layer 37, and a connection gate electrode 43. As shown in FIG. The first insulating layer 39 is provided on the first main surface 1 . First insulating layer 39 may be in contact with body region 12 , for example, on first main surface 1 . The first insulating layer 39 is in contact with the gate runner insulating film 52, for example. The second insulating layer 37 is provided on the first insulating layer 39 . The second insulating layer 37 may be provided facing the body region 12 . The connection gate electrode 43 continues to the second gate electrode 42, for example. A portion of the connection gate electrode 43 runs over the first insulating layer 39, for example. The connection gate electrode 43 is made of the same material as the second gate electrode 42, for example.

A portion of the second insulating layer 37 may run over the connection gate electrode 43 , for example. A portion of connection gate electrode 43 may be sandwiched between, for example, first insulating layer 39 and second insulating layer 37 . A portion of the gate runner 53 may run over the connection gate electrode 43 . The gate runner 53 may be continuous with the gate pad 80 on the connection gate electrode 43 . A gate pad 80 is provided on the second insulating layer 37 . Gate pad 80 may be in contact with connection gate electrode 43 . Gate pad 80 may be provided to face body region 12 . The gate pad 80 may be provided facing the fourth impurity region 14 .

Next, functions and effects of the MOSFET 100 according to the first embodiment will be described.
In the MOSFET 100 according to the first embodiment, a gate electrode trench 23 and a gate runner trench 33 are provided on the first main surface 1 . The gate electrode trench 23 is defined by a side surface 21 and a bottom surface 22 continuous with the side surface 21 . Gate insulating film 51 is in contact with both side surface 21 and bottom surface 22 . The first gate electrode 41 is provided on the gate insulating film 51 . The second gate electrode 42 is provided inside the gate runner trench 33 and electrically connected to the first gate electrode 41 . A gate runner 53 is provided on the second gate electrode 42 . Thereby, the height of the gate runners 53 can be reduced compared to the case where the gate runner trenches 33 are not provided in the first main surface 1 . Therefore, when an external wiring such as a wire is connected to source pad 25 , the possibility that the external wiring contacts gate runner 53 and impacts gate runner 53 can be reduced. As a result, cracks in the gate runners 53 can be suppressed.

Further, according to the MOSFET 100 according to the first embodiment, the boundary between the second gate electrode 42 and the gate runner 53 in the direction perpendicular to the second main surface 2 is the first main surface 1 and the second main surface 2 may be between Thereby, the height of the gate runner 53 can be further reduced. Therefore, cracks in the gate runners 53 can be further suppressed.

Furthermore, according to the MOSFET 100 according to the first embodiment, the silicon carbide substrate 10 is between the gate runner trench 33 and the second main surface 2 and includes the fourth impurity region 14 having the second conductivity type. good too. Thereby, concentration of an electric field on the gate runner insulating film 52 can be suppressed. Therefore, breakage of the gate runner insulating film 52 can be suppressed.

Furthermore, according to the MOSFET 100 according to the first embodiment, the width of the second gate electrode 42 in the cross section perpendicular to the extending direction of the second gate electrode 42 is may be larger than the width of the gate runner 53 at . If the width of the second gate electrode 42 is the same as the width of the gate runner 53, the gate runner 53 may protrude outside the gate runner trench 33 and ride on the first main surface 1 if the positioning error is large. By making the width of the second gate electrode 42 larger than the width of the gate runner 53, the gate runner 53 can be arranged inside the gate runner trench 33 even if the positioning error is large to some extent. can be prevented from running on the first main surface 1. As a result, even if the positioning error is large to some extent, the height of the gate runner 53 can be reduced.

Furthermore, the MOSFET 100 according to the first embodiment further has the source pad 25 electrically connected to the second impurity region 13 . Gate runner 53 includes a third major surface 7 facing second major surface 2 and a fourth major surface 5 opposite to third major surface 7 . Source pad 25 includes a fifth main surface 6 facing second main surface 2 and a sixth main surface 4 opposite to fifth main surface 6 . In the direction perpendicular to the second principal surface 2 , the distance between the fourth principal surface 5 and the second principal surface 2 is shorter than the distance between the sixth principal surface 4 and the second principal surface 2 . This allows the gate runner 53 to be lower than the source pad 25 . Therefore, when an external wiring such as a wire is connected to source pad 25 , the possibility that the external wiring contacts gate runner 53 and impacts gate runner 53 can be further reduced. As a result, cracks in the gate runners 53 can be further suppressed.

(Second embodiment)
Next, the configuration of the MOSFET 100 according to the second embodiment will be described. The MOSFET 100 according to the second embodiment differs from the MOSFET 100 according to the first embodiment in the configuration in which the fourth impurity region 14 is in contact with the gate runner trench 33, and other configurations are the same as those in the first embodiment. It is almost the same as MOSFET100. The following description focuses on the configuration different from that of the MOSFET 100 according to the first embodiment.

As shown in FIG. 6 , the fourth impurity region 14 may be in contact with the gate runner trench 33 . Specifically, part of the gate runner trench 33 is embedded in the fourth impurity region 14 . A second bottom surface 32 of the gate runner trench 33 is in contact with the fourth impurity region 14 . A portion of the second side surface 31 of the gate runner trench 33 is in contact with the fourth impurity region 14 . From another point of view, the gate runner insulating film 52 is in contact with the fourth impurity region 14 at the second bottom surface 32 . The gate runner insulating film 52 is in contact with the fourth impurity region 14 on part of the second side surface 31 . The second bottom surface 32 is composed of the fourth impurity region 14 . Second side surface 31 is composed of fourth impurity region 14 , drift region 11 , body region 12 , and contact region 15 .

According to the MOSFET 100 according to the second embodiment, the fourth impurity regions 14 are in contact with the gate runner trenches 33 . As a result, concentration of the electric field on the gate runner insulating film 52 can be further suppressed. Therefore, breakage of the gate runner insulating film 52 can be further suppressed.

(Third embodiment)
Next, the configuration of the MOSFET 100 according to the third embodiment will be explained. The MOSFET 100 according to the third embodiment differs from the MOSFET 100 according to the first embodiment in that the fifth impurity region 18 is provided on the body region 12. Other configurations are the same as those in the first embodiment. It is substantially the same as the MOSFET 100 concerned. The following description focuses on the configuration different from that of the MOSFET 100 according to the first embodiment.

As shown in FIG. 7 , silicon carbide substrate 10 may further have fifth impurity region 18 . Fifth impurity region 18 contains a p-type impurity such as aluminum, and has p-type conductivity. The concentration of p-type impurities in fifth impurity region 18 is higher than the concentration of p-type impurities in body region 12, for example. Fifth impurity region 18 forms part of first main surface 1 . The p-type impurity concentration of the fifth impurity region 18 may be the same as the p-type impurity concentration of the contact region 15 . Fifth impurity region 18 is located, for example, between body region 12 and first insulating layer 39 .

Fifth impurity region 18 is in contact with, for example, second side surface 31 of gate runner trench 33 . From another point of view, part of the second side surface 31 may be configured by the fifth impurity region 18 . The fifth impurity region 18 may be arranged facing the gate pad 80 . First insulating layer 39 may be located between fifth impurity region 18 and connection gate electrode 43 in the direction perpendicular to first main surface 1 . The gate runner insulating film 52 may be positioned between the fifth impurity region 18 and the connection gate electrode 43 in the direction perpendicular to the second side surface 31 .

According to the MOSFET 100 according to the third embodiment, the fifth impurity region 18 is positioned between the body region 12 and the first insulating layer 39 . As a result, concentration of the electric field on the first insulating layer 39 can be suppressed. Therefore, breakage of the first insulating layer 39 can be suppressed.

In each of the above embodiments, the n-type is assumed to be the first conductivity type and the p-type is assumed to be the second conductivity type. good. Further, in the above embodiments, MOSFET 100 is described as an example of the silicon carbide semiconductor device, but the silicon carbide semiconductor device may be an IGBT, for example. Further, the p-type impurity concentration and the n-type impurity concentration in each impurity region can be measured by, for example, SCM (Scanning Capacitance Microscope) or SIMS (Secondary Ion Mass Spectrometry). Also, the position of the interface between the p-type region and the n-type region (that is, the PN interface) can be specified by SCM or SIMS, for example.

It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all changes within the scope and meaning equivalent to the scope of the claims.

1 first principal surface, 2 second principal surface, 3 boundary, 4 sixth principal surface, 5 fourth principal surface, 6 fifth principal surface, 7 third principal surface, 10 silicon carbide substrate, 11 drift region (first impurity region), 12 body region (second impurity region), 13 source region (third impurity region), 14 fourth impurity region, 15 contact region, 16 silicon carbide single crystal substrate, 17 silicon carbide epitaxial layer, 18 fifth fifth Impurity region 21 side surface (first side surface) 22 bottom surface (first bottom surface) 23 gate electrode trench 24 contact electrode 25 source pad 26 first electrode (source electrode) 31 second side surface 32 second bottom surface , 33 gate runner trench, 34 passivation layer, 36 first interlayer insulating film, 37 second insulating layer, 38 second interlayer insulating film, 39 first insulating layer, 41 first gate electrode, 42 second gate electrode, 43 connection Gate electrode 51 Gate insulating film 52 Gate runner insulating film 53 Gate runner 60 Second electrode (drain electrode) 80 Gate pad 81 First gate runner part 82 Second gate runner part 83 Third gate runner part, 100 MOSFET (silicon carbide semiconductor device), 101 first direction, 102 second direction.

Claims (9)

a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate includes: a first impurity region having a first conductivity type; a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type; a third impurity region provided on the second impurity region so as to be separated from the impurity region and having the first conductivity type;
A gate electrode trench and a gate runner trench are provided on the first main surface,
the gate electrode trench is defined by a side surface and a bottom surface continuous with the side surface;
the side surface is composed of the first impurity region, the second impurity region, and the third impurity region;
The bottom surface is configured by the first impurity region, and
a gate insulating film in contact with both the side surface and the bottom surface;
a first gate electrode provided on the gate insulating film;
a second gate electrode provided in the gate runner trench and electrically connected to the first gate electrode;
a first electrode in contact with the third impurity region on the first main surface;
a second electrode in contact with the second main surface;
a gate runner provided on the second gate electrode ;
The silicon carbide semiconductor device , wherein the depth of the gate runner trench is greater than the depth of the gate electrode trench . 2. The method according to claim 1, wherein a boundary between said second gate electrode and said gate runner is between said first main surface and said second main surface in a direction perpendicular to said second main surface. Silicon carbide semiconductor device. 3. The silicon carbide semiconductor according to claim 1, wherein said silicon carbide substrate is between said gate runner trench and said second main surface and includes a fourth impurity region having said second conductivity type. Device. 4. The silicon carbide semiconductor device according to claim 3 , wherein said fourth impurity region is in contact with said gate runner trench. 5. The silicon carbide semiconductor device according to claim 1 , wherein said third impurity region is separated from said gate runner trench. 3. The width of the gate runner trench in a cross section perpendicular to the extending direction of the gate runner trench is larger than the width of the gate electrode trench in the cross section perpendicular to the extending direction of the gate electrode trench. The silicon carbide semiconductor device according to any one of claims 1 to 5 . 3. The width of said second gate electrode in a cross section perpendicular to the extending direction of said second gate electrode is larger than the width of said gate runner in a cross section perpendicular to said extending direction of said gate runner. The silicon carbide semiconductor device according to any one of claims 1 to 6 . further comprising a source pad electrically connected to the second impurity region;
The gate runner includes a third main surface facing the second main surface and a fourth main surface opposite to the third main surface,
the source pad includes a fifth main surface facing the second main surface and a sixth main surface opposite to the fifth main surface;
2. The distance between the fourth main surface and the second main surface is shorter than the distance between the sixth main surface and the second main surface in a direction perpendicular to the second main surface. 8. The silicon carbide semiconductor device according to claim 7 . a boundary between the second gate electrode and the gate runner is between the first main surface and the second main surface in a direction perpendicular to the second main surface;
the silicon carbide substrate includes a fourth impurity region having the second conductivity type between the gate runner trench and the second main surface,
the width of the second gate electrode in a cross section perpendicular to the extending direction of the second gate electrode is larger than the width of the gate runner in a cross section perpendicular to the extending direction of the gate runner;
further comprising a source pad electrically connected to the second impurity region;
The gate runner includes a third main surface facing the second main surface and a fourth main surface opposite to the third main surface,
the source pad includes a fifth main surface facing the second main surface and a sixth main surface opposite to the fifth main surface;
2. The distance between the fourth main surface and the second main surface is shorter than the distance between the sixth main surface and the second main surface in a direction perpendicular to the second main surface. The silicon carbide semiconductor device according to 1.

Images