JP7247822B2 - Light receiving element - Google Patents

Description

The technology disclosed in this specification relates to a light receiving element.

A lateral avalanche photodiode in which germanium (Ge), which is a light-receiving film, is laminated on silicon (Si), as disclosed in Non-Patent Document 1, is known. In this photodiode, an avalanche region is formed by a PN junction of silicon. Also, a light-receiving film of germanium is formed directly on the P-type silicon.

NICHOLAS J. D. MARTINEZ et al., “Single photon detection in a waveguide-coupled Ge-on-Si lateral avalanche photodiode”, Vol. 25, No. 14, 10 Jul 2017, OPTICS EXPRESS 16130

Germanium is a P-type semiconductor because lattice defects act as acceptors. Therefore, a junction between P-type silicon and germanium is a junction between P-types. Since germanium is a narrower band semiconductor than silicon, silicon has higher potential energy. Then, a potential barrier is generated at the junction between the P-types of germanium and silicon. In other words, a band discontinuity exists on the conduction band side of the junction, and a voltage drop occurs at this portion. As a result, the voltage required to develop avalanche amplification becomes high (for example, about 40 V).

The light receiving element disclosed in this specification includes, from a first electrode, a first P-type silicon, a light absorption layer formed of a P-type narrow gap semiconductor, a first N-type silicon, a second P-type silicon, a second 2 N-type silicon in this order to reach the second electrode. The first P-type silicon and the light absorbing layer are in contact with the first N-type silicon. The second N-type silicon is separated from the first N-type silicon by a second P-type silicon. A first electrode is connected to the first P-type silicon. A second electrode is connected to the second N-type silicon. A combined capacitance of a first capacitance between the first P-type silicon and the first N-type silicon and a second capacitance between the light absorption layer and the first N-type silicon is , a third capacitance between the second P-type silicon and the second N-type silicon.

A light absorption layer made of a P-type narrow gap semiconductor is in contact with the first N-type silicon. Since it is a junction between a P-type narrow gap semiconductor and an N-type silicon, a potential barrier can be reduced compared to a junction between P-types. Therefore, the voltage required to develop avalanche amplification can be lowered. Also, the combined capacitance of the first capacitance and the second capacitance is greater than the third capacitance. The combined capacitance of the first capacitance and the second capacitance and the third capacitance are present in series on the current path. Then, the voltage applied between the first electrode and the second electrode is mainly divided to the side of the third capacitance having a lower capacitance. That is, voltage can be preferentially applied to the junction between the second P-type silicon and the second N-type silicon. As a result, it is possible to reduce the voltage required to develop avalanche amplification at the junction between the second P-type silicon and the second N-type silicon.

The first capacitance may be greater than the second capacitance. Details of the effect will be described in Examples.

The junction area between the light absorption layer and the first N-type silicon may be smaller than the area of the light absorption layer. Details of the effect will be described in Examples.

Further, the light receiving element disclosed in this specification includes an N-type silicon substrate in which a first P-type region, a second P-type region and an N-type region are formed, a P-type narrow gap semiconductor layer, a first An electrode and a second electrode are provided. The first P-type region is formed in the surface layer of the N-type silicon substrate. The N-type region is formed on the surface layer of the N-type silicon substrate and is formed apart from the first P-type region. A second P-type region is formed over the sides and bottom of the N-type region to isolate the N-type region from the N-type silicon substrate. The second P-type region is formed apart from the first P-type region. A P-type narrow gap semiconductor layer is arranged above the N-type silicon substrate. At least part of the lower surface of the P-type narrow gap semiconductor layer is in contact with both the surface of the first P-type region and the surface of the N-type silicon substrate. The first electrode is connected to part of the first P-type region or part of the P-type narrow gap semiconductor layer. The second electrode is connected to part of the N-type region. A combined capacitance of a first capacitance between the first P-type region and the N-type silicon substrate and a second capacitance between the P-type narrow gap semiconductor layer and the N-type silicon substrate is Greater than a third capacitance between the second P-type region and the N-type region. Details of the effect will be described in Examples.

When the N-type silicon substrate is viewed vertically from above, the junction area between the lower surface of the P-type narrow gap semiconductor layer and the surface of the N-type silicon substrate may be smaller than the area of the upper surface of the P-type narrow gap semiconductor layer. Details of the effect will be described in Examples.

When viewed vertically from above the N-type silicon substrate, the area of the N-type region may be smaller than the area of the first P-type region. Details of the effect will be described in Examples.

1A and 1B are a top view and a cross-sectional view of a light receiving element 1 according to Example 1. FIG. 4 is a diagram showing a current path CP in the light receiving element 1; FIG. 2A and 2B are a top view and a cross-sectional view of a light receiving element 100 of a comparative example; FIG. It is a simulation figure of the band diagram of a comparative example. It is a simulation figure of the band diagram of a comparative example. FIG. 5 is a diagram showing current-voltage characteristics of a light receiving element 100 of a comparative example; 1 is a simulation diagram of a band diagram of Example 1. FIG. 1 is a simulation diagram of a band diagram of Example 1. FIG. 4 is a diagram showing current-voltage characteristics of the light receiving element 1 of Example 1. FIG. 8A and 8B are a top view and a cross-sectional view of a light receiving element 1a according to Example 2; FIG.

(Structure of light receiving element 1)
FIG. 1A shows a top view of the light receiving element 1. As shown in FIG. FIG. 1B shows a cross-sectional view taken along line BB in FIG. 1A. The light receiving element 1 is a device made using a silicon substrate. The light-receiving element 1 is a heterojunction photodiode having a germanium layer 30 as a light-receiving film. The light receiving element 1 includes an N-type silicon substrate 10 , an insulating layer 20 , a passivation layer 25 , a germanium layer 30 , a first electrode 40 and a second electrode 50 . The N-type silicon substrate 10 has a first P-type region 11 , a second P-type region 12 and an N-type region 13 . In the top view of FIG. 1A, the first P-type region 11 and the N-type region 13 are indicated by dotted lines.

The insulating layer 20 is arranged on the surface of the N-type silicon substrate 10 . A germanium layer 30 is arranged above the N-type silicon substrate 10 with an insulating layer 20 interposed therebetween. The insulating layer 20 is silicon oxide. The film thickness T1 of the insulating layer 20 is 1 micrometer or less. Passivation layer 25 is arranged to protect the surface of light receiving element 1 . The passivation layer 25 may be an insulator that transmits light of wavelengths absorbed by the germanium layer 30 . In this embodiment, passivation layer 25 is silicon oxide. The insulating layer 20 has a first opening 21 , a second opening 22 , a first electrode opening 23 and a second electrode opening 24 . In the top view of FIG. 1A, regions corresponding to the first opening 21 and the second opening 22 are indicated by dotted lines and filled with gray.

The first opening 21 is arranged near the center of the germanium layer 30 . As shown in FIG. 1B, the germanium layer 30 is arranged on the surface of the insulating layer 20 , inside the first opening 21 , and inside the second opening 22 . As shown in FIG. 1A, the germanium layer 30 has a circular shape centered on the first opening 21 . The germanium layer 30 arranged inside the first opening 21 forms a hetero PN junction region R1 with the N-type silicon substrate 10 at the bottom of the first opening 21 . The second opening 22 has a trench shape surrounding the first opening 21 . The germanium layer 30 located inside the second opening 22 is in contact with the surface of the first P-type region 11 . Thereby, the germanium layer 30 is electrically connected to the first electrode 40 via the first P-type region 11 functioning as a contact region. In other words, part of the lower surface of germanium layer 30 is in contact with both the surface of N-type silicon substrate 10 and the surface of first P-type region 11 .

Germanium layer 30 is an intrinsic semiconductor. However, in germanium, lattice defects act as acceptors even if no impurities are added. And due to lattice mismatch between silicon and germanium, germanium has a high defect density. Therefore, the germanium layer 30 functions as a high-concentration P-type semiconductor with a hole density in the lower half of 10 ¹⁷ cm ⁻³ to the order of 10 ¹⁸ cm ⁻³ . Therefore, the hetero PN junction region R1 functions as a PN diode.

When N-type silicon substrate 10 is viewed vertically from above, area A1 of hetero PN junction region R1 is smaller than area A2 of germanium layer 30 disposed on the surface of insulating layer 20 . As a result, as shown in FIG. 1B, the cross-sectional shape of the germanium layer 30 is substantially "T-shaped". The germanium layer 30 is single crystal at least in the vicinity of the hetero PN junction region R1. As a result, leakage current can be suppressed compared to the case of forming a hetero PN junction with polycrystalline germanium, so the characteristics of the light receiving element 1 can be improved.

The greater the film thickness T2 of the germanium layer 30, the higher the light receiving efficiency. Therefore, the film thickness T2 should be determined in consideration of the balance between the light receiving efficiency and the wiring reliability. In this embodiment, the film thickness T2 is approximately 1 micrometer.

The impurity of the N-type silicon substrate 10 is phosphorus, and its concentration is 1×10 ¹⁷ cm ⁻³ or less. A first P-type region 11 , a second P-type region 12 and an N-type region 13 are formed in a surface layer portion of an N-type silicon substrate 10 . The impurity of the first P-type region 11 is boron, and its concentration is 1×10 ¹⁸ cm ⁻³ or higher. The first P-type region 11 is separated from the hetero PN junction region R1 by the N-type silicon substrate 10 . The first P-type region 11 is arranged to surround the first opening 21 when the N-type silicon substrate 10 is viewed from the vertical direction (+Z direction). The first electrode 40 is connected to part of the first P-type region 11 through the first electrode opening 23 . The first electrode 40 is aluminum (Al) and is in ohmic contact with the first P-type region 11 .

The N-type region 13 is a region having a higher N-type impurity concentration than the N-type silicon substrate 10 . The impurity of the N-type region 13 is phosphorus or arsenic, and its concentration is 1×10 ¹⁸ cm ⁻³ or more. As shown in FIG. 1A, when the N-type silicon substrate 10 is viewed from the vertical direction (+Z direction), the area of the N-type region 13 (the area of the dotted circle) is the area of the first P-type region 11. (the area of the region surrounded by the dotted line indicating the first P-type region 11).

The second P-type region 12 is formed covering the side and bottom surfaces of the N-type region 13 so as to isolate the N-type region 13 from the first P-type region 11 and the N-type silicon substrate 10 . The second P-type region 12 is formed apart from the first P-type region 11 . The second electrode 50 is connected to part of the N-type region 13 through the second electrode opening 24 . The second electrode 50 is aluminum (Al) and is in ohmic contact with the N-type region 13 .

(explanation of capacitance and current path)
A capacitance C1 exists between the first P-type region 11 and the N-type silicon substrate 10 . A capacitance C2 exists between the germanium layer 30 and the N-type silicon substrate 10 . A capacitance C3 exists between the second P-type region 12 and the N-type region 13 . In FIG. 1B, these capacitances C1 to C3 are indicated by dotted lines. A relationship is established in which the capacitance C1 is larger than the capacitance C2. This is because the area of the first P-type region 11 (the area of the region surrounded by the dotted line indicating the first P-type region 11 in FIG. 1A) is the area of the hetero PN junction region R1 (the area of the hetero PN junction region R1 in FIG. 1A). , the area of the gray painted area corresponding to the first opening 21).

Also, the first P-type region 11 and the germanium layer 30 are both P-type and have the same potential. Therefore, since the electrostatic capacitance C1 and the electrostatic capacitance C2 are arranged in parallel in the current path, both can be combined to form a combined capacitance CC. A relationship is established in which the combined capacitance CC is greater than the electrostatic capacitance C3. This relationship can be established by making the area of the N-type region 13 (the area of the dotted circle in FIG. 1A) sufficiently smaller than the area of the first P-type region 11 . Since the light receiving element 1 is a lateral element, the area of the N-type region 13 can be designed to be small regardless of the areas of the first P-type region 11 and the germanium layer 30 .

FIG. 2 shows a current path CP in the light receiving element 1. As shown in FIG. The current path CP extends from the first electrode 40 through the first P-type region 11, the germanium layer 30 (light absorbing layer), the N-type silicon substrate 10, the second P-type region 12, and the N-type region 13 in this order to the second P-type region. This is the path leading to the electrode 50 . The above-described combined capacitance CC and electrostatic capacitance C3 exist in series on the current path CP.

(Operation of light receiving element 100 of comparative example)
Before describing the operation of the light receiving element 1 of this embodiment, the operation of the light receiving element 100 of the comparative example shown in FIG. 3 will be described. The light receiving element 100 has a germanium layer 130 (light absorbing layer) formed directly on a P-type silicon substrate 110 . The junction between the P-type silicon substrate 110 and the germanium layer 130 is a junction between P-types. The first electrode 140 is arranged on the side surface and top surface of the outer periphery of the germanium layer 130 . The same reference numerals are assigned to the same structures in the light receiving element 100 of the comparative example and the light receiving element 1 (FIG. 1) of the first embodiment, and the description thereof is omitted.

FIG. 4 shows a simulation result of a band diagram of the light receiving element 100 of the comparative example. FIG. 4 shows the results when the bias voltage (the voltage between the first electrode 140 and the second electrode 50) is 0V. The horizontal axis indicates the position of the conductive path. The germanium layer 130, the P-type silicon substrate 110, and the N-type region 13 are connected in order from the left side of FIG. The vertical axis is potential energy.

Since germanium is a narrower band semiconductor than silicon, silicon has higher potential energy. As a result, a potential barrier PB101 is generated at the junction JC101 where the P-type silicon substrate 110 and the germanium layer 130 are joined together. In other words, a band discontinuity exists on the conduction band side of the junction JC101, and a voltage drop occurs at this portion. Movement of electrons generated in the germanium layer 130 by light irradiation to the second electrode 50 side (the right side in FIG. 4) is restricted by the potential barrier PB101.

FIG. 5 shows simulation results of a band diagram of the light receiving element 100 of the comparative example when a reverse bias voltage of 10 V is applied. When a positive voltage is applied to the second electrode 50 with respect to the first electrode 140, it becomes a reverse bias voltage. That is, it is the reverse bias voltage for the PN junction between the P-type silicon substrate 110 and the N-type region 13 . The reverse bias voltage pulls the potential barrier height down from PB101 (FIG. 4) to PB102 (FIG. 5).

The light receiving operation of the light receiving element 100 of the comparative example will be described. Eye-safe band light (eg, 1550 nm, energy: 0.8 eV) is incident on the upper surface of the germanium layer 130, and when the light is absorbed by the germanium layer 130, electrons and holes are generated. In FIG. 5, the generated electrons move toward the second electrode 50 and the generated holes move toward the first electrode 40 due to the electric field generated by the reverse bias voltage. Electrons are accelerated by the high electric field region near the PN junction between the P-type silicon substrate 110 and the N-type region 13, resulting in avalanche amplification. This causes a photocurrent to flow.

FIG. 6 shows current-voltage characteristics of the light receiving element 100 of the comparative example. The horizontal axis is the reverse bias voltage. The vertical axis is the current value. As shown in FIG. 6, the threshold voltage Vth1 at which the current rises is about 30V. The threshold voltage Vth1 corresponds to a voltage at which avalanche amplification occurs. Further, the current value in a state where a sufficient reverse bias voltage is applied is approximately 20 to 40 (μA).

(Operation of light receiving element 1 of Example 1)
Next, the operation of the light receiving element 1 of Example 1 shown in FIG. 1 will be described. FIG. 7 shows a simulation result of a band diagram of the light receiving element 1 of Example 1. In FIG. FIG. 7 shows the results when the bias voltage is 0V. A first P-type region 11, a germanium layer 30, an N-type silicon substrate 10, a second P-type region 12, and an N-type region 13 are connected in order from the left side of FIG. That is, the light receiving element 1 of Example 1 differs from the light receiving element 100 of the comparative example in that N-type silicon is inserted between germanium and P-type silicon.

The P-type germanium layer 30 is bonded to the N-type silicon substrate 10 . Therefore, no potential barrier is formed at the junction JC1 between the two (region R11). That is, it is possible to eliminate the potential barrier PB101 (FIG. 4) due to the heterojunction between the P-types, which the light-receiving element 100 of the comparative example has. On the other hand, since the N-type silicon substrate 10 exists on the current path, the PN junction JC2 between the N-type silicon substrate 10 and the second P-type region 12 forms a potential barrier PB1. Therefore, the movement of electrons generated in the germanium layer 30 by light irradiation to the second electrode 50 side (the right side in FIG. 7) is restricted by the potential barrier PB1.

FIG. 8 shows simulation results of a band diagram of the light receiving element 1 of Example 1 when a reverse bias voltage of 10 V is applied. Due to the reverse bias voltage, the height of potential barrier PB1 is significantly lowered from PB1 (FIG. 7) to PB2 (FIG. 8). On the other hand, the potential difference (region R11) of junction JC1 hardly changes. The reason for this is explained. As described above with reference to FIG. 2, the combined capacitance CC and the electrostatic capacitance C3 exist in series on the current path CP. Therefore, the reverse bias voltage applied between the first electrode 40 and the second electrode 50 is divided by the combined capacitance CC and the electrostatic capacitance C3. Then, as described above, the combined capacitance CC is larger than the electrostatic capacitance C3. Therefore, most of the reverse bias voltage is applied to the side of the capacitance C3 having a low capacity. As a result, almost no voltage is applied to junction JC1 (see region R11 in FIGS. 7 and 8) having capacitance C2. That is, the reverse bias voltage can be preferentially applied to the junction between the second P-type region 12 and the N-type region 13 .

Thereby, as a first effect, the second P-type region 12 and the N-type silicon substrate 10 do not change the potential difference at the junction JC1 (see region R11 in FIGS. 7 and 8) between the germanium layer 30 and the N-type silicon substrate 10. A potential barrier PB1 formed near the junction with the mold region 13 can be selectively pulled down. Therefore, electrons generated in the germanium layer 30 by light irradiation can be made to move toward the second electrode 50 (the right side in FIG. 8). As a second effect, since the reverse bias voltage can be preferentially applied to the junction between the second P-type region 12 and the N-type region 13, the second P-type photodiode can be obtained with a lower reverse bias voltage than the conventional light receiving element 100. A high electric field region can be generated at the junction of region 12 and N-type region 13 . The value of reverse bias voltage required to generate avalanche amplification can be reduced.

FIG. 9 shows the current-voltage characteristics of the light receiving element 1 of Example 1. As shown in FIG. As shown in FIG. 9, the threshold voltage Vth2 at which current rises (avalanche amplification occurs) is about 2.4V. The voltage required to develop the avalanche amplification can be reduced to 1/10 or less of the threshold voltage Vth1 (30 V) of the light receiving element 100 of the comparative example. Also, the current value in the state where a sufficient reverse bias voltage is applied is 200 (mA) or more. The current value (20 to 40 (μA)) of the light-receiving element 100 of the comparative example can be increased about 10,000 times.

(effect)
Autonomous vehicles and ADAS (Advanced driver-assistance systems) use infrared cameras and LiDAR (Light Detection and Ranging) systems to recognize the surrounding environment. For safety reasons, these systems preferably use eye-safe band light (1300 nm to 1600 nm light). However, since the eye-safe band light has energy lower than the bandgap energy of silicon, it was necessary to create a light receiving element using a narrow bandgap semiconductor (eg germanium). If the light-receiving element is made using a germanium substrate or the like and the signal processing circuit is made using a silicon substrate, it is necessary to mount a plurality of chips on the light-receiving system, which leads to an increase in cost. In the light receiving element 1 described in this specification, the germanium layer 30 (light absorption layer) can be formed only by adding a step of depositing a germanium film to the silicon process. A light-receiving film and a signal processing circuit can be monolithically integrated on a Si substrate. It is possible to reduce the manufacturing cost of a light receiving system compatible with eye-safe band light.

If germanium is joined to N-type silicon, the potential barrier PB101 (FIG. 4) due to the heterojunction between P-types can be eliminated, so the sensitivity of the light receiving element can be enhanced. However, leakage current increases. The light receiving element 1 described in this specification has a structure in which the area A1 (FIG. 1) of the hetero PN junction region R1 is smaller than the area A2 of the germanium layer 30 which is the light receiving film. Since the leak current density depends on the heterojunction area, the leak current can be reduced by reducing the area A1 of the hetero PN junction region R1. Also, by making the area A2 of the light-receiving film larger than the area A1 of the hetero PN junction region R1, it is possible to suppress a decrease in sensitivity. Note that the value of the area A1 can be appropriately determined according to the allowable value of the leakage current. Further, sensitivity increases as the ratio of area A2 to area A1 increases, but the increase in sensitivity saturates when the ratio exceeds a predetermined value. Therefore, the area ratio should be increased to the extent that the saturation point of sensitivity is not exceeded.

In the technique described in this specification, the reverse bias voltage is preferentially applied to the junction between the second P-type region 12 and the N-type region 13 because the combined capacitance CC is larger than the electrostatic capacitance C3. can do. As a result, the potential barrier PB1 can be lowered and a high electric field region can be generated with a reverse bias voltage lower than that of the conventional light receiving element. It is possible to lower the voltage required to develop avalanche amplification compared to conventional light receiving elements.

FIG. 10A shows a top view of the light receiving element 1a according to the second embodiment. FIG. 10B shows a cross-sectional view taken along line BB of FIG. 10A. The photodetector 1a of Example 2 is an element in which the structure of the lower surface of the germanium layer 30 of the photodetector 1 (FIG. 1) of Example 1 is different. In the top view of FIG. 1A, the first P-type region 11 and the N-type region 13 are indicated by dotted lines. A structure specific to the light receiving element 1a of the second embodiment is distinguished by adding "a" to the end of the reference numeral. Further, the same reference numerals are assigned to the same structures in the light receiving element 1 of the first embodiment and the light receiving element 1a of the second embodiment, and the description thereof is omitted.

The insulating layer 20a has an opening 26a. The germanium layer 30a is arranged inside the opening 26a. The entire lower surface of germanium layer 30a is in contact with N-type silicon substrate 10 and first P-type region 11 at the bottom of opening 26a. A hetero PN junction region R1a is formed in the junction region between the germanium layer 30a and the N-type silicon substrate 10 . In the top view of FIG. 10(A), the region corresponding to the hetero PN junction region R1a is indicated by dotted lines and gray filling. On the lower surface of the germanium layer 30a, regions other than the hetero PN junction region R1a are electrically connected to the first electrode 40 via the first P-type region 11 functioning as a contact region.

When the N-type silicon substrate 10 is viewed vertically from above, the area A1a of the hetero PN junction region R1a (the area of the region filled in gray) is the area A2 of the upper surface of the germanium layer 30a disposed on the surface of the insulating layer 20. less than

A capacitance C1 exists between the first P-type region 11 and the N-type silicon substrate 10 . A capacitance C 2 exists between the germanium layer 30 a and the N-type silicon substrate 10 . A capacitance C3 exists between the second P-type region 12 and the N-type region 13 . In FIG. 10B, these capacitances C1 to C3 are indicated by dotted lines. As in the first embodiment, there is a relationship that the capacitance C1 is larger than the capacitance C2. Also, a relationship is established in which the combined capacitance CC of the capacitances C1 and C2 is greater than the capacitance C3.

(effect)
Also in the light-receiving element 1a according to the second embodiment, the reverse bias voltage is preferentially applied to the junction between the second P-type region 12 and the N-type region 13 because the combined capacitance CC is larger than the electrostatic capacitance C3. can be applied. It is possible to lower the voltage required to develop avalanche amplification compared to conventional light receiving elements. In addition, the light-receiving film (upper surface of the germanium layer 30a) has a larger area than the hetero PN junction region R1a. Therefore, it is possible to reduce the leakage current without lowering the sensitivity.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

(Modification)
The method of depositing the germanium layer may vary. For example, after depositing amorphous germanium, single crystallization may be performed by performing solid-phase crystal growth using the N-type silicon substrate 10 as a seed crystal by annealing. Alternatively, germanium may be epitaxially grown on silicon.

The cross-sectional shape of the germanium layer is not limited to the T shape. Any cross-sectional shape may be employed as long as the area of the hetero PN junction region is smaller than the area of the light-receiving film. In addition, when the silicon substrate is viewed vertically from above, the arrangement position of the hetero PN junction region is not limited to the center of the germanium layer, and can be arranged at any position.

The shape of the germanium layer in the vertically upward view of the silicon substrate is not limited to circular, and may be various shapes.

The shape of the first electrode 40 in this embodiment is an example. The shape and arrangement of the first electrode 40 can be arbitrarily set as long as it is electrically connected to the germanium layer 30 . For example, the first electrode 40 may be connected to the outer periphery of the germanium layer 30 .

The insulating layer 20 is not limited to silicon oxide and other insulators can be used.

The first P-type region 11 is an example of first P-type silicon. Germanium layers 30 and 30a are examples of light absorbing layers. The N-type silicon substrate 10 is an example of first N-type silicon. The second P-type region 12 is an example of second P-type silicon. The N-type region 13 is an example of second N-type silicon. Germanium layers 30 and 30a are examples of P-type narrow gap semiconductor layers.

Reference Signs List 1, 1a: light receiving element 10: N-type silicon substrate 11: first P-type region 12: first P-type region 13: N-type region 20, 20a: insulating layer 21: first opening 22: second opening 30, 30a : germanium layer 40: first electrode 50: second electrode C1 to C3: capacitance CC: combined capacitance R1, R1a: hetero PN junction region

Claims (7)

From the first electrode, via first P-type silicon, a light absorption layer formed of a P-type narrow gap semiconductor, first N-type silicon, second P-type silicon, and second N-type silicon in this order A light receiving element having a current path leading to the second electrode,
The first P-type silicon and the light absorption layer are in contact with the first N-type silicon,
said second N-type silicon is separated from said first N-type silicon by said second P-type silicon;
The first electrode is connected to the first P-type silicon,
the second electrode is connected to the second N-type silicon,
A first capacitance between the first P-type silicon and the first N-type silicon, and a second capacitance between the light absorbing layer and the first N-type silicon. is larger than a third capacitance between the second P-type silicon and the second N-type silicon. 2. The light receiving element according to claim 1, wherein said first capacitance is greater than said second capacitance. 3. The light receiving element according to claim 1, wherein a junction area between said light absorption layer and said first N-type silicon is smaller than an area of said light absorption layer. A light receiving element comprising an N-type silicon substrate on which a first P-type region, a second P-type region and an N-type region are formed, a P-type narrow gap semiconductor layer, a first electrode, and a second electrode and
The first P-type region is formed in a surface layer portion of the N-type silicon substrate,
The N-type region is formed in a surface layer portion of the N-type silicon substrate and is formed apart from the first P-type region,
the second P-type region is formed to cover the side and bottom surfaces of the N-type region so as to isolate the N-type region from the N-type silicon substrate;
The second P-type region is formed apart from the first P-type region,
The P-type narrow gap semiconductor layer is arranged above the N-type silicon substrate,
at least part of the lower surface of the P-type narrow gap semiconductor layer is in contact with both the surface of the first P-type region and the surface of the N-type silicon substrate;
the first electrode is connected to part of the first P-type region or part of the P-type narrow gap semiconductor layer,
The second electrode is connected to part of the N-type region,
a first capacitance between the first P-type region and the N-type silicon substrate and a second capacitance between the P-type narrow gap semiconductor layer and the N-type silicon substrate; A light receiving element, wherein a combined capacitance is larger than a third capacitance between the second P-type region and the N-type region. 5. The light receiving element according to claim 4, wherein said first capacitance is greater than said second capacitance. When viewed vertically from above the N-type silicon substrate, a junction area between the lower surface of the P-type narrow gap semiconductor layer and the surface of the N-type silicon substrate is smaller than the area of the upper surface of the P-type narrow gap semiconductor layer. The light receiving element according to claim 4 or 5. 7. The light-receiving element according to claim 4, wherein the area of said N-type region is smaller than the area of said first P-type region when viewed vertically from above said N-type silicon substrate.

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