JP7218289B2 - clock enabler circuit - Google Patents

Description

TECHNICAL FIELD The present technology relates to a clock enabler circuit, and more particularly to a clock enabler circuit that can prevent the occurrence of whiskers in an output clock.

2. Description of the Related Art Conventionally, a clock enabler circuit is known for aligning operation timing (clock input timing) and logic signal timing in a circuit that requires a clock. The clock enabler circuit operates so as not to output the clock to the subsequent stage until the operation of the preceding clock generation circuit stabilizes.

For example, Patent Document 1 discloses a clock enabler circuit that outputs an output clock after several cycles of an input clock from a clock generation circuit after an enable signal goes high.

JP 2012-39448 A

However, when high-speed operation is required for the clock enabler circuit disclosed in Japanese Patent Laid-Open No. 2002-200012, a delay due to flip-flops in the circuit causes the output clock to have a pulse-like pattern called a whisker (also referred to as a hazard). noise may occur.

The present technology has been made in view of such a situation, and is intended to prevent occurrence of whiskers in an output clock.

A clock enabler circuit of the present technology includes a gate signal generator that generates a gate signal that enables the input clock based on an input clock and an enable signal, and a gate signal generator that enables the input clock according to the level of the gate signal. a clock signal output unit for outputting an output clock, wherein the gate signal generation unit includes a delay circuit that differentiates and delays the enable signal; a latch circuit that outputs the gate signal by latching the enable signal, and delaying the timing of level change of the enable signal until the timing at which the input clock does not become valid in the clock signal output unit, generating the gate signal;

In the present technology, a delay circuit that differentiates and delays an enable signal and a latch circuit that outputs a gate signal by latching the enable signal that has been differentiated and delayed by the delay circuit are provided . A gate signal is generated by delaying the level change timing until the input clock does not become valid at the clock signal output section.

According to the present technology, it is possible to prevent occurrence of whiskers in the output clock.

Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

1 is a diagram showing a configuration example of a conventional clock enabler circuit; FIG. 4 is a timing chart showing the operation of a conventional clock enabler circuit; 4 is a timing chart showing the operation of a conventional clock enabler circuit; FIG. 10 is a diagram illustrating an operation example of a clock enabler circuit to which the present technology is applied; 1 is a block diagram showing a configuration example of a clock enabler circuit according to a first embodiment; FIG. 6 is a diagram showing a circuit configuration example of the clock enabler circuit of FIG. 5; FIG. 7 is a timing chart showing the operation of the clock enabler circuit of FIG. 6; It is a timing chart when no input clock delay unit is provided. 1 is a diagram showing a circuit configuration example of a clock enabler circuit that supports differential inputs; FIG. FIG. 11 is a block diagram showing a configuration example of a clock enabler circuit according to a second embodiment; FIG. 11 is a diagram showing a circuit configuration example of the clock enabler circuit of FIG. 10; FIG. 12 is a timing chart showing the operation of the clock enabler circuit of FIG. 11; It is a timing chart when the EN3 signal is always H. 11 is a diagram showing another circuit configuration example of the clock enabler circuit of FIG. 10; FIG. 11 is a diagram showing still another circuit configuration example of the clock enabler circuit of FIG. 10; FIG. 1 is a diagram showing a circuit configuration example of a clock enabler circuit that supports differential inputs; FIG.

Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The description will be given in the following order.

1. 2. Problems of conventional technology and overview of this technology. First embodiment 3. Second embodiment

<1. Problems of conventional technology and overview of this technology>
FIG. 1 is a block diagram showing a configuration example of a conventional clock enabler circuit.

The clock enabler circuit 10 of FIG. 1 is composed of a gate signal generator 11 and a clock signal output unit 12 .

The gate signal generation unit 11 has a flip-flop inside, and generates a gate signal for enabling the input clock based on an input clock from a clock generation circuit (not shown) and an enable signal (EN signal). It is supplied to the signal output section 12 .

The clock signal output unit 12 outputs an output clock by validating the input clock according to the level of the gate signal.

Specifically, as shown in FIG. 2, when the input clock falls at time t1, the gate signal generator 11 uses the EN signal that has changed from L (Low) level to H (High) level as the gate signal. Output. A flip-flop causes a delay from the fall of the input clock until the H-level EN signal is output as the gate signal.

In this state, that is, when the gate signal is at H level, when the input clock rises at time t2, the clock signal output unit 12 outputs the output clock by validating the input clock.

However, when a high-speed operation is required for the clock enabler circuit 10, as shown in FIG. 3, the flip-flop causes a large delay with respect to the input clock. In this case, as shown in FIG. 3, the gate signal may go high at time t3 while the input clock is high.

At this time, the clock signal output unit 12 enables the input clock, so that pulse-shaped noise Hd called whisker (also called hazard) is generated in the output clock. In particular, when the input clock and the EN signal are asynchronous, a whisker may occur even if the flip-flop has only one stage.

Therefore, as shown in FIG. 4, the clock signal output unit of the clock enabler circuit to which the present technology is applied sets the timing of the level change of the EN signal from the L level to the H level when the input clock is valid from time t11. The gate signal is generated by delaying the timing until the input clock becomes L level, for example, between times t12 and t13.

<2. First Embodiment>
(Configuration example of clock enabler circuit)
FIG. 5 is a block diagram showing a configuration example of a clock enabler circuit according to the first embodiment of the present technology;

The clock enabler circuit 30 of FIG. 5 comprises a gate signal generator 31, a clock signal output section 32, and an input clock delay section 33.

The gate signal generation unit 31 generates a gate signal for validating the input clock based on the input clock from the clock generation circuit (not shown) and the EN signal, and supplies the gate signal to the clock signal output unit 32 . The gate signal generator 31 has a delay circuit that delays the EN signal and a latch circuit that outputs the gate signal by latching the EN signal delayed by the delay circuit.

The clock signal output unit 32 outputs an output clock by validating the input clock from the input clock delay unit 33 according to the level of the gate signal from the gate signal generation unit 31 .

The input clock delay unit 33 delays an input clock from a clock generation circuit (not shown) and supplies it to the clock signal output unit 32 .

FIG. 6 is a diagram showing a circuit configuration example of the clock enabler circuit 30 of FIG.

In the example of FIG. 6, a NAND gate 34 is connected to the input terminal of the input clock of the gate signal generator 31, and the input clock and the second enable signal (EN2 signal) are input to the NAND gate 34. be. That is, the NAND gate 34 supplies an inverted input clock obtained by inverting the input clock to the gate signal generator 31 when the EN2 signal becomes H level.

The gate signal generator 31 in FIG. 6 is composed of four stages of flip-flops 41 to 44 and a latch circuit 45 .

The flip-flops 41 to 44 are connected in series to form a shift register. More specifically, the flip-flops 41 to 44 form a delay circuit that delays the EN signal by 4 pulses of the inverted input clock input thereto.

The latch circuit 45 outputs a gate signal by latching the EN signal delayed by the flip-flops 41 to 44 (delay circuits).

Although four stages of flip-flops are provided in the gate signal generator 31 of FIG. 6, the number of stages is not limited to four. Also, instead of the latch circuit 45, a flip-flop may be provided.

The clock signal output section 32 of FIG. 6 is composed of p-type transistors 51 and 52 , n-type transistors 53 and 54 and an inverter 55 . P-type transistors 51 and 52 and n-type transistors 53 and 54 form a switched inverter.

One of the source and drain of p-type transistor 51 is connected to the power supply potential, and the other of the source and drain is connected to one of the source and drain of p-type transistor 52 . The other of the source and drain of p-type transistor 52 is connected to the output terminal.

One of the source and drain of n-type transistor 54 is connected to GND, and the other of the source and drain is connected to one of the source and drain of n-type transistor 53 . The other of the source and drain of n-type transistor 53 is connected to the output terminal.

The gate of the p-type transistor 51 is connected to the output terminal of the gate signal generator 31 via the inverter 55, and the gate of the n-type transistor 54 is directly connected to the output terminal of the gate signal generator 31. . Gates of the p-type transistor 52 and the n-type transistor 53 are connected to the output end of the input clock delay section 33 .

With such a configuration, when the gate signal is at L level, the clock signal output section 32 does not output anything regardless of the input clock from the input clock delay section 33 (the output clock remains at H level). . When the gate signal is at H level, the clock signal output section 32 outputs a signal obtained by inverting the input clock from the input clock delay section 33 as an output clock.

The input clock delay unit 33 of FIG. 6 is composed of two inverters 61 and 62 connected in series. With such a configuration, the input clock delay unit 33 outputs a delayed input clock obtained by delaying the input clock without changing the polarity of the input clock. Note that the number of inverters forming the input clock delay unit 33 is not limited to two, and may be an even number.

(Operation of clock enabler circuit)
Next, the operation of clock enabler circuit 30 of FIG. 6 will be described with reference to the timing chart of FIG.

When the input clock rises at time t31 with the EN2 signal at H level, the NAND gate 34 outputs an inverted input clock delayed by time d11 from time t31.

When the input clock rises at time t31, the input clock delay unit 33 outputs a delayed input clock delayed by time d12 from time t31.

On the other hand, when the EN signal becomes H level, the flip-flops 41 to 44 delay the EN signal by 4 pulses of the inverted input clock. At time t32, when the inverted input clock falls, the latch circuit 45 latches the H-level EN signal at time t33 delayed by time d13 from time t32 and outputs it as a gate signal.

Since the gate signal is at L level until time t33, the clock signal output unit 32 does not output anything regardless of the delayed input clock from the input clock delay unit 33 (the output clock is at L level). . At time t33, the gate signal becomes H level, but the output clock remains at L level because the delayed input clock from the input clock delay unit 33 is at H level.

Then, at time t34, when the delayed input clock falls, the clock signal output unit 32 starts outputting a signal obtained by inverting the delayed input clock as an output clock.

When the input clock is directly supplied to the clock signal output section 32 without providing the input clock delay section 33, as shown in FIG. , the input clock is at L level, so the output clock is at H level, and a whisker (noise Hd) is generated.

According to the above operation, even when a high-speed operation is required for the clock enabler circuit 30 or when the input clock and the enable signal are asynchronous, the gate signal changes to H level, it is possible to reliably prevent the occurrence of whiskers in the output clock.

(Another circuit configuration example)
Although the input clock is input to the clock enabler circuit 30 as a single-ended signal in the above, it may be input as a differential signal.

FIG. 9 is a diagram showing a circuit configuration example of the clock enabler circuit 30 in which the input clock is input as a differential signal.

In the example of FIG. 9, differential input clocks INP and INN are input to clock signal output section 32 via input clock delay section 33 .

The input clock delay unit 33 of FIG. 9 is provided with inverters 61-1 and 62-1 corresponding to the signal INP and inverters 61-2 and 62-2 corresponding to the signal INN. Cross-coupled inverters 63 and 64 are connected to the output sides of the inverters 61-1 and 61-2. As a result, the timings of changes in the signals output from the inverters 61-1 and 61-2 are matched.

The clock signal output unit 32 of FIG. 9 includes p-type transistors 51-1 and 52-1, n-type transistors 53-1 and 54-1, and an inverter 55-1 corresponding to the signal INP, and an inverter 55-1 corresponding to the signal INN. P-type transistors 51-2, 52-2, n-type transistors 53-2, 54-2, and an inverter 55-2 are provided. The p-type transistors 51-1, 52-1, the n-type transistors 53-1, 54-1, the p-type transistors 51-2, 52-2, and the n-type transistors 53-2, 54-2 are switched. Configure the inverter.

With such a configuration, even when the input clock is input as a differential signal, it is possible to reliably prevent the generation of whiskers in the output clock.

By the way, in the clock enabler circuit 30 of the present embodiment, the input clock delay section 33 is provided in order to adjust the timing at which the gate signal becomes H level and the timing at which the input clock is enabled.

However, providing the input clock delay unit 33 (inverter) in the clock path, which is the transmission path of the input clock, causes jitter and increases power consumption.

In addition, the inverter 55 (55-1, 55-2) is provided by constructing a switched inverter in the clock signal output section 32, but this reduces the timing margin.

Therefore, in the following, a configuration is described in which a timing margin is ensured while suppressing the occurrence of jitter and power consumption.

<3. Second Embodiment>
(Configuration example of clock enabler circuit)
FIG. 10 is a block diagram illustrating a configuration example of a clock enabler circuit according to a second embodiment of the present technology;

The clock enabler circuit 130 of FIG. 10 is composed of a gate signal generation section 131 and a clock signal output section 132 .

The gate signal generation unit 131 generates a gate signal for validating the input clock based on the input clock from the clock generation circuit (not shown) and the EN signal, and supplies the gate signal to the clock signal output unit 132 . The gate signal generator 131 has a delay circuit that differentiates and delays the EN signal, and a latch circuit that outputs the gate signal by latching the EN signal that has been differentiated and delayed by the delay circuit.

The clock signal output unit 132 outputs an output clock by validating the input clock according to the level of the gate signal from the gate signal generation unit 131 .

FIG. 11 is a diagram showing a circuit configuration example of the clock enabler circuit 130. As shown in FIG.

In the example of FIG. 11, NAND gates 133-1 and 133-2 are connected to the input terminal of the input clock of the gate signal generator 131, and the input clock and a second enable signal (EN2 signal) are input. That is, the NAND gates 133 - 1 and 133 - 2 supply the inverted input clocks obtained by inverting the input clocks to the gate signal generator 131 when the EN2 signal becomes H level.

In addition, in the example of FIG. 11, the EN signal is directly input to the gate signal generator 131, and an inverted signal obtained by inverting the EN signal is input via the inverter .

The gate signal generation section 131 of FIG. 11 has a delay circuit 140 and a latch circuit 150 .

The delay circuit 140 is composed of a first shift register consisting of four stages of flip-flops 141-1 to 144-1 and a second shift register consisting of four stages of flip-flops 141-2 to 144-2. .

The flip-flops 141-1 to 144-1 form a delay circuit that delays the EN signal by four pulses of the inverted input clock input from the NAND gate 133-1.

The flip-flops 141-2 to 144-2 form a delay circuit that delays the inverted signal of the EN signal by four pulses of the inverted input clock input from the NAND gate 133-2.

However, in the example of FIG. 11, the inverted output of the second stage flip-flop 142-1 in the first shift register is the input of the third stage flip-flop 143-2 in the second shift register. . Therefore, the flip-flops 141-2 and 142-2 do not need to be provided electrically, but are provided to maintain symmetry between the first shift register and the second shift register.

In the example of FIG. 11, the inverted output of the second-stage flip-flop 142-1 of the first shift register is input to the third-stage flip-flop 143-2 of the second shift register. , the inverted output of the n-th stage flip-flop other than the second stage in the first shift register may be input to the (n+1)th-stage flip-flop in the second shift register.

By differentializing the EN signal in this way, it is possible to adjust the timing at which the gate signal changes to H level. However, simply differentializing the EN signal may cause the clock enabler circuit 130 to malfunction due to a mismatch in the differential EN signal. Therefore, by inputting the inverted output of the n-th flip-flop in the first shift register to the (n+1)-th flip-flop in the second shift register, the differential EN signal The effect of mismatch can be reduced.

Latch circuit 150 comprises transfer gates 151 - 1 and 151 - 2 , NOR gate 152 and NAND gate 153 .

The transfer gate 151-1 becomes conductive in response to the inverted input clock from the NAND gate 133-1, thereby transferring the EN signal delayed by the first shift register (flip-flops 141-1 to 144-1). , is output to the clock signal output unit 132 as a gate signal.

The transfer gate 151-2 becomes conductive in response to the inverted input clock from the NAND gate 133-2, thereby transferring the EN signal delayed by the second shift register (flip-flops 141-2 to 144-2). Outputs an inverted signal.

NOR gate 152 and NAND gate 153 are configured as a latch section for latching signals output from transfer gates 151-1 and 151-2, respectively.

The NOR gate 152 receives the output of the transfer gate 151-1 and the third enable signal (EN3 signal) for enabling the entire clock enabler circuit 130, and outputs the result to the output side of the transfer gate 151-2.

The NAND gate 153 receives the output of the transfer gate 151-2 and the EN3B signal, which is the inverted signal of the EN3 signal, and outputs it to the output side of the transfer gate 151-1.

For example, when the EN3 signal is at L level and the output of transfer gate 151-1 (that is, the gate signal) is at L level, NOR gate 152 determines the output of transfer gate 151-2 at H level. At this time, since the EN3B signal is at H level, NAND gate 153 determines the output of transfer gate 151-1 at L level.

When the EN3 signal is at L level, the output (gate signal) of the transfer gate 151-1 becomes H level, so that the NOR gate 152 determines the output of the transfer gate 151-2 at L level. At this time, since the EN3B signal is at the H level, the output (gate signal) of the transfer gate 151-1 is determined at the H level by the NAND gate 153. FIG.

When the EN3 signal is at H level, the output of the transfer gate 151-2 is fixed at L level by the NOR gate 152 regardless of the output (gate signal) of the transfer gate 151-1. At this time, since the EN3B signal is at the L level, the NAND gate 153 determines the output (gate signal) of the transfer gate 151-1 at the H level.

As described above, the logic is not determined only by the transfer gates 151-1 and 151-2, so the logic is determined by the NOR gate 152 and the NAND gate 153 forming the latch section.

The clock signal output section 132 in FIG. 11 is composed of a NAND gate 161 . The input clock and the output (gate signal) of the transfer gate 151-1 are input, and the output clock is output.

When the output (gate signal) of transfer gate 151-1 is at L level, NAND gate 161 sets the output clock to H level regardless of the level of the input clock. When the output (gate signal) of the transfer gate 151-1 is at H level, the NAND gate 161 outputs a signal obtained by inverting the input clock as an output clock in accordance with the level change of the input clock.

(Operation of clock enabler circuit)
Next, the operation of clock enabler circuit 130 of FIG. 11 will be described with reference to the timing chart of FIG.

In the example of FIG. 12, it is assumed that the EN3 signal is always at L level.

When the input clock rises at time t51 with the EN2 signal at H level, NAND gates 133-1 and 133-2 output inverted input clocks delayed by time d21 from time t51.

On the other hand, when the EN signal becomes H level, the flip-flops 141-1 to 144-1 delay the EN signal by 4 pulses of the inverted input clock. Then, at time t52, when the inverted input clock rises, the transfer gate 151-1 becomes conductive and outputs the H-level EN signal with a delay of time d22 from time t52. Latch circuit 150 latches the EN signal and outputs it as a gate signal.

Since the gate signal has been at the L level up to this point, the clock signal output unit 132 sets the output clock to the H level regardless of the input clock. Also when the gate signal becomes H level after time d22 from time t52, the output clock remains at H level because the input clock is at L level.

Then, at time t53, when the input clock rises, the clock signal output unit 132 starts outputting a signal obtained by inverting the input clock as an output clock.

According to the above operation, even when a high-speed operation is required for the clock enabler circuit 130 or when the input clock and the enable signal are asynchronous, the gate signal is generated at the timing when the input clock does not become valid. Since it changes to the H level, it is possible to reliably prevent the occurrence of whiskers in the output clock.

In addition, since it is not necessary to provide an input clock delay section (inverter) in the clock path, which is the transmission path of the input clock, and it is not necessary to provide an inverter in the clock signal output section 132, the occurrence of jitter and power consumption can be suppressed, and the A timing margin can be ensured.

Note that in the clock enabler circuit 130, the differential EN signal seems to increase the current consumption. However, by setting the EN2 signal to L level after the start of outputting the output clock, it is possible to stop the operation of the gate signal generator 131 (especially the delay circuit 140) while maintaining the level of the gate signal. Therefore, current consumption does not increase as a whole.

Also, in the example of FIG. 12, the EN3 signal is assumed to always be at L level, but as shown in FIG. , the output of the transfer gate 151-1 is fixed at H level, so that the signal obtained by inverting the input clock is always output as the output clock.

(Another circuit configuration example)
FIG. 14 is a diagram showing another circuit configuration example of the clock enabler circuit 130. As shown in FIG.

The clock enabler circuit 130 of FIG. 14 is similar to the clock enabler circuit of FIG. Different from 130. P-type transistors 171, 172 and n-type transistors 173, 174 form a switched inverter.

Even in such a configuration, the clock signal output unit 132 outputs nothing regardless of the input clock when the gate signal is at L level, and outputs a signal obtained by inverting the input clock when the gate signal is at H level. as the output clock.

FIG. 15 is a diagram showing still another circuit configuration example of the clock enabler circuit 130. As shown in FIG.

Clock enabler circuit 130 of FIG. 15 differs from clock enabler circuit 130 of FIG. 14 in that inverters 181 and 182 are provided in latch circuit 150 instead of NOR gate 152 and NAND gate 153 . Inverters 181 and 182 are also configured as latch sections for latching signals output from transfer gates 151-1 and 151-2, respectively.

Even in such a configuration, the logic is not determined only by the transfer gates 151-1 and 151-2, so the logic is determined by the inverters 181 and 182 forming the latch section.

Although the input clock is input to the clock enabler circuit 130 as a single-ended signal in the above description, it may be input as a differential signal.

FIG. 16 is a diagram showing a circuit configuration example of a clock enabler circuit in which an input clock is input as a differential signal.

In the example of FIG. 16, differential input clocks INP and INN are input to clock signal output section 132 .

The clock signal output unit 132 of FIG. 16 includes p-type transistors 171-1 and 172-1, n-type transistors 173-1 and 174-1 corresponding to the signal INP, and a p-type transistor 171-2 corresponding to the signal INN. , 172-2 and n-type transistors 173-2 and 174-2 are provided. p-type transistors 171-1, 172-1, n-type transistors 173-1, 174-1, and p-type transistors 171-2, 172-2, n-type transistors 173-2, 174-2 corresponding to signal INN. each form a switched inverter.

With such a configuration, compared to the configuration of FIG. 9 in which the input clock is also input as a differential signal, it is not necessary to provide an input clock delay section including a cross-couple inverter in the clock path which is the transmission path of the input clock. Since there is no need to provide an inverter in the clock signal output section 132, it is possible to secure a timing margin while suppressing jitter and power consumption.

In the example of FIG. 16, latch circuit 150 may be provided with NOR gate 152 and NAND gate 153 instead of inverters 181 and 182 . Furthermore, the clock signal output unit 132 includes p-type transistors 171-1 and 172-1, n-type transistors 173-1 and 174-1, p-type transistors 171-2 and 172-2, and n-type transistor 173-2. , 174-2, NAND gates corresponding to the signals INP and INN may be provided.

In this embodiment, when the load of the clock signal output unit 132, which is the output stage (the load of the clock path) is large, inverters may be connected before and after the transfer gates 151-1 and 151-2. , the size of the transistors forming the clock signal output unit 132 can be increased.

Embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

Furthermore, the present technology can be configured as follows.
(1)
a gate signal generator that generates a gate signal that enables the input clock based on the input clock and an enable signal;
a clock signal output unit that outputs an output clock by enabling the input clock according to the level of the gate signal;
A clock enabler circuit, wherein the gate signal generation unit generates the gate signal by delaying timing of level change of the enable signal to timing at which the input clock does not become valid in the clock signal output unit.
(2)
The gate signal generator is
a delay circuit that differentiates and delays the enable signal;
(1) The clock enabler circuit according to (1), further comprising: a latch circuit that outputs the gate signal by latching the enable signal that has been differentiated and delayed by the delay circuit.
(3)
The latch circuit is
first and second transfer gates that are rendered conductive in response to an inverted input clock obtained by inverting the input clock, thereby outputting the differential enable signal;
a latch unit that latches each of the enable signals output from the first and second transfer gates;
(2), wherein the latched enable signal from the first transfer gate is output as the gate signal.
(4)
The latch section includes a NOR gate that receives the output of the first transfer gate and outputs the output to the output side of the second transfer gate, and a NOR gate that receives the output of the second transfer gate and operates the first transfer gate. The clock enabler circuit according to (3), which is composed of a NAND gate that outputs to the output side of .
(5)
The latch section includes: a first inverter that receives the output of the first transfer gate and outputs the output to the output side of the second transfer gate; The clock enabler circuit according to (3), comprising a second inverter outputting to the output side of the transfer gate.
(6)
the delay circuit is composed of first and second shift registers each composed of n stages of flip-flops,
(3) to (5) according to any one of (3) to (5), wherein the inverted output of the n-th flip-flop in the first shift register is the input of the (n+1)-th flip-flop in the second shift register. Clock enabler circuit.
(7)
The gate signal generator is
a delay circuit for delaying the enable signal;
a latch circuit that outputs the gate signal by latching the enable signal delayed by the delay circuit;
The clock enabler circuit according to (1), further comprising an input clock delay section that delays the input clock input to the clock signal output section.
(8)
The clock enabler circuit according to (7), wherein the input clock delay section is configured by connecting an even number of inverters in series.
(9)
The clock signal output unit
an inverter that inverts and outputs the gate signal;
The clock enabler circuit according to (7) or (8), further comprising: a switched inverter that outputs the output clock based on the gate signal and an inverted gate signal output from the inverter.
(10)
The clock enabler circuit according to any one of (7) to (9), wherein the delay circuit is composed of a shift register composed of a plurality of stages of flip-flops.
(11)
The clock enabler circuit according to any one of (1) to (10), wherein the input clock is a single-ended signal.
(12)
The clock enabler circuit according to any one of (1) to (10), wherein the input clock is a differential signal.

30 clock enabler circuit, 31 gate signal generator, 32 clock signal output unit, 33 input clock delay unit, 41 to 44 flip-flops, 45 latch circuit, 51, 52 p-type transistors, 53, 54 n-type transistors, 55 inverter, 61, 62 inverter, 130 clock enabler circuit, 131 gate signal generator, 132 clock signal output unit, 140 delay circuit, 141-1 to 144-1, 141-2 to 144-2 flip-flop, 150 latch circuit, 151- 1, 151-2 transfer gate, 152 NOR gate, 153 NAND gate, 161 NAND gate, 171, 172 p-type transistor, 173, 174 n-type transistor, 181, 182 inverter

Claims (10)

a gate signal generator that generates a gate signal that enables the input clock based on the input clock and an enable signal;
a clock signal output unit that outputs an output clock by enabling the input clock according to the level of the gate signal;
The gate signal generator is
a delay circuit that differentiates and delays the enable signal;
a latch circuit that outputs the gate signal by latching the enable signal that has been differentiated and delayed by the delay circuit;
A clock enabler circuit that generates the gate signal by delaying timing of level change of the enable signal to timing at which the input clock does not become valid in the clock signal output unit. The latch circuit is
first and second transfer gates that are rendered conductive in response to an inverted input clock obtained by inverting the input clock, thereby outputting the differential enable signal;
a latch unit that latches each of the enable signals output from the first and second transfer gates;
2. The clock enabler circuit according to claim 1, wherein the latched enable signal from the first transfer gate is output as the gate signal. The latch section includes a NOR gate that receives the output of the first transfer gate and outputs the output to the output side of the second transfer gate, and a NOR gate that receives the output of the second transfer gate and operates the first transfer gate. 3. The clock enabler circuit according to claim 2, comprising a NAND gate outputting to the output side of . The latch section includes: a first inverter that receives the output of the first transfer gate and outputs the output to the output side of the second transfer gate; 3. The clock enabler circuit according to claim 2, comprising a second inverter outputting to the output side of the transfer gate. the delay circuit is composed of first and second shift registers each composed of n stages of flip-flops,
3. The clock enabler circuit according to claim 2, wherein the inverted output of the n-th stage flip-flop in said first shift register is the input of the (n+1)-th stage flip-flop in said second shift register. a gate signal generator that generates a gate signal that enables the input clock based on the input clock and an enable signal;
a clock signal output unit that outputs an output clock by enabling the input clock according to the level of the gate signal;
an input clock delay unit that delays the input clock input to the clock signal output unit;
The gate signal generator is
a delay circuit for delaying the enable signal;
a latch circuit that outputs the gate signal by latching the enable signal delayed by the delay circuit;
A clock enabler circuit that generates the gate signal by delaying timing of level change of the enable signal to timing at which the input clock does not become valid in the clock signal output unit. 7. The clock enabler circuit according to claim 6, wherein the input clock delay section is configured by connecting an even number of inverters in series. The clock signal output unit
an inverter that inverts and outputs the gate signal;
7. The clock enabler circuit according to claim 6, further comprising a switched inverter for outputting said output clock based on said gate signal and an inverted gate signal output from said inverter. 7. The clock enabler circuit according to claim 6, wherein said delay circuit comprises a shift register comprising a plurality of stages of flip-flops. 2. A clock enabler circuit as claimed in claim 1, wherein the input clock is a single-ended signal.

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