JP7208847B2 - Chip transfer plate, semiconductor chip stacking method, and semiconductor device manufacturing method - Google Patents

Chip transfer plate, semiconductor chip stacking method, and semiconductor device manufacturing method Download PDF

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Publication number
JP7208847B2
JP7208847B2 JP2019062427A JP2019062427A JP7208847B2 JP 7208847 B2 JP7208847 B2 JP 7208847B2 JP 2019062427 A JP2019062427 A JP 2019062427A JP 2019062427 A JP2019062427 A JP 2019062427A JP 7208847 B2 JP7208847 B2 JP 7208847B2
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chip
semiconductor
transfer plate
semiconductor device
manufacturing
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JP2020136650A (en
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靖典 橋本
昇 朝日
義之 新井
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Toray Engineering Co Ltd
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Toray Engineering Co Ltd
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Priority to PCT/JP2020/012204 priority Critical patent/WO2020196225A1/en
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Description

本発明は多数の半導体チップを転写するチップ転写板ならびに半導体チップ積層方法および半導体装置の製造方法に関する。 The present invention relates to a chip transfer plate for transferring a large number of semiconductor chips, a method of stacking semiconductor chips, and a method of manufacturing a semiconductor device.

近年、半導体チップ同士を積層させて実装密度を高める技術が進んでいる。特許文献１には、複数の半導体チップを仮圧着状態で積層したチップ積層体としてから、一括して本圧着するようにして、半導体チップが高温に曝される回数を少なくした構成が記されている。また、複数の半導体チップを仮圧着状態で積層するのに際して、特許文献１ではボンディングツールが半導体チップ１つずつを仮圧着して積層する例が示されている。 In recent years, there has been progress in technology for increasing the mounting density by stacking semiconductor chips. Patent Literature 1 describes a configuration in which a plurality of semiconductor chips are laminated in a state of being temporarily pressure-bonded to form a chip stack, which is then finally pressure-bonded all at once, thereby reducing the number of times the semiconductor chips are exposed to high temperatures. there is Further, when stacking a plurality of semiconductor chips in a state of being temporarily pressure-bonded, Patent Document 1 shows an example in which a bonding tool temporarily pressure-bonds and stacks the semiconductor chips one by one.

特開２０１２－２２２０３８号公報JP 2012-222038 A WO２０１６／１５８９３５号国際公開公報WO2016/158935 International publication

チップ積層体として本圧着することで、１回の本圧着により処理できる半導体チップの数が増しており、半導体チップ１つあたりの本圧着時間は短縮されることになる。昨今では、積層数が増すとともに、複数のチップ積層体を一括で本圧着することも可能となっており、本圧着工程で単位時間あたりに処理する半導体チップの数は飛躍的に増加している。 By performing main pressure bonding as a chip stack, the number of semiconductor chips that can be processed in one time of main pressure bonding is increased, and the main pressure bonding time per semiconductor chip is shortened. In recent years, as the number of stacked layers increases, it has become possible to perform full pressure bonding of multiple chip stacks at once, and the number of semiconductor chips processed per unit time in this pressure bonding process has increased dramatically. .

これに対して、仮圧着工程において、ボンディングツールが半導体チップをピックアップして仮圧着するまでのタクトタイムを短縮するための種々の方策が採られている。しかし、本圧着工程で単位時間あたりに処理する半導体チップの数の増加に対して、仮圧着工程での改善は充分ではなく、１台の本圧着装置に対する仮圧着装置の台数が増していく状況である。 On the other hand, in the temporary pressure bonding process, various measures have been taken to shorten the tact time from when the bonding tool picks up the semiconductor chip to when the semiconductor chip is temporarily pressure bonded. However, in response to the increase in the number of semiconductor chips processed per unit time in the main pressure bonding process, the improvement in the temporary pressure bonding process is not sufficient, and the number of temporary pressure bonding devices for one main pressure bonding device is increasing. is.

そこで、特許文献２では、半導体ウェハ同士を仮固定状態で積層してからダイシングして、多数のチップ積層体を形成する手法が示されている。この特許文献２の手法では、積層を半導体ウェハレベルで行なっていることから、極めて生産性高くチップ積層体を得ることが出来る。このため、半導体ウェハ内における欠陥率がゼロであれば極めて有効な手法である。 Therefore, Patent Document 2 discloses a method of stacking semiconductor wafers in a temporarily fixed state and then dicing them to form a large number of chip stacks. In the technique of Patent Document 2, since the stacking is performed at the semiconductor wafer level, a chip stack can be obtained with extremely high productivity. Therefore, it is a very effective method if the defect rate in the semiconductor wafer is zero.

しかし、半導体ウェハ内に不良チップとなるような欠点が含まれている場合においては、不良チップを含むチップ積層体が生じ、積層数が多きなるほど不良チップを含むチップ積層体の発生率は上昇してしまう。 However, when a semiconductor wafer contains a defect that may result in a defective chip, a chip stack containing defective chips is generated, and as the number of stacked layers increases, the occurrence rate of chip stacks containing defective chips increases. end up

半導体ウェハレベルにおいて欠陥箇所を掌握することは可能であるので、多数のチップ積層体のなかの何れの何層目が不良チップであるかを知ることが出来、仮固定状態であるので、不良チップを良品チップにリペアすることは可能である。しかし、このようなリペア作業を行なうことにより生産性は低下してしまう。また、不良チップを含むチップ積層体を廃棄するのであれば、多くの良品チップも廃棄することになり、製品歩留まりは大きく低下する。 Since it is possible to grasp the defect location at the semiconductor wafer level, it is possible to know which layer of a large number of chip stacks is the defective chip. can be repaired to a good chip. However, performing such repair work lowers productivity. Moreover, if a chip stack including defective chips is discarded, many good chips will also be discarded, resulting in a significant drop in product yield.

本発明は、上記問題を鑑みてなされたものであり、複数の半導体チップが仮固定状態で積層されたチップ積層体を得るのに好適なチップ転写板ならびに半導体チップ積層方法を提供し、生産性と歩留まりを両立させた半導体装置の製造方法を提供するものである。 The present invention has been made in view of the above problems, and provides a chip transfer plate suitable for obtaining a chip stack in which a plurality of semiconductor chips are stacked in a temporarily fixed state, and a semiconductor chip stacking method, thereby improving productivity. It is an object of the present invention to provide a method of manufacturing a semiconductor device that satisfies both the requirements and the yield.

上記の課題を解決するために、請求項１に記載の発明は、
サポート基板と、サポート基板の片面に設けられた粘着層と、前記粘着層に保持され、前記粘着層に保持された面の反対側にバンプ電極を有する、多数の半導体チップと、前記半導体チップ個々のバンプ電極側に未硬化の熱硬化性接着層が設けられた、チップ転写板
を用い、
前記チップ転写板の半導体チップを全て仮置板上に転写して仮固定し、仮固定した半導体チップ上に、前記チップ転写板を用いて、順次、半導体チップを位置合わせして転写して仮固定状態で積層し、前記仮置板上に多数の仮固定状態のチップ積層体を形成する工程と、
前記チップ積層体を、前記仮置板から個々に剥離およびピックアップして移動し、配線基板上の所定位置に配置し、熱圧着して前記配線基板に実装する工程を備えた、半導体装置の製造方法である。 In order to solve the above problems, the invention according to claim 1,
A support substrate, an adhesive layer provided on one side of the support substrate, a large number of semiconductor chips held by the adhesive layer and having bump electrodes on the opposite side of the surface held by the adhesive layer, and the individual semiconductor chips. A chip transfer plate provided with an uncured thermosetting adhesive layer on the bump electrode side of
using
All of the semiconductor chips on the chip transfer plate are transferred onto a temporary placement plate and temporarily fixed, and the semiconductor chips are sequentially aligned and transferred onto the temporarily fixed semiconductor chips by using the chip transfer plate. stacking in a fixed state to form a large number of chip stacks in a temporarily fixed state on the temporary placement plate;
Manufacture of a semiconductor device comprising a step of individually peeling and picking up the chip stack from the temporary placement plate, moving the chip stack, arranging the chip stack at a predetermined position on the wiring board, and thermally compressing the chip stack to mount the chip stack on the wiring board. The method .

請求項２に記載の発明は、請求項１に記載の半導体装置の製造方法であって、
バンプ電極が面上に配置された半導体ウェハを、粘着層を介してサポート基板に固定し、
前記半導体ウェハの前記バンプ電極が形成された面に、未硬化の熱硬化性接着フィルムを貼り合わせた後に、前記熱硬化性接着フィルムが積層された前記半導体ウェハをダイシングして多数の半導体チップに個片化して前記チップ転写板を形成する半導体装置の製造方法である。 The invention according to claim 2 is the method for manufacturing a semiconductor device according to claim 1,
A semiconductor wafer having bump electrodes arranged on its surface is fixed to a support substrate via an adhesive layer,
After bonding an uncured thermosetting adhesive film to the surface of the semiconductor wafer on which the bump electrodes are formed, the semiconductor wafer on which the thermosetting adhesive film is laminated is diced into a large number of semiconductor chips. It is a method of manufacturing a semiconductor device in which the chip transfer plate is formed by singulating .

請求項３に記載の発明は、請求項１または請求項２に記載の半導体装置の製造方法であって、
前記粘着層が、特定の波長の光により粘着力が低下して半導体チップを剥離する、光剥離性を有し、前記サポート基板が、前記特定の波長の光に対して透過性を有する前記チップ転写板を用いる半導体装置の製造方法である。 The invention according to claim 3 is the method for manufacturing a semiconductor device according to claim 1 or 2,
The adhesive layer has photo-peelability in which the adhesive strength is reduced by light of a specific wavelength and peels off the semiconductor chip, and the support substrate is transparent to the light of the specific wavelength. A method of manufacturing a semiconductor device using a transfer plate.

請求項４に記載の発明は、請求項３に記載の半導体装置の製造方法であって、
前記粘着層が、特定の波長の光によりガスを発生し、半導体チップとの界面で気泡化する特性を有する前記チップ転写板を用いる半導体装置の製造方法である。 The invention according to claim 4 is the method for manufacturing a semiconductor device according to claim 3,
In the method of manufacturing a semiconductor device using the chip transfer plate, the adhesive layer has the property of generating gas by light of a specific wavelength and forming bubbles at the interface with the semiconductor chip.

請求項５に記載の発明は、請求項１から請求項４の何れかに記載の半導体装置の製造方法であって、
サポート基板に保持された半導体チップのピッチおよび配列が、
転写先のピッチおよび配列一致する前記チップ転写板を用いる半導体装置の製造方法である。 The invention according to claim 5 is a method for manufacturing a semiconductor device according to any one of claims 1 to 4,
The pitch and arrangement of the semiconductor chips held on the support substrate are
This is a method of manufacturing a semiconductor device using the chip transfer plate that matches the pitch and arrangement of the transfer destination.

請求項６に記載の発明は、請求項１から請求項５の何れかに記載の半導体装置の製造方法であって、
前記チップ転写板の半導体チップを、仮置板上または仮固定した半導体チップ上に転写して仮固定する際に、前記チップ転写板の外周部に配置された半導体チップから転写を始め、順次内側に向けて転写を進める半導体装置の製造方法である。 The invention according to claim 6 is a method for manufacturing a semiconductor device according to any one of claims 1 to 5 ,
When the semiconductor chips on the chip transfer plate are transferred onto the temporary placement plate or onto the temporarily fixed semiconductor chips and temporarily fixed, the transfer is started from the semiconductor chips arranged on the outer periphery of the chip transfer plate, and sequentially inside. It is a method of manufacturing a semiconductor device in which the transfer is performed toward .

請求項７に記載の発明は、請求項１から請求項６の何れかに記載の半導体装置の製造方法であって、
前記チップ転写板の半導体チップの中に不良品がある場合、前記不良品のみを前記チップ転写板から剥離してから、仮置板または仮置板上に仮固定した半導体チップ上に、前記チップ転写板により半導体チップを転写し、前記不良品を剥離したため半導体チップが転写されなかった箇所に、別に用意した良品の半導体チップを配置する半導体装置の製造方法である。 The invention according to claim 7 is a method for manufacturing a semiconductor device according to any one of claims 1 to 6 ,
If there is a defective semiconductor chip on the chip transfer plate, only the defective product is peeled off from the chip transfer plate, and then the chip is placed on the temporary placement plate or on the semiconductor chip temporarily fixed on the temporary placement plate. In this method of manufacturing a semiconductor device, a semiconductor chip is transferred by a transfer plate, and a separately prepared non-defective semiconductor chip is arranged in a place where the semiconductor chip was not transferred because the defective product was peeled off.

本発明により、複数の半導体チップが仮固定状態で積層されたたチップ積層体を得るのに好適なチップ転写板ならびに半導体チップ積層方法が提供され、生産性と歩留まりを両立させた半導体装置の製造方法が実現する。 INDUSTRIAL APPLICABILITY According to the present invention, a chip transfer plate suitable for obtaining a chip stack in which a plurality of semiconductor chips are stacked in a temporarily fixed state, and a semiconductor chip stacking method are provided, thereby manufacturing a semiconductor device that achieves both productivity and yield. method is realized.

本発明の実施形態に係るチップ転写板の構成を示す図である。It is a figure which shows the structure of the chip transfer plate which concerns on embodiment of this invention. 本発明の実施形態に係るチップ転写板の形成から半導体装置の製造に至る概略フローを示す図である。1 is a diagram showing a schematic flow from forming a chip transfer plate to manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 本発明の実施形態に係るチップ転写板を形成する過程を示す図である。FIG. 4 is a diagram showing a process of forming a chip transfer plate according to an embodiment of the present invention; 本発明の実施形態に係るチップ転写板を形成するのに用いる半導体ウェハがサポート基板に貼り合わされた状態を示し、（ａ）上面図、（ｂ）断面図、（ｃ）断面の拡大図である。FIG. 3 shows a state in which a semiconductor wafer used for forming a chip transfer plate according to an embodiment of the present invention is attached to a support substrate, and is (a) a top view, (b) a cross-sectional view, and (c) an enlarged cross-sectional view. . 本発明の実施形態に係るチップ転写板を形成する途上で、半導体ウェハ上に熱硬化性接着フィルムを貼り合わせた状態を示し、（ａ）上面図、（ｂ）断面図、（ｃ）断面の拡大図である。1 shows a state in which a thermosetting adhesive film is laminated on a semiconductor wafer in the process of forming a chip transfer plate according to an embodiment of the present invention, (a) a top view, (b) a sectional view, and (c) a sectional view. It is an enlarged view. 本発明の実施形態に係り、サポート基板上の半導体ウェハを熱硬化性接着フィルムとともにダイシングしてチップ転写基板とした状態を示し、（ａ）上面図、（ｂ）断面図、（ｃ）断面の拡大図である。According to an embodiment of the present invention, showing a state in which a semiconductor wafer on a support substrate is diced together with a thermosetting adhesive film to form a chip transfer substrate, (a) a top view, (b) a cross-sectional view, and (c) a cross-sectional view. It is an enlarged view. 本発明の実施形態に係るチップ転写板を用いて、半導体チップを仮置板上に積層するフローを示す図である。It is a figure which shows the flow which laminates|stacks a semiconductor chip on a temporary placement board using the chip transfer board which concerns on embodiment of this invention. 本発明の実施形態に係るチップ転写板を用いて、半導チップを仮置板上に転写する様子を説明するもので、（ａ）チップ転写板の半導体チップを仮置板と対向させた状態を示し、（ｂ）チップ転写板の半導体チップを仮置板と密着させて転写を行なう状態を示し、（ｃ）半導体チップが仮置板に転写された状態を示す図である。1A illustrates a state in which a semiconductor chip is transferred onto a temporary placement plate using a chip transfer plate according to an embodiment of the present invention; , (b) shows a state in which the semiconductor chip of the chip transfer plate is brought into close contact with the temporary placement plate and transferred, and (c) shows a state in which the semiconductor chip is transferred to the temporary placement plate. 本発明の実施形態に係るチップ転写板を用いて、半導チップを仮置板上に積層する様子を説明するもので、（ａ）仮置板上に転写された半導体チップとチップ転写板の半導体チップを位置合わせして対向させた状態を示し、（ｂ）チップ転写板の半導体チップを仮置板上に転写済みの半導体チップと密着させて転写を行なう状態を示し、（ｃ）半導体チップが仮置板に転写済みの半導体チップ上に転写された状態を示す図である。It explains how semiconductor chips are stacked on a temporary placement plate using a chip transfer plate according to an embodiment of the present invention. (b) shows a state in which the semiconductor chips on the chip transfer plate are brought into close contact with the transferred semiconductor chips on the temporary placement plate, and (c) the semiconductor chips. is transferred onto the semiconductor chip that has already been transferred to the temporary placement plate. 本発明の実施形態に係る転写方法により、仮置板上に多数の仮固定状態のチップ積層体を形成した状態の一例（４層積層）を示す図である。FIG. 5 is a diagram showing an example (four-layer stacking) in which a large number of temporarily fixed chip stacks are formed on the temporary placement plate by the transfer method according to the embodiment of the present invention; 本発明の実施形態に係るチップ転写板から半導体チップを剥離させる手法について説明するもので、（ａ）光照射によって剥離する例を示し、（ｂ）加熱によって剥離する例を示すものである。The method of separating the semiconductor chip from the chip transfer plate according to the embodiment of the present invention will be explained, (a) showing an example of separating by light irradiation, and (b) showing an example of separating by heating. 本発明の実施形態に係るチップ転写板が有する半導体チップに不良品が含まれる場合の対応を説明するものであり、（ａ）不良（ＮＧ）半導体チップを有するチップ転写板の例を示し、（ｂ）同チップ転写板から不良チップを剥離して除去する状態を示し、（ｃ）不良チップが除去されたチップ転写板を仮置板上に配置した状態を示し、（ｄ）同転写板を用いて仮置板（上の半導体チップ）に半導体チップを転写する状態を示す図である。This is to explain how to deal with defective semiconductor chips included in the chip transfer plate according to the embodiment of the present invention, and (a) shows an example of a chip transfer plate having defective (NG) semiconductor chips, b) shows a state in which defective chips are peeled off and removed from the same chip transfer plate, (c) shows a state in which the chip transfer plate from which the defective chips have been removed is placed on the temporary placement plate, and (d) the same transfer plate is removed. FIG. 10 is a diagram showing a state in which a semiconductor chip is transferred to a temporary placement plate (upper semiconductor chip) using a temporary placement plate; 不良チップを除去した、本発明の実施形態に係るチップ転写板による仮置板（上の半導体チップ）への半導体チップの転写を行なった後の処置を説明するものであ、（ａ）別に用意した良品半導体チップを仮置板上の半導体チップ欠落箇所に配置する途上を示し、（ｂ）同欠落箇所に良品半導体チップを配置した状態を示し、（ｃ）仮置板上から半導体チップ欠落箇所がなくなった状態を示す図である。(a) separately prepared; (b) shows a state in which a non-defective semiconductor chip is placed on the missing portion of the temporary placement plate; (c) shows the missing portion of the semiconductor chip from the temporary placement plate; It is a figure which shows the state which disappeared. 仮置板上に形成された仮固定状態のチップ積層体のうち１つをピックアップする様子を説明するもので、（ａ）チップ積層体保持手段が最上層の半導体チップを保持した状態を示し、（ｂ）チップ積層体保持手段が仮固定状態のチップ積層体をピックアップした状態を示す図である。(a) shows a state in which the chip stack holding means holds the uppermost semiconductor chip; (b) is a diagram showing a state in which the temporarily fixed chip stack is picked up by the chip stack holding means. チップ積層体を配線基板上に配置する様子を説明するもので、（ａ）仮置板からピックアップしたチップ積層体を最下層の半導体チップと配線基板の電極の位置を合わせて配置した状態を示し、（ｂ）チップ積層体を配線基板に仮圧着した状態を示し、（ｃ）配線基板の表面に複数のチップ積層体が仮圧着された状態を示す図である。(a) shows a state in which the chip stack picked up from the temporary placement plate is arranged so that the positions of the semiconductor chips on the bottom layer and the electrodes of the wiring board are aligned; 3B shows a state in which a chip stack is temporarily pressure-bonded to a wiring substrate, and (c) a state in which a plurality of chip stacks are temporarily pressure-bonded to the surface of the wiring substrate; FIG. 仮圧着されたチップ積層体を本圧着して配線基板に実装する様子を説明する図であり、（ａ）本圧着ヘッドが実装対象のチップ積層体上に位置している状態を示し、（ｂ）同チップ積層体を本圧着ヘッドで加熱圧着している状態を示す図である。FIG. 10 is a diagram for explaining how the temporarily pressure-bonded chip stack is finally pressure-bonded and mounted on a wiring board, (a) showing a state in which the final pressure-bonding head is positioned on the chip stack to be mounted, and (b) ) is a diagram showing a state in which the same chip stack is heat-pressed by a main pressure-bonding head. チップ積層体について説明するもので（ａ）チップ積層体を構成する半導体チップの断面図、（ｂ）チップ積層体を配線基板上に実装した状態を示す図である。1A and 1B are cross-sectional views of semiconductor chips forming the chip laminate, and FIG. 1B are diagrams illustrating a state in which the chip laminate is mounted on a wiring substrate. FIG. 本発明のチップ転写板の全ての半導体チップを仮置板に転写する際の状態を示す図である。It is a figure which shows the state at the time of transferring all the semiconductor chips of the chip transfer board of this invention to a temporary placement board. 本発明のチップ転写板の全ての半導体チップを仮置板に転写する工程の例を説明するもので、（ａ）全ての半導体チップに同時に光を照射する状態を示し、（ｂ）チップ転写板から全ての半導体チップが剥離して転写された状態を示す図である。An example of the process of transferring all the semiconductor chips of the chip transfer plate of the present invention to the temporary placement plate will be described. FIG. 10 is a diagram showing a state in which all the semiconductor chips are peeled off and transferred from the substrate; 本発明のチップ転写板の全ての半導体チップを仮置板に転写する工程の別の例を説明するもので、（ａ）半導体チップに個別に光照射する状態を示し、（ｂ）半導体チップ個別に光照射した後の剥離の難さを示す図である。Another example of the process of transferring all the semiconductor chips of the chip transfer plate of the present invention to the temporary placement plate will be described. FIG. 10 is a diagram showing the difficulty of peeling after light irradiation on the substrate. 半導体チップに個別に光照射する方式でも転写を確実に行なうプロセスについて説明するもので、（ａ）スポット光の移動方向を上面から示したものであり、（ｂ）同移動方向について断面図で示したものである。A process for reliably performing transfer even in a method of individually irradiating light onto a semiconductor chip will be explained. (a) The moving direction of the spot light is shown from above, and (b) the same moving direction is shown in a sectional view. It is a thing. 半導体チップに個別に光照射する方式でも転写を確実に行なうプロセスの効果を説明するもので、（ａ）転写前の状態を示し、（ｂ）最外周部の半導体チップを転写する状態を示す、（ｃ）最外周の半導体チップ転写後に内側の半導体チップが転写できる状態を示す図である。It explains the effect of the process of reliably performing transfer even in the method of irradiating light on the semiconductor chips individually. (c) A diagram showing a state in which the inner semiconductor chip can be transferred after the outermost semiconductor chip is transferred.

本発明の実施形態について図面を用いて説明する。図１は本発明の実施形態に係るチップ転写板１の構成を示す断面図である。図２は本発明の実施形態に係る半導体装置の製造方法を説明する概略フロー図である。 An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the configuration of a chip transfer plate 1 according to an embodiment of the invention. FIG. 2 is a schematic flow diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

図１において、チップ転写板１は、サポート基板１０の表面に粘着層１１を介して、多数の半導体チップＣが配列された状態で保持されている。ここで、半導体チップＣには、粘着層１１と反対側にバンプ電極Ｂが形成されており、更に、バンプ電極Ｂを覆う熱硬化性接着層Ｒが設けられている。 In FIG. 1, a chip transfer plate 1 is held on the surface of a support substrate 10 with a large number of semiconductor chips C arranged thereon via an adhesive layer 11 . Here, on the semiconductor chip C, a bump electrode B is formed on the side opposite to the adhesive layer 11, and a thermosetting adhesive layer R covering the bump electrode B is further provided.

なお、本明細書において「接着層」と「粘着層」という用語を用いているが、原則的には「接着層」が最終的に接続された状態に固定するものに用いているのに対して、「粘着層」は最終的に剥離するものに対して用いている。 In this specification, the terms "adhesive layer" and "adhesive layer" are used. Therefore, the "adhesive layer" is used for the material that will eventually be peeled off.

図３はチップ転写板１を形成する工程（図２におけるＰＴ工程）を示す概略フローであり、概略フローの各ステップを説明するのが図４ないし図６である。 FIG. 3 is a schematic flow showing the process of forming the chip transfer plate 1 (PT process in FIG. 2), and FIGS. 4 to 6 explain each step of the schematic flow.

図４は、図３におけるステップＳＴ０を説明するものであり、図４（ａ）は上面図、図４（ｂ）は断面図、図４（ｃ）は断面の部分的拡大図である。図４において半導体ウェハＷは、所謂半導体ウェハ処理工程により、面内に多数の半導体回路が形成されたものであり、半導体回路毎の所定箇所にバンプ電極Ｂを形成されたものである。ここで、半導体ウェハＷは直径が数十ｃｍあるのに対して厚みが５０μｍと非常に薄く、取り扱いが難しいため、粘着層１１を介してサポート基板１０に固定された状態でハンドリングされる。サポート基板１０は平面性に優れた材質が好ましく、具体的な材質としてはガラスやシリコンが好適である。また、粘着層１１は所定の波長の光を照射されることで硬化して（粘着力が低下し）剥離性を発現するものが好ましい。特に、特定の波長の光を照射されることでガスが発生し、界面に生じる気泡により剥離性を高めたものが製品化（例えば積水化学工業株式会社のＳＥＬＦＡ（登録商標））されており、このような特性を有するものを粘着層１１に用いることが更に好ましい。なお、バンプ電極Ｂの高さは１５～２０μｍである。 4A and 4B illustrate step ST0 in FIG. 3, FIG. 4A is a top view, FIG. 4B is a cross-sectional view, and FIG. 4C is a partially enlarged cross-sectional view. In FIG. 4, a semiconductor wafer W has a large number of semiconductor circuits formed in its surface by a so-called semiconductor wafer processing process, and bump electrodes B are formed at predetermined positions for each semiconductor circuit. Here, the semiconductor wafer W has a diameter of several tens of centimeters but a thickness of 50 μm, which is very thin and difficult to handle. A material having excellent flatness is preferable for the support substrate 10, and glass or silicon is preferable as a specific material. Moreover, the adhesive layer 11 is preferably one that cures (lowers its adhesive strength) and exhibits releasability when irradiated with light of a predetermined wavelength. In particular, gas is generated by irradiation with light of a specific wavelength, and products with improved peelability due to bubbles generated at the interface (for example, SELFA (registered trademark) of Sekisui Chemical Co., Ltd.) have been commercialized. It is more preferable to use a material having such properties for the adhesive layer 11 . Incidentally, the height of the bump electrode B is 15 to 20 μm.

図５は、図３におけるステップＳＴ１を説明するものであり、図５（ａ）は上面図、図５（ｂ）は断面図、図５（ｃ）は断面の部分的拡大図である。図５は、図４の状態のバンプＢ形成面に熱硬化性接着層Ｒを設けた状態を示すものである。ここで、熱硬化性接着層Ｒを設けるのに際して、ＮＣＦ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）と呼ばれている熱硬化性接着フィルムを用いて、バンプ電極Ｂ形成面に貼り付けるのが好ましい。なお、熱硬化性接着フィルムの厚みは、バンプ電極Ｂの先端も覆うものを選ぶ。具体的には２０μｍ程度である。 5A and 5B illustrate step ST1 in FIG. 3, FIG. 5A is a top view, FIG. 5B is a cross-sectional view, and FIG. 5C is a partially enlarged cross-sectional view. FIG. 5 shows a state in which a thermosetting adhesive layer R is provided on the surface on which the bumps B are formed in the state shown in FIG. Here, when providing the thermosetting adhesive layer R, it is preferable to use a thermosetting adhesive film called NCF (Non-Conductive Film) and attach it to the bump electrode B forming surface. The thickness of the thermosetting adhesive film is selected to cover the tips of the bump electrodes B as well. Specifically, it is about 20 μm.

図６は、図３におけるステップＳＴ２を説明するものであり、図６（ａ）は上面図、図６（ｂ）は断面図、図６（ｃ）は断面の部分的拡大図である。図６は、バンプ電極Ｂ形成面に熱硬化性接着フィルムが貼られた状態の半導体ウェハＷをダイシングした状態を示すものであり、図１に構成を示したチップ転写板１が形成される。ここで、ダイシングは、ブレードダイシング等で、熱硬化性接着フィルムと半導体ウェハＷまで行なう。このため、所定ピッチのダイシングによって個片化された多数の半導体チップＣはサポート基板１０によって支持され、熱硬化性接着フィルムは個々の半導体チップＣ単位でバンプ電極Ｂ側に設けられた状態となる。 6A and 6B are for explaining step ST2 in FIG. 3, FIG. 6A is a top view, FIG. 6B is a cross-sectional view, and FIG. 6C is a partially enlarged cross-sectional view. FIG. 6 shows a state in which the semiconductor wafer W with the thermosetting adhesive film adhered to the bump electrode B formation surface is diced, and the chip transfer plate 1 having the configuration shown in FIG. 1 is formed. Here, the dicing is performed up to the thermosetting adhesive film and the semiconductor wafer W by blade dicing or the like. Therefore, a large number of semiconductor chips C separated into individual pieces by dicing with a predetermined pitch are supported by the support substrate 10, and the thermosetting adhesive film is provided on the bump electrode B side for each individual semiconductor chip C. .

ところで、図４のようにバンプ電極Ｂが形成された状態で、半導体ウェハＷ面内に形成された多数の半導体回路の動作チェックを行なって、動作不良の箇所を識別することが出来る。このため、図６のように個片化された多数の半導体チップＣのなかの何れが不良品（不良チップ）であるかという情報を後工程に引き継ぐことも出来る。 By the way, in the state where the bump electrodes B are formed as shown in FIG. 4, it is possible to check the operation of a large number of semiconductor circuits formed in the surface of the semiconductor wafer W to identify the location of the malfunction. For this reason, it is possible to take over the information as to which of the large number of individualized semiconductor chips C as shown in FIG. 6 is a defective product (defective chip) to the subsequent process.

次に、チップ転写板１を用いて、半導体チップＣを仮固定状態で積層したチップ積層体ＬＣを得る工程（図２に示すＰＬ工程）について説明する。図２に示したＰＬ工程は、図７に示すようにステップ分され、各ステップを図８ないし図１３を用いて説明する。 Next, a process (PL process shown in FIG. 2) of obtaining a chip stack LC in which the semiconductor chips C are stacked in a temporarily fixed state using the chip transfer plate 1 will be described. The PL process shown in FIG. 2 is divided into steps as shown in FIG. 7, and each step will be described with reference to FIGS. 8 to 13. FIG.

ここで、図８から図１１までは、図７のステップＳＬ３においてチップ転写板１に不良チップがないことを前提としており、ステップＳＬ３からステップＳＬ４１に進むケースを説明する図である。 Here, FIGS. 8 to 11 are diagrams for explaining a case where step SL3 proceeds to step SL41 on the assumption that there is no defective chip on chip transfer plate 1 in step SL3 of FIG.

図８（ａ）において、チップ転写１を仮置板２と対向させて用意した状態であり、図２のステップＳＬ４１の状態を示している。ここで、仮置板２はステップＳＬ１でステージ等に配置されるものであり、仮置基板２０の表面に光剥離性を有する粘着層２１が設けられたものである。粘着層２１なしも可能であるが、ある方が好ましく、粘着層１１と同様に、特定の波長の光を照射されること発生する気泡が剥離性を高める特性を有するものを用いることが更に好ましい。 FIG. 8A shows a state in which the chip transfer 1 is prepared facing the temporary placement plate 2, and shows the state of step SL41 in FIG. Here, the temporary placement plate 2 is arranged on a stage or the like in step SL1, and the surface of the temporary placement substrate 20 is provided with an adhesive layer 21 having photo-peelability. Although the adhesive layer 21 can be omitted, it is preferable to have the adhesive layer 21. As with the adhesive layer 11, it is more preferable to use the adhesive layer 11 that has the property that bubbles generated by irradiation with light of a specific wavelength enhance the peelability. .

仮置板２は、チップ転写板１の全ての半導体チップＣを転写するだけの表面積を有しており、仮置基板２０としては平面性に優れたものが望ましい。また、仮置板１を配置するステージの表面も平面性に優れている必要がある。 The temporary placement board 2 has a surface area sufficient to transfer all the semiconductor chips C on the chip transfer board 1, and it is desirable that the temporary placement board 20 has excellent flatness. Also, the surface of the stage on which the temporary placement plate 1 is arranged must be excellent in flatness.

ステップＳＬ１で仮置板２を配置した段階で、仮置板２には何も載っておらず、１層目の半導体チップＣを転写することになるため、工程チップ積層数ｎは１となる。 When the temporary placement plate 2 is arranged in step SL1, nothing is placed on the temporary placement plate 2, and the semiconductor chip C of the first layer is to be transferred. .

ステップＳＬ２ではチップ転写板１を用意し、前工程での検査情報よりステップＳＬ３でチップ転写板１に不良チップが無いことが判れば、ステップＳＬ４１でチップ転写板１の半導体チップＣを仮置板２に転写することになる。 At step SL2, the chip transfer plate 1 is prepared. If it is determined from the inspection information in the previous process that there are no defective chips on the chip transfer plate 1 at step SL3, the semiconductor chips C on the chip transfer plate 1 are placed on the temporary placement plate at step SL41. 2 will be transferred.

図８（ａ）では、チップ転写板１の半導体チップＣ側を仮置板２（粘着層２１がある場合は粘着層２１側）と対向させ、平行調整と位置合わせを行う。位置合わせは、チップ転写板１と仮置板２にそれぞれ設けられたアライメントマークを設けて、２視野カメラ等の画像認識手段を用いることが望ましい。 In FIG. 8A, the semiconductor chip C side of the chip transfer plate 1 is opposed to the temporary placement plate 2 (the adhesive layer 21 side if the adhesive layer 21 is present), and parallel adjustment and alignment are performed. Alignment is preferably performed by providing alignment marks on the chip transfer plate 1 and the temporary placement plate 2 and using image recognition means such as a two-view camera.

次に、チップ転写板１を仮置板２の相対距離を、チップ転写板１の熱硬化性接着層Ｒが仮置板２に密着するまで接近させる（図８（ｂ））。その後、チップ転写板１の粘着層１１が剥離性を発現するように硬化させ、チップ転写板１のサポート基板１０を仮置板２から離せば、図８（ｃ）のように、未硬化の熱硬化性接着層Ｒが有する粘着性により半導体チップＣは仮置板２に転写され仮固定される。ところで、粘着層１１を硬化させる方法としては、粘着層１１が光硬化性の場合は、光硬化させる波長の光を図１１（ａ）のように照射すればよい。なお、粘着層１１に熱硬化性のものを用いて、図１１（ｂ）のように加熱ヘッド４により硬化させることも可能であるが、熱硬化性接着層Ｒが硬化開始しない温度で硬化するような材料を選ぶ必要がある。 Next, the chip transfer plate 1 is brought closer to the temporary placement plate 2 until the thermosetting adhesive layer R of the chip transfer plate 1 is in close contact with the temporary placement plate 2 (FIG. 8(b)). After that, the adhesive layer 11 of the chip transfer plate 1 is cured so as to exhibit releasability, and when the support substrate 10 of the chip transfer plate 1 is separated from the temporary placement plate 2, as shown in FIG. The semiconductor chip C is transferred and temporarily fixed to the temporary placement plate 2 by the adhesiveness of the thermosetting adhesive layer R. As shown in FIG. By the way, as a method for curing the adhesive layer 11, when the adhesive layer 11 is photocurable, it may be irradiated with light having a wavelength for photocuring as shown in FIG. 11(a). It is also possible to use a thermosetting material for the adhesive layer 11 and cure it with the heating head 4 as shown in FIG. It is necessary to choose such materials.

以上でステップＳＬ４１は完了し、ステップＳＬ５の判定を行なう。ステップＳＬ５において、チップ積層体ＬＣとして積層すべきチップ積層数Ｎに、工程チップ積層数ｎが達しているか判定する。ここで、図８（ｃ）に示すように工程チップ積層数ｎは１であるので、積層すべきチップ積層数Ｎが２以上であれば、工程チップ積層数ｎを２としてステップＳＬ２に進む。 Step SL41 is completed as described above, and the determination of step SL5 is performed. At step SL5, it is determined whether or not the process chip stacking number n has reached the chip stacking number N to be stacked as the chip stack LC. Here, as shown in FIG. 8C, the process chip stack number n is 1, so if the chip stack number N to be stacked is 2 or more, the process chip stack number n is set to 2 and the process proceeds to step SL2.

前述のとおり、図９においてもチップ転写板１に不良チップがないことを前提としており、ステップＳＬ３からステップＳＬ４１に進む。図９（ａ）は、新たに用意したチップ転写板１の半導体チップＣを仮置板２に転写された半導体チップＣと対向させ、平行調整と位置合わせを行う状態である。ここで、チップ転写板１の半導体チップCは所定のピッチでサポート基板１０上に配置されているので、新たに用意したチップ転写板１の半導体チップCと仮置板２に転写された半導体チップCとは、ピッチ及び配列が一致している。このため、半導体チップＣ毎に位置合わせを行うのではなく、チップ転写板１の位置を合わせることで、多数の半導体チップＣの上下位置が揃う。ところで、位置合わせは、チップ転写板１と仮置板２にそれぞれ設けられたアライメントマークを設けて、２視野カメラ等の画像認識手段を用いるが、更に高精度に積層対象となる２つの半導体チップＣ同士の微調整を行うことが望ましい。そのために、ダイシングの際に形成された刃溝による格子模様を利用するのが良い。そこで、アライメントマークを用いた位置合わせにより半導体チップＣのサイズより小さいレベルでの精度で位置合わせを行ってから、格子模様を用いて位置合わせを行う事で、高精度な位置合わせが（チップ転写板１と仮置板２の相対移動で）実現する。 As described above, even in FIG. 9, it is assumed that there are no defective chips on the chip transfer plate 1, and the process proceeds from step SL3 to step SL41. FIG. 9(a) shows a state in which the semiconductor chip C on the newly prepared chip transfer plate 1 is opposed to the semiconductor chip C transferred on the temporary placement plate 2, and parallel adjustment and alignment are performed. Here, since the semiconductor chips C on the chip transfer plate 1 are arranged on the support substrate 10 at a predetermined pitch, the semiconductor chips C on the newly prepared chip transfer plate 1 and the semiconductor chips transferred on the temporary placement plate 2 The pitch and arrangement match with C. Therefore, by aligning the chip transfer plate 1 instead of performing alignment for each semiconductor chip C, the vertical positions of a large number of semiconductor chips C are aligned. For alignment, alignment marks are provided on the chip transfer plate 1 and the temporary placement plate 2, respectively, and image recognition means such as a two-view camera is used. It is desirable to perform fine adjustment between Cs. Therefore, it is preferable to use the lattice pattern formed by the blade grooves during dicing. Therefore, by performing alignment using alignment marks at a level smaller than the size of the semiconductor chip C, and then performing alignment using a grid pattern, highly accurate alignment can be achieved (chip transfer (by relative movement of the plate 1 and the temporary placement plate 2).

次に、チップ転写板１を仮置板２の相対距離を、チップ転写板１の熱硬化性接着層Ｒが仮置板２に転写された半導体チップに密着するまで接近させる（図９（ｂ））。その後、チップ転写板１の粘着層１１が剥離性を発現するように硬化させ、チップ転写板１のサポート基板１０を仮置板２から離せば、図９（ｃ）のように半導体チップＣは仮置板２に転写された半導体チップＣに積層された状態で仮固定される。 Next, the relative distance between the chip transfer plate 1 and the temporary placement plate 2 is brought closer until the thermosetting adhesive layer R of the chip transfer plate 1 comes in close contact with the semiconductor chip transferred to the temporary placement plate 2 (see FIG. 9B). )). After that, the adhesive layer 11 of the chip transfer plate 1 is cured so as to exhibit releasability, and when the support substrate 10 of the chip transfer plate 1 is separated from the temporary placement plate 2, the semiconductor chip C is formed as shown in FIG. 9(c). It is temporarily fixed in a state of being stacked on the semiconductor chip C transferred to the temporary placement plate 2 .

以上で工程チップ積層数ｎが２におけるステップＳＬ４１は完了し、ステップＳＬ５の判定を行なう。ステップＳＬ５において、チップ積層体ＬＣとして積層すべきチップ積層数Ｎに、工程チップ積層数ｎが達しているか判定する。 Step SL41 is completed when the process chip stacking number n is 2, and step SL5 is determined. At step SL5, it is determined whether or not the process chip stacking number n has reached the chip stacking number N to be stacked as the chip stack LC.

このようにして、工程チップ積層数が積層すべきチップ積層数ＮとなってステップＳＬ５の判定が行なわれるまで転写による積層が行なわれる。このため、積層すべきチップ積層数Ｎが４であれば、図１０に示した状態まで半導体チップＣの積層が進んだ段階でステップＳＬ５の判定を経てＰＬ工程は完了する。すなわち図１０は、４層の半導体チップＣが仮固定状態で積層されたチップ積層体ＬＣが、仮置板２に仮固定状態で多数配置された状態となっている。 In this manner, stacking by transfer is performed until the number of stacked chips in the process reaches the number N of stacked chips to be stacked, and the determination at step SL5 is performed. Therefore, if the chip lamination number N to be laminated is 4, the PL process is completed after the determination of step SL5 when the lamination of the semiconductor chips C has progressed to the state shown in FIG. That is, FIG. 10 shows a state in which a large number of chip stacks LC in which four layers of semiconductor chips C are laminated in a temporarily fixed state are arranged on the temporary placement plate 2 in a temporarily fixed state.

以上、図８から図１１までは、図７のステップＳＬ３においてチップ転写板１に不良チップがないことを前提として説明してきたが、チップ転写板１が有する多数の半導体チップＣの全てが良品チップであることは殆どなく、通常は不良チップが含まれる。 8 to 11 have been described on the assumption that there are no defective chips on the chip transfer plate 1 in step SL3 of FIG. and usually contains bad chips.

そこで、以下、本実施形態のＰＬ工程において、チップ転写板１の半導体チップCに不良チップが含まれる場合の処理について説明する。すなわち、図７のステップＳＬ３で「チップ転写板に不良チップ有」となった場合である。 Therefore, in the PL process of the present embodiment, processing when the semiconductor chips C on the chip transfer plate 1 include defective chips will be described below. That is, this is the case where "there is a defective chip on the chip transfer plate" at step SL3 in FIG.

ステップＳＬ３の段階で、前工程の検査情報から、チップ転写板１内の何処の半導体チップＣが不良チップであるか判る。そこで、図１２（ａ）で「ＮＧ」と記した半導体チップＣが不良チップであれば、チップ転写板１から不良チップを除去する。チップ転写板１から、不良チップを除去するのに際して、図１２（ｂ）の例では、光剥離性を有する粘着層１１にレーザー等のスポット光（光剥離性を発現する波長を含む）を照射して、不良チップを除去している。このように、ステップＳＬ４０では、チップ転写板１の半導体チップＣの内、全ての不良チップを除去する。 At the stage of step SL3, which semiconductor chip C in the chip transfer plate 1 is defective can be determined from the inspection information of the previous process. Therefore, if the semiconductor chip C indicated as “NG” in FIG. 12A is a defective chip, the defective chip is removed from the chip transfer plate 1 . When removing defective chips from the chip transfer plate 1, in the example of FIG. to remove bad chips. Thus, in step SL40, all the defective chips among the semiconductor chips C on the chip transfer plate 1 are removed.

この後、不良チップを除去したチップ転写１を用いて、ステップＳＬ４１で半導体チップＣの転写を行なう。図１２（ｃ）および図１２（ｄ）は、工程チップ積層数ｎが２の場合について、前述の図９（ａ）と図９（ｂ）と同じ過程を示すものであるが、部分的に半導体チップＣが欠落している。 Thereafter, using the chip transfer 1 from which the defective chips are removed, the transfer of the semiconductor chip C is performed in step SL41. FIGS. 12(c) and 12(d) show the same process as the above-described FIGS. 9(a) and 9(b) for the case where the process chip stacking number n is 2, but partially A semiconductor chip C is missing.

ところで、仮置板２に半導体チップＣを仮固定状態で転写しながら積層するのに際して、半導体チップＣが欠落した箇所の上には半導体チップＣを積層出来なくなる。そこで、図１２（ｄ）で半導体チップＣが欠落している箇所に、ステップＳＬ４２において、良品の半導体チップＣを補充するように配置する。このステップＳＬ４２を説明するのが図１３である。 By the way, when stacking the semiconductor chip C while transferring it to the temporary placement plate 2 in a temporarily fixed state, the semiconductor chip C cannot be stacked on the part where the semiconductor chip C is missing. Therefore, in step SL42, a non-defective semiconductor chip C is arranged so as to supplement the portion where the semiconductor chip C is missing in FIG. 12(d). FIG. 13 explains this step SL42.

図１３（ａ）は、チップ保持手段５が、（チップ転写基板１の半導体チップＣと同仕様でかつ良品の）半導体チップＣを別に用意して、吸着保持して搬送する状態である。次に、図１３（ｂ）のように、チップ保持手段５は良品の半導体チップＣを、仮置板２上で半導体チップＣが欠落した箇所で、下層の半導体チップＣ上に位置合わせして配置する。その後、図１３（ｃ）のように、チップ保持手段５が半導体チップＣの吸着を解除して上昇することで、仮置板２に積層された半導体チップＣの状況は、図９（ｃ）と同様になる。 FIG. 13A shows a state in which the chip holding means 5 separately prepares a semiconductor chip C (which has the same specifications as the semiconductor chip C of the chip transfer substrate 1 and is of good quality), sucks and holds it, and conveys it. Next, as shown in FIG. 13(b), the chip holding means 5 aligns the non-defective semiconductor chip C on the lower layer semiconductor chip C at the location where the semiconductor chip C is missing on the temporary placement plate 2. Deploy. After that, as shown in FIG. 13(c), the chip holding means 5 releases the adsorption of the semiconductor chip C and rises, so that the state of the semiconductor chip C stacked on the temporary placement plate 2 is as shown in FIG. 9(c). becomes similar to

このように、本発明では、チップ転写板１を用い、多数の半導体チップＣを同時に積層することが出来るとともに、不良チップはチップ転写板１から転写（積層）する前に除去される。このため、半導体チップＣを積層する過程で不良チップが入りこむことはなくなる。なお、不良チップを除去して、良品を補充するための工程が必要となるが、半導体チップＣに占める不良品の割合は数％にも満たないことから、図７のステップＳＬ４０とステップＳＬ４２がＰＬ工程全体のタクトタイムに及ぼす影響も小さい。 As described above, according to the present invention, a large number of semiconductor chips C can be stacked simultaneously using the chip transfer plate 1, and defective chips are removed from the chip transfer plate 1 before they are transferred (stacked). As a result, defective chips do not enter during the process of stacking the semiconductor chips C. FIG. A process for removing defective chips and replenishing non-defective chips is required. The effect on the takt time of the entire PL process is also small.

図１０のように仮置板２上に仮固定状態で積層された多数のチップ積層体ＬＣは、図２のＰＡ工程で配線基板上の所定位置に仮圧着された後に、ＰＢ工程で本圧着され実装される。そこで、ＰＡ工程とＰＢ工程についても、図を用いて簡単に説明する。 A large number of chip laminates LC laminated in a temporarily fixed state on the temporary placement plate 2 as shown in FIG. and implemented. Therefore, the PA process and the PB process will also be briefly described with reference to the drawings.

図１４および図１５は、ＰＡ工程について説明するものである。図１４は、多数のチップ積層体ＬＣの中から、チップ積層体保持手段６が任意のチップ積層体ＬＣをピックアップする様子を示したものである。図１４（ａ）のようにチップ積層体ＬＣの最上層の半導体チップＣをチップ積層体保持手段６が吸着保持してから上昇して、図１４（ｂ）のようにチップ積層体ＬＣをピックアップする。ここで、チップ積層体ＬＣをピックアップするためには、（未硬化の）光硬化性接着層Ｒの粘着力に比べて、粘着層２１の粘着力（粘着層２１がない場合は仮置基板２０と熱硬化性接着層Ｒの密着力）よりも強い必要がある。そこで、粘着層２１を光剥離性のものにして、ピックアップする際に対象のチップ積層体ＬＣ直下の粘着層２１にスポット光を照射してもよい。 14 and 15 explain the PA process. FIG. 14 shows how the chip stack holding means 6 picks up an arbitrary chip stack LC out of many chip stacks LC. As shown in FIG. 14(a), the semiconductor chip C on the uppermost layer of the chip laminated body LC is sucked and held by the chip laminated body holding means 6, and then lifted to pick up the chip laminated body LC as shown in FIG. 14(b). do. Here, in order to pick up the chip laminate LC, the adhesive strength of the adhesive layer 21 (if there is no adhesive layer 21, the temporary placement substrate 20 and the adhesive strength of the thermosetting adhesive layer R). Therefore, the adhesive layer 21 may be made of a material having photo-peelability, and the spot light may be irradiated to the adhesive layer 21 immediately below the target chip laminate LC when picking up.

図１４（ｂ）のようにピックアップされたチップ積層体ＬＣは、チップ積層体保持手段６に保持された状態で移動し、図１５（ａ）の所定位置に、若干の圧力で仮圧着して配置される。ここで、所定位置とはチップ積層体ＬＣの最下層の半導体チップＣのバンプ電極Ｂと配線基板Ｓの電極Ｅが上下に揃った位置である。この後、チップ積層体保持手段６による吸着保持を解除し、仮置板２からチップ積層体ＬＣを順次ピックアップして、配線基板Ｓの実装箇所全てにチップ積層体ＬＣを仮圧着状態で配置する。 The chip stack LC picked up as shown in FIG. 14(b) is moved while being held by the chip stack holding means 6, and is temporarily crimped to a predetermined position shown in FIG. 15(a) with a slight pressure. placed. Here, the predetermined position is a position where the bump electrodes B of the semiconductor chip C in the lowermost layer of the chip stack LC and the electrodes E of the wiring board S are vertically aligned. After that, the sucking and holding by the chip stack holding means 6 is released, the chip stacks LC are sequentially picked up from the temporary placement plate 2, and the chip stacks LC are placed on all mounting locations of the wiring board S in a state of being temporarily crimped. .

配線基板Ｓに仮圧着されたチップ積層体ＬＣは加熱圧着による本圧着を行うことで、配線基板Ｓ上に実装される。仮圧着されたチップ積層体ＬＣを本圧着する際は、図１６のように複数を同時に熱圧着してもよい。図１６（ａ）は複数のチップ積層体ＬＣを同時に加熱圧着する本圧着ヘッド７をチップ積層体ＬＣの上に配置した状態で、図１６（ｂ）は本圧着ヘッド７がチップ積層体ＬＣの熱圧着を開始した状態である。 The chip laminate LC temporarily pressure-bonded to the wiring board S is mounted on the wiring board S by performing final pressure-bonding by thermocompression. When the temporarily pressure-bonded chip stacks LC are finally pressure-bonded, a plurality of them may be thermocompression-bonded at the same time as shown in FIG. FIG. 16(a) shows a state in which the main pressure bonding head 7 for simultaneously heat-pressing a plurality of chip stacks LC is arranged on the chip stack LC, and FIG. This is the state where thermocompression bonding is started.

ところで、半導体チップＣは積層してから熱圧着して実装することで積層した半導体チップＣ同士が電気的にも接続されるものである。すなわち、図１７（ａ）に示すように半導体チップＣはバンプ電極Ｂから貫通電極Ｖを経てバンプ電極Ｂの反対面に露出した電極ＥＣを有しており、半導体チップＣを積層してから熱圧着することで、最下層の半導体チップＣのバンプ電極Ｂが配線基板Ｓの電極Ｅと電気的に接続し、２層目より上の半導体チップＣのバンプ電極Ｂは直下の半導体チップＣの電極ＥＣと電気的に接続された状態となる。また、熱圧着により熱硬化性接着層Ｒが硬化するため、図１７（ｂ）のように熱圧着時に形成された電気的な接続は実装後に固定される。 By the way, the stacked semiconductor chips C are also electrically connected to each other by mounting the semiconductor chips C by thermocompression bonding after stacking them. That is, as shown in FIG. 17A, the semiconductor chip C has electrodes EC exposed on the opposite surface of the bump electrodes B from the bump electrodes B via the through electrodes V. By crimping, the bump electrodes B of the semiconductor chip C on the bottom layer are electrically connected to the electrodes E of the wiring board S, and the bump electrodes B of the semiconductor chip C above the second layer are connected to the electrodes of the semiconductor chip C immediately below. It will be in the state electrically connected with EC. Further, since the thermosetting adhesive layer R is cured by thermocompression bonding, the electrical connection formed during thermocompression bonding as shown in FIG. 17B is fixed after mounting.

このように、積層された半導体チップＣ同士が電気的に接続され、配線基板Ｓに接続されたチップ積層体ＬＣは配線基板Ｓ上に固定されるが、配線基板Ｓとともに個片化やパッケージングすることで半導体装置となる。なお、本発明は同仕様の半導体チップＣを積層するのに適したものであることから、大容量化が進むメモリー素子のような半導体装置の製造に特に適している。 In this manner, the stacked semiconductor chips C are electrically connected to each other, and the chip stack LC connected to the wiring board S is fixed on the wiring board S. By doing so, it becomes a semiconductor device. Since the present invention is suitable for stacking semiconductor chips C of the same specification, it is particularly suitable for manufacturing semiconductor devices such as memory elements, which are becoming increasingly large capacity.

本発明は、同時に多数のチップ積層体を形成できることから生産性が極めて高いとともに、積層前の段階で不良チップを除去することができるので、チップ積層体を得る際の
歩留まりも高く、半導体装置の製造において生産性と歩留まりを両立したものだと言える。 According to the present invention, a large number of chip stacks can be formed at the same time, so productivity is extremely high, and defective chips can be removed at a stage before stacking. It can be said that in manufacturing, both productivity and yield are achieved.

ところで、ここまでの説明において、粘着層１１が特定の波長の光を照射されることで半導体チップＣを確実に剥離する例について説明した。これは、（特定の波長の光を照射されることで粘着力が低下するとともに）気泡発生により剥離性を高めた材質を粘着層１１として用いることにより容易に実現し得るものとなっている。 By the way, in the description so far, an example has been described in which the semiconductor chip C is reliably peeled off by irradiating the adhesive layer 11 with light of a specific wavelength. This can be easily realized by using a material for the adhesive layer 11 whose adhesive strength is lowered by being irradiated with light of a specific wavelength and whose peelability is enhanced by generating air bubbles.

しかし、気泡発生により剥離性を高めた材質を粘着層１１において、特定の波長の光を照射された時にしか気泡は発生しない。このため、硬化して粘着力が低下した粘着層１１でも、特定の波長の光を照射されていなければ半導体チップＣを弱い粘着力ながらも保持する。 However, in the adhesive layer 11 made of a material whose releasability is improved by generating air bubbles, air bubbles are generated only when light of a specific wavelength is irradiated. For this reason, even the adhesive layer 11 that has been hardened and whose adhesive strength has decreased retains the semiconductor chip C with weak adhesive strength unless it is irradiated with light of a specific wavelength.

そこで、このような残存保持力の影響と対策に関して以下に記述するが、残存保持力の影響を考慮しなければならないのは、図８（ｂ）から図８（ｃ）および図９（ｂ）から図９（ｃ）に示す、チップ転写板１の全ての半導体チップＣを仮置板２または（仮置板２上に）仮固定した半導体チップＣ上に転写する段階である。 Therefore, the influence of the residual holding force and countermeasures will be described below. 9(c), all the semiconductor chips C on the chip transfer plate 1 are transferred onto the temporary placement plate 2 or onto the semiconductor chips C temporarily fixed (on the temporary placement plate 2).

チップ転写板１の全ての半導体チップＣを仮置板２に転写する際の状態を図１８に示すが、チップ転写板１は周囲を基板保持手段１０１で保持して、半導体チップＣ側を仮置板２に対向させた状態から転写する。 FIG. 18 shows a state in which all the semiconductor chips C on the chip transfer plate 1 are transferred to the temporary placement plate 2. The chip transfer plate 1 is held by the substrate holding means 101 around its circumference, and the semiconductor chips C side is temporarily held. The image is transferred from the state in which it is opposed to the placing plate 2. - 特許庁

転写に際して、全ての半導体チップＣを同時に剥離するように、図１９（ａ）のようにサポート基板１０に全面的に光を特定の波長の光を照射する場合、全ての半導体チップＣに剥離力が働くため、光照射と同時に仮置板２から遠ざかるように垂直に基板保持手段１０１を移動させれば、図１９（ｂ）のように半導体チップＣの転写が行なわれ問題ない。ところが、サポート基板１０全面に同時に、半導体チップＣを剥離させる光を照射しようとすると大型な光源が必要になる。 In order to peel off all the semiconductor chips C at the time of transfer, as shown in FIG. works, if the substrate holding means 101 is vertically moved away from the temporary placement plate 2 at the same time as the light irradiation, the semiconductor chip C is transferred as shown in FIG. However, in order to irradiate the entire surface of the support substrate 10 with light for exfoliating the semiconductor chip C at the same time, a large-sized light source is required.

このため、図２０（ａ）のように、レーザー等のスポット光源を走査しながら、半導体チップCを順次剥離させる方法がある。しかし、この方法で、全ての半導体チップCに光を照射してから、基板保持手段１０１を仮置板２から遠ざかるように垂直に移動させようとしても半導体チップCと粘着層１１が密着した状態になっており、全ての半導体チップCを粘着層１１から剥離するのが難しくなる。すなわち、チップ転写板１の全ての半導体チップＣを転写する工程では、特定の波長の光により界面に発生する気泡の効果を充分に活かすことができない。 Therefore, as shown in FIG. 20A, there is a method of peeling off the semiconductor chips C sequentially while scanning with a spot light source such as a laser. However, even if it is attempted to vertically move the substrate holding means 101 away from the temporary placement plate 2 after irradiating all the semiconductor chips C with this method, the semiconductor chips C and the adhesive layer 11 are in close contact with each other. This makes it difficult to separate all the semiconductor chips C from the adhesive layer 11 . That is, in the step of transferring all the semiconductor chips C on the chip transfer plate 1, the effect of air bubbles generated at the interface by light of a specific wavelength cannot be fully utilized.

そこで、特定の波長の光により界面に発生する気泡の効果をスポット光源を用いても活かすための方法を模索した結果、新たな発明に至った。そのプロセスは、図２１のように、基板保持手段１０１を仮置板２から遠ざかる方向に僅かな力を加えた状態で、チップ転写板１の外周部に配置された半導体チップＣから内側に配置された半導体チップＣに、順次（特定の波長の）光を照射するというものである。すなわち、図２１（ａ）において、最外周に配置された半導体チップＣをＤＲ方向に移動するスポット光を照射した後に、内側に配置された半導体チップＣ方向（ＤＣ方向）に順次移動しながら、ＤＲ方向に移動するスポット光を照射して、チップ転写板１の外周部に配置された半導体チップＣから順次転写するものである。 Therefore, as a result of searching for a method for making use of the effect of air bubbles generated at the interface by light of a specific wavelength even when using a spot light source, a new invention was achieved. As shown in FIG. 21, the substrate holding means 101 is placed inward from the semiconductor chip C arranged on the outer periphery of the chip transfer plate 1 while applying a slight force in the direction away from the temporary placement plate 2 . The semiconductor chip C thus formed is sequentially irradiated with light (with a specific wavelength). That is, in FIG. 21A, after irradiating the semiconductor chip C arranged on the outermost periphery with the spot light moving in the DR direction, while sequentially moving in the direction of the semiconductor chip C arranged inside (DC direction), A spot light moving in the DR direction is irradiated, and the semiconductor chips C arranged on the outer peripheral portion of the chip transfer plate 1 are sequentially transferred.

このようにすることで、図２２（ａ）から図２２（ｂ）に示すようにスポット光を受けた粘着層１１が、基板保持手段１０１の移動により半導体チップＣから完全に離れるため、粘着層１１と半導体チップＣの再密着が回避できる。以後、図２２（ｃ）のように、順次内側の半導体チップＣから粘着層が剥離するようにすることで、基板保持手段１０１に大きな力を加えることなく、チップ転写板１の全ての半導体チップＣを確実に転写することが可能となる。 22(a) to 22(b), the adhesive layer 11 receiving the spot light is completely separated from the semiconductor chip C by the movement of the substrate holding means 101. 11 and the semiconductor chip C can be prevented from re-adhering to each other. Thereafter, as shown in FIG. 22(c), the adhesive layer is sequentially peeled off from the inner semiconductor chip C, so that all the semiconductor chips on the chip transfer plate 1 can be removed without applying a large force to the substrate holding means 101. C can be reliably transferred.

１ チップ転写板
２ 仮置板
４ 加熱ヘッド
５ チップ保持手段
６ チップ積層体保持手段
７ 本圧着ヘッド
１０ サポート基板
１１ 粘着層
２０ 仮置基板
２１ 粘着層
１０１ 基板保持手段
Ｂ バンプ電極
Ｃ 半導体チップ
Ｅ 電極（配線基板上の電極）
ＥＣ 電極（半導体チップのバンプ電極形成面の反対側に形成）
ＬＣ チップ積層体
Ｒ 熱硬化性接着フィルム
Ｓ 配線基板
Ｖ 貫通電極
Ｗ 半導体ウェハ REFERENCE SIGNS LIST 1 chip transfer plate 2 temporary placement plate 4 heating head 5 chip holding means 6 chip laminate holding means 7 main pressure bonding head 10 support substrate 11 adhesive layer 20 temporary placement substrate 21 adhesive layer 101 substrate holding means B bump electrode C semiconductor chip E electrode (electrode on wiring board)
EC electrode (formed on the opposite side of the bump electrode forming surface of the semiconductor chip)
LC chip laminate R thermosetting adhesive film S wiring substrate V through electrode W semiconductor wafer

Claims (7)

サポート基板と、サポート基板の片面に設けられた粘着層と、前記粘着層に保持され、前記粘着層に保持された面の反対側にバンプ電極を有する、多数の半導体チップと、前記半導体チップ個々のバンプ電極側に未硬化の熱硬化性接着層が設けられた、チップ転写板
を用い、
前記チップ転写板の半導体チップを全て仮置板上に転写して仮固定し、仮固定した半導体チップ上に、前記チップ転写板を用いて、順次、半導体チップを位置合わせして転写して仮固定状態で積層し、前記仮置板上に多数の仮固定状態のチップ積層体を形成する工程と、
前記チップ積層体を、前記仮置板から個々に剥離およびピックアップして移動し、配線基板上の所定位置に配置し、熱圧着して前記配線基板に実装する工程を備えた、半導体装置の製造方法。 A support substrate, an adhesive layer provided on one side of the support substrate, a large number of semiconductor chips held by the adhesive layer and having bump electrodes on the opposite side of the surface held by the adhesive layer, and the individual semiconductor chips. A chip transfer plate provided with an uncured thermosetting adhesive layer on the bump electrode side of
using
All of the semiconductor chips on the chip transfer plate are transferred onto a temporary placement plate and temporarily fixed, and the semiconductor chips are sequentially aligned and transferred onto the temporarily fixed semiconductor chips by using the chip transfer plate. stacking in a fixed state to form a large number of chip stacks in a temporarily fixed state on the temporary placement plate;
Manufacture of a semiconductor device comprising a step of individually peeling and picking up the chip stack from the temporary placement plate, moving the chip stack, arranging the chip stack at a predetermined position on the wiring board, and thermally compressing the chip stack to mount the chip stack on the wiring board. Method. 請求項１に記載の半導体装置の製造方法であって、
バンプ電極が面上に配置された半導体ウェハを、粘着層を介してサポート基板に固定し、
前記半導体ウェハの前記バンプ電極が形成された面に、未硬化の熱硬化性接着フィルムを貼り合わせた後に、前記熱硬化性接着フィルムが積層された前記半導体ウェハをダイシングして多数の半導体チップに個片化して前記チップ転写板を形成する半導体装置の製造方法。 A method for manufacturing a semiconductor device according to claim 1,
A semiconductor wafer having bump electrodes arranged on its surface is fixed to a support substrate via an adhesive layer,
After bonding an uncured thermosetting adhesive film to the surface of the semiconductor wafer on which the bump electrodes are formed, the semiconductor wafer on which the thermosetting adhesive film is laminated is diced into a large number of semiconductor chips. A method of manufacturing a semiconductor device in which the chip transfer plate is formed by singulating . 請求項１または請求項２に記載の半導体装置の製造方法であって、
前記粘着層が、特定の波長の光により粘着力が低下して半導体チップを剥離する、光剥離性を有し、前記サポート基板が、前記特定の波長の光に対して透過性を有する前記チップ転写板を用いる半導体装置の製造方法。 A method for manufacturing a semiconductor device according to claim 1 or claim 2,
The adhesive layer has photo-peelability in which the adhesive strength is reduced by light of a specific wavelength and peels off the semiconductor chip, and the support substrate is transparent to the light of the specific wavelength. A method of manufacturing a semiconductor device using a transfer plate. 請求項３に記載の半導体装置の製造方法であって、
前記粘着層が、特定の波長の光によりガスを発生し、半導体チップとの界面で気泡化する特性を有する前記チップ転写板を用いる半導体装置の製造方法。 A method for manufacturing a semiconductor device according to claim 3,
A method of manufacturing a semiconductor device using the chip transfer plate, wherein the adhesive layer has a characteristic of generating gas by light of a specific wavelength and forming bubbles at the interface with the semiconductor chip. 請求項１から請求項４の何れかに記載の半導体装置の製造方法であって、
サポート基板に保持された半導体チップのピッチおよび配列が、
転写先のピッチおよび配列一致する前記チップ転写板を用いる半導体装置の製造方法。 A method for manufacturing a semiconductor device according to any one of claims 1 to 4,
The pitch and arrangement of the semiconductor chips held on the support substrate are
A method of manufacturing a semiconductor device using the chip transfer plate that matches the pitch and arrangement of the transfer destination. 請求項１から請求項５の何れかに記載の半導体装置の製造方法であって、
前記チップ転写板の半導体チップを、仮置板上または仮固定した半導体チップ上に転写して仮固定する際に、前記チップ転写板の外周部に配置された半導体チップから転写を始め、順次内側に向けて転写を進める半導体装置の製造方法。 A method for manufacturing a semiconductor device according to any one of claims 1 to 5,
When the semiconductor chips on the chip transfer plate are transferred onto the temporary placement plate or onto the temporarily fixed semiconductor chips and temporarily fixed, the transfer is started from the semiconductor chips arranged on the outer periphery of the chip transfer plate, and sequentially inside. A method of manufacturing a semiconductor device in which transfer is performed toward 請求項１から請求項６の何れかに記載の半導体装置の製造方法であって、
前記チップ転写板の半導体チップの中に不良品がある場合、
前記不良品のみを前記チップ転写板から剥離してから、仮置板または仮置板上に仮固定した半導体チップ上に、前記チップ転写板により半導体チップを転写し、
前記不良品を剥離したため半導体チップが転写されなかった箇所に、別に用意した良品の半導体チップを配置する半導体装置の製造方法。 A method for manufacturing a semiconductor device according to any one of claims 1 to 6,
If there is a defective semiconductor chip on the chip transfer plate,
After peeling off only the defective product from the chip transfer plate, the semiconductor chip is transferred by the chip transfer plate onto the temporary placement plate or the semiconductor chip temporarily fixed on the temporary placement plate,
A method of manufacturing a semiconductor device, wherein a non-defective semiconductor chip prepared separately is arranged in a place where the semiconductor chip was not transferred because the defective product was peeled off.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111675A (en) 2002-09-19 2004-04-08 Sony Corp Mounting method
JP2009110995A (en) 2007-10-26 2009-05-21 Toray Eng Co Ltd Three-dimensional packaging method and apparatus
JP2009170455A (en) 2008-01-10 2009-07-30 Toshiba Corp Method of manufacturing semiconductor device
JP2013021058A (en) 2011-07-08 2013-01-31 Elpida Memory Inc Manufacturing method of semiconductor device
JP2013187529A (en) 2012-03-12 2013-09-19 National Institute Of Advanced Industrial & Technology Assembly method of chip
WO2018034299A1 (en) 2016-08-18 2018-02-22 富士フイルム株式会社 Chip production method and laminate
JP2018117106A (en) 2017-01-21 2018-07-26 東レエンジニアリング株式会社 Mounting method and mounting device
WO2018173764A1 (en) 2017-03-21 2018-09-27 富士フイルム株式会社 Laminated device, laminated body, and method for manufacturing laminated device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111675A (en) 2002-09-19 2004-04-08 Sony Corp Mounting method
JP2009110995A (en) 2007-10-26 2009-05-21 Toray Eng Co Ltd Three-dimensional packaging method and apparatus
JP2009170455A (en) 2008-01-10 2009-07-30 Toshiba Corp Method of manufacturing semiconductor device
JP2013021058A (en) 2011-07-08 2013-01-31 Elpida Memory Inc Manufacturing method of semiconductor device
JP2013187529A (en) 2012-03-12 2013-09-19 National Institute Of Advanced Industrial & Technology Assembly method of chip
WO2018034299A1 (en) 2016-08-18 2018-02-22 富士フイルム株式会社 Chip production method and laminate
JP2018117106A (en) 2017-01-21 2018-07-26 東レエンジニアリング株式会社 Mounting method and mounting device
WO2018173764A1 (en) 2017-03-21 2018-09-27 富士フイルム株式会社 Laminated device, laminated body, and method for manufacturing laminated device

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