JP7198473B2 - Information processing system, information processing program, information processing apparatus, and information processing method - Google Patents

Description

The present invention relates to an information processing system, an information processing program, an information processing apparatus, and an information processing method.

With the development of multi-core processors, research and development for improving cost performance using multi-core processors has been widely carried out in various fields. It goes without saying that these processors are used in companies or homes, but they are also often installed in data centers and used for searching various data, mining, and the like.

In route search, the Dijkstra method, which gradually determines the route from the starting node based on the weight of the link from each node, is often used as a search method. However, in the Dijkstra method, links that reach the same node at different timings (steps) occur, and it is generally difficult to perform parallel processing.

Sho Shimizu, et al., "Study on Shortest Path Search Using Reconfigurable Processor", Institute of Electronics, Information and Communication Engineers Technical Research Report, The Institute of Electronics, Information and Communication Engineers, December 2005, Vol.105, No.451, p. .1-6

Accordingly, the present invention proposes an information processing system, an information processing program, an information processing apparatus, and an information processing method that can perform route search at high speed and with high accuracy using a multi-core processor.

An information processing system according to an embodiment comprises a GPU comprising a built-in device memory and a plurality of arithmetic cores that execute a plurality of arithmetic processes in parallel; and route network data storage means for storing route network data. a target link storage means for storing target links which are links to be processed; and target link extraction for extracting one or a plurality of target links at a first point based on the route network data. means, cost calculation means for performing parallel calculation of costs for one or more of said links to be processed, updating said links to be processed for which cost calculation has been completed as processed links, and connecting said links to said processed links. target link updating means for newly setting one or a plurality of unprocessed links to be processed as the target link; a route acquisition means for acquiring a route to the destination, and at least the route network data storage means and the cost calculation means are provided on the GPU.

Realize high-speed and accurate route search using a multi-core processor.

1 is a block diagram showing an example of functions of an information processing system according to an embodiment; FIG. 1 illustrates an example hardware configuration of an information processing system according to an embodiment; FIG. 4 is a flowchart showing the flow of processing of the information processing system according to one embodiment; The figure which shows an example of the outline of the link process which concerns on one Embodiment. FIG. 4 is a diagram illustrating an example of an outline of memory management according to one embodiment;

First, the terms used in this embodiment will be explained. In addition, in the explanation of the terms, only the parts necessary for the explanation of the present embodiment are explained, and the terms are not strictly accurate, and the detailed explanation is omitted.

A “GPU (Graphical Processing Unit)” is a processor specialized for image processing. Today, due to its excellent parallel arithmetic accuracy, it is often used for general arithmetic processing as the application of GPGPU (General-Purpose computing on GPU).

A "computing core" is the minimum unit of a core that performs one computation provided in a GPU, and one GPU includes several hundred to several thousand computing cores.

"Device memory" refers to a storage area provided in the GPU, and is used to secure programs for operating the arithmetic cores, data used by the arithmetic cores, and buffer areas required for arithmetic operations. A single GPU is provided with a device memory with a capacity of several G to several tens of G.

"Host program" refers to a program that is executed by the CPU (Central Processing Unit) in a computer equipped with a GPU.

A "kernel (or kernel program)" refers to a program that is executed by an arithmetic core or a control unit in a GPU.

A "thread" refers to a unit for performing arithmetic processing, and here refers to an arithmetic processing (program) executed by one arithmetic core.

A “block” refers to a unit of a set of operation cores or threads, and refers to a predetermined number of operation cores or a predetermined number of threads. Within the block, it is possible to perform synchronous processing for each running thread.

"Atomic access" is a process that prevents writing from other threads when accessing (writing/reading) a certain memory when multiple threads are operating in parallel. say.

A “node” indicates point information in a search, for example, reference point information at each time during a search. More specifically, it refers to points that can be checkpoints in searches, such as important points such as intersections on roads, points of departure and destinations, and entrances to highways.

A "link" is information that connects a certain node with a node adjacent to the node. Further, the route search may be performed using the information of the start point and end point of each link without using the node information. In this case, using the same example as above, the link is, for example, road information from an intersection to the next intersection.

"Unprocessed links" are links that have not yet been traversed at the time the search is performed. In the initial state, all links are unprocessed links.

A "processed link" refers to a link that is currently being processed when a search is executed. An unprocessed link becomes a processed link when it is scanned in a search.

A "processed link" refers to a link that has already been processed and has been processed when a search is executed. A processed link becomes a processed link when its scanning is completed in the search.

(structure)
FIG. 1 is a block diagram showing an outline of an information processing system according to this embodiment. An information processing system according to this embodiment will be described with reference to FIG.

The information processing system 1 includes a terminal device 2 and a server 3 . The terminal device 2 and the server 3 are connected via a wired or wireless network 4 .

The terminal device 2 is a device that acquires and outputs route search information searched by the server 3. For example, a device such as a client PC, a mobile phone, a tablet, a smart phone, etc., that outputs search results by display or voice. . Alternatively, the terminal device 2 may be used to input information on the starting point and the destination as search conditions.

The server 3 searches for the optimum route based on the starting point and destination designated by the user or the like, and outputs the search result to the terminal device 2 .

The network 4 is a network that connects the terminal device 2 and the server 3. For example, communication means from the terminal device 2 such as an intranet, the Internet, Wi-Fi (registered trademark), or Bluetooth (registered trademark). The request is transmitted to the server 3, and the output result from the server 3 is transmitted to the terminal device 2 by communication.

The server 3 includes a control section 30 , a storage section 32 and a communication section 34 .

The control unit 30 includes a target link extraction unit 300 , a cost calculation unit 302 and a route acquisition unit 304 , and controls the server 3 . In addition to these, means for performing necessary control for the server 3 to start up or operate may be provided.

The processing target link extraction unit 300 extracts the processing target link in the search. For example, when scanning of a certain link to be processed ends and the node at the end point of the link is reached, the next link to be processed at the node is extracted. At the start of the search, links starting from the starting point are extracted. That is, the processing target link extraction unit 300 operates as processing target link updating means for updating the processing target link after the cost calculation of the processing target link is completed. As another example, processing target link updating means for updating the processing target link may be provided as a separate configuration from the processing target link extraction unit 300 .

When there are a plurality of links to be extracted as process target links, the process target link extraction unit 300 assigns each process target link to one calculation core, and causes each calculation core to execute the calculation of each process target link. In other words, the relationship between the arithmetic core and the link to be processed may be one-to-one. Further, the number of processing target links is not limited to one-to-one, and a predetermined number of processing target links may be calculated by one calculation core. That is, the relationship between the arithmetic cores and the links to be processed may be one-to-many.

The cost calculator 302 calculates the cost of the target link. The costs are stored together with the link information in the route network DB 320, which will be described later. For example, for all links to be processed, the cost is decreased by 1 for each iteration, and when the cost reaches 0, the processing of the link to be processed is terminated, and the state is transferred to the processed link. Update. If there is an unprocessed link at the destination node of the link, the cost calculation is continued with the unprocessed link as a new link to be processed.

Links with a cost of 0 are stored in the device memory of the GPU together with link information that has been passed so far. The location to be stored may be memory outside the GPU instead of the device memory. Further, as information attached to the newly set link to be processed, link information that has been passed so far may be held.

This cost calculation is processed in parallel for each calculation core that executes the calculation for each link to be processed. In parallel processing, for example, by synchronizing the processing cores for each iteration, each processing core holds the progress of the link at the same timing. Doing arithmetic is eliminated. Synchronous processing is not essential, for example, if the processing of the arithmetic cores in a predetermined area in one block (for example, one warp in CUDA (registered trademark) processing) is synchronized, explicit need not be synchronized with

Although the cost calculation unit 302 calculates the cost and updates the link to be processed when the cost becomes 0, the present invention is not limited to this. For example, based on the result calculated by the cost calculation unit 302, the processing target link extraction unit 300, which operates as a processing target link updating unit, updates the processing target link to a processed link, and the end point of the processed link becomes the starting point. , may be updated as a new link to be processed. In this way, cost calculation and processing target link update processing may be performed by separate modules.

The storage unit 32 includes a route network DB 320 and a processing target link storage unit 322, and stores data required when the server 3 performs search processing.

The route network DB 320 functions as route network data storage means for storing route network data necessary for route searches. Further, the elapsed time, the data of the search source link, and the like may be stored as data required during the search. Route network data is, for example, data that associates information on a node that serves as a reference point on a road with information on the cost of moving from that node to an adjacent node. The route is not limited to roads, and may be route information of public transportation. This routing network DB 320 may be atomically accessed.

The cost mentioned above is a value determined based on the distance between nodes. It may be determined according to road conditions that change due to a traffic accident. Parameters other than the distance may change with the time of day, or may change with the season or day of the week. In the case of public transportation, the cost may be determined including the fare. The cost may be unique between nodes, i.e. the same cost for reverse links, or different along the direction of travel between nodes, i.e. for reverse links. You may set so that it may not necessarily be the same cost.

The target link storage unit 322 is a buffer that stores information on target links. The processing target link storage unit 322 may be configured with a ring buffer. When parallel computation is performed by a plurality of computation cores, this ring buffer may be atomically accessed. By doing so, it is possible to prevent the same processing target link from being accessed by a plurality of operation cores.

FIG. 2 is a diagram showing an example of the hardware configuration of the server 3 according to this embodiment. As shown in FIG. 2, the server 3 has a host 36 and devices 38 .

The host 36 is a device that includes a CPU 360 and a host memory 362 and controls the server 3 . For example, host 36 may comprise a computer, workstation, or the like.

CPU 360 is a processor for controlling host 36 and device 38 . Any CPU that is commonly used may be used, and the type, system, number of clocks, etc. are not particularly limited.

The host memory 362 is memory provided in the host 36 to hold data used for running programs or holding data. For example, it is configured with a RAM (Random Access Memory). Any type of RAM may be used.

In addition, the host 36 may be provided with a large number of modules and the like having functions for causing the functions of the host 36 to be exhibited. It also has a network interface and communicates with the terminal device 2 . Furthermore, it may have an input/output interface, for example, to output data to a display or the like and receive input from a user via a keyboard or the like.

The device 38 includes an arithmetic unit 380 and a device memory 382 and performs parallel arithmetic processing based on control signals from the host 36 . Device 38 is configured with a GPU, for example. In FIG. 2, the host 36 and the device 38 are shown as separate configurations, but the present invention is not limited to this, and a configuration in which the device 38 is built in the host 36 is also possible.

The computing unit 380 includes a large number of computing cores 384 . The arithmetic core 384 is a core capable of independently performing an arithmetic operation, and each core can perform an arithmetic operation. Performing calculations independently includes performing the same calculation processing on different data by a predetermined number of calculation cores 384 based on a program recorded in the device memory 382 .

A predetermined number of operation cores 384 may constitute one block. Also, a unit in one arithmetic core 384 is called one thread. That is, it is possible to perform processing of a predetermined number of threads in parallel in one block at the same timing. Furthermore, the same processing may be performed in parallel at the same timing in a plurality of blocks.

The device memory 382 is memory that can be referenced from the arithmetic core 384 . This device memory 382 may further comprise a large-capacity memory that is accessible from all the arithmetic cores 384, and a memory that is fast accessible from the arithmetic cores 384 in units of one block, for example.

The device memory 382 and the host memory 362 are connected via PCIe (PCI (Peripheral Component Interconnect) Express), for example. A program for controlling the arithmetic core 384 may be transferred from the host 36 to the device memory 382 via PCIe, compiled by a compiler or the like provided in the device 38 , and the arithmetic core 384 may be controlled. As another example, a program may be transferred as a binary file to control computing core 384 .

FIG. 3 is a flow chart showing the operation of the information processing system 1 according to this embodiment. The route search operation of the information processing system 1 will be described with reference to FIG.

First, the server 3 acquires information about the starting point and the destination via the communication unit 34, and sets the starting point and the destination as the starting point and the ending point of the route search (step S100).

Next, a link to be processed is extracted from the set departure point (step S102). The processes of steps S100 and S102 can be executed even if, for example, the host 36 of the server 3 extracts the link to be processed and transfers the initial link to be processed to the link storage unit 322 of the device 38. good. As another example, the starting point of the link may be transferred to the device 38 , the target link may be extracted in the device 38 , and stored in the target link storage section 322 . In this way, the target link extraction unit 300 may be provided in at least one of the host 36 and the device 38 and stores the extracted link in the target link storage unit 322 .

Next, the cost calculator 302 decrements the set cost for each of the one or more extracted links to be processed (step S104). The cost of the link to be processed is obtained based on data stored in the route network DB 320 . For example, one cost calculation unit 302 is provided in one calculation core 384, and one thread performs cost calculation for one link to be processed.

For example, when a GPU is used as a device, the arithmetic cores 384 are thousands to tens of thousands of cores. Arithmetic can be performed. As described above, the number of links for which calculations are performed in one thread is not limited to one, and calculations for a plurality of links to be processed may be performed in one thread.

Next, the cost calculator 302 determines whether or not the cost of the link to be processed has become 0 (step S106). Determination of whether or not this cost has become 0 is also executed for each arithmetic core 384, and determination is executed for a plurality of processing target links at the same timing.

In the arithmetic core 384 including the thread whose cost of the link to be processed is 0 (step S106: YES), the cost calculator 302 updates the link to be processed whose cost is 0 as a processed link (step S108). A processed link that has become a processed link is erased from the processed link storage unit 322 . Instead of being erased, the threads may share an index indicating an empty link in the buffer. As described above, this may be performed by the target link extraction unit 300 functioning as the target link update unit instead of the cost calculation unit 302 .

Subsequently, an unprocessed link having the end node of the processed link as the start node is extracted from the route network DB 320 and updated as the process target link (step S110). Information about the newly extracted link to be processed is stored in the link to be processed storage unit 322 . By performing atomic access when storing, it becomes possible to perform exclusive access with other threads, that is, with other arithmetic cores 384, and it is possible to prevent writing to duplicate buffers (addresses). .

When there are a plurality of newly extracted links to be processed, the threads of the computation core 384 that are not performing the computations for the links to be processed may perform the computations for the links to be processed. One of the plurality of new links to be processed may be operated by the computation core 384 that has been performing the computation of the link to be processed that has subsequently become the processed link. As another example, the calculation core 384 that has been performing calculations for the link to be processed that has become a processed link may perform calculations for a plurality of new links to be processed.

The processed link information or the newly extracted link to be processed may store information of the processed link used as a base point for extraction. The stored processed link information may be stored in the storage unit 32 . In this way, by providing the information of the processed link or the new link to be processed with the information of the link that has been traced until reaching the link, what kind of link the link is, that is, what kind of link It stores whether the route has been traced.

Next, synchronization between the arithmetic cores 384 is performed (step S112). Through this synchronization processing, the thread whose cost is determined not to be 0 (step S106: NO) and the thread whose cost is 0 and have updated the link to be processed are synchronized, and the next processing is performed at the same timing. becomes possible.

After synchronization, it is determined whether or not there is a link that reaches the destination (step S114). If there is no link that reaches the destination (step S114: NO), each arithmetic core 384 repeats the processing from step S104 to step S112. In this way, loop processing is executed in each thread with a series of processing starting from the processing that reduces the cost by 1 as one iteration.

On the other hand, if there is a link reaching the destination (step S114: YES), the route acquisition unit 304 acquires information on the link reaching the destination (step S116).

Next, the route acquisition unit 304 can acquire information on links through which the link that reached the destination traveled to reach the destination from the stored route information of the links (step S118). ).

Next, the route acquisition unit 304 outputs the acquired route and terminates the process (step S120). In this way, by executing cost calculations in the plurality of arithmetic cores 384 and updating the links while storing the link information, it is possible to obtain the optimum route taking into consideration the cost.

The processing from step S104 to step S114 is performed at the same timing by a plurality of arithmetic cores 384, that is, by a plurality of threads, as described above. Here, the same timing does not have to be exactly the same time, and a certain amount of time lag may occur. Synchronization processing is executed for multiple threads in one block, but it does not matter whether blocks are synchronized or not.

If the blocks are not synchronized, for example, after the processing from step S104 to step S114 is performed a predetermined number of times, the processing target link Synchronization may be performed as a whole. In this case, the state of the link in the middle of the calculation, that is, the remaining cost at the interruption timing of the link to be processed may be stored in the storage unit 32 .

By storing the remaining costs in this way, it becomes possible to rearrange the threads when the host 36 again controls the arithmetic processing in the device 38 . By rearranging the threads, for example, it is possible to place nearby links to be processed in the same block, and it is possible to perform processing in a state in which nearby links to be processed can be synchronized. becomes.

When outputting a plurality of candidate routes in addition to the optimum route in the search, for the link reaching the destination, the route to the node immediately before the destination may be searched again.

As another example, if the cost of a certain link to be processed is 0 and there is already a processed link whose end point is the end node of that link, the cost difference is calculated, and if it is within a predetermined value, the Information may be stored with links as candidate links. That is, in the processed link, the calculation of the cost for a predetermined number of iterations may be continued, and information on route candidates other than the optimum route may be acquired based on this information.

FIG. 4 is a diagram showing how the information processing system 1 according to this embodiment searches for a route. ○ represents a node, and the alphabet described therein is the identifier of the node. A line segment connecting nodes is a link, and a numerical value written at the end of the link represents the cost. For example, for a route like FIG. 4(a), the A to B link has a cost of two. We show that the B to C link has a cost of 2 and the reverse C to B link has a cost of 3. A case of searching for a route from the starting point A to the destination H on this route will be described. Below, the link from A to B is denoted as AB and so on. In FIG. 4, costs are set for all links other than the link reaching the node H, but the present invention is not limited to this. For example, if the link includes a one-way road, the cost may be infinite (or a very large numerical value) and the link may not be set.

First, information on the departure point A and the destination H is set. From the path network DB 320, links starting from A, AB, AC, and AD are extracted.

The cost calculations for AB, AC, and AD are assigned to separate calculation cores 384, respectively. Each iteration decrements the cost by one. Conceptually, there are virtual vehicles that depart from A to B, C, and D at the same timing, and each iteration is replaced by a process of advancing the link at a cost of 1.

After two iterations, the vehicle traveling on AB reaches B as shown in FIG. 4(b). On the other hand, the vehicle traveling on AC and AD is in a position two links ahead, and has not arrived at C and D yet.

The arithmetic core 384 that has been processing the AB link updates the process target link in B. FIG. The AB link is updated from a processed link to a processed link. On the other hand, unprocessed links BA, BC, and BE are updated as new links to be processed, and subsequent processing is performed in separate arithmetic cores 384 respectively. Also, since only one link reaches B at this timing, AB is stored as the optimum route to B. FIG.

Subsequently, after one iteration, the vehicle following AC reaches C, AC is updated as a processed link, CA, CB, CD, CE, and CF are updated as new links to be processed, and the optimal route to C , AC is stored.

FIG. 4(c) is a diagram showing the state after two more iterations. A link indicated by a dashed line is a link that has reached a node that has already been reached by another link, and indicates a link that, at the time of arrival, is a link to be processed or a link that has already been processed at the destination node. Thin arrows indicate processed links.

A vehicle or the like running on AB reaches C via the BC link and is present at a remaining cost of 1 on the BE link. At node C, there is already a vehicle following the link AC, so the unprocessed link at C no longer exists, and the links following AB and BC are the processed links. After that, the process ends without updating the new link to be processed. A link following BA from B reaches A, but since all the links in A are similarly processed links, the process ends.

A vehicle following the link of AC first reaches C after three iterations from the initial state. After two iterations have passed, the CA and CB links progress to a point where the remaining cost is 1, and the CF link progresses to a point where the remaining cost is 2. Vehicles, etc. that have been proceeding on the link of CE have reached E, and since there is no vehicle, etc. that has reached E at this point, a link following AC and CE is stored as a link to reach E. Then, the CE link is updated as a processed link, and the EB and EH links are updated as new links to be processed.

After arriving at D, the vehicle or the like traveling on the CD link is updated to a processed link at D, and DA, DC, DF, and DG are updated as new links to be processed. Also, as the optimum route to reach D, the route following AC and CD is stored. Since one iteration of computation is performed after the route is updated, the vehicle traveling on each link is located at a distance from D by one cost.

Such processing is repeated until a link reaching the destination H is generated. In the case of a route network as shown in FIG. 4A, by repeating the above processing, a route following the links of AC, CE, and EH is acquired as an optimum route and output.

The output from the device 38 to the host 36 and the output from the server 3 to the terminal device 2 may be link information. It may be converted to the above route information and output. The user can, for example, obtain the optimum route from information on the map output to the display.

In this way, by performing cost processing in parallel and changing links into unprocessed links, processed links, and processed links, sort processing, which is a heavy process that tends to become a bottleneck in computation, can be reduced. can be omitted. In other words, unlike Dijkstra's algorithm, which does not perform parallel processing, the cost of each target link is sorted and the cost is calculated in parallel for each iteration instead of searching for which link to be processed constitutes the optimal route. By decrementing by , it is possible to simulate the position of the car on each route at the same timing, and it is possible to omit the sorting process, which is a relatively heavy process. In the above description, processing is performed by decrementing, but the same effect can be obtained by providing a parameter that is incremented for each iteration and comparing the parameter with the cost of the link. That is, the processing may be performed by decrementing or by incrementing.

Next, memory management will be described. FIG. 5 is a diagram conceptually showing the memory allocation of information on links to be processed in the case of the route in FIG. As described above, in this embodiment, a ring buffer may be used as the target link storage unit 322 .

In the initial state, as shown in FIG. 5A, nothing is recorded in the ring buffer, or any numerical value may be recorded.

When the departure point is determined as A and the initial values of the links to be processed are extracted as AB, AC, and AD, buffers for AB, AC, and AD are allocated as shown in FIG. 5(b). For the purpose of explanation, the links are shown using symbols, but these links may have IDs assigned uniquely, and may be managed using the IDs. This is the same for the route network DB 320 as well. At this time, up to which buffer is used at each timing is also stored. For example, the address of the position of the arrow shown in FIG. 5(b) is shared and stored.

After synchronization after one iteration, the numerical value stored in each buffer is decremented by one as shown in FIG. 5(c). Subtraction processing of each numerical value is executed by the arithmetic core 384 that processes each link.

Further, after synchronization after one iteration, the buffer is used as shown in FIG. 5(d). The buffer following AD stores the values of BA, BC, and BD, and the arrow indicates the address behind the buffer of BD. Note that the links derived from B need not be assigned in the order of BA, BC, and BD as shown in the figure, and may be assigned in the order of the thread with the earliest memory acquisition processing. A memory area may be secured by atomic access, that is, atomic processing so that multiple threads do not obtain duplicate addresses.

After synchronization after the next one iteration, the buffer is used as shown in FIG. 5(e). At this time, the numerical value related to AB remains 0, but is not limited to this, and may be processed to become -1. If a thread is discarded as a processed link, or if it is used as a thread for a new link to be processed after being discarded, the cost of AB remains 0 as shown in FIG. 5(e).

When the last buffer is reached, the AB buffers are reused in order. After the next one iteration, the buffer for BC becomes 0 before the buffer for AD and BA. ensure Incidentally, as described above, the processing may be performed by increment instead of decrement. In the case of increment, for example, the cost may be represented by a negative value, and the link may be processed when the cost is incremented to 0. Alternatively, the parameter may be prepared as described above, and the incremented value and the link cost You may make it compare with a value.

By processing the buffer in this way, it is possible to efficiently reuse the buffer without performing complicated processing such as memory calculation within the thread. Set the capacity of the ring buffer to be larger than the maximum number of links to be processed, that is, to be sufficiently larger than the number of links that have been processed so far minus the number of links that have been processed. Therefore, in the ring buffer, it is possible to allocate the buffer for the next link to be processed without overlapping with the link in use.

In order to store the link to be processed in the ring buffer, the link to be processed may be restricted, that is, branch pruning may be performed.

As a first example of pruning, a restriction may be added to update the link on the opposite side of the destination as the link to be processed. For example, after obtaining the direction and distance from the starting point to the destination, for a link that goes in the opposite direction from the starting point to the destination, 1 of the distance from the starting point to the destination If the distance is /10 or more, it may not be extracted as a link to be processed. As an example, when obtaining a route from Osaka to Tokyo, a link exceeding 60 km in the opposite direction from Osaka to Tokyo is not obtained as a link to be processed.

A predetermined distance, for example, 20 km, may be used instead of the ratio. In this case, a link exceeding 20 km in the opposite direction from Osaka to Tokyo is not treated as a link to be processed.

This pruning may not be done based on the distance between the origin and destination. For example, when the distance between the starting point and the destination is 10 km, even if the vehicle travels 1 km in the opposite direction, it may arrive early. In such a case, if the target link is not restricted, for example, if the distance between the departure point and the destination is about 20 km, it may be set so that branch pruning is not performed based on the distance. Alternatively, branches may be pruned up to a predetermined distance when the fixed distance is exceeded, but when the predetermined distance is exceeded, branch pruning may be performed based on the ratio.

As a second example of pruning, links are classified based on road width, and roads that do not have, for example, one lane on each side other than the vicinity of the departure point and destination (hereinafter referred to as unguaranteed roads) may be set as the link to be processed so as to exclude the . An unguaranteed road is not limited to a road that does not have one lane on each side. For example, a road passing through a residential area, or a road with a width of 5 m or less, or another index may be used. By setting unguaranteed roads in this way, links are extracted so as to exclude unguaranteed roads from the links to be processed in the vicinity of the departure point and the destination, for example, outside the range of 1 km from the departure point and the destination. may be performed.

As a third example of pruning, an area in which links exist may be divided into, for example, an urban area and a suburban area, and links may be diffused using different indexes for the urban area and the suburban area. For example, in urban areas, non-guaranteed roads are extracted as links to be processed, but in suburban areas, non-guaranteed roads may not be extracted as links to be processed.

As a fourth example of pruning, when the number of buffers currently used as the storage area for the link to be processed exceeds a predetermined number, restrictions such as those in the first to third examples are added. good too.

As described above, in addition to securing a sufficiently large capacity of the ring buffer, it is also possible to limit the links extracted as the links to be processed.

However, without using a ring buffer, the memory usage status in the memory can be checked by, for example, substituting a numerical value (eg, 2147483647) that is not used as a cost in the memory related to the link that has become a processed link. The storage unit 32 may be provided with a table for managing that the target link is stored in an open address by referring to the table.

As described above, the information processing system 1 according to the present embodiment performs parallel computation in an accelerator equipped with a multi-core processor, for example, a GPU using a GPGPU. can be greatly reduced. As in this embodiment, by enabling parallel computation by using a multi-core processor, it becomes possible to lighten the processing in the server and handle processing from a plurality of users at high speed.

In the above-described embodiment, the link to be processed is extracted each time the cost becomes 0, but the present invention is not limited to this. For example, arithmetic processing may be performed until the cost of the current link to be processed becomes 0, and the next link to be processed may be extracted collectively. At this time, based on the information of the link to be processed that is updated as the processed link, the optimal route to the new link to be processed may be stored, and the optimal route to the destination may be acquired. When processing is performed by link instead of cost in this way, it is possible to manage threads for each spread of links, so link management is changed to a simpler one compared to the above-described embodiment. becomes possible.

At least part of the information processing system described in the above embodiments may be configured with hardware or software. When configured with software, a program that implements at least part of the functions of the information processing system may be stored in a recording medium such as a flexible disk or CD-ROM, and read and executed by a computer. The recording medium is not limited to a detachable one such as a magnetic disk or an optical disk, and may be a fixed recording medium such as a hard disk device or a memory.

Also, a program that implements at least part of the functions of the information processing system may be distributed via a communication line (including wireless communication) such as the Internet. Furthermore, the program may be encrypted, modulated, or compressed, and distributed via a wired line such as the Internet or a wireless line, or stored in a recording medium and distributed.

Furthermore, the information processing system may be operated by one or more information processing devices. When a plurality of information processing apparatuses are used, one of the information processing apparatuses may be a computer, and the computer may implement a function as at least one means of the information processing system by executing a predetermined program.

Additions, effects, and various modifications of the present invention may be conceived by those skilled in the art based on the above description, but aspects of the present invention are not limited to the individual embodiments described above. . Various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present invention derived from the content defined in the claims and equivalents thereof.

For example, in the above description, the range of route search is defined as the starting point and the destination, but the range is not limited to this. For example, a route search for the first point and the second point existing between the departure point and the destination may be obtained as in the above embodiment. Specifically, a route search from an arbitrary first point to a second point may be obtained as in the above-described embodiment, without being limited to the starting point and the destination. By doing so, it is also possible to perform a detailed route search section by section. That is, in the above description, it is also possible to replace the starting point with an arbitrary first point and the destination with an arbitrary second point.

Furthermore, in the above description, the GPU on the server side performs the route search, but the present invention is not limited to this. That is, a GPU may be installed in the terminal device 2, and the route search may be performed using the GPU of the terminal device 2. FIG. In such a configuration, the server 3 and the network 4 are not essential components at the timing of performing the route search, but the components of the server 3 shown in FIG. It may be a configuration provided.

1 information processing system 2 terminal device 3 server 30 control unit 300 processing target link extraction unit 302 cost calculation unit 304 route acquisition unit 32 storage unit 320 route network DB
322 target link storage unit 34 communication unit 36 host 360 CPU
362 host memory 38 device 380 arithmetic unit 382 device memory 384 arithmetic core

Claims (8)

A GPU (Graphical Processing Unit) comprising a built-in device memory and a plurality of arithmetic cores that execute a plurality of arithmetic processes in parallel;
route network data storage means for storing route network data;
a processing target link storage means for storing a processing target link which is a link to be processed;
processing target link extracting means for extracting one or more processing target links at a first point based on the route network data;
cost calculation means for calculating costs in parallel for one or more of the links to be processed;
Processing target link updating means for updating the processing target link for which the cost calculation has been completed as a processing link, and newly setting one or a plurality of unprocessed links connected to the processing link as the processing target link. When,
route acquisition means for acquiring a route from the first point to the second point based on the cost calculated for each of the processed links;
with
comprising at least the route network data storage means and the cost calculation means on the GPU ;
The links comprise directional information, and the links connecting the same two points can have different costs in both directions.
Information processing system. 2. The information processing system according to claim 1, wherein each of said calculation cores calculates a cost for one of said links to be processed. The process target link extracting means extracts a range within a predetermined distance from at least one of the first point and the second point based on the route network data, and extracts the process target within the predetermined distance range. 3. The information processing system according to claim 1, wherein the extraction granularity of links is higher than the extraction granularity of the links to be processed outside the range of the predetermined distance. The GPU is
comprising the route network data storage means and the processing target link storage means on the device memory;
The processing target link extraction means, the cost calculation means, and the processing target link update means are provided on the computing core,
The information processing system according to any one of claims 1 to 3. A computer comprising a GPU, comprising a built-in device memory and a plurality of arithmetic cores that execute a plurality of arithmetic processes in parallel,
path network data storage means for storing path network data;
processing target link storage means for storing a processing target link which is a link to be processed;
Processing target link extraction means for extracting one or more processing target links at a first point based on the route network data;
cost calculation means for calculating costs in parallel for one or more of the links to be processed;
processing target link updating means for updating the processing target link for which cost calculation has been completed as a processing link, and newly setting one or a plurality of unprocessed links connected to the processing link as the processing target link;
route acquisition means for acquiring a route from the first point to the second point based on the cost calculated for each of the processed links;
function as
The links comprise directional information, and the links connecting the same two points can have different costs in both directions.
Information processing program. By a plurality of information processing devices communicatively connected, at least one of which includes a GPU,
path network data storage means for storing path network data;
processing target link storage means for storing a processing target link which is a link to be processed;
Processing target link extraction means for extracting one or more processing target links at a first point based on the route network data;
cost calculation means for calculating costs in parallel for one or more of the links to be processed;
processing target link updating means for updating the processing target link for which cost calculation has been completed as a processing link, and newly setting one or a plurality of unprocessed links connected to the processing link as the processing target link;
route acquisition means for acquiring a route from the first point to the second point based on the cost calculated for each of the processed links;
wherein the links comprise direction information, and the links connecting the same two points can have different costs in both directions.
An information processing apparatus comprising at least one of the means described above to constitute an information processing system. a computer with a GPU,
path network data storage means for storing path network data;
processing target link storage means for storing a processing target link which is a link to be processed;
Processing target link extraction means for extracting one or more processing target links at a first point based on the route network data;
cost calculation means for calculating costs in parallel for one or more of the links to be processed;
processing target link updating means for updating the processing target link for which cost calculation has been completed as a processing link, and newly setting one or a plurality of unprocessed links connected to the processing link as the processing target link;
route acquisition means for acquiring a route from the first point to the second point based on the cost calculated for each of the processed links;
wherein the links comprise directional information, and the links connecting the same two points can have different costs in both directions,
Information processing program . In an information processing device equipped with a GPU,
the path network data storage means storing the path network data;
a step of storing, in the processing target link storage means, a processing target link which is a link to be processed;
a step of extracting one or a plurality of links to be processed at a first point based on the route network data by the target link extracting means;
a step in which the cost computing means computes the respective costs in parallel for one or more of the links to be processed;
A step of updating the link to be processed, for which cost calculation has been completed, as a processed link, and newly setting one or a plurality of unprocessed links connected to the processed link as the link to be processed. ,
obtaining a route from the first point to the second point based on the cost calculated for each of the processed links;
with
The links comprise directional information, and the links connecting the same two points can have different costs in both directions.
Information processing methods.

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