JP7197969B2 - Inverter device - Google Patents

Description

An embodiment of the present invention relates to an inverter device including a bootstrap capacitor for generating power for driving upper switching elements that form an inverter circuit.

Conventionally, for example, Patent Documents 1 and 2 disclose a configuration in which a power source for driving an upper switching element that constitutes an inverter circuit is generated by controlling charging of a bootstrap capacitor. In such a configuration, it is necessary to start switching control, for example PWM control, in the inverter circuit after completing the initial charging of the bootstrap capacitor. Depending on the specifications of the control circuit that performs switching control, the PWM control may become unstable during the initial period after the start of operation. As a result, if the bootstrap capacitor is not sufficiently charged initially, the driving voltage for the switching element will be insufficient. As a result, the switching element on the upper arm side may be on-latched, causing a short-circuit current to flow between the upper and lower arms, or the element to generate heat.

Japanese Patent No. 3661395 JP-A-5-292755

However, neither of the configurations disclosed in Patent Literatures 1 and 2 mentions anything about how to deal with the case where PWM control becomes unstable during the initial period after the start of operation.
Therefore, an inverter device is provided that can reliably prevent short-circuit currents and malfunctions due to heat generation even when using a control circuit in which PWM control becomes unstable during the initial operation period.

According to the inverter device of the embodiment, an inverter circuit having a plurality of phases of switching legs formed by connecting an upper switching element and a lower switching element in series;
a bootstrap capacitor for generating a power supply for driving the upper switching element;
PWM-controls a plurality of switching elements constituting the inverter circuit, has a timer for generating a carrier wave used for the PWM control, and generates a PWM signal by comparing the count value of the timer with a set comparison value. and a control circuit having a signal generator for
After setting the comparison value and starting the counting operation of the timer, the control circuit disables at least the signal output from the signal generator to the upper switching element until a predetermined disablement time elapses. At the same time, the upper switching element is kept off.
Two signal generators, one for the upper switching element and the other for the lower switching element, are provided. is set to an inactive level, and the output terminal of the lower switching element signal generator is set to an active level.
Further, two signal generation units, one for the upper switching element and the other for the lower switching element, are provided. is set to an inactive level, and the output terminal of the lower switching element signal generator is maintained at an active level, or the active level and the inactive level are alternately repeated.
Further, when the control circuit sets the comparison value and causes the timer to start counting, it sets a counter value in a standby counter for setting the invalidation time.

1 is a circuit diagram showing an electrical configuration of a washing machine according to a first embodiment; FIG. Timing chart showing a period immediately after starting the counting operation of timers RD0 and RD1 Timing chart showing operation over a longer period than FIG. Flowchart showing details of processing by the control unit Partial longitudinal side view schematically showing the configuration of the washing machine Flowchart showing the contents of processing by the control unit, which is the second embodiment Flowchart showing contents of processing by the control unit according to the third embodiment

(First embodiment)
A first embodiment applied to a washing machine, which is a laundry machine, will be described below with reference to FIGS. 1 to 5. FIG. As shown in FIG. 5, the washing machine 10 has a bottomed cylindrical water tank 12 with an open upper surface, which is elastically supported by an elastic suspension mechanism 13 inside an outer casing 11 forming the outer shell of the washing machine 10 . Inside the water tank 12, a cylindrical rotating tank 14 with an open top is rotatably provided. A reinforcing member 15 for reinforcing the bottom of the rotating tub 14 is provided at the bottom of the rotating tub 14 . The rotating tub 14 is configured to rotate about a vertical axis, and serves as a washing tub in the washing process of washing the laundry and a rinsing process of rinsing the laundry, and a dehydrating tub in the dehydrating process of dehydrating the laundry. Also used. In other words, the washing machine 10 is a so-called vertical shaft washing machine in which the central axis of rotation of the rotary tub 14 extends in the vertical direction.

This rotary tub 14 has a large number of holes 16 in its peripheral wall. These holes 16 are penetrating and allow water and ventilation. 5 shows only some of the many holes 16. As shown in FIG. A balance ring 17 made of synthetic resin and filled with a liquid such as salt water is attached to the top of the rotating tub 14 . A pulsator 18 made of synthetic resin, for example, is rotatably provided as an agitator at the bottom of the rotating tub 14 .

A drainage path 19 is provided at the bottom of the water tank 12 . A drain valve 20 is provided in the drain path 19, and when the drain valve 20 is opened, the water in the water tank 12 is drained out of the machine. An air trap 21 for water level detection is provided at the bottom of the water tank 12 .

A drive mechanism section 23 is provided in the central portion of the lower portion of the water tank 12 . The drive mechanism section 23 includes a motor 24, a clutch mechanism section (not shown), and the like. The drive mechanism portion 23 transmits the rotational force to the pulsator 18 by means of the clutch mechanism portion during the washing process or the rinsing process. Therefore, during the washing process or the rinsing process, the rotating tub 14 is not rotationally driven, and only the pulsator 18 is rotationally driven. Further, during the dehydration process, the drive mechanism section 23 transmits the rotational force of the motor 24 to the pulsator 18 and the rotary tub 14 through the clutch mechanism section. Therefore, the pulsator 18 is driven to rotate integrally with the rotating tub 14 during the dewatering process.

A top cover 26 is provided on the upper portion of the outer casing 11 . The top cover 26 is provided with, for example, a double-fold lid 27 that opens and closes the entrance for laundry. A tank cover (not shown) is attached to the top of the water tank 12 so as to be openable and closable. An operation panel 28 is provided on the front portion of the top cover 26 . A control unit 29 that controls the overall operation of the washing machine 10 is arranged on the back side of the operation panel 28 .

A water supply mechanism 30 for supplying water from a water source into the water tank 12 is provided in the rear portion of the top cover 26 . The water supply mechanism 30 includes a water supply valve (not shown) and a water supply path (not shown) communicating with the water tank 12. The control unit 29 controls the opening and closing of the water supply valve, thereby controlling the water supply to the water tank 12. be.

Next, the electrical configuration of the control system of washing machine 10 will be described. As shown in FIG. 1, the control unit 29 comprises an inverter circuit 50 which is a PWM controlled inverter. The inverter circuit 50 is configured by connecting six IGBTs 51 in a three-phase bridge connection, and a flywheel diode 52 is connected between the collector and emitter of each IGBT 51 . The IGBT 51 corresponds to a switching element. Each phase output terminal of the inverter circuit 50 is connected to each motor winding 24 a of the motor 24 . In this embodiment, the motor 24 is, for example, an outer rotor type three-phase brushless DC motor.

A shunt resistor 53, which is a current detection resistor, is connected in series between the emitter of the IGBT 51 on the lower arm side and the ground. A common connection point between the emitter of the IGBT 51 on the lower arm side and the shunt resistor 53 is connected to an overcurrent detection circuit 54 and a level shift circuit 64 composed of a resistance voltage dividing circuit. The same motor phase current as the motor winding 24a flows through the shunt resistor 53 at the timing when the IGBT 51 on the lower arm side is ON. Therefore, the terminal voltage indicates a level according to the motor phase current. A switching leg corresponding to each phase is configured by connecting the IGBTs 51 of the upper arm and the lower arm in series.

The overcurrent detection circuit 54 detects overcurrent that occurs when the upper and lower arms of the inverter circuit 50 are short-circuited, and has three comparators (not shown) for detecting three phases. In one or more of these three comparators, the output level changes when the input voltage exceeds a preset threshold value. Then, the control circuit 55 that has received the change in the comparator output immediately turns off the output of the PWM signal. This prevents breakage of circuit elements.

The shunt resistor 53 generates positive and negative terminal voltages with respect to the ground potential when the inverter circuit 50 operates. Therefore, the level shift circuit 64 shifts the terminal voltage of the shunt resistor 53, that is, the voltage at the common connection point between the emitter of the IGBT 51 and the shunt resistor 53, into the input range of an A/D converter (not shown) incorporated in the control circuit 55. Level shift accordingly. The power supply voltage of the level shift circuit 64 is generated from a 5V power supply by, for example, a three-terminal regulator (not shown), and is 3.3V in this embodiment.

The level shift circuit 64 has three resistors 65a to 67a connected to the power supply voltage and three resistors 65b to 67b connected in series between the resistors 65a to 67a and the shunt resistor 53. The terminal voltages of the shunt resistors 53 are divided by resistors and input to the control circuit 55 .

The motor 24 is provided with a rotational position sensor 56 composed of, for example, a Hall IC for detecting the position of the rotor. The control circuit 55 generates a PWM signal by feedback control, for example vector control, based on the current value flowing through each motor winding 24 a of the motor 24 , and supplies it to the inverter circuit 50 to control the motor 24 . The control circuit 55 is composed of a microcomputer containing an A/D converter and the like as described above.

A drive power supply circuit 57 is connected to the input side of the inverter circuit 50 . The driving power supply circuit 57 includes a full-wave rectifier circuit 58 composed of a diode bridge, whose input terminal is connected to the 100 V AC power supply 61, and capacitors 59a and 59b connected between the output terminals of the full-wave rectifier circuit 58 in series. circuit. A common connection point of the capacitors 59 a and 59 b is connected to one of the input terminals of the full-wave rectifier circuit 58 . The drive power supply circuit 57 supplies the inverter circuit 50 with a DC voltage of about 280 V generated by voltage doubler full-wave rectification.

A power supply circuit 62 is provided on the output side of the full-wave rectifier circuit 58 to generate two types of power supply voltages, for example, 5V and 16V, for use in the control unit 29 by chopping. The 5V power supply voltage generated by the power supply circuit 62 is also used as the power supply voltage for the operation of the control circuit 55 and the power supply for the inverting buffer for inputting the sensor signal of the rotational position sensor 56 to the control circuit 55 . When a user operates a power-on switch (not shown), the driving power supply circuit 57 outputs a voltage to generate 16V and 5V power, and the control circuit 55 starts operating. Also, the 16V power supply is used for the gate drive voltage of the IGBT 51 as will be described later.

The control circuit 55 corresponds to the three-phase inverter circuit 50, and has an input terminal for detecting the U-phase motor phase current: U-phase current A/D, and an input terminal for detecting the V-phase motor phase current: V-phase current. Input terminals for detecting A/D and W-phase motor phase currents: W-phase current A/D.

Control circuit 55 generates a PWM command for driving motor 24 . Further, the control circuit 55 selects at least two phases near the middle of the timing at which the IGBT 51 on the lower arm side turns on, for example, a phase with a long ON time of the lower arm, for each carrier wave cycle of the PWM signal, and selects the terminal voltages of these phases. is A/D converted to obtain the motor phase current. The control circuit 55 acquires the position of the rotor based on the output of the rotational position sensor 56 accompanying the rotation of the motor 24, adjusts the PWM signal, and adjusts the d-axis current and the q-axis current of the motor 24 to appropriate values. A vector control calculation is performed to drive and control the motor 24 .

The control circuit 55 has two timers RD0 and RD1 to generate the PWM signal. The timer RD0 generates and outputs a PWM signal for driving the upper IGBT 51, and corresponds to an upper switching element signal generator. The timer RD1 generates and outputs a PWM signal for driving the lower IGBT 51, and corresponds to a lower switching element signal generator. The output terminals of the timers RD0 and RD1 can be switched to high level, low level, and high impedance (Hi-z) from the outside. Details of these operations will be described later.

The output terminals of the timers RD0 and RD1 are connected to the input terminal of the driving circuit 86. FIG. The input terminal is pulled down by a resistor 85 . The PWM signals generated by the timers RD0 and RD1 are input to the gates of the IGBTs 51 via the driving circuit 86 and the high voltage driver 87 on the upper arm side. A bootstrap capacitor 88 is connected between the emitter of each IGBT 51 and the high voltage driver 87 . The control circuit 55 charges these bootstrap capacitors 88 to generate a power supply voltage for the high voltage driver 87 to drive the gate of the upper IGBT 51 .

Next, the operation of this embodiment will be described with reference to FIGS. 2 to 4. FIG. As shown in FIG. 2, the timers RD0 and RD1 provided in the control circuit 55 synchronize with each other and generate carrier waves with a period of 64 μs, for example, used for PWM control. However, the timer value of timer RD1 is set to be higher than the value of timer RD0 by a predetermined value. Due to the difference of the predetermined value, a dead time of 0.7 μs is caused in switching between the upper IGBT 51 and the lower IGBT 51 . Timers RD0 and RD1 have buffers for setting values that are compared with the carrier timer value to determine the PWM duty. The value set in the buffer is hereinafter referred to as a "compare value".

Here, as a characteristic of the microcomputer, the operation of the control circuit 55 becomes unstable immediately after starting the operation of the timers RD0 and RD1, and the result of comparison with the compare value set in the buffer may not be output correctly. . The portion where the output levels of the timers RD1 and RD0 momentarily change to low and high levels after "compare value update=0" shown in FIG. 2 is due to unstable operation. Therefore, in this embodiment, as shown in FIG. 3, a predetermined period of time, for example, 256 μs after the start of operation of the timers RD0 and RD1 is set as an initial inhibition period to inhibit the output of the PWM signal. The initial inhibition period corresponds to the invalidation time.

FIG. 4 is a flow chart showing a portion of the process executed by the control circuit 55 relating to the gist of the present embodiment. Assume that the execution cycle of this flow is, for example, 128 μs. If the washing operation is not started, that is, if it is not necessary to drive the motor 24 and it is in a state before PWM control is started (S1; NO), a terminal for outputting a PWM signal to six IGBTs 51 from timers RD0 and RD1. is set to an input state, that is, to a high impedance, Hi-z state (S7). In this case, since the input terminal of the driving circuit 86 is pulled down, the input becomes low level. Then, both the timers RD0 and RD1 are set to reset state or stopped state (S8).

Even if the PWM control is started (S1; YES), if the timers RD0 and RD1 are not in operation (S2; NO), the same processing as in step S7 is performed (S3) and "1" is set as the compare value (S4). ). The compare value set here is arbitrary as long as it is not a value corresponding to PWM duty 100% or 0%. The compare value is set via a double buffer, and the compare value set by the control circuit 55 is transferred to the buffer for comparison at the timing when the carrier wave peaks, as shown in FIG. be. Then, the timers RD0 and RD1 are started to count (S5), and the counter value "2" is set to the standby counter for setting the initial inhibition period (S6).

In the next execution, it is determined whether or not "YES" is determined in step S2 and the value of the standby counter is not "0" (S9). If the counter value is not "0" (YES), the value of the standby counter is decremented (S10), and it is determined whether the counter value is "0" (S11). If the counter value is not "0" (NO), "0" is set as the compare value (S12), and the terminals for outputting PWM signals to the respective IGBTs 51 from the timers RD0 and RD1 are switched to the output state (S13). . Further, a value equivalent to 10 ms is set in a 10 ms counter for setting the charging time of the bootstrap capacitor 88 (S14).

A compare value=“0” corresponds to a PWM duty of 100%. Therefore, the upper IGBT 51 continues to be ON over the PWM period, and the lower IGBT 51 is in a state of continuing to be OFF due to the inversion. As a result, initial charging of the bootstrap capacitor 88 is started via the upper IGBT 51 . The high level given to the gate signal is the active level for turning on the IGBT 51, and the low level is the non-active level.

Furthermore, in the next execution, the value of the standby counter becomes "0" (S9; NO), and 256 μs have passed since the timing operation of the timers RD0 and RD1 started, and the initial inhibition period ends. As shown in FIG. 2, even if the control circuit 55 sets the compare values "1" and "0" within the initial inhibition period, the operation of the timers RD0 and RD1 is unstable. is not generated, the output of the PWM signal based on the timers RD0 and RD1 is prohibited, that is, invalidated, during the above period.

If "NO" is determined in step S9, it is determined whether or not the value of the 10 ms counter is "0" (S15). If the counter value is not "0" (YES), the value of the 10 ms counter is subtracted (S16). When 10 milliseconds have passed since the start of the initial charging (S15; NO), the initial charging of the bootstrap capacitor 88 is completed and normal PWM control is started. set (S17).

As described above, according to the present embodiment, in the configuration including the bootstrap capacitor 88 for generating the power supply for driving the upper IGBT 51 constituting the inverter circuit 50, the control circuit 55 including the timers RD0 and RD1 is used to PWM signals whose phases are opposite to each other are generated and output on the upper and lower sides. When the control circuit 55 sets the compare values in the timers RD0 and RD1 and starts the count operation, it sets the output terminals of the timers RD0 and RD1 to high impedance until the initial inhibition period elapses, and outputs a signal to the IGBT 51. is disabled and at least the upper IGBT 51 is maintained in the off state.

With this configuration, it is possible to reliably prevent the flow of a short-circuit current even when the control circuit 55 whose operation becomes unstable immediately after starting the counting operation of the timers RD0 and RD1 is used. Further, since the upper IGBT 51 is not driven with insufficient gate voltage, it is possible to prevent malfunction due to heat generation.

When the initial inhibition period elapses, the control circuit 55 sets the compare value to "0" to enable signal output by the timers RD0 and RD1, and sets the duty ratio to 0%. The output terminal of timer RD0 is set to low level, and the output terminal of timer RD1 is set to high level. As a result, the bootstrap capacitor 88 is reliably initially charged, and the gate voltage of the upper IGBT 51 can be secured at a sufficient level before the actual PWM control is started.

(Second embodiment)
FIG. 6 shows the second embodiment. Hereinafter, the same reference numerals are given to the same parts as in the first embodiment, and the explanation is omitted, and the different parts will be explained. In the second embodiment, in step S21 replacing steps S3 and S7, the PWM signal output terminal corresponding to the upper IGBT 51 is fixed at low level, and the PWM signal output terminal corresponding to the lower IGBT 51 is fixed at high level. . As a result, the signal output state is the same as when the duty ratio is set to 0% in the first embodiment, so that the same effects as in the first embodiment can be obtained.

(Third embodiment)
In the third embodiment shown in FIG. 7, steps S21 and S4 of the second embodiment are replaced with steps S22 and S23. Also, steps S12 and S13 are deleted. In step S22, the compare value is set to, for example, 1/10 of the maximum value of timer RD0. Then, the output terminal of timer RD0 is set to a high impedance state to enable the output terminal of timer RD0 (S23).

Here, 1/10 of the maximum value of timer RD0 corresponds to a duty ratio of 10%. Therefore, the output terminal of the timer RD0 is at high impedance during the initial inhibition period, and the output terminal of the timer RD0 is repeatedly turned on and off at a duty ratio of 10%. As for the initial inhibition period, at least the upper IGBT 51 should be kept in the OFF state, and the switching state of the lower IGBT 51 does not matter. Therefore, this operation charges the bootstrap capacitor 88 even during the initial inhibition period.

When the initial inhibition period elapses, the operating state of the lower IGBT 51 continues and shifts to the charging period. When 10 milliseconds have passed since the start of the initial charging (S15; NO), the timers RD0 and RD1 switch the terminals for outputting the PWM signals to the six IGBTs 51 to the output state (S24; NO), as in step S13. ), the process proceeds to step S17. Even when configured in this manner, the same effect as in the first embodiment can be obtained.

(Other embodiments)
The control circuit may be configured to use one timer to generate PWM signals whose phases are opposite to each other on the upper and lower sides.
The present invention is not limited to sine wave drive, and may be applied to a 120-degree energization method.
Each power supply voltage and the like may be changed according to individual designs. The same applies to the frequency, cycle, and specific numerical values of each period.
The switching element is not limited to the IGBT 51, and may be a MOSFET, a power transistor, or the like.
It may be applied to laundry equipment such as a drum-type washing machine, a washing/drying machine, and a drying machine. In addition, the present invention is not limited to laundry equipment, and may be applied to inverter devices used in other products.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

In the drawing, 10 is a washing machine, 50 is an inverter circuit, 51 is an IGBT, 55 is a control circuit, and RD0 and RD1 are timers.

Claims (3)

an inverter circuit having a plurality of phases of switching legs formed by connecting an upper switching element and a lower switching element in series;
a bootstrap capacitor for generating a power supply for driving the upper switching element;
PWM-controls a plurality of switching elements constituting the inverter circuit, has a timer for generating a carrier wave used for the PWM control, and generates a PWM signal by comparing the count value of the timer with a set comparison value. and a control circuit having a signal generator for
After setting the comparison value and starting the counting operation of the timer, the control circuit disables at least the signal output from the signal generator to the upper switching element until a predetermined disablement time elapses. and maintaining the upper switching element in an off state,
Two signal generation units, one for the upper switching element and one for the lower switching element,
When the invalidation time elapses, the output terminal of the upper switching element signal generation section is set to an inactive level and the output terminal of the lower switching element signal generation section is set to an active level until a predetermined charging time elapses. Inverter device to level. an inverter circuit having a plurality of phases of switching legs formed by connecting an upper switching element and a lower switching element in series;
a bootstrap capacitor for generating a power supply for driving the upper switching element;
PWM-controls a plurality of switching elements constituting the inverter circuit, has a timer for generating a carrier wave used for the PWM control, and generates a PWM signal by comparing the count value of the timer with a set comparison value. and a control circuit having a signal generator for
After setting the comparison value and starting the counting operation of the timer, the control circuit disables at least the signal output from the signal generator to the upper switching element until a predetermined disablement time elapses. and maintaining the upper switching element in an off state,
Two signal generation units, one for the upper switching element and one for the lower switching element,
When the invalidation time elapses, the output terminal of the upper switching element signal generation section is set to an inactive level and the output terminal of the lower switching element signal generation section is set to an active level until a predetermined charging time elapses. An inverter device that maintains a level or alternates between an active level and an inactive level. 3. The inverter device according to claim 1, wherein the control circuit keeps the output terminal of the signal generator in a high impedance state until the invalidation time elapses.

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