JP7196699B2 - voltage converter - Google Patents

Description

The present invention relates to a voltage conversion device having a plurality of drive phases connected in parallel to an input side and an output side.

Conventionally, this type of voltage conversion device includes a voltage conversion section having a plurality of drive phases (boost chopper circuits) connected in parallel to a power source (input side) and a smoothing capacitor (output side); and a control unit that controls the operation of the conversion unit (see, for example, Patent Document 1). In this device, the control unit generates a plurality of drive signals (pulse signals) having the same carrier frequency and a uniform phase difference, and supplies the generated drive signals to the corresponding drive phases, thereby controlling the voltage conversion unit. controlling the action. Accordingly, it is possible to reduce the variation width (ripple current) of the current flowing through the reactor and suppress the heat generation of the smoothing capacitor. Further, when switching of the carrier frequency is requested, the voltage conversion device inserts one cycle of the adjustment signal between the signal of the carrier frequency before switching and the signal of the carrier frequency after switching in the plurality of drive signals. By doing so, the carrier frequency is switched.

JP 2017-108517 A

However, in the voltage conversion device described above, if the phase difference between the drive signals generated in each of the plurality of drive phases deviates from the proper value, there is no means for determining whether the phase difference is proper. It is difficult to confirm whether the operation of the unit is performed properly.

A voltage conversion device according to the present invention generates PWM timers having the same period and a predetermined phase difference, generates a drive signal based on the timer value of the generated PWM timer, and controls the corresponding drive phase, A main object of the present invention is to make it possible to determine whether or not the phase difference of the PWM timer is appropriate by simple processing.

The voltage conversion device of the present invention employs the following means in order to achieve the above main object.

The voltage conversion device of the present invention is
a voltage conversion unit having a plurality of drive phases connected in parallel with respect to the input side and the output side;
Using the same timer clock, start measuring a plurality of PWM timers so as to have the same period and a predetermined phase difference, generate a drive signal based on the timer value of each PWM timer, and output it to the corresponding drive phase a control unit that
A voltage conversion device comprising:
The control unit sets the current timer values of the PWM timer in the two drive phases to be compared among the plurality of drive phases as the reference phase with one of the two drive phases as a reference phase and the other as a comparison phase. , the comparison phase, and the reference phase in this order, and from the obtained timer value of the PWM timer, set a possible range of the phase difference of the PWM timer in the two driving phases as a phase difference range, and set the phase difference Determining whether the phase difference between the PWM timers in the two driving phases is normal based on whether the predetermined phase difference is included in the range;
This is the gist of it.

In the voltage conversion device of the present invention, the same timer clock is used to start measurement of a plurality of PWM timers so as to have the same period and a predetermined phase difference, and the driving signal is generated based on the timer value of each PWM timer. A controller is provided for generating and outputting to the corresponding drive phase. This control unit acquires the current timer values of the PWM timers in the two drive phases to be compared among the plurality of drive phases in the order of the reference phase, the comparison phase, and the reference phase. Set the possible phase difference range of the PWM timer phase difference between the two drive phases, and determine whether the above-mentioned predetermined phase difference is included in the set phase difference range. Determine whether it is normal or not. As a result, it is possible to determine whether or not the phase difference between the PWM timers of the driving phases is appropriate by a simple process without using a dedicated circuit.

1 is a configuration diagram showing an outline of the configuration of a voltage conversion device 20 as one embodiment of the present invention; FIG. 4 is a configuration diagram showing an outline of the configuration of a control unit 40; FIG. FIG. 4 is an explanatory diagram showing how a drive signal is generated using a PWM timer; 4 is a flow chart showing an example of a control routine executed by a CPU 41 of a control unit 40; FIG. 4 is an explanatory diagram showing how each phase PWM timer measures; 9 is a flowchart showing an example of phase difference deviation determination processing; FIG. 4 is an explanatory diagram showing a reference phase PWM timer and a comparison phase PWM timer; FIG. 10 is an explanatory diagram showing variations in acquisition timing of a timer value of a reference phase PWM timer and a timer value of a comparison phase PWM timer; FIG. 10 is an explanatory diagram showing how determination of no phase difference deviation and determination of presence of phase difference deviation are performed; FIG. 5 is an explanatory diagram showing how phase difference correction is performed; FIG. 4 is an explanatory diagram showing acquisition timings of a timer value of a reference phase PWM timer and a timer value of a comparison phase PWM timer;

Next, a mode for carrying out the present invention will be described using examples.

FIG. 1 is a configuration diagram showing an outline of the configuration of a voltage conversion device 20 as one embodiment of the present invention. As illustrated, the voltage converter 20 of the embodiment is connected to a low-voltage power line 14 connected to a DC power supply 12 and a high-voltage power line 18 connected to a smoothing capacitor 16, and converts the low-voltage power A boost converter 30 that boosts the voltage of the line 14 and supplies it to the high-voltage power line 18 , and a controller 40 that controls the boost converter 30 . For example, in an electric vehicle having a motor for running, the voltage conversion device 20 can be configured to boost the voltage of a fuel cell or a secondary battery and supply it to an inverter that drives the motor.

As shown in FIG. 1, the boost converter 30 has a plurality of (four in the figure) boost phases 31a to 31d connected in parallel to the low-voltage power line 14 and the high-voltage diameter power line 18. is configured as a multi-phase boost converter with When N (N is an integer equal to or greater than 2) boosting phases are provided, the respective boosting phases are also referred to as S0 phase, S1 _phase , . . . , S _{N-1 phase} . Each of the boost phases 31a to 31d is configured as a boost chopper circuit having a reactor 32, a switching element 33, a rectifying diode 34, and a drive circuit 35 for switching the switching element 33, and is pulse width modulated (PWM ) control, the switching element 33 is switched by the drive circuit 35 to boost the voltage of the low-voltage power line 14 and supply it to the high-voltage power line 18 . The switching element 33 is composed of an IGBT having a free wheel diode in this embodiment. When the DC power supply 12 is configured by a secondary battery, the boost converter 30 boosts the voltage of the low-voltage power line 14 and supplies it to the high-voltage power line 18, and the voltage of the high-voltage power line 18 may be configured as a step-up/step-down chopper circuit capable of stepping down the voltage and supplying it to the low-voltage power line 14 .

The control unit 40 is configured as a microcomputer. As shown in FIG. 2, the control unit 40 includes a CPU 41 that controls the entire voltage conversion device 20, and a main clock oscillator that generates a main clock necessary for the operation of the CPU 41 and the like based on an oscillation signal from an oscillation circuit 42. 43, a frequency divider 44 that divides the main clock from the main clock oscillator 42 to generate a timer clock for generating a PWM timer, which will be described later, and drive signals ( and a drive signal output unit 50 that outputs a PWM signal).

As shown in FIG. 2, the drive signal output unit 50 includes a plurality of (four in the embodiment) drive circuits 35 for outputting drive signals to corresponding boost phase drive circuits 35 among the plurality of boost phases 31a to 31d. It has signal output units 51a to 51d. Each of the drive signal output units 51a to 51d includes a PWM timer generation unit 52 that generates a PWM timer from a common timer clock generated by the frequency divider 44, and a PWM timer generated by the PWM timer generation unit 52. and a drive signal generation unit 54 that generates a drive signal based on the timer value and outputs it to the corresponding boost phase drive circuit 35 .

FIG. 3 is an explanatory diagram showing how a drive signal is generated using a PWM timer. In this embodiment, the PWM timer is configured as a count-up timer that counts up by 1 every unit time (timer resolution) from an initial value (value 0). The PWM timer may be configured as a countdown timer that counts down from the initial value by 1 per unit time. The PWM timer generator 52 receives a set value (PWM timer cycle set value) for the PWM timer cycle from the CPU 41, and returns the timer value to the initial value when the timer value of the PWM timer reaches the PWM timer cycle set value. The drive signal generation unit 54 receives a set value (duty set value) related to the duty when switching-controlling the corresponding boost phase from the CPU 41, and is turned on until the timer value of the PWM timer reaches the duty set value from the initial value. , a pulse signal that is turned off from the duty set value to the initial value is generated as a drive signal and output to the corresponding boost phase drive circuit 35 . By equalizing the periods of the drive signals output to the boosting phases 31a to 31d and equalizing the phase differences, the pulsation (ripple current) of the current flowing through the reactor 31 can be reduced, and the smoothing capacitor 16 generates heat. can be suppressed.

Next, the operation of the voltage converter 20 of the embodiment thus configured will be described. FIG. 4 is a flow chart showing an example of a control routine executed by the CPU 41 of the control section 40. As shown in FIG. This routine is executed when the activation of the system including the voltage converter 20 of the embodiment is instructed.

When the control routine is executed, the CPU 41 first sets the PWM timer cycle setting values of the S ₀ to S _N-1 phases to the initial cycle T ₀ to T _N-1 and adjusts the phase of the PWM timer in each phase. to set the phase adjustment values d _0,1 to d _N-2,N-1 , and instruct the PWM timer generation unit 52 of the S ₀ to S _N-1 phases to start the measurement of the PWM timer (step S100 ). The initial period T _n of the S _n phase is set using the initial period T _n−1 of the S _n−1 phase so as to satisfy the following equation (1). However, it is set so that sufficient time is secured for executing the next step S110. In this embodiment, the instruction to the PWM timer generator 52 of the S _n ( _n = ₁ , 2, . This is done by instructing the timer to start counting at the PWM timer cycle corresponding to the set value at the timing specified. The phase adjustment value d _n-1,n takes into consideration the time the timer value of the PWM timer advances from the start of measurement of the S _n-1 phase to the start of measurement of the S _n phase, and is programmed in advance. A value obtained by analyzing the execution time of or experimentally is set. When the measurement of the PMW timers of the S ₀ to S _N-1 phases is started in this way, next, the PMW timer cycle setting values of the S ₀ to S _N-1 phases are reset to the cycle T for all phases (step S110). As a result, the S _n -phase PMW timer is measured with the same cycle T and a phase difference (T/N) between the S _n−1 phase and the S _n phase from the second cycle onwards. For example, when N _{= 4} , the PWM timers of the _S0 , S1, S2 _, and S3 _phases can be derived from FIG. The initial period T2 is expressed by the following formula ( ₃ ), and the initial period T3 is expressed by the following formula ( ₄ ). Therefore, by resetting the PWM timer cycle for all phases to cycle T in the _second cycle of phases S0, S1, S2, and _{S3 ,} as shown in _FIG . Measurement can be performed so as to have a period T and a phase difference (T/4).

Tn= _Tn-1 +(T/N)-dn _{-1,n (} 1)
T1= _T0 +(T _/ 4) _-d0,1 (2)
T2 ₌ T1+(T _/ 4) _-d1,2 (3)
T3=T2 ₊ (T/ ₄ ) _-d2,3 (4)

Subsequently, boosting operations of the S ₀ to S _N-1 phases are performed (step S120). The step-up operation is performed by setting a duty set value according to the target voltage of the smoothing capacitor 16 and outputting it to the drive signal generator 54 of each phase. Then, it is determined whether or not a predetermined determination condition is satisfied (step S130). The determination condition may be satisfied immediately after the boost converter 30 is activated, satisfied when the elapsed time from the execution of the previous determination reaches a predetermined time, or may be satisfied when the PWM timer period is set. It can be set to be true when the value is changed. When it is determined that the determination condition is established, a phase difference deviation determination process for determining whether or not the phase difference of the S ₀ to S _N-1 phases is appropriate is executed (step S140).

FIG. 6 is a flowchart illustrating an example of phase difference deviation determination processing. In the phase difference deviation determination process, first, a variable i is initialized to a value of 0 (step S200). _Then , among the _{S 0} , _{S 1} , _. The timer values Q _i,0 , Q _i+1,0 , Q _i ,1 of the PWM timer are acquired from the PWM timer generator 52 in order of the _i+1 phase and the S _i phase (step S210). Then, the acquired timer values Q _i,0 , Q _i+1,0 , Q _i ,1 are time-converted by the following equations (5) to (7) using the conversion coefficient α (step S220). Here, the conversion factor α is the time required for the PWM timer to count a value of 1, ie, the resolution of the timer, as shown in the partially enlarged view surrounded by the dashed-dotted line in FIG.

t _i,0 =Q _i,0・α (5)
t _i+1,0 =Q _i+1,0・α …(6)
t _i,1 =Q _i,1・α (7)

_{Next ,} the _{reference phase} ( _{S i ,i+ 1_min} and upper limit δi, _i +1_min of the actual phase difference δi _,i+1 between the phase i) and the comparison phase ( _Si+1 phase) _max is set by the following equations (8) and (9) (step S230). The formula for calculating the phase difference δ _{i,i+1 has three patterns} shown in FIG. That is, as shown in FIG. 8A, when t _i,0 ≧t _i+1,0 and t _i,0 ≦t _i,1 , t _i,0 ≦δ _i,i+1 +t _{i+ Since 1,0≤t i,1} holds, the phase difference δ _i,i+1 is given by the following equation (10). Also, as shown in FIG. 8B, when t _i,0 ≧t _i+1,0 and t _i,0 ≧t _i,1 , t _i,0 ≦δ _i,i+1 +t _{i+ Since 1,0≤T} +t _i,1 holds, the phase difference δ _i,i+1 is given by the following equation (11). Furthermore, as shown in FIG. 8C, when t _i,0 ≤t _i+1,0 and t _i,0 ≤t _i,1 , T+t _i,0 ≤δ _i,i+1 +t _{i+ Since 1,0≤T} +t _i,1 holds, the phase difference δ _i,i+1 is given by the following equation (12). Considering that the timer values t _i,0 , t _i+1,0 , and t _i ,1 circulate with a period T, an arbitrary t (0≦t≦T) is given by the following equation (13). where mod(a,b) is the remainder of a/b. Equation (14) also holds from Equation (13). From equation (13), "t _i,0 -t _i+1,0 " in equations (10) and (11) is "mod ((T+t _i,0 -t _i+1,0 ),T) ”, and “T + t _i,0 −t _i+1,0 ” in equation (12) can be replaced by “mod ((2 · T + t _i,0 −t _i+1,0 ), T)” can be replaced with Similarly, “t _i,1 −t _i+1,0 ” in formula (10) can be replaced with “mod ((T+t _i,1 −t _i+1,0 ), T)”. "T + t _i,1 - t _{i +1, 0} " in formulas (11) and (12) can be changed to "mod ((2 · T + t _{i, 1} - t _{i + 1, 0} ), T)" can be replaced. From the equation (14), mod ((T + t _i,0 - t _{i +1,0} ), T) = mod ((2 T + t _i,0 - t _{i +1,0} ), T) holds, and mod Since ((T+t _i,1 −t _i+1,0 ),T)=mod((2·T+t _i,1 −t _i+1,0 ),T) holds, equations (10)-(12 ) can be summarized in the following equation (15), and equations (8) and (9) are obtained.

δ _i,i+1 _min=mod((T+t _i,0 -t _i+1,0 ),T) …(8)
δ _i,i+1 _max=mod((T+t _i,1 -t _i+1,0 ),T) …(9)
t _i,0 −t _i+1,0 ≦δ _i,i+1 ≦t _i,1 −t _i+1,0 (10)
t _i,0 −t _i+1,0 ≦δ _i,i+1 ≦T+t _i,1 −t _i+1,0 (11)
T+t _i,0 -t _i+1,0 ≦δ _i,i+1 ≦T+t _i,1 -t _i+1,0 (12)
t=mod(T+t,T) …（13）
mod(T+t,T)=mod(2・T+t,T) …(14)
mod((T+t _i,0 -t _i+1,0 ),T)≦δ _i,i+1 ≦mod((T+t _i,1 -t _i+1,0 ),T) …（ 15)

When the lower limit value δi _{,i+ 1_min} and the upper limit value δi _,i+ 1_max of the actual phase difference _{δi ,i+1} are set in this way, the appropriateness of the phase difference δi _,i+1 can be determined. It is determined whether or not the value T/N is within the actual phase difference range determined by the lower limit value δ _{i,i+1 — min} and the upper limit value δ _{i,i+1 — max} (step S240). When it is determined that the proper value T/N is within the actual phase difference range (see FIG. 9(a)), there is a phase difference deviation from the proper value T/N between the _Si phase and the _Si+1 phase. It is determined that there is not (step S250), and it is determined whether or not the variable i is equal to or greater than the value N-1 (step S280). If it is determined that the variable i is less than the value N−1, the variable i is incremented by 1 to update the reference phase _Si phase and the comparison phase _Si+1 phase, respectively, and step S210. and repeat the process. In step S240, if it is determined that the proper value T/N is not within the actual phase difference range (see FIG. 9B), the phase difference with respect to the proper value T/N between the _Si phase and the _Si+1 phase is It is determined that there is a deviation (step S260), and a phase adjustment value γ _i+1 for adjusting the phase of _Si+1 phase (comparison phase) with respect to _Si phase (reference phase) is set ( step S270). In this embodiment, as shown in FIG. _9B , the phase adjustment value γ _{i+1 is the median} value ( It is calculated from the difference between δi, _i + _{1_min} + δi _{,i+ 1_max} )/2 and the proper value T/N.

Returning to the control routine of FIG. 4, if it is determined that there is no phase difference deviation as a result of the phase difference deviation determination process, the process returns to step S120 and boost control is performed. On the other hand, when it is determined that a phase difference has occurred as a result of the phase difference determination process, a phase correction process is performed to correct the phase of the _Si+1 phase in which a phase difference has occurred with respect to the _Si phase. (Step S170) and returns to step S120. As shown in FIG. 10, the phase correction process is performed by inserting one cycle of the PWM timer obtained by adding the phase adjustment value γi ₊₁ to the cycle T to the S _i+1 phase.

In the voltage converter 20 of this embodiment described above, the Si phase (i=0, 1, . . . , N-2) among the _N boosted phases S ₀ , S ₁ , . With the S _i+1 phase as the comparison phase, the current timer values of the PWM timer are acquired in the order of S _i phase, S _i+1 phase, and S _i phase, and the acquired timer value t _i,0 of the PWM timer , t _i+1,0 , t _i ,1 to set the possible range (actual phase difference range) of the actual phase difference δ _i,i+1 between the S _i phase and the S _i+1 phase, It is determined whether or not the PWM timer phase difference between the reference phase and the comparison phase is normal depending on whether or not the proper value T/N is included in the set range. As a result, it is possible to determine whether or not the phase difference between the PWM timers of the boosting phases is appropriate by simple processing without using a dedicated circuit. When the phase difference δi _,i+1 of the PWM timer is not appropriate, the phase of the Si ₊₁ phase, which is the comparison phase, is adjusted so that the PWM timer between the _Si phase and the _Si+1 phase is adjusted. can be corrected to the proper value T/N.

In this embodiment, the _{actual phase} difference _{δ i , i} A lower limit value δi _{,i+ 1_min} and an upper limit value δi, _i + _{1_max} that can be taken by ₊₁ are set, and the proper value T/N of the phase difference δi _,i+1 is the lower limit value _{δi ,i+ 1_min} and the upper limit value δ _{i,i+ 1_max} , it is determined whether or not there is a phase difference deviation. However, as shown in FIG. 11, the acquisition interval of the timer values t _i,0 , t _i+1,0 , t _i ,1 is sufficiently small with respect to the resolution of the PWM timer, and the first and second S _i phases If the timer values t _i,0 and t _i ,1 respectively acquired for the first and second times are the same, Equation (15) is expressed by Equation (16) below. Therefore, in the phase difference determination process, when the phase difference δi _,i+1 obtained by the equation (16) matches the proper value T/N, the phase difference between the S _i phase and S _i+1 is is not generated, and when the phase difference δ _i,i+1 does not match the proper value T/N, it can be determined that a phase difference deviation has occurred.

δ _i,i+1 =mod((T+t _i,0 -t _i+1,0 ),T) …(16)

The correspondence relationship between the main elements of the embodiments and the main elements of the invention described in the column of Means for Solving the Problems will be described. In the embodiment, the boost converter 30 corresponds to the "voltage converter", the boost phases 31a to 31d correspond to the "drive phases", and the controller 40 corresponds to the "controller".

Note that the correspondence relationship between the main elements of the examples and the main elements of the invention described in the column of Means for Solving the Problems is the Since it is an example for specifically explaining the mode for solving the problem, it does not limit the elements of the invention described in the column of the means for solving the problem. That is, the interpretation of the invention described in the column of Means to Solve the Problem should be made based on the description in that column, and the Examples are based on the description of the invention described in the column of Means to Solve the Problem. This is only a specific example.

Although the embodiments for carrying out the present invention have been described above, the present invention is not limited to such embodiments at all, and can be modified in various forms without departing from the scope of the present invention. Of course, it can be implemented.

INDUSTRIAL APPLICABILITY The present invention is applicable to the manufacturing industry of voltage converters.

12 DC power supply, 14 low-voltage power line, 16 smoothing capacitor, 18 high-voltage power line, 20 voltage converter, 30 boost converter, 31a to 31d boost phase, 32 reactor, 33 switching element, 34 diode, 35 drive circuit , 40 control section, 41 CPU, 42 oscillation circuit, 43 main clock oscillator, 44 frequency divider, 50, 51a to 51d drive signal output section, 52 PWM timer generation section, 54 drive signal generation section.

Claims (1)

a voltage conversion unit having a plurality of drive phases connected in parallel with respect to the input side and the output side;
Using the same timer clock, start measuring a plurality of PWM timers so as to have the same period and a predetermined phase difference, generate a drive signal based on the timer value of each PWM timer, and output it to the corresponding drive phase a control unit that
A voltage conversion device comprising:
The control unit sets the current timer values of the PWM timer in the two drive phases to be compared among the plurality of drive phases as the reference phase with one of the two drive phases as a reference phase and the other as a comparison phase. , the comparison phase, and the reference phase in this order, and from the obtained timer value of the PWM timer, set a possible range of the phase difference of the PWM timer in the two driving phases as a phase difference range, and set the phase difference Determining whether the phase difference between the PWM timers in the two driving phases is normal based on whether the predetermined phase difference is included in the range;
Voltage converter.

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