JP7185980B2 - Superconducting qubits with Josephson junctions for improved qubits, methods of fabricating superconducting qubits, and methods of forming microwave devices - Google Patents

Description

The present invention relates generally to superconducting devices. More particularly, the present invention relates to Josephson junctions for improved qubits.

Several physical objects have been proposed as potential implementations of qubits. However, solid-state circuits, and especially superconducting circuits, are of great interest because they offer scalability that allows circuits to be formed with large numbers of interacting qubits. Superconducting qubits are typically based on Josephson junctions. A Josephson junction, for example, is two superconductors joined by a thin insulating barrier. A Josephson junction can be fabricated with an insulating tunnel barrier such as Al ₂ O ₃ between the superconducting electrodes. For such a Josephson junction, the maximum allowable supercurrent is the critical current _Ic . Superconducting tunnel junctions (also called Josephson junctions) used in superconducting quantum chips exhibit Josephson inductance, which is equivalent to conventional inductors in circuits except for their ability to provide superconducting current. be.

Superconducting qubits with Josephson junctions for improved qubits, methods of fabricating superconducting qubits, and methods of forming microwave devices are provided.

Embodiments of the present invention are directed to superconducting qubits. A non-limiting example of a superconducting qubit is a Josephson junction comprising a first superconductor and a second superconductor formed on a non-superconducting metal, and a capacitor in parallel with the Josephson junction. including.

Embodiments of the present invention are directed to methods of fabricating superconducting qubits. A non-limiting example of a method is to provide a Josephson junction, the Josephson junction comprising a first superconductor and a second superconductor formed on a non-superconducting metal. and coupling a capacitor in parallel with the Josephson junction.

Embodiments of the present invention are directed to superconducting qubits. A non-limiting example of a superconducting qubit is a Josephson junction comprising a non-superconducting metal formed between a first superconductor and a second superconductor and a capacitor in parallel with the Josephson junction. including.

Embodiments of the present invention are directed to methods of fabricating superconducting qubits. A non-limiting example of how the method works is to provide a Josephson junction, the Josephson junction comprising a non-superconducting metal formed between a first superconductor and a second superconductor. , and coupling a capacitor in parallel with the Josephson junction.

Embodiments of the present invention are directed to methods of forming microwave devices. A non-limiting example of a method is to provide a superconducting qubit, the superconducting qubit comprising a Josephson junction having a first superconductor, a second superconductor and a non-superconducting metal, and coupling a readout resonator to the superconducting qubit.

Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, please refer to the detailed description and drawings.

Specifics of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the appended claims. The foregoing and other features and advantages of embodiments of the invention are apparent from the detailed description below, taken in conjunction with the accompanying drawings.

FIG. 3A is a top view of fabricating a superconducting qubit according to an embodiment of the present invention. 2 is a cross-sectional view of FIG. 1 according to an embodiment of the invention; FIG. FIG. 3A is a top view of fabricating a superconducting qubit according to an embodiment of the present invention. 4 is a cross-sectional view of FIG. 3 according to an embodiment of the invention; FIG. FIG. 3A is a top view of fabricating a superconducting qubit according to an embodiment of the present invention. 6 is a cross-sectional view of FIG. 5 according to an embodiment of the invention; FIG. FIG. 2A is a top view of fabricating a superconducting qubit 100 according to an embodiment of the present invention. 8 is a cross-sectional view of FIG. 7 according to an embodiment of the invention; FIG. FIG. 3A is a top view of fabricating a superconducting qubit according to an embodiment of the present invention. 10 is a cross-sectional view of FIG. 9 according to an embodiment of the invention; FIG. FIG. 3A is a top view of fabricating a superconducting qubit according to an embodiment of the present invention. 12 is a cross-sectional view of FIG. 11 according to an embodiment of the invention; FIG. FIG. 3A is a top view of fabricating a superconducting qubit according to an embodiment of the present invention. 14 is a cross-sectional view of FIG. 13 according to an embodiment of the invention; FIG. 1 is a schematic diagram of a microwave device that can be utilized in quantum computing according to embodiments of the invention; FIG. 1 is a flow chart of a method of fabricating a superconducting qubit according to an embodiment of the invention; 1 is a flow chart of a method of fabricating a superconducting qubit according to an embodiment of the invention; 4 is a flow chart for forming a microwave device according to embodiments of the present invention;

The figures depicted herein are exemplary. There may be many variations to the figures or acts described herein without departing from the spirit of the invention. For example, acts may be performed in a different order, or acts may be added, deleted or modified. Also, the term "coupled" and variations thereof describes having a communication path between two elements, and the elements without intervening elements/connections between them. does not necessarily include a direct connection between them. All of these variations are considered part of the specification.

In the accompanying figures and the following detailed description of the disclosed embodiments, various elements illustrated in the figures are given two or three digit reference numerals. With few exceptions, the leftmost digit of each reference number corresponds to the figure in which the element is first illustrated.

For the sake of brevity, the prior art relating to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into more generic procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and so for the sake of brevity, many conventional steps will only be briefly described herein. , or omit it entirely without providing details of the well-known process.

により与えられる、ここでＬがジョセフソン接合の非線形インダクタンスであり、Ｃがシャント・キャパシタンスである。各ジョセフソン接合は超伝導臨界電流Ｉ_ｃを有し、そしてジョセフソン・インダクタンスを式

によりＩ_ｃに関係させる、ここでφ_０は磁束量子である。これらの２つの式を組み合わせると、狭い周波数分布（これは、名目上同一のキュービットの周波数の差を指す）は、ジョセフソン接合およびシャント・キャパシタンスＣの臨界電流の変動性によるものである。名目上同一のキュービットの集合（population）の周波数広がりは、標準リソグラフィおよびパターニング法により形成されるキャパシタンスとは対照的にジョセフソン接合の臨界電流（Ｉ_ｃ）の広がりとして始まることが知られている。加えて、内部のどこかからデバイスへのまたは外部システムへのいずれかのキュービットからのエネルギー損失のすべての源を減少させることによりキュービットのコヒーレンス時間を増加させることが望ましい。（トンネル障壁それ自体のために使用される酸化物などの）誘電体を含むことが、さらなる損失およびコヒーレンス時間の関連する減少につながることがある。 Turning now to an overview of the technology more specifically concerned with aspects of the invention, for gate-based superconducting quantum computing, the frequency of the qubits (forming the circuit) is well controlled. It is important to have a narrow distribution. In the state of the art, qubits use oxide tunnel junctions to form Josephson junctions, and Josephson junctions provide nonlinear inductance to circuits/devices. A shunt capacitor is fabricated to create a nonlinear oscillator that acts as a qubit. The frequency of this qubit is given by the formula

where L is the nonlinear inductance of the Josephson junction and C is the shunt capacitance. Each Josephson junction has a superconducting critical current _Ic , and the Josephson inductance is given by the expression

to I _c by where φ ₀ is the flux quantum. Combining these two equations, the narrow frequency distribution (which refers to the frequency difference of nominally identical qubits) is due to the variability of the critical currents of the Josephson junctions and the shunt capacitance C. It is known that the frequency spread of a nominally identical qubit population begins as a spread of the critical current (I _c ) of a Josephson junction as opposed to the capacitance created by standard lithographic and patterning methods. there is In addition, it is desirable to increase the coherence time of the qubit by reducing all sources of energy loss from the qubit either from somewhere inside to the device or to an external system. Including a dielectric (such as the oxide used for the tunnel barrier itself) can lead to further losses and an associated decrease in coherence time.

のように変化する、ここでＡが接合の面積である。この依存性は、ジョセフソン接合で、またＭｇＯ_２およびＡｌＯ_２の両方が障壁として使用されてきている磁気抵抗ランダム・アクセス・メモリ（ＭＲＡＭ）トンネル接合でも観察されてきている。このことは、臨界電流Ｉ_ｃの値に対する面積Ａの依存性が普遍的な振る舞いであることを示している。この問題が何十年にわたり研究されてきているとはいえ、所与の大きさのジョセフソン接合に関して広がり（すなわち臨界電流Ｉ_ｃの違い）を減少させることにおいて、事実上何の進歩も報告されていない。広がりの狭い制御をともなう多くのキュービットを作らなければならない量子コンピューティングのケースでは、この問題はますます重要になってくる。酸化物接合の広がりを制御する（すなわち、所与の大きさのジョセフソン接合を用いてそれぞれ設計されたジョセフソン接合デバイス同士の間の酸化物接合の違いを制御する）際に、さらなる進歩がなされ得ることが可能であるはずであるけれども、実際的な量子コンピュータが作られようとしている場合には、代替案の探究は、新たな緊急性を持つようになる。 The spread (i.e. difference) in the critical current _Ic of the junction (or similarly the difference in resistance) is approximately

where A is the area of the junction. This dependence has been observed in Josephson junctions and also in magnetoresistive random access memory (MRAM) tunnel junctions where both MgO ₂ and AlO ₂ have been used as barriers. This indicates that the dependence of area A on the value of critical current _Ic is a universal behavior. Although this problem has been studied for decades, virtually no progress has been reported in reducing the broadening (i.e., the critical current I _c difference) for a given size Josephson junction. not This issue becomes even more important in the case of quantum computing, where many qubits must be created with narrow control over their spread. Further advances have been made in controlling oxide junction spread (i.e., controlling oxide junction differences between Josephson junction devices each designed with a given Josephson junction size). What could be done should be possible, but the search for alternatives takes on new urgency when practical quantum computers are about to be built.

Turning now to an overview of aspects of the invention, one or more embodiments of the invention instead of using superconducting-insulator-superconducting Josephson junctions for transmon qubits, superconducting-normal - Addressing the above-described drawbacks of the prior art by using superconducting Josephson junctions. Initially, it may or may not appear that the junction characteristics are similar for the two cases, ie with the same phase/voltage relationship for both. However, the origin of the fluctuations in the critical current _Ic for the nominally identical superconducting-insulator superconducting junction is emphasized by the steep exponential dependence of the tunneling current _Ic on the barrier thickness. It is believed that this is due to subtle differences. In addition, _Ic fluctuations can originate from defects in the oxide barrier or at the oxide/metal interface, often referred to as two-level systems (TLS). According to embodiments of the present invention, the characteristic length scale for the decay of the order parameter is 10-100 times longer for superconducting normal metal superconducting junctions than for superconducting insulator superconducting junctions. There is Control of the critical current I _c is therefore proportionally easier to obtain by having a capacitor and a superconducting qubit formed from a superconducting normal-metal Josephson junction. Ordinary metals are not superconducting metals, which means that ordinary metals (non-superconducting metals) do not become superconducting at low temperatures (such as below 9 Kelvin (K), 4K, etc.). Metals are commonly used as tunnel metals instead of dielectric materials such as oxide layers. Nominally identical superconducting qubits with Josephson junctions made using superconducting normal metal superconducting junctions Nominally identical superconducting qubits with Josephson junctions made using superconducting insulator superconducting junctions have a smaller spread of the critical currents I _c than for superconducting qubits (which means that the critical currents I _c are almost the same (ie, narrowly distributed)). Eliminating the oxide tunnel barrier and replacing it with a normal metal improves coherence as a result of the removal of the TLS-containing dielectric material.

Turning now to a more detailed description of aspects of the present invention, FIGS. 1-8 depict fabrication of a superconducting qubit 100 according to embodiments of the present invention. FIG. 1 depicts a top view of fabricating a superconducting qubit 100 according to an embodiment of the present invention. FIG. 2 depicts a cross-sectional view of FIG. 1 according to an embodiment of the invention. Fabrication of superconducting qubit 100 uses a contacts first process in which the contacts (ie, superconducting electrodes) are deposited before the tunnel barrier material, which is a non-superconducting material.

A superconducting material 102 is formed on top of the substrate 202 . Non-limiting examples of superconducting material 102 include materials such as niobium (Nb), aluminum (Al), titanium nitride (TiN), and other suitable superconductors.

Non-limiting examples of suitable materials for substrate 202 include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g. GaAs (Gallium Arsenide), InAs (Indium Arsenide), InP (Indium Phosphorus), or Aluminum Arsenide (AlAs)), II-VI materials (e.g. CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or these Including any combination. Other non-limiting examples of semiconductor materials include III-V materials such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. III-V materials include at least one "group III element" such as aluminum (Al), boron (B), gallium (Ga), indium (In), and nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and at least one “group V element” can be included.

FIG. 3 depicts a top view of fabricating a superconducting qubit 100 according to an embodiment of the present invention. FIG. 4 depicts a cross-sectional view of FIG. 3 according to an embodiment of the invention. The superconducting material 102 of the superconducting qubit 100 is patterned. Although the respective elements involved in superconducting qubit 100 are not shown so as not to obscure the figure, the fabrication process uses single-step lithography and subsequent etching to form the readout resonator, ground plane, and ground plane. ), pattern capacitors or junction contacts or a combination thereof. As an example, performing lithography to deposit a layer of resist (which may be a positive or negative resist) on top of superconducting material 102 and pattern it into the desired pattern. can be done. Optionally, etching of superconducting material 102 (eg, TiN or Nb) can be accomplished with _Cl2 or _BCl3 etchants during reactive ion etching (RIE). Etching of TiN can also be accomplished using a wet etch such as "standard clean 1" ( _NH4OH + _{H2O2 )} .

The patterning of superconducting material 102 results in space 302 between superconducting electrodes 304A and 304B. Spaces 302 are provisioned for depositing non-superconducting materials (ie, usually metals). The spacing of spaces 302 (ie, gaps) may range from approximately 0.1 to 10 microns (μm). In addition, the patterning of superconducting material 102 results in shunt capacitors for superconducting qubit 100, capacitor 310 C1 and capacitor 312 C2. Both capacitors 310 C1 and 312 C2 may be utilized in some embodiments of the present invention. In some embodiments of the invention, only one of capacitors 310 C1 or 312 C2 may be utilized such that only one capacitor is patterned.

FIG. 5 depicts a top view of fabricating a superconducting qubit 100 according to an embodiment of the present invention. FIG. 6 depicts a cross-sectional view of FIG. 5 according to an embodiment of the invention. As can be seen, non-superconducting metal 502 is deposited on top of superconducting material 102 and substrate 202 . A non-superconducting metal 502 is deposited in space 302 to act as a tunnel barrier. For example, the surface of superconducting qubit 100 can be cleaned in situ, then metal deposition of non-superconducting metal 502 is performed. The non-superconducting metal 502 can be copper (Cu), platinum (Pt), or the like. Other examples of other suitable tunneling non-superconducting metals 502 can include Au, Ag, Pd, and the like. The choice of which metal pairs to use for the superconducting and normal metals will depend on several factors. First, the cleanliness of the material can be a factor, especially metals, where most of the concern is the coherence length, which is governed in part by the mean free path of the electrons in the material. . In addition, the desired operating temperature (as a factor) will set the minimum limit for the superconducting transition temperature. Finally, the ease of processing and coexistence of the two metals can be a factor, especially when forming, a clean, non-scattering interface will be important.

The height H1 or thickness of the non-superconducting metal 502 may range from approximately 10 to 1000 nanometers (nm), with approximately 200 nm being preferred (but not required).

FIG. 7 depicts a top view of fabricating a superconducting qubit 100 according to an embodiment of the present invention. FIG. 8 depicts a cross-sectional view of FIG. 7 according to an embodiment of the invention.

The non-superconducting metal 502 is patterned only within the junction area, thereby forming a Josephson junction 702 . The junction area is between two superconducting electrodes 304A and 304B. Josephson junction 702 is formed from superconducting electrode 304A, non-superconducting metal 502, and superconducting electrode 304B. A portion of non-superconducting metal 502 may or may not remain on top of superconducting electrodes 304A and 304B. Non-superconducting metal 502 is removed from substrate 202 and other portions of superconducting metal 102 . In some embodiments of the present invention, non-superconducting metal 502 can be patterned to remain only in spaces 302 . In some embodiments of the present invention, non-superconducting metal 502 may be patterned to completely cover (or more than 80%, 90%, etc.) superconducting electrodes 304A and 304B.

Lithography is performed (eg, photoresist can be deposited and patterned) to pattern the tunnel junction, which is the non-superconducting metal 502, and the tunnel metal is deposited according to the pattern formed using lithography. is selectively etched with respect to superconducting metal 102 and silicon (eg, substrate 202). Thus, desired portions of non-superconducting metal 502 are removed while leaving (or not etching) superconducting metal 102 and silicon (eg, substrate 202). For example, Cu (as non-superconducting metal 502) can be selectively etched with respect to TiN (as superconducting metal 102) using a number of commercially available etchants. An example commercially available etchant is Chromium Etchant CR-7, Transene Company, Inc. by Cyantek Corporation (merged with KMG Electronic Chemicals). aluminum etchant Etch A from Transene Company, Inc.; can contain a copper etchant from

As an arbitrary direction for illustrating the electrical flow of the critical/superconducting current _{I c} at superconducting temperatures in FIG. It can tunnel through non-superconducting metal 502 and flow back to superconducting electrode 304B. Using the techniques discussed herein, nominally identical superconducting qubits 100 (or nominally identical superconducting qubits 900, discussed below) can have the same or approximately the same value for their respective critical currents I _c . can be formed to the same value, whereby the value for their critical current _{I c} is lower than that for nominally identical state-of-the-art qubits using superconductor-insulator-superconductor Josephson junctions. have a small spread.

9-14 depict fabrication of a superconducting qubit 900 according to embodiments of the present invention. FIG. 9 depicts a top view of fabricating a superconducting qubit 900 according to an embodiment of the present invention. FIG. 10 depicts a cross-sectional view of FIG. 9 according to an embodiment of the invention. Fabrication of the superconducting qubit 900 uses a two-layer process in which a non-superconducting tunnel barrier material is deposited in front of/below the contact (ie superconducting electrode).

A non-superconducting metal 502 is deposited on top of substrate 202 . Superconducting material 102 is deposited on top of non-superconducting metal 502 . As such, the non-superconducting metal 502 can be copper (Cu), platinum (Pt), or the like. Other examples of other suitable tunneling non-superconducting metals 502 can include Au, Ag, Pd, and the like. Non-limiting examples of superconducting material 102 include materials such as niobium (Nb), aluminum (Al), titanium nitride (TiN), and other suitable superconductors.

FIG. 11 depicts a top view of fabricating a superconducting qubit 100 according to an embodiment of the present invention. FIG. 12 depicts a cross-sectional view of FIG. 11 according to an embodiment of the invention. Both the superconducting material 102 and the non-superconducting metal 502 are patterned. Although the elements involved in superconducting qubit 100 are not shown to avoid obscuring the figure, the fabrication process still uses single-step lithography and subsequent etching to form the readout resonator, ground and Planes, capacitors or junction contacts or combinations thereof are also patterned. For example, perform lithography (e.g., using patterned photoresist) to lay out patterns for non-superconducting metal 502 and superconducting material 102, and superconducting material 102 (e.g., TiN, Nb) and Etching of the non-superconducting metal 502 (Cu) can be done with a Cl ₂ -based etchant during reactive ion etching (RIE). FIG. 11 illustrates forming shunt capacitors 310 C1 and 312 C2. As such, two shunt capacitors may not be necessary, and only one of shunt capacitors 310 C1 and 312 C2 may be utilized in some embodiments of the invention. Note at this point that the patterning will still leave shorted junctions and the junctions will be subsequently patterned. In some embodiments of the invention, the bond can be formed at this point. Note that this is just one example sequence of patterning for some embodiments of the present invention. In other embodiments of the invention, it may be advantageous to form the junction only at some later point in time, as the Josephson junction is preserved until the end of fabrication.

FIG. 13 depicts a top view of fabricating a superconducting qubit 900 according to an embodiment of the present invention. FIG. 14 depicts a cross-sectional view of FIG. 13 according to an embodiment of the invention.

Superconducting metal 102 is patterned in the junction area to form gap 1402 and to form superconducting electrodes 304 A and 304 B, thereby forming Josephson junction 1302 . The junction area is between but below the two superconducting electrodes 304A and 304B. Josephson junction 1302 is formed from superconducting electrode 304A, underlying non-superconducting metal 502, and superconducting electrode 304B.

To pattern gaps 1402 (ie, superconducting electrodes 304A and 304B) in the contacts, lithography is performed (eg, using photoresist) to selectively etch superconducting material 102 and remove the underlying superconducting material 102. A reactive ion etch is performed so as not to etch the tunnel metal (ie, the non-superconducting metal 502). Etch TiN (superconducting material 102) selectively to Cu (non-superconducting metal 502) using a number of commercially available etchants such as, for example, DuPont™ CuSolve™ EKC™ 575 can do.

The height H2 or thickness of the non-superconducting metal 502 may range from about 10-1000 nm, preferably (but not necessarily) 200 nm.

As an arbitrary direction to illustrate the electrical flow of the critical/superconducting current I _c at superconducting temperatures in FIG. It can tunnel through the non-superconducting metal 502 in the region and flow back up to the superconducting electrode 304B. As can be seen, there is no tunnel barrier within the gap 1402 as would have been placed in the state of the art. Rather, the critical current travels in the underlying non-superconducting metal 502 below the gap 1402 . A portion of non-superconducting metal 502 underlying the ends of superconducting electrodes 304A and 304B closest to gap 1402 acts as a tunnel barrier with non-superconducting metal 502 under gap 1402. FIG.

In circuit quantum electrodynamics, quantum computing refers to nonlinear superconducting devices (i.e., qubits) for manipulating and storing quantum information, and for reading and/or facilitating interactions between qubits. (eg, as a two-dimensional (2D) planar waveguide or as a three-dimensional (3D) microwave cavity). As an example, each superconducting qubit includes one or more Josephson junctions shunted by capacitors in parallel with the junctions. A qubit is capacitively coupled to a 2D or 3D microwave cavity. Electromagnetic energy associated with a qubit is stored in the Josephson junctions and capacitive and inductive elements that form the qubit. FIG. 15 schematically depicts a microwave device 1500 that can be utilized in quantum computing according to embodiments of the present invention. Microwave device 1500 includes a superconducting qubit 100 or 900 . One microwave device 1500 is shown by way of example, and it should be understood that multiple microwave devices 1500 may be included in a quantum computer, as will be appreciated by those skilled in the art. A microwave device 1500 can be utilized to energize (ie, drive) and read out the superconducting qubits 100,900. In this example, the superconducting qubits 100, 900 can be reflectively energized and read out. In other implementations, the superconducting qubits 100, 900 can be energized and read out in transmission, as will be appreciated by those skilled in the art.

Microwave device 1500 includes qubit 100 or 900 capacitively coupled to readout resonator 1505 by coupling capacitors 1520A and 1520B. Readout resonator 1505 can represent a 2D planar waveguide or a 3D microwave cavity. Readout resonator 1505 is capacitively coupled to port 1550 by resonator coupling capacitor 1525 . Port 1550 accepts microwave signals (eg, qubit drive signals to energize the qubits 100, 900 and resonator readout signals to read out the readout resonator 1505 and thereby read out the state of the qubits 100, 900). and for measuring the microwave signal reflected from the readout resonator 1505 (ie, receiving the state of the qubits 100, 900).

FIG. 16 depicts a flow chart 1600 of a method of fabricating a superconducting qubit 900 according to an embodiment of the invention. At block 1602, a Josephson junction 1302 is provided that includes a first superconductor 304A and a second superconductor 304B formed over non-superconducting metal 502. FIG. At block 1604 , a shunt capacitor (eg, capacitor C 1 310 , capacitor C 2 312 , or both capacitors C 1 and C 2 ) is coupled in parallel with Josephson junction 1302 .

The first superconductor 304A and the second superconductor 304B are separated from each other. The first superconductor and the second superconductor have a space (eg, gap 1402) separating them. The space (gap 1402) is about 0.1-10 μm. A non-superconducting metal is formed over the semiconductor. A non-superconducting metal is copper. The non-superconducting metal is platinum.

FIG. 17 depicts a flow chart 1700 of a method of fabricating a superconducting qubit 100 according to an embodiment of the invention. At block 1702, a Josephson junction 702 is provided comprising a non-superconducting metal 502 formed between the first superconductor 304A and the second superconductor 304B. At block 1704 , a shunt capacitor (eg, capacitor C 1 310 , capacitor C 2 312 , or both capacitors C 1 and C 2 ) is coupled in parallel with Josephson junction 702 .

A non-superconducting metal 502 is formed on top of portions of both the first superconductor 304A and the second superconductor 304B. A non-superconducting metal 502 , a first superconductor 304 A, and a second superconductor 304 B are each formed over a portion of substrate 202 . First superconductor 304 A and second superconductor 304 B are separated from each other by gap 302 . The spacing of the gaps 302 may range from approximately 0.1-10 μm. A non-superconducting metal is formed over the silicon. A non-superconducting metal is copper. The non-superconducting metal is platinum.

FIG. 18 depicts a flow chart 1800 of a method of forming microwave device 1500 according to an embodiment of the present invention. At block 1802, a superconducting qubit 100 or 900 is provided, where the superconducting qubit 100, 900 has a first superconductor 304A, a second superconductor 304B, and a non-superconducting metal 502 Josephson Includes junctions 702 , 1302 . At block 1804, the readout resonator 1505 is coupled to the superconducting qubits 100,900.

The circuit elements of circuits 100, 702, 1500 can be made from superconducting materials. Each resonator, transmission/feed/pump line is made from superconducting material. Examples of superconducting materials (at low temperatures typically ranging from 0.1 to 20 Kelvin (K)) include niobium, aluminum, tantalum, and the like. For example, the proximity effect junction is made from superconducting material and the tunnel region is made from non-superconducting material. Capacitors can be made from superconducting materials separated by a vacuum as opposed to a (typically lossy) dielectric. The transmission lines (ie, wires) connecting the various elements are made from superconducting material.

Various embodiments of the present invention are described herein with reference to related drawings. Alternate embodiments may be devised without departing from the scope of the invention. Although various connections and positions (e.g., overlying, underlying, adjacent, etc.) are set forth in the following description and between elements in the drawings, the described functionality is maintained regardless of orientation. Those skilled in the art will recognize that many of the positional relationships described herein are orientation independent when maintained. These connections and/or positions may be direct or indirect, unless specified otherwise, and the invention is not limited in this respect. Thus, binding between entities may refer to either direct binding or indirect binding, and the positional relationship between entities may be direct or indirect. As an example of an indirect relationship, reference herein to forming layer "A" over layer "B" means that the associated properties and functionality of layer "A" and layer "B" are intermediate. Unless substantially varied by layer, includes the situation in which one or more intermediate layers (eg, layer "C") are between layer "A" and layer "B".

The following definitions and abbreviations should be used for the interpretation of the claims and specification. As used herein, "comprises", "comprising", "includes", "including", "has", "has" The terms having," "contains," or "containing," or any other variation thereof, are intended to cover non-exclusive inclusion. is. For example, a composition, mixture, process, method, article, or apparatus that includes a set of elements need not necessarily be limited to those elements, but rather other elements or such that are not expressly listed. It can include other elements specific to a composition, mixture, process, method, article, or device.

Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to 1, ie, 1, 2, 3, 4, and the like. The term "plurality" is understood to include any integer greater than or equal to 2, ie, 2, 3, 4, 5, and so on. The term "connection" can include indirect "connection" and direct "connection".

References herein to "one embodiment," "an embodiment," "an example embodiment," etc. may include certain features, structures, or characteristics of the described embodiment. indicates that all embodiments may or may not include that particular feature, structure, or property. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with one embodiment, such feature, structure, or characteristic is described in connection with other embodiments, whether or not explicitly stated. , or properties are intended to be within the knowledge of those skilled in the art.

For the purposes of the discussion below, "upper", "lower", "right", "left", "vertical", "horizontal", " The terms "top", "bottom" and derivatives thereof refer to the structures and methods described as oriented in the drawings. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" means that a first element, such as a first structure, resides above a second element, such as a second structure, where an intervening element such as an interfacial structure is the first element and the second may be present between elements of The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are in direct contact with any intervening conductive, insulating layer at the interface of the two elements. Or it means connecting without a semiconductor layer.

For example, the phrase "selectively to", such as "selective to the first element relative to the second element", allows the first element to be etched and the second element to be etched. • Means that it can act as a stop.

The terms "about," "substantially," "approximately," and variations thereof relate to measurements of specific quantities based on equipment available at the time of filing the application. It includes the degree of error to be made. For example, "about" can include ±8% or 5% or 2% of a given value.

As previously noted herein, for the sake of brevity, the prior art relating to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. By way of background, however, a more general description of a semiconductor device manufacturing process that may be utilized in implementing one or more embodiments of the present invention will now be provided. Although the specific manufacturing operations used in implementing one or more embodiments of the invention may be known separately, the described combination of operations and/or resulting structures of the invention may be Like no other. Thus, the unique combination of the operations described in connection with the fabrication of semiconductor devices according to the present invention allows for various individually known physical and chemical processes to be performed on semiconductor (e.g., silicon) substrates. We use processes, some of which are described in the paragraphs immediately below.

In general, the various processes used to form micro-chips that are packaged into ICs fall into four general categories: film deposition, removal/etching, semiconductor doping, and patterning/lithography. be. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and most recently atomic layer deposition (ALD), among others. . Stripping/etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry), chemical mechanical polishing (CMP), and the like. Semiconductor doping is the modification of electrical properties, generally by diffusion and/or by ion implantation, for example, by doping transistor sources and drains. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. used. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be varied with the application of a voltage. By fabricating these various component structures, millions of transistors can be made and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, a pattern is formed by a photosensitive polymer called photoresist. Lithography and etch pattern transfer steps are repeated multiple times to create complex structures that create many wires connecting transistors and millions of transistors in a circuit. Each pattern that is printed onto the wafer is aligned with previously formed patterns, slowly creating conductors, insulators and selectively doped regions to form the final device.

The flowcharts and block diagrams in the Figures illustrate possible implementations of methods of manufacture and/or methods of operation in accordance with various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved.

STATEMENT REGARDING GOVERNMENT SPONSORED RESEARCH OR DEVELOPMENT This invention was made with government support under Contract No. H98230-13-D-0173 awarded by the National Security Agency. The Government has certain rights in this invention.

The description of various embodiments of the invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is used to best describe principles of embodiments, practical applications, or technical improvements over technology found in the market, or as described herein by those skilled in the art. It was chosen to make it possible to understand the embodiment.

Claims (19)

comprising a first superconductor and a second superconductor formed on a non-superconducting metal, wherein said first superconductor and said second superconductor are provided separated from each other by a space , a superconducting-normal-superconducting Josephson junction, and
a capacitor coupled in parallel with the superconducting-normal-superconducting Josephson junction. 2. The superconducting qubit of claim 1, wherein the capacitor comprises portions of the superconducting-normal-superconducting Josephson junction extending from each of the first superconductor and the second superconductor. 3. The superconducting qubit of claim 1 or 2, wherein the capacitors are formed of superconducting material separated by vacuum. A superconducting qubit according to any one of claims 1 to 3, wherein the dimension of said space is about 0.1-10 microns. 5. The superconducting qubit of any of claims 1-4, wherein the non-superconducting metal is formed on a semiconductor. A superconducting qubit as claimed in any preceding claim, wherein the non-superconducting metal comprises copper or platinum. a superconductor comprising a non-superconducting metal formed between a first superconductor and a second superconductor, wherein said first superconductor and said second superconductor are provided separately; a conducting-normal-superconducting Josephson junction;
a capacitor coupled in parallel with the superconducting-normal-superconducting Josephson junction. 8. The superconducting qubit of claim 7, wherein the capacitor includes portions of the superconducting-normal-superconducting Josephson junction extending from each of the first superconductor and the second superconductor. 9. The superconducting qubit of claim 7 or 8, wherein the non-superconducting metal is formed on top of portions of both the first superconductor and the second superconductor. 10. The superconducting qubit of any of claims 7-9, wherein the non-superconducting metal, the first superconductor, and the second superconductor are each formed over a portion of a substrate. . A method of manufacturing a superconducting qubit, comprising:
a first superconductor and a second superconductor formed on a non-superconducting metal, wherein the first superconductor and the second superconductor are separated from each other by a space; providing a superconducting-normal-superconducting Josephson junction,
coupling a capacitor in parallel with the superconducting-normal-superconducting Josephson junction. 12. The method of claim 11, wherein said capacitor comprises a portion of said superconducting-normal-superconducting Josephson junction extending from each of said first superconductor and said second superconductor. 13. The method of claim 11 or 12, wherein the dimensions of said spaces are about 0.1-10 microns. 14. The method of any of claims 11-13, wherein the non-superconducting metal is formed over a semiconductor. 15. The method of any of claims 11-14 , wherein the non-superconducting metal comprises copper or platinum. A method of manufacturing a superconducting qubit, comprising:
a superconductor comprising a non-superconducting metal formed between a first superconductor and a second superconductor, wherein said first superconductor and said second superconductor are provided separately; providing a conducting-normal-superconducting Josephson junction;
coupling a capacitor in parallel with the superconducting-normal-superconducting Josephson junction. 17. The method of claim 16, wherein said capacitor comprises a portion of said superconducting-normal-superconducting Josephson junction extending from each of said first superconductor and said second superconductor. 18. A method according to claim 16 or 17, wherein said non-superconducting metal is formed on top of portions of both said first superconductor and said second superconductor. A method of forming a microwave device, comprising:
A superconducting qubit comprising a first superconductor, a second superconductor, and a non-superconducting metal between the first superconductor and the second superconductor. , a superconducting-normal-superconducting Josephson junction in which said first superconductor and said second superconductor are provided separately from each other and coupled in parallel with said superconducting-normal-superconducting Josephson junction. providing the superconducting qubit comprising a capacitor that
coupling a readout resonator to the superconducting qubit.

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