JP7176341B2 - Information processing device for motor control - Google Patents

Description

The present invention relates to an information processing apparatus for motor control, and more particularly to an information processing apparatus for motor control that includes a multi-core processor and a memory.

2. Description of the Related Art Conventionally, an information processing apparatus has been proposed that includes a multi-core processor (multi-core CPU) and a memory (RAM) (see, for example, Patent Document 1). The memory is divided into a plurality of blocks, stores data for each block, and stores pointers indicating states of the plurality of blocks. Multi-core processors run multiple applications that write data to and read data from memory. The multi-core processor appropriately switches between a block for writing data and a block for reading data for a plurality of blocks of memory. This avoids memory access (data read/write) conflicts between multiple applications.

JP 2009-110063 A

In the information processing apparatus described above, memory access conflicts between two applications are avoided, but in a multi-core processor, memory accesses (data reading and writing) may conflict between a plurality of processor cores. For example, if the multi-core processor includes a control-side processor core that executes control processing for controlling a motor, and a determination-side processor core that executes abnormality determination for determining an abnormality in the memory, the control-side processor core accesses If the processor core on the judgment side tries to execute the abnormality judgment for the storage area of the memory in which there is an access conflict. It is desirable to avoid such access conflicts.

In an information processing apparatus for motor control provided with a multi-core processor having a control-side processor core and a determination-side processor core according to the present invention, conflict between access to memory of the control-side processor core and access to memory of the determination-side processor core The main purpose is to avoid

The information processing apparatus of the present invention employs the following means in order to achieve the above main object.

The information processing device of the present invention includes:
a multi-core processor and
a memory accessed by the multi-core processor;
An information processing device for motor control used for controlling a motor, comprising:
The multi-core processor is
a control-side processor core that repeatedly executes a predetermined control process for controlling the motor in each control cycle based on the number of revolutions of the motor while accessing the memory;
After writing predetermined data to an inspection target area of the memory, data is read from the inspection target area, and the predetermined data and the read data are compared to determine whether or not an abnormality has occurred in the memory. a judgment-side processor core that executes an abnormality judgment to
has
The judging-side processor core has a constant control cycle, and the control-side processor core detects the abnormality during an idle period from when the control-side processor core ends the predetermined control processing to when it next starts the predetermined control processing. carry out the judgment
This is the gist of it.

In the information processing apparatus of the present invention, the control-side processor core repeatedly executes predetermined control processing for controlling the motor in each control cycle based on the number of rotations of the motor while accessing the memory. After writing predetermined data to the inspection target area of the memory, the determination-side processor core reads the data from the inspection target area, compares the predetermined data with the read data, and determines whether or not there is an abnormality in the memory. Execute the abnormality determination to be determined. The determination-side processor core has a constant control cycle, and executes the abnormality determination during an idle period from when the control-side processor core ends a predetermined control process to when it next starts a predetermined control process. This makes it possible to avoid competition between access to the memory of the control-side processor core and access to the memory of the determination-side processor core.

In such an information processing apparatus of the present invention, the determination-side processor core may perform the abnormality determination in order from the area storing data with the highest priority in the predetermined control process. In this way, abnormality determination can be performed from the data with the highest priority.

Further, in the information processing apparatus of the present invention, the multi-core processor repeats part of motor control processing for controlling the motor at predetermined intervals longer than the control interval while accessing the memory. a first processor core to be executed, a second processor core as the control-side processor core to repeatedly execute the remainder of the motor control process as the predetermined control process, and the determination-side processor core. and the determination-side processor core has a constant control cycle, and an idle time from when the first processor core finishes the part of the processing until it next executes the part of the processing. and the abnormality determination may be performed at a timing of an idle time from when the second processor core finishes the processing of the remaining part to when it executes the next processing of the remaining part. In this way, since the judgment-side processor core executes memory abnormality judgment at the timing when both the first and second processor cores are not executing processing, access to the memory of the first and second processor cores and the judgment-side processor core are performed. Conflicts with processor core memory access can be avoided.

1 is a configuration diagram showing an outline of the configuration of a motor device 20 equipped with an information processing device as one embodiment of the present invention; FIG. 4 is a flow chart showing an example of a periodic processing routine executed by a processor core 34a of a multi-core processor 32; 4 is a flow chart showing an example of a feedback processing routine executed by a processor core 34b; FIG. 4 is an explanatory diagram showing an example of the relationship between priority and data type; 4 is a flowchart showing an example of an abnormality determination processing routine executed by a processor core 34c; 4 is a timing chart showing an example of operations of processor cores 34a to 34c;

Next, a mode for carrying out the present invention will be described using examples.

FIG. 1 is a configuration diagram showing an outline of the configuration of a motor device 20 equipped with an information processing device for motor control as an embodiment of the present invention. The motor device 20 includes a motor 22 , an inverter 24 , a boost converter 26 , a battery 28 and an electronic control unit 30 . Such a motor device 20 is mounted, for example, on an electric vehicle that runs with power from the motor 22 . In the embodiment, the electronic control unit 30 corresponds to the "information processing device for motor control".

The motor 22 is configured as a synchronous generator motor, and includes a rotor in which permanent magnets are embedded and a stator around which three-phase coils are wound.

Inverter 24 is used to drive motor 22 . This inverter 24 is connected to a boost converter 26 via a high voltage side power line 25 . The inverter 24 includes a plurality of transistors (switching elements), not shown, which are power semiconductor elements. The motor 22 is rotationally driven by the switching control of a plurality of transistors of the inverter 24 by the electronic control unit 30 when voltage is applied to the high-voltage side power line 25 .

The boost converter 26 is connected to the high-voltage power line 25 and the low-voltage power line 27, and although not shown, two transistors as switching elements and two transistors are connected in parallel to each of the two transistors. It has two diodes and a reactor. The boost converter 26 boosts the power on the low-voltage power line 27 and supplies it to the high-voltage power line 25 or supplies it to the high-voltage power line 25 by adjusting the ratio of the ON time of the two transistors by the electronic control unit 30 . The power on the voltage side power line 25 is stepped down and supplied to the low voltage side power line 27 .

The battery 28 is configured as, for example, a lithium-ion secondary battery or nickel-hydrogen secondary battery with a rated voltage of 200 V or 250 V, and is connected to the low-voltage side power line 27 .

The electronic control unit 30 is configured as a multicore microcomputer and includes a multicore processor 32 , shared memory 40 and timer 42 . The electronic control unit 30 also includes a ROM for storing processing programs and various maps (not shown) and an input/output port.

The multicore processor 32 includes processor cores 34a to 34c and registers 36a and 36b. The processor cores 34a to 34c function as a central processing unit (CPU), exchange data with the registers 36a and 36b and the shared memory 40 via the bus 50, and output various processing requests to the shared memory 40. there is

The shared memory 40 is configured as a random access memory that temporarily stores various data, and functions as a main storage device. The shared memory 40 includes shared buffers 40a to 40b accessible by the processor cores 34a to 34c of the multicore processor 32 via the bus 50, storage areas for storing various applications, and the like.

The timer 42 is configured as a free-running counter, and increments the timer value T at predetermined time intervals after the motor device 20 is activated.

Signals from various sensors are input to the electronic control unit 30 through input ports. Signals input to the electronic control unit 30 include the rotational position θm from a rotational position detection sensor 22a that detects the rotational position of the rotor of the motor 22, and phase currents Iv and Iw from current sensors 22b and 22c attached to the V-phase and W-phase power lines, voltage VH from a voltage sensor 25a that detects the voltage of the high-voltage side power line 25, and the low-voltage side power line voltage VL from a voltage sensor 27a that detects the voltage of 27, detection values from various sensors that detect the state of the battery 28 (battery current and battery voltage), and the like. Signal values from various sensors are stored in the shared memory 40 .

Various control signals are output from the electronic control unit 30 through an output port. Signals output from the electronic control unit 30 include switching control signals to each transistor of the inverter 24 and switching control signals to two transistors of the boost converter.

In the motor device 20 equipped with the information processing device of the embodiment configured as described above, switching control of each transistor of the inverter 24 is performed by pulse width modulation control (PWM control) so that the motor 22 is driven by the torque command Tm*. . Further, the target voltage VH* of the high-voltage power line 25 is set so that the motor 22 can be driven by the torque command Tm*, and the boost converter 26 is set so that the voltage VH of the high-voltage power line 25 becomes the target voltage VH*. performs switching control of the two transistors of .

Next, the operation of the motor device 20 equipped with the information processing device for motor control according to the embodiment configured as described above, in particular, the operation of detecting an abnormality in the shared memory 40 will be described. FIG. 2 is a flowchart showing an example of a periodic processing routine executed by the processor core 34a of the multicore processor 32. As shown in FIG. The periodic processing routine is executed every predetermined time X (for example, every several milliseconds).

When the periodic processing routine is executed, the processor core 34a refers to the timer value T of the timer 42 and executes processing for acquiring the start time T1s of the periodic processing (step S100).

Next, a torque command Tm* for the motor 22 is set and written in the shared memory 40 (step S110). When the motor device 20 is mounted on an electric vehicle, the torque command Tm* is a required torque required for traveling to the drive shaft connected to the drive wheels through the axle based on the accelerator opening and the vehicle speed. is set to be output.

Subsequently, a carrier voltage cycle (hereinafter referred to as a “carrier cycle”) Tc (reciprocal of the carrier frequency fc) for PWM control of the inverter 24 is set and written in the shared memory 40 (step S120). The period Tc is set to a constant period in a low rotation speed region where the rotation speed Nm of the motor 22 is equal to or lower than a predetermined rotation speed Nref (for example, 2000 rpm, 2500 rpm, 3000 rpm, etc.). The period Tc is shortened when the rotation speed Nm is high compared to when the rotation speed Nm is low in the middle to high rotation speed region where the rotation speed Nm is higher than the predetermined rotation speed Nref, that is, the higher the rotation speed Nm, the shorter the period Tc. is set to Note that the rotation speed Nm of the motor 22 is calculated by the processor core 34b from the rotational position θm stored in the shared memory 40 and read out from the shared memory 40 .

After setting the carrier cycle Tc in this manner, it is determined whether the carrier cycle Tc is constant (no change over time) (step S130) and whether the carrier frequency fc is a switching point (step S140). In step S130, the carrier period Tc (hereinafter referred to as "previous period Tcpre") written in the shared memory 40 when the previous periodic processing routine was executed is set in step S120 of the current periodic processing routine. When the carrier cycle Tc matches, it is determined that the carrier cycle Tc is constant. In step S140, the absolute value of the difference between the rotation speed Nm of the motor 22 and the predetermined rotation speed Nref, which is the threshold value for switching between the low rotation speed region and the middle to high rotation speed region, is determined as the determination threshold value dNm (for example, 80 rpm, 100 rpm, 120 rpm), it is determined that the carrier frequency fc is the switching point.

When the carrier cycle Tc is constant in step S130 and the carrier frequency fc is not the switching point in step S140, it is determined that the carrier cycle Tc does not change for a while, and is shared in the feedback processing executed by the processor core 34b. The start time T2s stored in the memory 40 is obtained (step S150). Here, feedback processing will be described.

FIG. 3 is a flow chart showing an example of a feedback processing routine executed by the processor core 34b. The feedback processing routine is executed every carrier cycle Tc (for example, several hundred microseconds).

When the feedback process routine is executed, the processor core 34b refers to the timer value T of the timer 42 and executes the process of acquiring the start time T2s of the feedback process (step S300). Next, the immediately preceding start time T2sjb is written into one of the shared buffers 40a to 40c of the shared memory 40 (step S310).

Then, it generates a PWM signal for controlling switching of each transistor of the inverter 24 (step S320). A method of generating the PWM signal is as follows. The processor core 34b uses the electrical angle θe of the motor 22 based on the rotational position θm to convert the phase currents Iu (=0−Iv−Iw), Iv, and Iw of the U, V, and W phases to the d- and q-axes. The currents Id and Iq are subjected to coordinate conversion (three-phase to two-phase conversion). Subsequently, based on the torque command Tm* of the motor 22, the d-axis and q-axis current commands Id* and Iq* are set. Then, the d-axis and q-axis voltages are adjusted by current feedback control so that the differences ΔId1 and ΔIq1 between the d-axis and q-axis current commands Id1* and Iq1* and the d-axis and q-axis currents Id1 and Iq1 approach the value 0. Set commands Vd* and Vq*. Then, using the electrical angle θe of the motor 22, the d-axis and q-axis voltage commands Vd* and Vq* are coordinate-converted (two-phase to three-phase conversion) into voltage commands Vu*, Vv* and Vw* for each phase. , voltage commands Vu*, Vv*, Vw* of each phase and a triangular wave (carrier wave, carrier) voltage to generate a PWM signal for each transistor of the inverter 24 .

When the PWM signal is generated, switching control of each transistor of the inverter 24 is executed using the generated PWM signal (step S330), and the feedback process ends.

The execution interval (carrier cycle Tc) of the feedback processing routine executed by the processor core 34b is shorter than the execution interval (predetermined time X) of the periodic processing routine executed by the processor core 34a. Therefore, the feedback processing routine is executed a plurality of times while the periodic processing routine is executed once, and the shared buffers 40a to 40c of the shared memory 40 are stored a plurality of times while the periodic processing routine is executed once. Time T2s is written. Step S150 of the periodic processing routine illustrated in FIG. to get as

When the immediately preceding start time T2sjb is obtained in step S150, an idle period in which each step of the fixed period processing routine and the feedback processing routine is not executed is set as the checkable period T3(l) (n is a natural number), and the checkable period T3 is set. (l) is written in the shared memory 40 (step S160). The method of deriving the vacant period is as follows. The end time T1e of the current periodic processing routine is calculated from the required time T1ref. Next, from the immediately preceding start time T2sjb acquired in step S150, the time required to end steps S300 to S330 of the predetermined feedback processing routine, and the execution interval (carrier cycle Tc) of the feedback processing routine, A period T2exe(m) during which the feedback processing routine is executed until time T1ns (=T1s+X) before the periodic processing routine is started is calculated. “m” is an integer with a value of 0 or greater. Since the feedback process routine is executed one or more times while the periodic process routine is executed once, one or more periods T2exe are set. A period other than the period T2exe from the end time T1e of each process of the periodic processing routine to the start time T1ns of the next periodic processing routine is defined as a checkable period T3(l) (l is a natural number). "l" is an integer with a value of 0 or greater.

When the checkable period T3(l) is set in this way, the storage capacity (determination capacity) Mc of the shared memory 40 to be subjected to one abnormality determination and the area to be subjected to abnormality determination are calculated for each checkable period T3(l). (Determination area) Ac is set and written in the shared memory 40 (step S170), the check availability flag Fc is set to 1 and written in the shared memory 40 (step S180), and the periodic processing routine ends. . In step S<b>170 , the determination area Ac sets the priority for executing the abnormality determination in advance for the data stored in the shared memory 40 .

FIG. 4 is an explanatory diagram showing an example of the relationship between priority and data type. In the embodiment, the priority is set in five levels of priority 1 to 5 in descending order of priority.

The data with the highest priority "priority 1" includes information that relatively strongly contributes to the output of PWM control, such as torque command Tm*, rotation speed Ne of motor 22, carrier frequency fc, generated PWM signal. Output commands, voltage commands Vu*, Vv*, Vw* for each phase, current commands Id*, Iq* for d-axis and q-axis, phase currents Iv, Iw for V-phase and W-phase, electrical angle θe of motor 22, etc. can be mentioned. In addition, the vector phase and vector amplitude of the command voltage based on the d-axis and q-axis voltage commands Vd* and Vq*, the voltage VH of the high-voltage side power line 25, and the carrier period Tcd when PWM-controlling the boost converter 26 etc. can be mentioned.

As the data of "priority 2", information that contributes to the output of PWM control but is less contributing to the output of PWM control than the information of priority 1, for example, voltage commands Vd* of d-axis and q-axis, Vq*, the voltage VL of the low-voltage side power line 27, the reactor current flowing through the reactor of the boost converter 26, and the like can be mentioned. In addition, current sampling magnification, which is the number of times of current sampling for each half cycle, torque estimation value obtained using a map from d-axis and q-axis currents Id and Iq, target voltage VH*, PWM control mode, square wave When the inverter 24 is controlled in one of a plurality of control modes such as control, the control state, which is information about which control mode the inverter 24 is controlled in, can be cited.

Data of "priority 3" can include temperature and state flags detected by various sensors. The temperature detected by various sensors includes the cooling water temperature from a temperature sensor that detects the temperature of the cooling water for cooling the inverter 24, the element temperature from a temperature sensor that detects the temperature of the transistor that constitutes the inverter 24, and the like. can be mentioned. Examples of the state flag include a rotational speed sudden change state flag indicating whether or not the rotational speed Ne of the motor 22 is suddenly changing, a shift position from a shift position detection sensor, and the like.

The data of "priority 4" can be information used for learning. The information used for learning includes the offset value obtained by learning the offset value of the rotational position detection sensor 22a that detects the rotation speed of the motor 22, the implementation state of the learning, and the phase currents Iv and Iw of the V-phase and W-phase. offset values obtained by learning the offset values of the current sensors 22b and 22c for detecting , the implementation state of the learning, and the implementation state of the learning of the offset values of the temperature sensor.

Data of “priority 5” may include information indicating an abnormal state of the motor device 20 . Examples of information indicating an abnormal state include an abnormal state of a cooling system that cools the motor 22 and the inverter 24, and various other abnormal states.

If the carrier cycle Tc is not constant in step S130, or if the carrier frequency fc is the switching point in step S140 even if the carrier cycle Tc is constant in step S130, there is a high possibility that the carrier cycle Tc will change in the future. There is a high possibility that the vacant period in which each step of the periodic processing routine and the feedback processing routine is not executed cannot be properly calculated using the immediately preceding start time T2sjb. In this case, the checkability flag Fc is set to 0 and written to the shared memory 40 (step S190), the checkable period T3(l) is initialized (step S200), and the periodic processing routine ends.

FIG. 5 is a flowchart showing an example of an abnormality determination processing routine executed by the processor core 34c. The abnormality determination processing routine is repeatedly executed at the same cycle as the carrier cycle Tc when the above-described check availability flag Fc is set to 1.

When the abnormality determination processing routine is executed, the processor core 34c executes processing to read the checkable period T3(l) written in the shared memory 40 (step S400). Then, by referring to the timer value T of the timer 42, it is determined whether or not it is the checkable period T3(l) (step S410). If the current time is not the checkable period T3(l), the abnormality determination processing routine is terminated.

When it is the checkable period T3(l) in step S410, it is determined whether or not there is an abnormality in the determination capacity Mc and the determination area Ac of the shared memory 40 corresponding to the checkable period T3(l). Abnormality determination is performed (step S420). The abnormality determination is performed by the following method, assuming that an abnormality (memory sticking) in which data stored in the shared memory 40 cannot be rewritten is determined. First, the data stored in the determination area Ac of the shared memory 40 is read by the determination capacity Mc and saved in the register 36a. Subsequently, the confirmation data Dc is written in the determination area Ac from which the data has been read. The confirmation data Dc is predetermined data for checking the shared memory 40 . Then, the data Dr is read from the determination area Ac to the register 36b, and the confirmation data Dc and the data Dr read from the register 36b are compared. When the determination area Ac is normal, the confirmation data Dc and the data Dr match. Therefore, when the confirmation data Dc and the data Dr match, it is determined that the shared memory 40 is normal, and when the confirmation data Dc and the data Dr do not match, an abnormality (memory sticking) occurs in the shared memory 40. It is determined that After that, the original data saved in the register 36 a is returned to the determination area Ac of the shared memory 40 .

When the data in the determination capacity Mc stored in the determination area Ac of the shared memory 40 is normal in step S420 (step S430), the abnormality determination processing routine is terminated.

In step S420, when an abnormality occurs in the data of the determination capacity Mc stored in the determination area Ac of the shared memory 40 (step S430), a predetermined process executed when the shared memory 40 has an abnormality Diagnosis determination processing is executed (step S440), and the abnormality determination processing routine ends.

FIG. 6 is a timing chart showing an example of operations of the processor cores 34a-34c. In the figure, the hatched areas in the "periodic processing routine" indicate the period during which steps S130 and S140 of the periodic processing routine are executed and the period during which step S180 is executed. The hatched area of "checkable period (T3(l))" indicates the period set as the checkable period T3(l) in the periodic processing routine. A hatched area in the “abnormality determination processing routine” indicates a period during which the abnormality determination processing routine is executed.

When the feedback processing routine of the processor core 34b is executed, as shown in the figure, the time when the execution of the feedback processing routine is started is stored in the shared buffers 40a to 40c of the shared memory 40 each time it is executed (every carrier cycle Tc). (T2s(m), T2s(m+1), T2s(m+2), etc. in the figure) are written.

In the constant cycle processing routine of the processor core 34a, when the carrier cycle Tc changes from the previous value (when it changes from the cycle T1 to the cycle T2 in the figure), the check availability flag Fc is set to the value 0 (step S190). ). When the check availability flag Fc is set to 0, the abnormality determination routine for the processor core 34c is not executed, so the abnormality determination for the shared memory 40 is not executed.

When the carrier cycle Tc is constant (when the carrier cycle Tc2 is constant), the immediately preceding start time T2sjb (T2s(m+7) in the figure) written in the shared buffer of the shared memory 40 immediately before step S150 is executed. (step S150), set the checkable period T3(l) (n is a natural number) in the shared memory 40 to an idle period during which each step of the periodic processing routine and the feedback processing routine is not executed, and set the checkable period T3(l) is written in the shared memory 40 (step S160), the determination capacity Mc and the determination area Ac are set (step S170), and the check availability flag Fc is set to 1 (step S180). When the checkability flag Fc is set to a value of 1, the abnormality determination routine of the processor core 34c is executed, and the high-priority data illustrated in FIG. The abnormality determination processing routine is executed in order from the storage area in which is stored. In this way, during an idle period during which the carrier cycle Tc is constant or the carrier frequency fc is not changed, and the processor cores 34a and 34b are not executing the fixed cycle processing routine and the feedback processing, the processor core 34c executes the abnormality determination of the shared memory 40, it is possible to avoid conflict between the access to the shared memory 40 of the processor cores 34a and 34b and the access to the shared memory 40 of the processor core 34c. In addition, since the abnormality determination is executed in order from the storage area in which the data with the highest priority is stored in the storage area of the shared memory 40, the motor device 20 or the electric vehicle equipped with the motor device 20 can be operated more appropriately. can be made

According to the information processing apparatus for motor control of the embodiment described above, the processor core 34c has a constant carrier period (control period) Tc, and the period from the end of the feedback process to the start of the next feedback process. By executing the abnormality determination of the shared memory 40 during the idle period, it is possible to avoid conflict between the access to the shared memory 40 by the processor core 34b and the access to the shared memory 40 by the processor core 34c.

In the information processing apparatus for motor control of the embodiment, the processor core 34a performs abnormality determination in order from the storage area of the memory in which the data with the highest priority is stored. However, it is possible to appropriately determine which area of the shared memory 40 the abnormality determination is to be performed in order, such as executing the abnormality determination in order from the area with the smallest address in the shared memory 40 without considering the priority. can. Moreover, it is not necessary to perform the abnormality determination for all areas of the shared memory 40, and it is possible to perform the abnormality determination only for a predetermined partial area of the shared memory 40. FIG.

In the information processing apparatus for motor control of the embodiment, the PWM control of the inverter 24 is shared between the processor cores 34a and 34b, but the processor core 34b may perform all the processing. The above processor cores may share and execute.

In the embodiments, the information processing device for motor control of the present invention is applied to the motor device 20 mounted on the electric vehicle, but it is applied to the motor device 20 mounted on another device other than the electric vehicle. Alternatively, it may be applied to the motor device 20 alone.

The correspondence relationship between the main elements of the embodiments and the main elements of the invention described in the column of Means for Solving the Problems will be described. In the embodiment, the multi-core processor 32 corresponds to the "multi-core processor", the shared memory 40 corresponds to the "memory", the processor core 34b corresponds to the "control-side processor core", and the processor core 34c corresponds to the "determining-side processor core". Equivalent to

Note that the correspondence relationship between the main elements of the examples and the main elements of the invention described in the column of Means for Solving the Problems is the Since it is an example for specifically explaining the mode for solving the problem, it does not limit the elements of the invention described in the column of the means for solving the problem. That is, the interpretation of the invention described in the column of Means to Solve the Problem should be made based on the description in that column, and the Examples are based on the description of the invention described in the column of Means to Solve the Problem. This is only a specific example.

Although the embodiments for carrying out the present invention have been described above, the present invention is not limited to such embodiments at all, and can be modified in various forms without departing from the scope of the present invention. Of course, it can be implemented.

INDUSTRIAL APPLICABILITY The present invention is applicable to the manufacturing industry of information processing devices for motor control.

20 motor device, 22 motor, 22a rotational position detection sensor, 22b, 22c current sensor, 24 inverter, 25 high-voltage power line, 25a, 27a voltage sensor, 26 boost converter, 27 low-voltage power line, 26 boost converter, 28 battery, 30 electronic control unit, 32 multi-core processor, 32a, 32b, 32c processor cores, 36a, 36b registers, 40 shared memory, 40a shared buffer, 42 timer, 50 bus.

Claims (1)

a multi-core processor and
a memory accessed by the multi-core processor;
An information processing device for motor control used for controlling a motor, comprising:
The multi-core processor is
a control-side processor core that repeatedly executes a predetermined control process for controlling the motor in each control cycle based on the number of revolutions of the motor while accessing the memory;
After writing predetermined data to an inspection target area of the memory, data is read from the inspection target area, and the predetermined data and the read data are compared to determine whether or not an abnormality has occurred in the memory. a judgment-side processor core that executes an abnormality judgment to
has
The judging-side processor core has a constant control cycle, and the control-side processor core detects the abnormality during an idle period from when the control-side processor core ends the predetermined control processing to when it next starts the predetermined control processing. carry out the judgment
Information processing device for motor control.

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