JP7162559B2 - Wafer polishing method and wafer polishing apparatus - Google Patents

Description

The present invention relates to a wafer polishing method and a wafer polishing apparatus.

Patent Documents 1 and 2 disclose conventional wafer polishing methods. These wafer polishing methods use a wafer polishing apparatus having a surface plate and a carrier to polish a wafer by CMP (Chemical Mechanical Polishing). The platen has a polishing pad extending in a direction orthogonal to the first axis and is rotated around the first axis. The carrier has a fixing surface extending in a direction orthogonal to a second axis parallel to the first axis and facing the polishing pad. The carrier has a fixed surface on which a wafer is fixed, and the wafer and polishing pad are rotated about the second axis under a predetermined surface pressure.

Wafers such as silicon have a first center point, which is the center of the arc, as well as a reference edge consisting of an orientation flat or notch that indicates the direction of the crystallographic axis. In the wafer polishing method of Patent Document 1, when a first center point and a second center point, which is the center of the reference edge, are assumed with respect to the fixed surface of the carrier, the second axis is moved away from the second center point. there is Further, in the wafer polishing method of Patent Document 2, when a single wafer polishing apparatus performs a plurality of polishing steps, the holding position of the wafer is rotated for each step with respect to the fixed surface of the carrier.

According to these wafer polishing methods, wafers with orientation flats or notches can be polished to high flatness and high parallelism.

Japanese Patent Publication No. 7-38381 Japanese Patent No. 3978780

However, according to the test results of the inventors, in the conventional wafer polishing method, when the wafer is a SiC single crystal and the outermost surface is tilted with respect to the crystal axis, When the wafer is a SiC single crystal having an off-angle, scratches are likely to occur depending on the fixed position on the fixed surface.

The present invention has been made in view of the above conventional circumstances, and when the wafer is an SiC single crystal having an off angle, the wafer is polished to high flatness and high parallelism with a low scratch rate. This is an issue that should be resolved.

A wafer polishing method of the present invention is a wafer polishing method for polishing a wafer by a CMP method using a wafer polishing apparatus,
The wafer polishing apparatus has a polishing pad extending in a direction orthogonal to a first axis, a surface plate rotated around the first axis, and a second axis parallel to the first axis and orthogonal to the second axis. a carrier having the wafer fixed to a fixed surface facing the polishing pad and extending in a direction extending in a direction facing the polishing pad, and rotating the wafer and the polishing pad around the second axis under a predetermined surface pressure;
The wafer has a first center point that is the center of an arc, a reference edge that is an orientation flat or a notch, and is made of a SiC single crystal having an off angle ,
The wafer is fixed to the fixing surface such that the first center point is separated from the second axis and the reference edge faces outward from the second axis.

Further, the wafer polishing apparatus of the present invention has a polishing pad extending in a direction orthogonal to a first axis, and is rotated around the first axis;
a carrier that extends in a direction perpendicular to a second axis parallel to the first axis and has a wafer fixed to a fixing surface facing the polishing pad and rotated about the second axis;
The wafer has a first center point that is the center of an arc, a reference edge that is an orientation flat or a notch, and is made of a SiC single crystal having an off angle ,
The wafer is fixed to the fixing surface such that the first center point is separated from the second axis and the reference edge faces outward from the second axis.

According to the test results of the inventors, when the wafer is polished by the CMP method with the posture of the wafer fixed on the fixing surface as described above, the rate of occurrence of scratches decreases. If the wafer posture is set as described above, polishing can be performed in a direction that causes less damage to the step terrace resulting from the off-angle of the wafer made of SiC single crystal, so excessive polishing of the wafer can be reduced. I think it's for the sake of

Therefore, according to the wafer polishing method and wafer polishing apparatus of the present invention, when the wafer is an SiC single crystal having an off-angle, the wafer can be polished to high flatness and high parallelism with a low scratch rate. can.

Further, according to the wafer polishing method and the wafer polishing apparatus of the present invention, the step terrace of the wafer made of SiC single crystal can be stably polished, and stable workability can be exhibited by stabilizing the polishing efficiency. be able to.

A first imaginary line is assumed on the fixed surface with the second axis as the coordinate center and connecting the first center point and the second center point, which is the center of the reference edge. Also assume a second imaginary line extending from the second axis toward the first center point. Assuming that the second virtual line is the y-axis toward the coordinate center, and the y-axis is the coordinate center and is orthogonal to the x-axis, the first virtual line is located in the first and second quadrants. preferably. According to the test results of the inventors, the scratch rate is low in this case.

The first imaginary line is preferably located on y=ax+b (-1<a<1, b>0) assumed in the xy coordinates. According to the inventors' test results, the scratch rate is lower in this case.

Most preferably, the first virtual line is located on the y-axis. In this case, the scratch occurrence rate is the lowest.

A plurality of wafers are preferably fixed to the fixing surface around the second axis. In this case, since a plurality of wafers can be polished simultaneously on one fixing surface, high workability can be exhibited. Further, when the wafer polishing apparatus has a plurality of carriers for one surface plate, it is more preferable to fix a plurality of wafers to the fixing surface of each carrier.

When performing the CMP method, a polishing liquid containing abrasive particles can be supplied between the polishing pad and the wafer while employing a polishing pad such as a non-woven fabric having no abrasive particles. However, it is preferable that the polishing pad is of a free abrasive grain type, which is made of resin and has a base material in which a plurality of air bubbles are formed and abrasive particles held in the air bubbles. Further, it is preferable to supply a polishing liquid containing no abrasive particles between the polishing pad and the wafer. In this case, the abrasive particles are less likely to damage the surface of the wafer, and the wafer is less likely to scratch.

According to the wafer polishing method and wafer polishing apparatus of the present invention, when the wafer is a SiC single crystal having an off-angle, the wafer can be polished to high flatness and high parallelism with a low scratch rate.

FIG. 1 is a side view of the essential parts of the wafer polishing apparatus used in the test. FIG. 2 is a plan view of a fixing surface on the carrier; FIG. 3 is an explanatory diagram for explaining the fixed surface of the carrier and the posture of the wafer. FIG. 4 is an explanatory diagram for explaining the fixed surface of the carrier and the posture of the wafer. FIG. 5 is an explanatory diagram for explaining the fixed surface of the carrier and the posture of the wafer.

The present invention will now be illustrated by tests. The wafer polishing apparatus used for the test comprises a surface plate 1 and a carrier 3, as shown in FIG.

A polishing pad 5 is provided on the upper surface of the platen 1 . The surface plate 1 is rotated at a predetermined speed around the first axis O1 by a first rotating shaft 7 extending in the direction of the first axis O1. Polishing pad 5 extends in a direction perpendicular to first axis O1. Specifically, the first axis O1 extends vertically, and the polishing pad 5 extends horizontally. A nozzle 9 is arranged on the polishing pad 5 . The nozzle 9 is connected to a tank (not shown) that stores the polishing liquid.

The carrier 3 has a fixing surface 3a facing the polishing pad 5. As shown in FIG. The carrier 3 is rotated at a predetermined speed around the second axis O2 by a second rotating shaft 11 extending in the direction of the second axis O2. The second axis O2 is parallel to the first axis O1. The fixed surface 3a extends in a direction orthogonal to the second axis O2. Specifically, the second axis O2 also extends vertically, and the fixing surface 3a also extends horizontally.

As shown in FIG. 2, three wafers W are fixed to the fixed surface 3a by suction means (not shown). As shown in FIG. 1, the carrier 3 is pressurized toward the surface plate 1 so that each wafer W and the polishing pad 5 have a predetermined surface pressure.

As the polishing pad 5, a polishing body of free abrasive grain type, which is composed of a polysulfone-based resin base material and silica polishing particles held in air bubbles of the base material, is employed. The abrasive particles of this polishing pad 5 have an average particle diameter of 0.005 to 3 μm, a volume ratio of 20 to 50% by volume with respect to the polishing body, and a mass ratio of 51 to 90% by weight with respect to the polishing body. Specifically, the polishing pad 5 is a product name "LHA (Loosely Held Abrasive) pad" manufactured by Noritake Co., Ltd.

Each wafer W is made of SiC single crystal. Each wafer W has a first center point A, which is the center of the arc, and an orientation flat B as a reference edge, as shown in FIG. Each wafer W has its outermost surface inclined by 4° with respect to the crystal axis. That is, the off angle of each wafer W is 4°. The dimensions of the wafer W used in the test are 4 (inch) in diameter and 300 to 400 (μm) in thickness.

A first imaginary line L1 connecting a first center point A and a second center point B0, which is the center of the orientation flat B, with the second axis O2 as the coordinate center O on the fixed surface 3a is assumed. The first center point A is spaced apart from the second axis O. Also, a second virtual line L2 extending from the second axis O2 toward the first center point A is assumed. Then, it is assumed that the second virtual line L2 is the y-axis directed toward the coordinate center O, and that the y-axis is the coordinate center O and the x-y coordinates that are perpendicular to the x-axis.

As shown in FIG. 4B, the position of the orientation flat B is defined as the angle θ (°) formed by the first imaginary line L1 and the y-axis in the xy-coordinates. Tests 1 to 7 were performed with θ set to −180, −90, −45, 0, 45, 90 or 180 under the following conditions. The number of test items is one at each angle.

Surface plate rotation speed: 35 (rpm)
Polishing pad size: diameter 910 (mm)
Carrier rotation speed: 35 (rpm)
Processing surface pressure: 300 (gf/cm ² )
Polishing liquid: KMnO4-based polishing liquid (concentration 0.25 mol, pH = 3)
Polishing liquid supply timing: 700 ml/min Polishing time: 2 hours

The number of scratches at each position of the orientation flat B, surface roughness Sa (nm) (ISO25178) and polishing efficiency index were determined. Table 1 shows the results. Here, the presence or absence of scratches was confirmed with a hybrid laser microscope (manufactured by OPTELCS HYBRID Lasertec). Further, the index of polishing efficiency represents the ratio of the time required for the wafer W to have high flatness and high parallelism in Test 1 with θ=−180 (°).

As shown in Table 1, when the position θ of the orientation flat B is -90 to 90°, the number of scratches is small. In these postures of the wafer W, as shown in FIGS. 4A to 4C, the first imaginary line L1 is located in the first and second quadrants in the xy coordinates. This is because, in these postures, the orientation flat B faces outward when viewed from the second axis O2, so the wafer W is polished in a direction that causes less damage to the step terrace resulting from the off-angle. This is considered to be because it is possible to perform

In particular, if the position θ of the orientation flat B is -45° to 45°, no scratch occurs. As shown in FIGS. 5A and 5B, these attitudes of the wafer W are such that the first imaginary line L1 is on y=ax+b (−1<a<1, b>0) on the xy coordinates. located in

More particularly, when the position θ of the orientation flat B is 0°, no scratches occur and the surface roughness is the lowest. In this posture of the wafer W, as shown in FIG. 3, in the xy coordinates, the first imaginary line L1 is positioned on the y axis.

Therefore, according to the wafer polishing methods of Tests 2 to 6, when the wafer W is a SiC single crystal having an off-angle, the wafer W can be polished to high flatness and high parallelism with a low scratch rate. I know you can.

Further, according to the wafer polishing methods of Tests 2 to 6, stable polishing can be performed on the step terrace of the wafer W made of SiC single crystal, and stable workability can be exhibited by stabilizing the polishing efficiency. It is also possible to

In the above, the present invention has been described in terms of tests, but it is needless to say that the present invention is not limited to the above tests, and can be appropriately modified and applied without departing from the spirit of the present invention.

For example, in the above test, the off-angle of the wafer W made of SiC single crystal was 4°, but the off-angle of the wafer W may be 8° or less than 4°. In the above test, the wafer was polished using the orientation flat B as the reference edge, but it is also possible to polish a larger wafer W using the notch as the reference edge.

In the above test, three wafers W were fixed to the fixing surface 3a and polished at the same time, so that high workability was exhibited. By adopting other means of the present invention while separating the first center point A from the second axis O, the effects of the present invention can be obtained.

Furthermore, in the above test, the base material of the polishing pad 5 was made of polysulfone resin and the abrasive particles were made of silica, but the base material and abrasive particles are not limited to these. For example, the base material of the polishing pad 5 includes epoxy resin, polyurethane resin, polyethersulfone (PES) resin, polyvinyl fluoride, vinyl fluoride-hexafluoropropylene copolymer, polyvinylidene fluoride, and vinylidene fluoride.・It is possible to adopt fluorine-based synthetic resin such as hexafluoropropylene copolymer, polyethylene resin, polymethyl methacrylate, and the like. The abrasive grains of the polishing pad 5 include diamond, CBN (cubic boron nitride), B ₄ C (boron carbide), silicon carbide, ceria, alumina, zirconia, titania, manganese oxide, barium carbonate, and chromium oxide. , iron oxide, etc. can be employed.

In addition, in the present invention, a polishing liquid containing abrasive particles can be supplied between the polishing pad and the wafer while employing a polishing pad such as a non-woven fabric that does not have abrasive particles.

INDUSTRIAL APPLICABILITY The present invention can be used for semiconductor manufacturing methods, semiconductor manufacturing apparatuses, and the like.

W... Wafer O1... First axis 5... Polishing pad 1... Surface plate O2... Second axis 3a... Fixed surface 3... Carrier A... First center point B... Orientation flat, reference edge 0... Coordinate center B0... No. 2 center points L1... First virtual line L2... Second virtual line

Claims (7)

A wafer polishing method for polishing a wafer by a CMP method using a wafer polishing apparatus,
The wafer polishing apparatus has a polishing pad extending in a direction orthogonal to a first axis, a surface plate rotated around the first axis, and a second axis parallel to the first axis and orthogonal to the second axis. a carrier having the wafer fixed to a fixed surface facing the polishing pad and extending in a direction extending in a direction facing the polishing pad, and rotating the wafer and the polishing pad around the second axis under a predetermined surface pressure;
The wafer has a first center point that is the center of an arc, a reference edge that is an orientation flat or a notch, and is made of a SiC single crystal having an off angle ,
The wafer is fixed to the fixing surface such that the first center point is separated from the second axis and the reference edge faces outward from the second axis. polishing method. Assuming a first imaginary line connecting the first center point and a second center point, which is the center of the reference edge, with the second axis as the coordinate center on the fixed surface,
Assuming a second imaginary line extending from said second axis towards said first center point,
Assuming that the second virtual line is the y-axis toward the coordinate center, and the y-axis is an x-y coordinate orthogonal to the x-axis at the coordinate center,
2. The wafer polishing method according to claim 1, wherein said first virtual line is located in a first quadrant and a second quadrant. 3. The wafer polishing method according to claim 2, wherein said first imaginary line is located on y=ax+b (-1<a<1, b>0) assumed for said xy coordinates. 4. The wafer polishing method according to claim 3, wherein said first virtual line is positioned on said y-axis. 5. The wafer polishing method according to claim 1, wherein a plurality of said wafers are fixed on said fixing surface around said second axis. The polishing pad is made of a resin and is of a free abrasive grain type having a base material in which a plurality of air bubbles are formed and abrasive particles held in the air bubbles,
6. A wafer polishing method according to claim 1, wherein a polishing liquid containing no abrasive particles is supplied between said polishing pad and said wafer. a surface plate having a polishing pad extending in a direction orthogonal to a first axis and rotated around the first axis;
a carrier that extends in a direction perpendicular to a second axis parallel to the first axis and has a wafer fixed to a fixing surface facing the polishing pad and rotated about the second axis;
The wafer has a first center point that is the center of an arc, a reference edge that is an orientation flat or a notch, and is made of a SiC single crystal having an off angle ,
The wafer is fixed to the fixing surface such that the first center point is separated from the second axis and the reference edge faces outward from the second axis. polishing equipment.

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