JP7153479B2 - comparator circuit - Google Patents

Description

The present invention relates to comparator circuits.

2. Description of the Related Art In recent years, a comparator circuit that compares a reference voltage and an input voltage is mounted in an AD conversion circuit used in a drive circuit of a display device or the like. Since a comparator circuit usually has an offset voltage, an offset error occurs in the comparison result of the comparator circuit.

A chopper type comparator circuit is used as a comparator having an offset canceling function. A chopper-type comparator circuit includes, for example, a selector that receives an input voltage signal or a reference voltage signal in response to switching of a switch, an input coupling capacitor connected to an input line from the selector, an N-channel MOS (Metal and an inverter composed of an Oxide Semiconductor) transistor and a P-channel MOS transistor. The gate of each transistor in the inverter is connected to the input coupling capacitance.

In such a comparator circuit, in order to operate the circuit at high speed while canceling the offset, a second amplifier circuit is provided in the path for feedback from the output section of the first amplifier circuit to the input section. A comparator circuit has been proposed in which the amplification factor is set lower than that of the second amplification circuit so that the feedback part from the second amplification circuit is cut off during the comparison operation (for example, Patent Document 1).

JP 2008-178079 A

Since AD conversion circuits used in drive circuits for organic EL devices are required to have high precision, multi-value bit conversion type AD conversion circuits such as 4-bit conversion type pipeline type ADCs (Analog to Digital Converters) are used. is used. Such a multi-value bit conversion type AD conversion circuit requires a large number of comparator circuits, so it is desirable to keep the circuit scale of the comparator circuits small. Also, if the input coupling capacitance is large, the operating speed will be low. Therefore, it is desirable to suppress the circuit scale of each comparator circuit by suppressing the input coupling capacitance as small as possible.

However, when the input coupling capacitance is reduced, the CV characteristics of the transistors that make up the inverter change abruptly in the strong inversion region near the threshold voltage (for example, the capacitance of an N-channel MOS transistor abruptly increases). No charge is stored in the input coupling capacitance. For this reason, when common mode noise is input, there is a problem that a large fluctuation (fluctuation) occurs in the output signal of the inverter, resulting in a determination error.

Methods other than the chopper type include a comparator in which a differential element is connected to a constant current source, but in this method there is an offset caused by Vth variations in the input differential. When constructing a multi-level flash type comparator to improve accuracy, this offset causes an erroneous decision and becomes a factor in lowering the yield.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a comparator circuit capable of accurately correcting an offset while suppressing an increase in circuit size due to an increase in input coupling capacitance.

A comparator circuit according to the present invention compares a reference voltage consisting of a pair of voltages having the same absolute value but different polarities with an input voltage consisting of a pair of voltages having the same absolute value but different polarities, and outputs a comparison result. A circuit having an input receiving a first voltage and a second voltage corresponding to the voltage pair of the reference voltage or the input voltage, and a first input holding a charge based on the first voltage. an input capacitor pair consisting of a capacitor and a second input capacitor that holds a charge based on the second voltage; and a first input differential element connected to the first input capacitor and the second input capacitor. an input differential pair of connected second input differential elements for converting said first voltage into a first current through said first input differential element and said second voltage. into a second current flowing through the second input differential element; and a first current for sending a current having a current amount corresponding to the first current to a first current path a mirror section, a second current mirror section for transmitting a current having a current amount corresponding to the second current to the second current path, and a first node connected to the first current path. and a current corresponding to the voltage of the second node and connected to the second current path via a first correction differential element through which a current corresponding to the voltage of the first node flows and a second node and an offset correction unit including an offset correction differential pair formed of a second correction differential element through which a current flows ; and the first current and the second current when the voltage pair forming the input voltage are input to the input section as the first voltage and the second voltage. a second current, and a comparator that compares the reference voltage and the input voltage based on the first current mirror and the second current mirror, wherein the first current mirror and the second current mirror are configured to perform the first correction. A current flowing through the differential element is fed back to the first input differential element, and a current flowing through the second correction differential element is fed back to the second input differential element .

According to the comparator circuit of the present invention, it is possible to accurately correct the offset while suppressing the circuit scale.

2 is a circuit diagram showing the configuration of a comparator circuit of this embodiment; FIG. 4 is a time chart showing temporal changes of voltages in the comparator circuit of the embodiment; 3 is a circuit diagram showing the configuration of a comparator circuit of a comparative example; FIG. 10 is a time chart showing changes over time of voltages in a comparator circuit of a comparative example; 8 is a circuit diagram showing the configuration of a comparator circuit of Example 2; FIG.

Preferred embodiments of the present invention are described in detail below. In the following description of each embodiment and the attached drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

The comparator circuit 100 of this embodiment is mounted in an AD conversion circuit used in a drive circuit or the like of an organic EL display device. A comparator circuit 100 compares a reference voltage and an input voltage and outputs a comparison result.

FIG. 1 is a circuit diagram showing the configuration of a comparator circuit 100 of this embodiment. The comparator circuit 100 includes a selector 11, a voltage-current conversion section 12, an input equalizer 13, a first current mirror section 14, a second current mirror section 15, an offset correction section 16, a first current mismatch detection circuit 17, and a second current mismatch detection. It is composed of a circuit 18 and a comparison section 19 .

Reference voltage signals REFP and REFN, which are a pair of voltages having the same absolute value but different polarities, are supplied to the comparator circuit 100 as reference voltages. Input voltage signals INP and INN, which are a pair of voltages having the same absolute value but different polarities, are supplied as input voltages to the comparator circuit 100 .

Selector 11 includes transistors M1, M2, M3 and M4. The transistors M1, M2, M3 and M4 are composed of, for example, N-channel MOS transistors of the second conductivity type.

An input voltage signal INP is input to the source of the transistor M1. The transistor M1 receives at its gate the comparison control signal H3CK whose signal level changes to logic level 0 or 1, and is turned on or off according to the signal level of the comparison control signal H3CK. By turning on the transistor M1, the input voltage signal INP is supplied to the voltage-current converter 12 through the drain of the transistor M1.

An input voltage signal INN is input to the source of the transistor M2. The transistor M2 receives the comparison control signal H3CK at its gate, and is turned on or off according to the signal level of the comparison control signal H3CK. By turning on the transistor M2, the input voltage signal INN is supplied to the voltage-current converter 12 via the drain of the transistor M2.

A reference voltage signal REFP is input to the source of the transistor M3. The transistor M3 receives at its gate the equalization control signal S3CK whose signal level changes to logic level 0 or 1, and is turned on or off according to the signal level of the equalization control signal S3CK. By turning on the transistor M3, the reference voltage signal REFP is supplied to the voltage-current converter 12 via the drain of the transistor M3.

A reference voltage signal REFN is input to the source of the transistor M4. The transistor M4 receives the equalization control signal S3CK at its gate, and is turned on or off according to the signal level of the equalization control signal S3CK. By turning on the transistor M4, the reference voltage signal REFN is supplied to the voltage-current converter 12 via the drain of the transistor M4.

The equalize control signal S3CK and the comparison control signal H3CK become logic level 1 at different timings. When the equalize control signal S3CK is at logic level 1, the reference voltage signals REFP and REFN are supplied to the voltage-current converter 12 . When the comparison control signal H3CK is at logic level 1, the input voltage signals INP and INN are supplied to the voltage-current converter 12 .

In this manner, the selector 11 switches the voltage signals input to the comparator circuit 100 between the input voltage signals INP and INN and the reference voltage signals REFP and REFN according to the signal levels of the control signal H3CK and the control signal S3CK. That is, the selector 11 selects a first voltage and a second voltage (reference voltage signals REFP and REFN) corresponding to a voltage pair of reference voltages or a first voltage and a second voltage (input voltage signal (INP and INN).

The voltage-current converter 12 includes transistors M5, M6 and M7. The transistors M5, M6 and M7 are composed of, for example, N-channel MOS transistors. Further, the current converter 12 includes capacitors C1 and C2.

The source of the transistor M5 is connected to the ground line (ground potential VSS). A bias voltage BIAS2 is supplied to the gate of the transistor M5. The transistor M5 is a constant current source that supplies a constant current according to the bias voltage BIAS2. The transistor M5 has a function of limiting the current so that a large current does not flow through the transistors M6 and M7.

Transistors M 6 and M 7 form an input differential pair 21 . The sources of transistor M6 and transistor M7 are connected together and to the drain of transistor M5.

Capacitor C1 has one end connected to the drains of transistors M1 and M3 and the other end connected to the gate of transistor M6. The capacitor C2 has one end connected to the gate of the transistor M7 and the other end connected to the drains of the transistors M2 and M4. Capacitors C1 and C2 function as input coupling capacitors that hold charges based on the reference voltage signals REFP and REFN input via the selector 11 and the input voltage signals INP and INN.

Input equalizer 13 includes transistors M10 and M11. The transistors M10 and M11 are, for example, N-channel MOS transistors.

The drain of transistor M10 is connected to the connection node between the other end of capacitor C1 and the gate of transistor M6. The drain of transistor M11 is connected to the connection node between the other end of capacitor C2 and the gate of transistor M7. A bias voltage BIAS1 is supplied to the sources of each of the transistors M10 and M11.

The transistors M10 and M11 receive the equalization control signal S3CK at their gates, and are turned on or off according to the signal level of the equalization control signal S3CK. Bias voltage BIAS1 is applied to capacitor C1 by turning on transistor M10. Similarly, turning on transistor M11 provides bias voltage BIAS1 to capacitor C2.

The first current mirror section 14 includes transistors M8, M12 and M17. The transistors M8, M12 and M17 are composed of, for example, P-channel MOS transistors of the first conductivity type.

The source of the transistor M8 is connected to the power supply line (power supply voltage VCC). The gate and drain of the transistor M8 are connected to each other and to the drain of the transistor M6 forming the input differential pair 21. FIG.

The source of the transistor M12 is connected to the power supply line (power supply voltage VCC). The drain of the transistor M12 is connected through the first current mismatch detection circuit 17 to the ground line (ground potential VSS). The gate of transistor M12 is connected to the gate of transistor M8.

The source of the transistor M17 is connected to the power supply line (power supply voltage VCC). The drain of the transistor M17 is connected through the second current mismatch detection circuit 18 to the ground line (ground potential VSS). The gate of transistor M17 is connected to the gate of transistor M12.

The drain current of transistor M8 is current mirrored by transistors M12 and M17. That is, the same current as the drain current of the transistor M8 flows between the sources and drains of the transistors M12 and M17.

The second current mirror portion 15 includes transistors M9, M13 and M16. The transistors M9, M13 and M16 are composed of P-channel MOS transistors, for example.

The source of the transistor M9 is connected to the power supply line (power supply voltage VCC). The gate and drain of the transistor M9 are connected to each other and to the drain of the transistor M7 forming the input differential pair 21. FIG.

The source of the transistor M13 is connected to the power supply line (power supply voltage VCC). The drain of the transistor M13 is connected through the first current mismatch detection circuit 17 to the ground line (ground potential VSS). The gate of transistor M13 is connected to the gate of transistor M9.

The source of the transistor M16 is connected to the power supply line (power supply voltage VCC). The drain of the transistor M16 is connected through the second current mismatch detection circuit 18 to the ground line (ground potential VSS). The gate of transistor M16 is connected to the gate of transistor M13.

The drain current of transistor M9 is current mirrored by transistors M13 and M16. That is, the same current as the drain current of the transistor M8 flows between the sources and drains of the transistors M13 and M16.

The offset correction section 16 includes transistors M20, M21, M22, M23 and M24. Transistors M20, M21, M22, M23 and M24 are, for example, N-channel MOS transistors. Also, the offset correction unit 16 includes capacitors C3 and C4.

The source of the transistor M20 is connected to the ground line (ground potential VSS). A bias voltage BIAS3 is supplied to the gate of the transistor M20. The transistor M20 is a constant current source that supplies a constant current according to the bias voltage BIAS3. If there is no current mismatch, a current obtained by equally dividing the constant current flows through the transistors M21 and M22.

Transistors M21 and M22 form an offset correction differential pair 22 . The sources of transistors M21 and M22 are connected together and to the drain of transistor M20. A gate of the transistor M21 is connected to a node diffp (first node). A gate of the transistor M22 is connected to a node diffn (second node).

The source of the transistor M23 is connected to the connection line that connects the drain of the transistor M13 and the first current mismatch detection circuit 17. FIG. The drain of transistor M23 is connected to the gate of transistor M21 via node diffp. An equalize control signal S3CK is supplied to the gate of the transistor M23. The transistor M23 functions as an offset correction switch that is turned on or off according to the signal level of the equalize control signal S3CK.

The source of the transistor M24 is connected to the connection line that connects the drain of the transistor M17 and the second current mismatch detection circuit 18. FIG. The drain of transistor M24 is connected to the gate of transistor M22 via node diffn. An equalize control signal S3CK is supplied to the gate of the transistor M24. The transistor M24 functions as an offset correction switch that is turned on or off according to the signal level of the equalize control signal S3CK.

The capacitor C3 has one end connected to the node diffp and the other end connected to the ground line (ground potential VSS). The capacitor C4 has one end connected to the node diffn and the other end connected to the ground line (ground potential VSS). Capacitors C3 and C4 function as differential gate holding capacitances that hold charge when the offset correction switch consisting of transistors M23 and M24 is in the ON state.

The first current mismatch detection circuit 17 includes transistors M14 and M15. The transistors M14 and M15 are, for example, N-channel MOS transistors. The first current mismatch detection circuit 17 has a function of detecting, as a current mismatch, the difference between the currents flowing through the transistors M12, M14, and M15 and the current flowing through the transistor M13. The detected current mismatch is reflected in the voltage of node diffp via transistor M23.

Each source of the transistors M14 and M15 is connected to the ground line (ground potential VSS). Also, the gates of the transistors M14 and M15 are connected to each other. The drain of the transistor M14 is connected to the gate of the transistor M14 and to the drain of the transistor M12 forming the first current mirror section 14 .

The drain of the transistor M15 is connected to the drain of the transistor M13 forming the second current mirror section 15 via the node mip. The voltage at node mip changes according to the currents flowing through transistors M13 and M15.

The second current mismatch detection circuit 18 includes transistors M18 and M19. The transistors M18 and M19 are composed of, for example, N-channel MOS transistors. The second current mismatch detection circuit 18 has a function of detecting the difference between the currents flowing through the transistors M16, M18 and M19 and the current flowing through the transistor M17 as a current mismatch. The detected current mismatch is reflected in the voltage of node diffn via transistor M24.

Each source of the transistors M18 and M19 is connected to the ground line (ground potential VSS). Also, the gates of the transistors M18 and M19 are connected together. The drain of the transistor M18 is connected to the gate of the transistor M18 and also to the drain of the transistor M16 forming the second current mirror section 15 .

The drain of the transistor M19 is connected to the drain of the transistor M17 forming the first current mirror section 14 via the node min. The voltage at node min changes according to the currents flowing through transistors M17 and M19.

The comparator 19 includes transistors M25, M26, M27, M28, M29, M30, M31 and M32. The comparison unit 19 also includes capacitors C5 and C6.

One end of the capacitor C5 is connected to a node mip between the drain of the transistor M15 and the drain of the transistor M13. One end of the capacitor C6 is connected to a node min between the drain of the transistor M19 and the drain of the transistor M17. Capacitors C5 and C6 function as inverter coupling capacitors that hold charges corresponding to the voltages of nodes mip and min, respectively.

The transistor M25 is composed of, for example, a P-channel MOS transistor. The source of the transistor M25 is connected to the power supply line (power supply voltage VCC). A bias voltage BIAS4 is supplied to the gate of the transistor M25. The transistor M25 is a constant current source that supplies a constant current according to the bias voltage BIAS4.

Transistors M26, M27, M28, M29, M30 and M31 form chopper inverter 23. FIG. The transistors M26 and M28 are composed of P-channel MOS transistors, for example. The transistors M27, M29, M30 and M31 are composed of, for example, N-channel MOS transistors.

The drains of the transistors M26 and M27 are connected to each other to form a positive side (POS side) inverter. The source of transistor M26 is connected to the drain of transistor M25. The source of the transistor M27 is connected to the ground line (ground potential VSS). An output signal OUT is output from the connection terminal of the drains of the transistors M26 and M27.

The source of the transistor M30 is connected to the connecting end of the drains of the transistors M26 and M27. The drain of transistor M30 is connected to the gates of transistors M26 and M27. The transistor M30 receives the equalization control signal S3CK at its gate, and is turned on or off according to the signal level of the equalization control signal S3CK. By turning on the transistor M30, the gates and drains of the transistors M26 and M27 are connected to short-circuit the input and output of the inverter.

The drains of the transistors M28 and M29 are connected to each other to form a negative electrode side (NEG side) inverter. The source of transistor M28 is connected to the drain of transistor M25. The source of the transistor M29 is connected to the ground line (ground potential VSS). An output signal OUTB is output from the connection terminal of the drains of the transistors M28 and M29.

The source of the transistor M31 is connected to the connecting end of the drains of the transistors M28 and M29. The drain of transistor M31 is connected to the gates of transistors M28 and M29. The transistor M31 receives the equalization control signal S3CK at its gate, and is turned on or off according to the signal level of the equalization control signal S3CK. By turning on the transistor M31, the gates and drains of the transistors M28 and M29 are connected to short-circuit the input and output of the inverter.

The transistor M32 is composed of, for example, a P-channel MOS transistor. The source of the transistor M32 is connected to the power supply line (power supply voltage VCC). The drain of transistor M32 is connected to the source of transistor M26 and the source of transistor M28. The transistor M32 receives at its gate the latch control signal H1CK whose signal level changes to logic level 0 or 1, and is turned on or off according to the signal level of the latch control signal H1CK. The comparison result in the comparison period is latched in the chopper inverter 23 by turning on the transistor M32. That is, transistor 32 functions as an inverter latch.

Next, the operation of the comparator circuit 100 of this embodiment will be described with reference to the time chart of FIG.

First, an equalization control signal S3CK of logic level 1 is supplied from the outside (not shown) of the comparator circuit 100 during the equalization period. The transistors M3, M4, M10 and M11 are turned on by receiving the equalize control signal S3CK of logic level 1 at their gates. As a result, the capacitor C1 is charged to "bias voltage BIAS1-reference voltage signal REFP". Similarly, capacitor C2 is charged to "bias voltage BIAS1-reference voltage signal REFN".

Also, since the transistors M10 and M11 are turned on, the gates of the transistors M6 and M7 are shorted. The drain current of transistor M6 flows through transistor M8, is current mirrored by transistors M12, M14 and M15, and is also current mirrored by transistor M17. On the other hand, the drain current of transistor M7 flows through transistor M9, is current mirrored by transistor M13, and is also current mirrored by transistors M16, M18 and M19.

The transistors M23 and M24 are turned on by receiving the equalization control signal S3CK of logic level 1 at their gates. As a result, the transistors M23 and M24 are turned on during the equalization period. The voltage at node diffp is supplied to the gate of transistor M21, and the voltage at node diffn is supplied to the gate of transistor M22. As a result, currents corresponding to the voltages of the nodes diffp and diffn flow between the drains and sources of the transistors M21 and M22, respectively.

At this time, the voltage of node diffp fluctuates due to the difference (current mismatch) detected by the first current mismatch detection circuit 17 between the current flowing through M15 and the current flowing through transistor M13. Similarly, the voltage at the node diffn fluctuates due to the difference (current mismatch) detected by the second current mismatch detection circuit 18 between the current flowing through the transistor M19 and the current flowing through the transistor M17.

That is, the current flows through the differential elements of the input differential pair 21 and 22 (transistors M6 and M7, transistors M21 and M22), the elements that make up the current mirror (transistors M8, M12, M17, M9, M13 and M16), etc. If there is variation in the current, the voltage on nodes diffp and diffn will rise or fall.

A change in the voltages of nodes diffp and diffn causes a change in the current through transistors M21 and M22. That is, the current flowing through the transistors M21 and M22 (that is, the output current of the offset correction differential pair 22) is a current reflecting the difference in the differential currents.

The current through transistor M21 is fed back through first current mirror section 14 to transistors M8 and M6. The current flowing through transistor M22 is fed back through second current mirror section 15 to transistors M9 and M7. Feedback is performed until the differential current flowing through the input differential pair 21 has no variation. Thereby, the offset of the comparator circuit 100 is corrected.

Equalization control signal S3CK at logic level 1 is also provided to the gates of transistors M30 and M31. Therefore, during the equalization period, the transistors M30 and M31 are turned on and the chopper comparator 23 consisting of the transistors M26, M27, M28 and M29 is reset.

Next, during the comparison period, the comparison control signal H3CK and the latch control signal H1CK of logic level 1 are supplied to the comparator circuit 100 . On the other hand, the equalize control signal S3CK is at logic level 0. This turns off transistors M3, M4, M10, M11, M23, M24, M30 and M31.

The transistors M1 and M2 are turned on by receiving the comparison control signal H3CK of logic level 1 at their gates. As a result, the input voltage signals INP and INN are input to the comparator circuit 100 . The input voltage signals INP and INN are supplied to the comparing section 19 through current conversion by the voltage-to-current conversion section 12 and current mirroring by the first current mirror section 14 and the second current mirror section 15, and are converted into the reference voltage signals REFP and REFN. be compared.

The currents flowing through the transistors M13 and M15 change according to the comparison voltage CP (=INP-REFP) obtained by comparing the input voltage signal INP and the reference voltage signal REFP, and the voltage at the node mip rises or falls. Similarly, the currents flowing through the transistors M17 and M19 change according to the comparison voltage CN (=INN-REFN) obtained by comparing the input voltage signal INN and the reference voltage signal REFN, and the voltage at the node min rises or falls.

Chopper comparator 23 changes state as nodes mip and min rise or fall. The transistor M32 is turned on by receiving the latch control signal H1CK of logic level 0 at its gate. Thereby, the comparison result in the comparison period is latched by the chopper comparator 23 in the latch period.

By the above operation, the comparison results are latched and output as the output signals OUT and OUTB.

In the comparator circuit 100 of this embodiment, the differential voltage input from the selector 11 (for example, the reference voltage signals REFP and REFN during the equalization period) is converted to the differential current flowing through the input differential pair 21 in the voltage-current converter 12. (current through each of transistors M6 and M7). The differential current is current mirrored by the first current mirror section 14 and the second current mirror section 15 and supplied to the offset correction section 16 . The offset correction unit 16 corrects current variations by feeding back the output current of the offset correction differential pair 22 corresponding to the difference in the differential current via the first current mirror unit 14 and the second current mirror unit 15. . According to such a configuration, during the equalization period, variations in the currents flowing through the elements forming the input differential pair 21, the first current mirror section 14, and the second current mirror section 15 are corrected, and errors are eliminated. Therefore, offset correction can be performed with high accuracy.

A current mismatch caused by the offset of the comparator circuit 100 is detected by the first current mismatch detection circuit 17 and the second current mismatch detection circuit 18 . Then, the offset correction unit 16 corrects the offset based on the detected current mismatch. According to such a configuration, it is possible to accurately perform offset correction with a simple configuration.

Further, in the comparator circuit 100 of this embodiment, the transistors M6 and M7 are connected to the transistor M5, which is a constant current source, and the drain currents of the transistors M6 and M7 are limited. Therefore, even if the capacitances of capacitors C1 and C2 are reduced, strong inversion does not occur in transistors M6 and M7. Therefore, since the CV characteristics of the transistors M6 and M7 do not change abruptly in the strong inversion region, the capacitors C1 and C2 do not lose charge storage.

Therefore, large fluctuations (fluctuations) in current and voltage due to noise do not occur. For example, as shown in FIG. 2, the voltages of nodes mip and min stably converge from the equalization period to the comparison period. Therefore, during the equalization period, current variations in the input differential pair 21, the first current mirror section 14, and the second current mirror section 15 are stably corrected, and the occurrence of determination errors is suppressed.

FIG. 3 is a circuit diagram showing the configuration of a comparator circuit 110 of a comparative example that does not have a voltage-current converter or a current mirror, unlike the comparator circuit 100 of this embodiment. The comparator circuit of the comparative example is composed of a selector 111 and a comparison section 119 .

Selector 111 includes transistors M1 to M4. Comparator 119 includes transistors M5 to M12 and capacitors C1 and C2. Transistors M1 to M4, M7, M8, M10 and M11 are composed of N-channel MOS transistors. The transistors M5, M6, M9 and M12 are composed of P-channel MOS transistors.

The transistors M6 and M7 form a positive side (POS side) inverter. Transistors M9 and M10 form a negative-side (NEG-side) inverter. The transistor M5 is a constant current source that receives a bias voltage PBIAS at its gate and supplies a constant current.

FIG. 4 is a time chart showing temporal changes in voltages in the comparator circuit 110 of the comparative example.

During the equalize period, the equalize control signal S3CK of logic level 1 is supplied to turn on the transistors M8 and M11. As a result, the positive inverter and the negative inverter are short-circuited. Also, transistors M3 and M4 are turned on and capacitors C1 and C2 are charged by reference voltage signals REFP and REFN.

During the comparison period, the comparison control signal H3CK of logic level 1 is supplied to the comparator circuit 110 . On the other hand, the equalize control signal S3CK is at logic level 0. Transistors M3, M4, M8 and M11 are turned off and transistors M1 and M2 are turned on. Thus, the input voltage signals INP and INN are input and compared with the reference voltage signals REFP and REFN.

During the latch period, the latch control signal H1CK of logic level 1 is supplied to the comparator circuit 110 . Transistor M12 is turned on and the result of the comparison during the comparison period is latched into the inverter consisting of transistors M6, M7, M9 and M10.

In the comparator circuit 110 of such a comparative example, the sources of the transistors M7 and M10, which are NMOS transistors, are not connected to the constant current source. Therefore, the gate capacitance of each transistor sharply increases in the strong inversion region from near the threshold voltage. Therefore, when the capacitances of the capacitors C1 and C2 are small, the charge is not stored. In such a state, the voltage of the input gate of the inverter fluctuates due to common noise, and a judgment error occurs in the comparison result of the comparator circuit 110 .

On the other hand, in the comparator circuit 100 of the present embodiment, as described above, even if the capacities of the capacitors C1 and C2 are reduced, the electric charge is not stored, and fluctuations (fluctuations) of current and voltage due to noise are suppressed. be done.

Therefore, according to the comparator circuit 100 of this embodiment, it is possible to accurately correct the offset while suppressing an increase in circuit size due to an increase in capacitance.

Next, the comparator circuit of Example 2 will be described. FIG. 5 is a circuit diagram showing the configuration of the comparator circuit 200 of this embodiment. The comparator circuit 200 has a lower voltage limiter 24 and an upper voltage limiter 25 in addition to the configuration of the comparator circuit 100 of the first embodiment shown in FIG.

Voltage lower limiter 24 includes transistors M33, M34, M35 and M36. The transistors M33, M34, M35 and M36 are composed of, for example, N-channel MOS transistors.

The transistor M33 is inserted between the connection line connecting the transistor M12 and the transistor M14. The source of transistor M33 is connected to the drain of transistor M14. The drain of transistor M33 is connected to the drain of transistor M12.

The transistor M34 is inserted between the connection line connecting the transistor M13 and the transistor M15. The source of transistor M34 is connected to the drain of transistor M15. A drain of the transistor M33 is connected to the node mip. The gates of transistors M33 and M34 are connected together and supplied with bias voltage BIAS5.

The transistor M35 is inserted between the connection line connecting the transistor M17 and the transistor M19. The source of transistor M35 is connected to the drain of transistor M19. The drain of transistor M35 is connected to node min.

The transistor M36 is inserted between the connection line connecting the transistors M16 and M18. The source of transistor M36 is connected to the drain of transistor M18. The drain of transistor M36 is connected to the drain of transistor M16. The gates of transistors M35 and M36 are connected together and supplied with bias voltage BIAS5.

Voltage upper limiter 25 includes transistors M37 and M38. The transistors M37 and M38 are composed of P-channel MOS transistors, for example.

The transistor M37 is inserted between the drain of the transistor M13 and the node mip. The source of transistor M37 is connected to the drain of transistor M13. A drain of the transistor M37 is connected to the node mip. A bias voltage BIAS6 is supplied to the gate of the transistor M37.

The transistor M38 is inserted between the drain of the transistor M17 and the node min. The source of transistor M38 is connected to the drain of transistor M17. The drain of transistor M38 is connected to node min. A bias voltage BIAS6 is supplied to the gate of the transistor M38.

The lower voltage limiter 24 has a function of limiting the voltage of the node to which the drains of the transistors M15 and M19 are connected so that the voltage does not drop too much. The voltage upper limiter 25 has a function of limiting the voltage of the node to which the drains of the transistors M13 and M17 are connected so that the voltage does not drop too much.

Next, the operation of the comparator circuit 200 of this embodiment will be described.

First, the equalization control signal S3CK of logic level 1 is supplied from the outside (not shown) of the comparator circuit 200 during the equalization period. The transistors M3, M4, M10 and M11 are turned on by receiving the equalize control signal S3CK of logic level 1 at their gates. As a result, the capacitor C1 is charged to "bias voltage BIAS1-reference voltage signal REFP". Similarly, capacitor C2 is charged to "bias voltage BIAS1-reference voltage signal REFN".

Also, since the transistors M10 and M11 are turned on, the gates of the transistors M6 and M7 are shorted. The drain current of transistor M6 flows through transistor M8, is current mirrored into transistors M12 and M14, and is further mirrored into transistors M17 and M19. On the other hand, the drain current of transistor M7 flows through transistor M9, is current mirrored by transistors M13 and M15, and is also current mirrored by transistors M16 and M18.

At this time, the voltage of the node to which the drain of the transistor M15 is connected is limited by the transistor M34 so that the voltage does not drop too much. On the other hand, the voltage of the node to which the drain of the transistor M13 is connected is limited by the transistor M37 so that the voltage does not rise too much.

Also, the voltage of the node to which the drain of the transistor M17 is connected is limited by the transistor M38 so that the voltage does not drop too much. On the other hand, the voltage of the node to which the drain of the transistor M19 is connected is limited by the transistor M35 so that the voltage does not rise too much.

The transistors M23 and M24 are turned on by receiving the equalization control signal S3CK of logic level 1 at their gates. As a result, the transistors M23 and M24 are turned on during the equalization period. The voltage at node diffp is supplied to the gate of transistor M21, and the voltage at node diffn is supplied to the gate of transistor M22. As a result, currents corresponding to the voltages of the nodes diffp and diffn flow between the drains and sources of the transistors M21 and M22, respectively.

At this time, the voltage of the node diffp fluctuates due to the difference (current mismatch) detected by the first current mismatch detection circuit 17 between the current flowing through the transistor M15 and the current flowing through the transistor M13. Similarly, the voltage at the node diffn fluctuates due to the difference (current mismatch) detected by the second current mismatch detection circuit 18 between the current flowing through the transistor M19 and the current flowing through the transistor M17.

That is, the current flows through the differential elements of the input differential pair 21 and 22 (transistors M6 and M7, transistors M21 and M22), the elements that make up the current mirror (transistors M8, M12, M17, M9, M13 and M16), etc. If there is variation in the current, the voltage on nodes diffp and diffn will rise or fall.

The change in voltage at node diffp is fed back to transistor M8 via the current flowing through transistor M21. The change in voltage at node diffn is fed back to transistor M9 via the current flowing through transistor M22.

When the current variation exceeds the correction range of the offset correction differential pair 22 (transistors M21 and M22), the voltages at nodes diffp and diffn are either low clamped (fixed to a low voltage) by transistors M34 and M35 or It is clamped to the upper limit (fixed to the upper limit voltage) by M37 and M38.

Also, during the equalization period, the equalization control signal S3CK at logic level 1 is supplied to the gates of the transistors M30 and M31. This turns on the transistors M30 and M31 and resets the chopper comparator 23 consisting of the transistors M26, M27, M28 and M29.

Next, during the comparison period, the comparison control signal H3CK and the latch control signal H1CK of logic level 1 are supplied to the comparator circuit 200 . On the other hand, the equalize control signal S3CK is at logic level 0. This turns off transistors M3, M4, M10, M11, M23, M24, M30 and M31.

The transistors M1 and M2 are turned on by receiving the comparison control signal H3CK of logic level 1 at their gates. As a result, the input voltage signals INP and INN are input to the comparator circuit 200 . The input voltage signals INP and INN are supplied to the comparing section 19 through current conversion by the voltage-to-current conversion section 12 and current mirroring by the first current mirror section 14 and the second current mirror section 15, and are converted into the reference voltage signals REFP and REFN. compared.

The currents flowing through the transistors M13 and M15 change according to the comparison voltage CP (=INP-REFP) obtained by comparing the input voltage signal INP and the reference voltage signal REFP, and the voltage at the node mip rises or falls. Similarly, the currents flowing through the transistors M17 and M19 change according to the comparison voltage CN (=INN-REFN) obtained by comparing the input voltage signal INN and the reference voltage signal REFN, and the voltage at the node min rises or falls.

Chopper comparator 23 changes state as nodes mip and min rise or fall. The transistor M32 is turned on by receiving the latch control signal H1CK of logic level 0 at its gate. Thereby, the comparison result in the comparison period is latched by the chopper comparator 23 in the latch period.

By the above operation, the comparison results are latched and output as the output signals OUT and OUTB.

According to the comparator circuit 200 of the present embodiment, the lower voltage limiter 24 including the transistors M34 and M35 prevents the voltage at the nodes diffp and diffn from dropping to a voltage level that would turn off the transistors M21 and M22. be able to. Therefore, offset correction can be performed with high accuracy.

Also, the voltage upper limiter 25 including the transistors M37 and M38 limits the voltage rise of the nodes diffp and diffn, so that the current flowing through the input differential pair 21, the first current mirror section 14 and the second current mirror section 15 is exceeds the correction range of the offset correction differential pair 22 (transistors M21 and M22), the comparator circuit 200 can perform the comparator operation.

In addition, this invention is not limited to the said embodiment. For example, in the above embodiment, the comparison result of the comparator circuit 200 is held by the operation of the inverter latch (transistor M32). However, the configuration for holding the comparison result is not limited to this, and for example, a configuration for inputting the comparison result to a logic gate such as a D flip-flop may be used.

Further, in the above embodiments, a comparator circuit as a 1-bit comparator has been described, but the present invention is not limited to this. Alternatively, the comparator circuit may be configured as a successive comparator.

100 Comparator circuit 11 Selector 12 Voltage-current conversion unit 13 Input equalizer 14 First current mirror unit 15 Second current mirror unit 16 Offset correction unit 17 First current mismatch detection circuit 18 Second current mismatch detection circuit 19 Comparison unit 21 Input differential pair 22 offset correction differential pair 23 chopper inverter 24 voltage lower limiter 25 voltage upper limiter

Claims (8)

A comparator circuit for comparing a reference voltage consisting of a pair of voltages having the same absolute value but different polarities with an input voltage consisting of a pair of voltages having the same absolute value but different polarities and outputting a comparison result,
an input unit that receives inputs of a first voltage and a second voltage corresponding to a voltage pair of the reference voltage or the input voltage;
an input capacitor pair consisting of a first input capacitor that holds charge based on the first voltage and a second input capacitor that holds charge based on the second voltage; and an input capacitor pair connected to the first input capacitor. an input differential pair comprising a first input differential element and a second input differential element connected to the second input capacitor, wherein the first voltage is applied to the first input differential element. a voltage-to-current converter for converting the second voltage into a second current flowing through the second input differential element;
a first current mirror unit that sends a current having a current amount corresponding to the first current to a first current path;
a second current mirror unit that sends a current having a current amount corresponding to the second current to a second current path;
a first correction differential element connected to the first current path through a first node and through which a current corresponding to the voltage of the first node flows ; and the second current through a second node. an offset correction unit including an offset correction differential pair consisting of a second correction differential element connected to a path and through which a current corresponding to the voltage of the second node flows ;
When the pair of voltages forming the reference voltage is input to the input unit as the first voltage and the second voltage, the first current and the second current and the pair of voltages forming the input voltage are a comparison unit that compares the reference voltage and the input voltage based on the first current and the second current when input to the input unit as the first voltage and the second voltage;
has
The first current mirror section and the second current mirror section feed back the current flowing through the first corrective differential element to the first input differential element and the second corrective differential element. A comparator circuit , wherein a flowing current is fed back to said second input differential element . The offset correction unit includes a first correction capacitor connected to the first correction differential element through the first node and holding a charge according to the voltage of the first node ; a second correction capacitor connected to the second correction differential element via a node of and holding a charge corresponding to the voltage of the second node ;
The offset correction capacitor pair is connected to the first current mirror section and the second current mirror section .
2. The comparator circuit according to claim 1 , wherein: current mismatch detection for detecting a difference between the current flowing through the first current path and the current flowing through the second current path based on the current flowing through each of the first current path and the second current path; having a circuit,
The offset correction differential pair changes the output current based on the difference between the current flowing through the first current path and the current flowing through the second current path detected by the current mismatch detection circuit. 3. The comparator circuit according to claim 2 , wherein: the first input differential element and the second input differential element are composed of N-channel MOS transistors,
the first input differential element has a gate connected to the first input capacitor,
the second input differential element has a gate connected to the second input capacitor,
4. The sources of said first input differential element and said second input differential element are connected to each other and grounded via a first constant current source. Comparator circuit as described in . the first correction differential element and the second correction differential element are composed of N-channel MOS transistors,
the first correction differential element has a gate connected to the first correction capacitor through the first node;
the second correction differential element has a gate connected to the second correction capacitor via the second node;
5. The apparatus according to claim 4 , wherein the sources of the first correction differential element and the second correction differential element are connected to each other and grounded via a second constant current source. comparator circuit. including a first transistor provided on the first current path, and defining a lower limit voltage so that the voltage value of the first node does not fall below a predetermined value in response to application of a bias voltage to the first transistor a first lower limiter;
including a second transistor provided in the first current path, and defining an upper limit voltage so that the voltage value of the first node does not exceed a predetermined value in response to application of a bias voltage to the second transistor ; a first upper limiter;
6. A comparator circuit according to any one of claims 2 to 5 , characterized in that it has: including a third transistor provided in the second current path, and defining a lower limit voltage so that the voltage value of the second node does not fall below a predetermined value in response to application of a bias voltage to the third transistor. a second lower limiter;
including a fourth transistor provided in the second current path, and defining an upper limit voltage so that the voltage value of the second node does not exceed a predetermined value in response to application of a bias voltage to the fourth transistor ; a second upper limiter;
7. A comparator circuit according to any one of claims 2 to 6 , characterized in that it has: The input unit receives the first voltage and the second voltage corresponding to the reference voltage during a first period, and receives the first voltage and the second voltage corresponding to the input voltage during a second period. receives a voltage input of
The offset correction unit corrects variations in the first current and the second current during the first period,
8. The comparator circuit according to claim 1 , wherein the comparison section compares the reference voltage and the input voltage during the second period.

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