JP7142047B2 - schottky barrier diode - Google Patents

Description

The present invention relates to a Schottky barrier diode in which a metal and a semiconductor are in Schottky contact.

Conventionally, a Schottky barrier diode using SiC is known as a high withstand voltage diode used in, for example, an inverter circuit (see, for example, Patent Document 1). A Schottky barrier diode generally has a smaller forward voltage (VF) and a shorter reverse recovery time (trr) than a PN junction diode with a similar current capacity, and has excellent switching characteristics. However, there is a strong demand for higher voltage resistance and higher efficiency, and further higher voltage resistance and lower forward voltage are required.

JP 2006-253521 A

Generally, in a Schottky barrier diode, there is a trade-off relationship between forward voltage (VF) and reverse withstand voltage (VRM) when a reverse bias voltage is applied. This is because the carrier concentration must be lowered in order to increase the reverse breakdown voltage (VRM), and the lower the carrier concentration, the higher the electric resistance and the higher the forward voltage (VF). In addition, when the carrier concentration is lowered, the contact resistance with the ohmic electrode layer increases, and the forward voltage (VF) increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a Schottky barrier diode capable of suppressing an increase in forward voltage and an increase in contact resistance with an ohmic electrode layer even if the reverse breakdown voltage is increased.

In order to achieve the above objects, the present invention provides the following Schottky barrier diodes [1] to [6].

[1] A first n-type semiconductor layer consisting of a β-Ga ₂ O ₃ -based single crystal epitaxial layer having a first carrier concentration that defines a reverse breakdown voltage and a forward voltage, and a forward voltage is defined; a second n-type semiconductor layer made of a β-Ga ₂ O ₃ -based single crystal substrate having a second carrier concentration higher than the first carrier concentration; a Schottky electrode provided on the surface opposite to the second n-type semiconductor layer; and an ohmic electrode provided on the surface of the second n-type semiconductor layer opposite to the first n-type semiconductor layer and wherein the β-Ga ₂ O ₃ system single crystal substrate has a substrate plane orientation rotated by an angle of 37.5° or less from the (010) plane.

[2] The Schottky barrier diode according to [1], wherein the first n-type semiconductor layer has a thickness greater than the thickness of the depletion layer determined by the first carrier concentration.

[3] The Schottky barrier diode according to [1], wherein the first carrier concentration of the first n-type semiconductor layer is 1×10 ¹⁸ /cm ³ or less.

[4] The Schottky barrier diode according to [1], wherein the first carrier concentration of the first n-type semiconductor layer is 1×10 ¹⁷ /cm ³ or less.

[5] The Schottky barrier diode according to [1], wherein the first carrier concentration of the first n-type semiconductor layer is 1×10 ¹⁶ /cm ³ or less.

[6] The Schottky barrier diode according to [1], wherein the second carrier concentration of the second n-type semiconductor layer is 1×10 ¹⁸ /cm ³ or more.

According to the present invention, even if the reverse withstand voltage of the Schottky barrier diode is increased, it is possible to suppress an increase in forward voltage and an increase in contact resistance with the ohmic electrode layer.

FIG. 1 is a cross-sectional view showing a configuration example of a Schottky diode according to an embodiment of the invention. FIGS. 2(a) to ₂ ( ^d ) show the electron carrier concentration ^, resistivity _, thickness, and a comparison table showing current density and the like. FIG. 3 is a schematic diagram illustrating energy bands in the Schottky diode according to the embodiment of the invention. FIG. 4 is a cross-sectional view showing a configuration example of a Schottky diode according to a comparative example. FIG. 5 is a graph showing voltage-current density characteristics of a Schottky diode according to an example and a Schottky diode according to a comparative example. FIG. 6 shows a Schottky diode according to a first modification of the embodiment of the invention, where (a) is a plan view and (b) is a sectional view taken along the line AA of (a). FIG. 7 shows a Schottky diode according to a second modification of the embodiment of the invention, where (a) is a plan view and (b) is a cross-sectional view taken along line AA of (a). FIG. 8 shows a Schottky diode according to a third modification of the embodiment of the invention, where (a) is a plan view and (b) is a cross-sectional view taken along line AA of (a).

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a Schottky barrier diode (hereinafter referred to as "Schottky diode") according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram schematically showing a cross-sectional configuration of a Schottky diode 1 according to this embodiment. The Schottky diode 1 includes an n-type semiconductor layer 3 made of a Ga ₂ O ₃ -based compound semiconductor having n-type conductivity, and a Schottky electrode layer in Schottky contact with a first main surface 3 a of the n-type semiconductor layer 3 . 2 and an ohmic electrode layer 4 in ohmic contact with a second main surface 3b of the n-type semiconductor layer 3 opposite to the first main surface 3a. On the first main surface 3a side of n-type semiconductor layer 3, a laminated film including Schottky electrode layer 2 as the lowermost layer may be provided. A laminated film including ohmic electrode layer 4 as the lowermost layer may be provided on the second main surface 3b side of n-type semiconductor layer 3 .

The n-type semiconductor layer 3 is based on β-Ga ₂ O ₃ , but Ga added with one or more selected from the group consisting of Cu, Ag, Zn, Cd, Al, In, Si, Ge and Sn. It may be composed of an oxide as a main component. More specifically, for example, gallium oxide represented by (Al _x In _y Ga _(1−x−y) ) ₂ O ₃ (where 0≦x<1, 0≦y<1, 0≦x+y<1) can use objects.

Further, the n-type semiconductor layer 3 includes an n ⁻ semiconductor layer 31 with a low electron carrier concentration as a first semiconductor layer and a high electron carrier concentration as a second semiconductor layer having a higher electron carrier concentration than the n ⁻ semiconductor layer 31 . and an n ⁺ semiconductor layer 32 with an electron carrier concentration. The n ⁻ semiconductor layer 31 with a low electron carrier concentration is formed on the side of the n-type semiconductor layer 3 that is in Schottky contact with the Schottky electrode layer 2 .

This n-type semiconductor layer 3 is formed by, for example, the MBE (Molecular Beam Epitaxy) method by supplying Ga vapor and an oxygen-based gas into a vacuum chamber to form a β-Ga ₂ O ₃ single crystal on a β-Ga ₂ O ₃ substrate. can be formed by epitaxial crystal growth. Further, in order to improve the controllability of the low electron carrier concentration, the purity of the Ga raw material is desirably 6N or higher. This β-Ga ₂ O ₃ substrate corresponds to the n ⁺ semiconductor layer 32 and the epitaxial layer formed thereon corresponds to the n ⁻ semiconductor layer 31 .

The β-Ga ₂ O ₃ substrate can be produced, for example, by an EFG (Edge-defined Film-fed Growth) method. In this case, the electron carrier concentration of the β-Ga ₂ O ₃ substrate (the electron carrier concentration of the n ⁺ semiconductor layer 32) is determined by the amounts of oxygen defects and dopants such as Si that occur during substrate fabrication. Also, the dopant is preferably Si, the amount of dopant taken in during crystal growth is stable. By using Si as a dopant, controllability of the electron carrier concentration is enhanced. Further, the electron carrier concentration of the n ⁻ semiconductor layer 31 can be adjusted by, for example, controlling the supply amount of group IV dopants such as Si and Sn or oxygen defects during epitaxial crystal growth. Furthermore, considering substitution with Ga, Sn having a close ionic radius is preferable.

In the Schottky diode 1 of the present embodiment, the electron carrier concentration Nd of the n ⁻ semiconductor layer 31 is, for example, 10 ¹⁶ cm ⁻³ , but the electron carrier concentration Nd is in a range lower than 10 ¹⁸ cm ⁻³ . can be set with Also, the electron carrier concentration Nd is preferably set to a value lower than 10 ¹⁷ cm ⁻³ . Furthermore, the n ⁻ semiconductor layer 31 may be composed of an n ^{− layer having a relatively low electron carrier concentration and an n layer having an electron carrier concentration between the n − layer} and the n ⁺ semiconductor layer 32 . The electron carrier concentration Nd of the n ⁻ semiconductor layer 31 can be set based on the reverse withstand voltage VRM required for the Schottky diode 1 and the electric field breakdown strength Em of Ga ₂ O ₃ .

Here, the electric field breakdown strength Em is a value specific to Ga ₂ O ₃ , and compared with the electric field breakdown strength of Si and SiC used as conventional n-type semiconductor materials, the electric field breakdown strength Em of Ga ₂ O ₃ is lower. It has been confirmed by the inventors that the

In general, the reverse withstand voltage of a Schottky diode is proportional to the square of the electric field breakdown strength and inversely proportional to the electron carrier concentration. Therefore, if the electric field breakdown strength increases, the reverse breakdown voltage increases even if the electron carrier concentration is the same. Further, if the reverse withstand voltage is the same, the electron carrier concentration can be increased by increasing the electric field breakdown strength. The higher the electron carrier concentration, the lower the electrical resistance and the lower the forward voltage (VF).

FIG. 2 shows the electron carrier concentration, resistivity, and thickness of the n ⁻ semiconductor layer (epitaxial layer) and the n ⁺ semiconductor layer (substrate) when Si or SiC is used as the semiconductor material and when Ga ₂ O ₃ is used. , and a table showing an example of the voltage drop relationship when the current density is 200 A / cm ² , (a) is a comparison table when the reverse breakdown voltage is 100 V using Si and Ga ₂ O ₃ , (b) is a comparison table when the reverse breakdown voltage is 600 V using SiC and Ga ₂ O ₃ , and (c) is a comparison table when the reverse breakdown voltage is 1000 V (1 kV) using SiC and Ga ₂ O ₃ A comparison table, (b) is a comparison table in the case of using SiC and Ga ₂ O ₃ and setting the reverse breakdown voltage to 10000 V (10 kV).

As shown in FIG. 2A, when the reverse breakdown voltage is set to 100 V, the electron carrier concentration and thickness of the n ⁻ semiconductor layer are 2.47×10 ¹⁵ cm ⁻³ and 7.5 μm for Si. On the other hand, Ga ₂ O ₃ according to the present embodiment has 8.29×10 ¹⁷ cm ⁻³ and 0.402 μm. This results in a voltage drop across the n ^- semiconductor layer of 0.1955 V for Si versus 0.0005 V for Ga ₂ O ₃ . As a result, the total voltage drop including the n ⁻ semiconductor layer and the n ⁺ semiconductor layer is 0.2226 V for Si and 0.0811 V for Ga ₂ O ₃ , reducing the voltage drop by about 64%. can do.

Further, as shown in FIG. 2B, when the reverse breakdown voltage is set to 600 V, the electron carrier concentration and thickness of the n ⁻ semiconductor layer are 2.16×10 ¹⁶ cm ⁻³ and 5.46 μm in SiC. In contrast, Ga ₂ O ₃ according to the present embodiment has a density of 1.66×10 ¹⁷ cm ⁻³ and 2.0 μm. This results in a voltage drop across the n ^- semiconductor layer of 0.0345 V for SiC and 0.0107 V for Ga ₂ O ₃ . As a result, the total voltage drop including the n ⁻ semiconductor layer and the n ⁺ semiconductor layer is 0.0546 V for SiC and 0.0376 V for Ga ₂ O ₃ , reducing the voltage drop by about 31%. can do.

Further, as shown in FIG. 2(c), when the reverse breakdown voltage is set to 1000 V, the electron carrier concentration and thickness of the n ⁻ semiconductor layer are 1.30×10 ¹⁶ cm ⁻³ and 9.1 μm in SiC. In contrast, the Ga ₂ O ₃ according to the present embodiment has 9.95×10 ¹⁶ cm ⁻³ and 3.3 μm. This results in a voltage drop across the n ^- semiconductor layer of 0.0914 V for SiC and 0.0296 V for Ga ₂ O ₃ . As a result, the total voltage drop including the n ⁻ semiconductor layer and the n ⁺ semiconductor layer is 0.1115 V for SiC and 0.0565 V for Ga ₂ O ₃ , reducing the voltage drop by about 49%. can do.

Further, as shown in FIG. 2(d), when the reverse breakdown voltage is set to 10000 V, the electron carrier concentration and thickness of the n ⁻ semiconductor layer are 1.30×10 ¹⁵ cm ⁻³ and 90.9 μm in SiC. On the other hand, in Ga ₂ O ₃ according to the present embodiment, it is 9.95×10 ¹⁵ cm ⁻³ and 33.3 μm. This gives a voltage drop across the n ^- semiconductor layer of 8.118 V for SiC and 2.9449 V for Ga ₂ O ₃ . As a result, the total voltage drop including the n ⁻ semiconductor layer and the n ⁺ semiconductor layer is 8.1319 V for SiC and 2.9718 V for Ga ₂ O ₃ , reducing the voltage drop by about 63%. can do.

The Schottky electrode layer 2 shown in FIG. 1 is formed on the first main surface 3a of the n-type semiconductor layer 3 (n ⁻ semiconductor layer 31) by, for example, EB (Electron Beam) vapor deposition, vacuum vapor deposition, or sputtering. filmed. A material for the Schottky electrode layer 2 is selected from a metal capable of Schottky contact with Ga ₂ O ₃ forming the n ⁻ semiconductor layer 31 . In this embodiment, Pt is deposited on the n-type semiconductor layer 3 as the Schottky electrode layer 2 .

Generally, in order to enable Schottky contact that causes rectification between a semiconductor and a metal, the relationship between the electron affinity χ of the semiconductor and the work function _φm of the metal that serves as the electrode must be χ< _φm . . Metals satisfying this relationship include V, Mo, Ni, Pd, etc., in addition to Pt according to the present embodiment.

Ohmic electrode layer 4 is formed on second main surface 3b of n-type semiconductor layer 3 (n ⁺ semiconductor layer 32) by vacuum deposition or sputtering. Ti, for example, is selected as the material of the ohmic electrode layer 4 . Note that other elements may be used as the material of the ohmic electrode layer 4 as long as the metal has a work function φ _m smaller than the electron affinity χ of Ga ₂ O ₃ .

FIG. 3 is a schematic diagram showing the energy band of the Schottky contact portion. Here, q is the single electron charge, _φBn is the Schottky barrier, and φd is the potential barrier (internal potential).

As shown in FIG. 3, the thickness t of the n ⁻ semiconductor layer 31 corresponds to the depletion layer width W when a reverse voltage of the reverse withstand voltage VRM is applied, and is made larger than the depletion layer width W. . However, ideally, it is most desirable that the depletion layer width W and the thickness t of the n ⁻ semiconductor layer 31 match. This is because if the thickness t of the n ⁻ semiconductor layer 31 is greater than the depletion layer width W, the electrical resistance of the n ⁻ semiconductor layer 31 increases accordingly.

Here, the depletion layer width W of the Schottky diode 1 depends on the electron carrier concentration Nd of the n ⁻ semiconductor layer 31 as expressed by the following formula (1). where ε is the dielectric constant of Ga ₂ O ₃ . In other words, the depletion layer width W can be obtained when the reverse breakdown voltage VRM and the electron carrier concentration Nd are determined. Then, with this depletion layer width W as a target, the n ⁻ semiconductor layer 31 is formed so that the epitaxial growth thickness of Ga ₂ O ₃ with a low electron carrier concentration is equal to or greater than the depletion layer width W (t≧W).

The electron carrier concentration of the n ⁺ semiconductor layer 32 is set to a required concentration (for example, higher than 10 ¹⁸ cm ⁻³ value). Further, it is desirable that the electron carrier concentration of the n ⁺ semiconductor layer 32 is ten times or more higher than the electron carrier concentration of the n ⁻ semiconductor layer 31 . This is because the electrical resistance of the entire n-type semiconductor layer 3 decreases as the electron carrier concentration of the n ⁺ semiconductor layer 32 increases.

(Operation of Schottky diode 1)
When a voltage V is applied to the Schottky diode 1 in the forward direction (positive potential on the side of the Schottky electrode layer 2), φ _d shown in FIG _. The current due to electrons moving to layer 2 increases. Thereby, a forward current flows from the Schottky electrode layer 2 to the ohmic electrode layer 4 .

On the other hand, when a voltage V in the reverse direction (negative potential on the side of the Schottky electrode layer 2) is applied to the Schottky diode 1, φ _d becomes (φ _d +V), and from the n-type semiconductor layer 3 to the Schottky electrode layer 2 The current due to moving electrons is almost zero. Also, the depletion layer spreads toward the n ⁺ semiconductor layer 32 according to the voltage V. FIG. However, since the thickness t of the n ⁻ semiconductor layer 31 is formed to be larger than the depletion layer width W obtained based on the above equation (1), a reverse voltage of the reverse withstand voltage VRM is applied. However, the depletion layer does not reach the n ⁺ semiconductor layer 32 .

(Action and effect of the embodiment)
According to this embodiment, there are the following effects.

In the Schottky diode 1 of this embodiment, a Ga ₂ O ₃ -based compound is used as the material of the n-type semiconductor layer 3 . This Ga ₂ O ₃ -based compound has a higher electric field breakdown strength than Si and SiC, which have been used as materials for conventional Schottky diodes. can.

Also, the n-type semiconductor layer 3 is composed of an n ⁻ semiconductor layer 31 with a low electron carrier concentration and an n ⁺ semiconductor layer 32 with a high electron carrier concentration. As described above, the Ga ₂ O ₃ -based compound has a high electric field breakdown strength, so that the reverse withstand voltage can be increased. is inversely proportional to the electron carrier concentration, there is a limit to the effect of increasing the reverse breakdown voltage. However, in the present embodiment, since the n ⁻ semiconductor layer 31 is formed on the Schottky electrode layer 2 side, the reverse withstand voltage can be further increased.

Further, since the thickness of the n ⁻ semiconductor layer 31 is formed to be thicker than the depletion layer width W when a reverse voltage of the reverse withstand voltage VRM is applied, the reverse voltage of the reverse withstand voltage VRM is applied. Also, the depletion layer does not reach the n ⁺ semiconductor layer 32 .

Also, by setting the electron carrier concentration of the n ⁻ semiconductor layer 31 to a range lower than 10 ¹⁷ cm ⁻³ , a reverse breakdown voltage VRM of 1000 V or more can be ensured. Furthermore, by setting the electron carrier concentration of the n ⁻ semiconductor layer 31 to a range lower than 10 ¹⁶ cm ⁻³ , a reverse breakdown voltage VRM of 10000 V or higher can be ensured. By setting the electron carrier concentration of the n ⁺ semiconductor layer 32 to 10 ¹⁸ cm ⁻³ or more, the electric resistance of the entire n-type semiconductor layer 3 can be suppressed, and furthermore, the contact resistance with the ohmic electrode layer 4 can be reduced. Increase can be suppressed. Thereby, the forward voltage of the Schottky diode 1 can be reduced.

Next, more specific examples of the present invention will be described.

In this example, a β-Ga ₂ O ₃ substrate with a thickness of 600 μm manufactured by the FZ (Floating Zone) method was used as the n ⁺ semiconductor layer 32 . This β-Ga ₂ O ₃ substrate was doped with Si as a dopant to an electron carrier concentration of 1×10 ¹⁹ cm ⁻³ . The plane orientation of the substrate was (010). Although the plane orientation of the substrate is not particularly limited, it is preferably a plane rotated from the (100) plane by an angle of 50° or more and 90° or less. For example, there are (010), (001), (−201), (101), and (310) planes. By doing so, re-evaporation from the substrate can be suppressed during epitaxial growth, and the growth rate can be increased. Alternatively, the plane orientation of the substrate may be rotated by an angle of 37.5° or less from the (010) plane. In this case, the interface between the n ⁺ semiconductor layer 32 and the n ⁻ semiconductor layer 31 can be sharpened, and the thickness of the n ⁻ semiconductor layer 31 can be controlled with high accuracy.

The n ⁻ semiconductor layer 31 was formed by epitaxially growing a β-Ga ₂ O ₃ single crystal having a thickness of 1.4 μm on the β-Ga ₂ O ₃ substrate (n ⁺ semiconductor layer 32) by MBE. Sn was used as the dopant, and the electron carrier concentration was set to 4×10 ¹⁶ cm ⁻³ .

The Schottky electrode layer 2 had a two-layer structure of Pt with a thickness of 30 nm which was in Schottky contact with the n ⁻ semiconductor layer 31 and Au with a thickness of 170 nm formed on the Pt.

The ohmic electrode layer 4 has a two-layer structure of Ti with a thickness of 100 nm which is in ohmic contact with the n ⁺ semiconductor layer 32 and Au with a thickness of 100 nm formed on the Ti.

(Comparative example)
FIG. 4 is a diagram schematically showing a cross-sectional configuration of a Schottky diode 10 shown as a comparative example. This Schottky diode 10 has a single ^- layer structure in which a 400 μm-thick β-Ga ₂ O ₃ substrate manufactured by the EFG method is used as an n ⁻ semiconductor layer 33. A Schottky electrode layer 2 was formed on the other main surface 33b, and an ohmic electrode layer 4 was formed on the other main surface 33b. The configurations of the Schottky electrode layer 2 and the ohmic electrode layer 4 are the same as those of the above-described examples. The n ⁻ semiconductor layer 33 has a thickness of 400 μm, is non-doped, and is not subjected to heat treatment in a nitrogen atmosphere to have an electron carrier concentration of 8×10 ¹⁶ cm ⁻³ .

FIG. 5 is a graph showing voltage-current density characteristics of the Schottky diode 1 according to the example of the present invention and the Schottky diode 10 according to the comparative example configured as described above. As shown in this figure, in the Schottky diode 1, the current density rises steeply when a forward voltage is applied, whereas in the Schottky diode 10, the current density rises more than the Schottky diode 1. is slowing down.

This is because the semiconductor layer 3 in the Schottky diode 1 has a multi-layer structure consisting of the n ⁻ semiconductor layer 31 and the n ⁺ semiconductor layer 32, and the electric resistance of the n ⁺ semiconductor layer 32 is lowered, thereby reducing the forward voltage. shows that it has been done. Further, by increasing the electron carrier concentration of the n ⁺ semiconductor layer 32 in contact with the ohmic electrode 4, the contact resistance between the ohmic electrode 4 and the semiconductor layer 3 is lowered, which also contributes to the reduction of the forward voltage. it seems to do.

(Modification of Schottky diode)
Next, three modifications of the Schottky diode structure according to the embodiment of the present invention will be described with reference to FIGS. In these modified examples, the specifications such as the carrier concentration and thickness of the n ⁻ semiconductor layer 31 and the n ⁺ semiconductor layer 32 can be set in the same manner as described above.

(Modification 1)
FIG. 6 shows a Schottky diode 1A according to a first modification of the embodiment of the invention, where (a) is a plan view and (b) is a cross-sectional view taken along line AA of (a).

The Schottky diode 1A has a square shape in a plan view, and a similarly square Schottky electrode layer 2 is formed in the central portion of the Schottky diode 1A. The Schottky diode 1A also includes an n-type semiconductor layer 3, which includes an n ⁻ semiconductor layer 31 with a low electron carrier concentration and a high electron carrier concentration higher than the n ⁻ semiconductor layer 31 . and an n ⁺ semiconductor layer 32 with an electron carrier concentration. The n ⁻ semiconductor layer 31 with a low electron carrier concentration is formed on the side of the n-type semiconductor layer 3 that is in Schottky contact with the Schottky electrode layer 2 . An ohmic electrode 4 is formed on the surface of the n ⁺ semiconductor layer 32 opposite to the n ⁻ semiconductor layer 31 .

The n ⁻ semiconductor layer 31 has a flat top surface 31a formed on the side opposite to the n ⁺ semiconductor layer 32 and side surfaces 31b formed so as to incline from the outer edge of the top surface 31a toward the n ⁺ semiconductor layer 32. and has a mesa structure. A lower surface 31c parallel to the upper surface 31a is formed outside the side surface 31b so as to surround the side surface 31b. The Schottky electrode layer 2 is formed on the upper surface 31a with a predetermined gap from the side surface 31b.

A PV (passivation) film 6 is formed in a region between the peripheral portion of the Schottky electrode layer 2 and a portion of the lower surface 31c on the side surface 31b side. The PV film 6 is formed so as to cover the peripheral portion of the Schottky electrode layer 2 and part of the upper surface 31a, the side surface 31b, and the lower surface 31c of the n ⁺ semiconductor layer 32 outside the Schottky electrode layer 2 on the side surface 31b side. It is

According to this Schottky diode 1A, electric field concentration at the ends of the Schottky electrode layer 2 is relaxed due to the electric field relaxation effect of the mesa structure of the n ⁻ semiconductor layer 31. The concentration of the electric field suppresses the decrease in the reverse breakdown voltage.

(Modification 2)
FIG. 7 shows a Schottky diode 1B according to a second modification of the embodiment of the invention, where (a) is a plan view and (b) is a cross-sectional view taken along line AA of (a).

The Schottky diode 1B differs from the Schottky diode 1A in that a resistive layer 310 is formed on a portion of the n ⁻ semiconductor layer 31, and the rest of the configuration is the same as the Schottky diode 1A. The resistance layer 310 is formed from a portion of the n ⁻ semiconductor layer 31 on the side of the upper surface 31a that is in contact with the peripheral portion of the Schottky electrode layer 2 to the side surface 31b. This resistance layer 310 can be formed by annealing in an oxygen atmosphere, for example, after forming the n ⁻ semiconductor layer 31 on the n ⁺ semiconductor layer 32 . Also, instead of the resistive layer 310, this region may be a P-type layer.

According to this Schottky diode 1A, in addition to the electric field relaxation effect of the mesa structure of the n ⁻ semiconductor layer 31, electric field concentration at the end of the Schottky electrode layer 2 is reduced by the electric field relaxation effect of the resistance layer 310 or the P-type layer. Since it is further alleviated, it is further suppressed that the reverse breakdown voltage is lowered due to the electric field concentration at the end portion of the Schottky electrode layer 2 .

(Modification 3)
FIG. 8 shows a Schottky diode 1C according to a third modification of the embodiment of the invention, where (a) is a plan view and (b) is a cross-sectional view taken along line AA of (a).

The Schottky diode 1C has a square shape in plan view, and includes an n-type semiconductor layer 3 composed of an n ⁻ semiconductor layer 31 and an n ⁺ semiconductor layer 32 . A PV film 6 is formed on the periphery of the upper surface 31a of the n ⁻ semiconductor layer 31 . A Schottky electrode layer 2 is formed at the center of the upper surface 31a of the n ⁻ semiconductor layer 31. As shown in FIG. The Schottky electrode layer 2 is formed so that a part of its peripheral region covers the PV film 6 .

A resistance layer 310 is formed in a region including the boundary between the Schottky electrode layer 2 and the PV film 6 on the upper surface 31a side of the n ⁻ semiconductor layer 31 . Also, instead of the resistive layer 310, this region may have a guard ring structure composed of a P-type layer. Further, the resistive layer 310 and the PV film 6 may have a structure of only the PV film 6 without the resistive layer 310 .

An ohmic electrode 4 is formed on the surface of the n ⁺ semiconductor layer 32 opposite to the n ⁻ semiconductor layer 31 .

According to this Schottky diode 1C, the field plate effect of the Schottky electrode layer 2 formed on the PV film 6 alleviates the electric field concentration at the end of the Schottky electrode layer 2. A decrease in reverse breakdown voltage due to electric field concentration at the edge of the layer 2 is suppressed. Further, when the resistance layer 310 is formed, the electric field concentration at the edge of the Schottky electrode layer 2 is further alleviated due to its electric field relaxation effect. Lowering of the reverse withstand voltage is further suppressed.

Although a plurality of preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and applications are possible without changing the gist of the invention. For example, the Schottky diode 1 may be of a horizontal type in which the Schottky electrode layer 2 and the ohmic electrode layer 4 are deposited on the same surface side of the n-type semiconductor layer 3 in addition to the configuration (vertical type) of the above embodiment. good.

1, 1A, 1B, 1C... Schottky diode, 2... Schottky electrode layer, 3... N-type semiconductor layer, 3a... First main surface, 3b... Second main surface, 4... Ohmic electrode layer, 5... Protective electrode layer 6 PV film 31 n ⁻ semiconductor layer 31 a top surface 31 b side surface 31 c bottom surface 32 n ⁺ semiconductor layer 33 n ⁻ semiconductor layer t n ⁻ thickness of semiconductor layer , W... Depletion layer width, _φBn ... Schottky barrier, φd... Potential barrier, _φm ... Metal work function, χ... Electron affinity

Claims (6)

a first n-type semiconductor layer made of a β-Ga ₂ O ₃ -based single crystal epitaxial layer having a first carrier concentration that determines a reverse breakdown voltage and a forward voltage;
a second n-type semiconductor layer made of a β-Ga ₂ O ₃ -based single crystal substrate and having a second carrier concentration higher than the first carrier concentration, which determines a forward voltage;
a Schottky electrode provided on the surface of the first n-type semiconductor layer opposite to the second n-type semiconductor layer;
an ohmic electrode provided on the surface of the second n-type semiconductor layer opposite to the first n-type semiconductor layer,
The Schottky barrier diode, wherein the β-Ga ₂ O ₃ -based single crystal substrate has a substrate plane orientation rotated by an angle of 37.5° or less from the (010) plane. 2. The Schottky barrier diode according to claim 1, wherein said first n-type semiconductor layer has a thickness greater than the thickness of a depletion layer determined by said first carrier concentration. 2. The Schottky barrier diode according to claim 1, wherein said first carrier concentration of said first n-type semiconductor layer is 1×10 ¹⁸ /cm ³ or less. 2. The Schottky barrier diode according to claim 1, wherein said first carrier concentration of said first n-type semiconductor layer is 1×10 ¹⁷ /cm ³ or less. 2. The Schottky barrier diode according to claim 1, wherein said first carrier concentration of said first n-type semiconductor layer is 1×10 ¹⁶ /cm ³ or less. 2. The Schottky barrier diode according to claim 1, wherein said second carrier concentration of said second n-type semiconductor layer is 1×10 ¹⁸ /cm ³ or more.

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