JP7138543B2 - game machine - Google Patents

Description

The present invention relates to a game machine that performs lottery processing based on game operations and executes image effects corresponding to the lottery results, and more particularly to a game machine that can stably execute powerful image effects.

A pinball game machine such as a pachinko machine is equipped with a pattern starting port provided on a game board, a pattern display section for displaying a series of pattern variations by a plurality of display patterns, and a prize winning port in which an opening/closing plate is opened and closed. configured as follows. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the displayed symbols are changed in the symbol display unit for a predetermined period of time. After that, when the symbols stop in a predetermined manner such as 7, 7, 7, etc., a big hit state is entered, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a jackpot lottery that is executed on the condition that a game ball has entered the symbol start opening, and the above-described symbol variation operation is based on the results of this lottery. It is a thing. For example, when the lottery result is a winning state, a performance operation called reach action is executed for about 20 seconds, and then the special symbols are arranged. On the other hand, a similar ready-to-win action may be executed even in the case of a losing state, and in this case, the player will pay attention to the transition of the performance action while strongly hoping for a big win state. Then, when the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed a big hit state.

JP 2017-093633 A JP 2017-093632 A JP 2016-159030 A JP 2016-159029 A

In this type of game machine, there is a desire to make various effects more complex and rich, and there is a high demand for image effects in particular. Therefore, the applicant has made various proposals (cited documents 1 to 4), but further sophistication of image presentation and improvement of image presentation control are desired.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine capable of executing more improved image effect control.

In order to achieve the above object, a game machine according to the present invention provides image control means having a CPU circuit for creating a display list specifying a display screen of a display device, and an instruction command described in the display list. an image generating means having a drawing circuit for generating image data, a data transfer circuit for receiving the display list configuration data for each unit size , and a preloader capable of acquiring transfer data from the data transfer circuit. and the image control means includes a DMAC circuit capable of executing a DMA (Direct Memory Access) operation based on an instruction from the CPU of the CPU circuit, and a control register in which a setting value defining the operation of the DMAC circuit is set. and a list buffer for storing the display list created by the CPU, and the image control means, regarding the DMA operation, stores the start address of the list buffer and the DMA transfer destination of the display list. setting means for setting DMA operation conditions including an address of a certain data transfer circuit in one or more predetermined control registers; and initial setting of the data transfer circuit prior to starting the DMA operation. the data transfer circuit of the image generation means transfers the data transferred from the list buffer based on the DMA operation of the DMAC circuit to an integral multiple of the unit size. It is collected into a predetermined transfer size and transferred to the drawing circuit or the preloader.

According to the present invention described above, it is possible to execute a smooth and appropriate image control operation even with an advanced image effect.

It is a perspective view showing the pachinko machine of the present embodiment. 2 is a front view showing a game area of the gaming machine of FIG. 1; FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1; FIG. 2 is a block diagram showing in some detail the circuit configuration of an effect control unit in the gaming machine of FIG. 1; FIG. It is drawing explaining the composite chip|tip which comprises a production|presentation control part. FIG. 10 is a drawing for explaining cycle steal transfer operation and pipeline transfer for DMAC; FIG. 4A and 4B are diagrams for explaining an index space, an index table, a virtual drawing space, and a drawing area; 2 is a block diagram describing the internal configuration of a data transfer circuit together with related circuit configurations; FIG. 2 is a block diagram describing the internal configuration of a display circuit together with related circuit configurations; FIG. It is a flowchart explaining the control operation of production|presentation control CPU63 about the case where a preloader is not used. 4 is a diagram for explaining the configuration of a display list; FIG. FIG. 10 is a flowchart showing DL issuing processing for issuing a display list DL; FIG. FIG. 13 is a flowchart for explaining the operation when the DMAC is involved in the operation of FIG. 12; FIG. FIG. 14 is a flowchart for explaining the operation following the processing in FIG. 13; FIG. It is a flowchart explaining the control operation of production|presentation control CPU63 about the case where a preloader is used. FIG. 16 is a flow chart explaining a part of FIG. 15; FIG. FIG. 16 is a flowchart illustrating another part of FIG. 15; FIG. 5 is a time chart showing the operation of each part of the VDP in an example that does not use a preloader; 4 is a time chart showing the operation of each part of the VDP in an example using a preloader; FIG. 11 is a block diagram showing the overall circuit configuration of another embodiment; Figure 21 is a block diagram showing a portion of Figure 20 in slightly more detail; 9 is a flow chart for explaining the operation content of another embodiment.

The present invention will be described in detail below based on examples. FIG. 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM comprises a rectangular wooden outer frame 1 detachably attached to an island structure, and a front frame 3 pivotally attached to the outer frame 1 through hinges 2 so as to be openable and closable. It is configured. A game board 5 is detachably attached to the front frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side thereof so as to be freely opened and closed.

Illuminated lamps such as LED lamps are arranged in a substantially C shape around the outer periphery of the glass door 6 . On the other hand, a total of three speakers are arranged on the upper left and right positions of the glass door 6 and on the lower side. The two upper speakers are configured to output left and right channel R and L sounds, respectively, and the lower speaker is configured to output bass sounds.

An upper plate 8 for storing game balls to be shot is attached to the front plate 7, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a shooting handle are provided at the lower part of the front frame 3. 10 are provided. A shooting handle 10 is interlocked with a shooting motor, and a game ball is shot by a hitting mallet that operates according to the rotation angle of the shooting handle 10.例文帳に追加

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. - 特許庁The chance button 11 is provided at a position where it can be operated with the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the shooting handle 10.例文帳に追加The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp lights up and becomes operable. Note that the button chance state is a game state provided as necessary.

A rotary switch-type volume switch VLSW is arranged below the chance button 11, and the player operates the volume switch VLSW to change the level from silent level (=0) to maximum level (=7). The speaker volume can be adjusted in eight steps. The volume of the speaker is initially set by a setting switch (not shown) that can be operated only by the staff, and the initially set volume is maintained unless the player operates the volume switch VLSW. Also, the abnormal notification sound for notifying that an abnormal situation has occurred is emitted at the maximum volume regardless of the initial volume set by the staff or the volume set by the player.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for the card-type ball lending machine is provided, and a frequency display section for displaying the remaining card amount in three digits and a predetermined amount of game balls are provided. A ball lending switch for instructing lending and a return switch for instructing card return at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 consisting of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO is provided substantially in the center thereof. Under the central opening HO, a movable effect body (not shown) is housed in a concealed state. We have realized the preview performance. Here, the notice performance is a performance that uncertainly notifies the occurrence of a big win state advantageous to the player, and the reliability of the notice performance means the probability of the occurrence of the big win state.

A main display device DS1 composed of a large liquid crystal color display (LCD) (for example, 1280 pixels wide by 1024 pixels long) is arranged in the central opening HO. A movable sub-display device DS2 composed of a liquid crystal color display of 480×800 pixels is arranged. The main display device DS1 is a device that variably displays specific symbols related to a big win state and also displays a background image, various characters, and the like in an animated manner. This display device DS1 has special symbol display portions Da to Dc in the central portion and a normal symbol display portion 19 in the upper right portion. Then, in the special pattern display parts Da to Dc, a ready-to-win performance to expect the arrival of a big hit state is sometimes executed, and in and around the special pattern display parts Da to Dc, an appropriate advance notice performance is executed.

The sub-display device DS2 normally displays image information in a stationary state in which the display screen is tilted at an angle that is easy for the player to see. However, during a predetermined notice effect, it moves to the left side of the drawing while changing the tilt angle to an angle that is easy for the player to see, and displays a predetermined notice image.

In other words, the sub-display device DS2 of the embodiment functions not only as a display device but also as a movable effect body for executing the advance notice effect. Here, the advance notice effect by the sub-display device DS2 is set to have a high degree of reliability, and the player pays attention to the moving action of the sub-display device DS2 with great anticipation.

By the way, the game area where the game ball falls and moves includes the first symbol starting port 15a, the second symbol starting port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17, and the gate 18. are arranged. Each of these winning holes 15 to 18 has a detection switch inside so that the passage of a game ball can be detected.

Above the first symbol starting port 15a, a production stage 14 is arranged so that the first symbol starting port 15 can win after the game ball entering from the introduction port IN moves in a seesaw or roulette shape. there is Then, when a game ball wins the first symbol starting port 15, the special symbol display portions Da to Dc are configured to start varying operations.

The second symbol start port 15b is configured to be opened and closed by an electric tulip provided with a pair of left and right opening and closing claws, and when the stop symbol after the change of the normal symbol display unit 19 is displayed as a winning symbol, a predetermined The opening/closing claw is opened for a period of time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays normal symbols, and when a game ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined period of time, and is extracted when the game ball passes through the gate 18. A stop pattern determined by the selected random number for lottery is displayed and stopped.

The first big prize winning port 16a has a sliding board that advances and retreats in the front-rear direction, and the second big prize winning port 16b has an opening/closing plate whose lower end is pivotally supported and which opens forward. . Although the operations of the first big winning hole 16a and the second big winning hole 16b are not particularly limited, in this embodiment, the first big winning hole 16a corresponds to the first symbol starting hole 15a, and the second big winning hole 16b is configured to correspond to the first symbol starting port 15b.

That is, when the game ball wins in the first symbol start port 15a, the special symbol display portions Da to Dc start to fluctuate, and after that, when the predetermined jackpot symbols are arranged in the special symbol display portions Da to Dc, the first jackpot. A special game is started, and the slide board of the first big winning hole 16a is opened forward to facilitate the winning of game balls.

On the other hand, as a result of the fluctuation operation started by the winning of the game ball to the second symbol starting port 15b, when the predetermined big winning symbols are arranged in the special symbol display parts Da to Dc, the second big winning special game is started. The opening/closing plate of the second prize winning port 16b is opened to facilitate winning of game balls. The game value of the special game (jackpot state) varies depending on the jackpot symbols to be arranged, but which game value is given is determined in advance based on the lottery result corresponding to the winning timing of the game ball. It is determined.

In a typical jackpot state, after the opening/closing plate of the big winning hole 16 is opened, the opening/closing plate closes when a predetermined time elapses or when a predetermined number (for example 10) of game balls win. Such actions are continued up to, for example, 15 times, and are controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the special game ends will be in a high probability state (definite variable state). Granted.

FIG. 3 is a block diagram showing the overall circuit configuration of the pachinko machine GM that implements the operations described above, and FIG. 4(a) shows a portion thereof in detail.

As shown in FIG. 3, the pachinko machine GM includes a power board 20 that receives AC24V and outputs various DC voltages and power failure signals ABN1 and ABN2, and a main control board 21 that centrally and centrally performs game control operations. , an effect interface board 22 on which a circuit element SND for sound effect is mounted, and an effect control board 23 for uniformly executing lamp effect, sound effect, and image effect based on the control command CMD received from the main control board 21. Then, based on the control command CMD' received from the main control board 21 and the liquid crystal interface board 24 located between the performance control board 23 and the display devices DS1 and DS2, the payout motor M is controlled to pay out the game balls. It is mainly composed of a payout control board 25 and a shooting control board 26 for shooting game balls in response to player's operation.

In the case of this embodiment, the effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are directly connected by male connectors and female connectors without wiring cables. Therefore, even if the circuit configuration of each electronic circuit is complicated and advanced, the storage space for the entire board can be minimized, and noise resistance can be enhanced by shortening the connection line.

As shown, the control command CMD' output by the main control board 21 is transmitted to the payout control board 25 via the main board relay board 33. On the other hand, the control command CMD output by the main control board 21 is transmitted to the effect control board 23 via the effect interface board 22 . Each of the control commands CMD and CMD' has a 16-bit length, but is divided into two 8-bit lengths and transmitted in parallel.

A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25 . Also, the performance control board 23 is equipped with a composite chip 50 in which computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51 are built. Therefore, these control boards 21, 25, 23, the circuits mounted on the effect interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are collectively functionally referred to in this specification as , the main control unit 21, the performance control unit 23, and the payout control unit 25. Note that the effect control unit 23 and the payout control unit 25 are sub-control units for the main control unit 21 .

Further, the pachinko machine GM is roughly divided into a frame-side member GM1 surrounded by a dashed line in FIG. The frame-side member GM1 includes a front frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof, so that the game hall can be used for a long time regardless of model changes. fixedly installed in the On the other hand, the board-side member GM2 is replaced in response to the model change, and the new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame side member 1 are board side members GM2.

3, the frame-side member GM1 includes a power supply board 20, a payout control board 25, a firing control board 26, and a frame relay board 36. These circuit boards are Each is fixed to the proper place of the front frame 3. On the other hand, on the back surface of the game board 5, a main control board 21 and an effect control board 23 are fixed together with the display devices DS1, DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by connectors C1 to C4 centrally arranged in one place.

The power board 20 is connected to the main board relay board 33 through the connector C2, and is connected to the power relay board 34 through the connector C3. The power supply substrate 20 is provided with a power monitoring unit MNT for monitoring whether the AC power is turned on or off. When the power monitoring unit MNT detects the interruption of the AC power, it immediately changes the power failure signals ABN1 and ABN2 to the L level. The power failure signals ABN1 and ABN2 quickly become H level after the power is turned on.

The main board relay board 33 outputs the power failure signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power supply board 20 to the main control section 21 as they are. Also, the power supply relay board 34 outputs the AC and DC power supply voltages received from the power supply board 20 to the presentation interface board 22 as they are.

As shown, the effect interface board 22 is equipped with a sound circuit SND such as a sound processor 27, and the effect control board 23 is equipped with a composite chip 50 containing computer circuits such as a VDP circuit 52 and a CPU circuit 51. is installed.

In addition, the performance interface board 22 is equipped with a reset circuit RST3 that detects an increase in the power supply voltage and generates a reset signal SYS (CPU reset signal) when the power is turned on. This CPU reset signal SYS is transmitted to the sound circuit SND of the effect interface board 22 and the composite chip 50 of the effect control board 23, thereby synchronously resetting the power supply of each electronic element. As will be described later, when the program processing of the CPU circuit 51 enters an infinite loop state, the watchdog timer 58 (see FIG. 4(a)) incorporated in the CPU circuit 51 is started, and the sound circuit SND and the composite chip are activated. 50 are synchronously and abnormally reset.

Next, the payout control board 25, which is the frame-side member GM1, is directly connected to the power supply board 20 without going through the relay board, and outputs the same power failure signal ABN2 as the main control unit 21 receives, the backup power supply BAK, and the like. is received with the supply voltage of In addition, reset circuits RST1 and RST2 are installed in the main control unit 21 and the payout control unit 25, respectively, and a power reset signal is generated when power is turned on, and each computer circuit is power reset. .

Thus, in this embodiment, the reset circuits RST1 to RST3 are arranged in the main control section 21, the payout control section 25, and the performance interface board 22, respectively, and the CPU reset signal SYS is transmitted between the circuit boards. never transmitted. That is, since there is no wiring cable for transmitting the CPU reset signal SYS, the risk of abnormal resetting of the computer circuit due to noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each incorporate a watchdog timer, and do not receive regular clear pulses from the CPUs of the control units 21 and 25. If so, each CPU is forced to reset.

Further, the main control unit 21 is provided with an initialization switch SW that can be operated by a staff member. It is configured. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 25. ing.

In addition, the main control unit 21 and the payout control unit 25 receive the power failure signals ABN1 and ABN2 from the power supply board 20, and start necessary end processing prior to the power outage or closing of business. In addition, the backup power supply BAK is a DC 5V DC power supply that retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 even after the AC power supply 24V is cut off due to the end of business or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before the power shutdown after the power is turned on (power backup function). This pachinko machine is designed so that the memory contents of the RAM of each one-chip microcomputer are retained for at least several days.

As shown in FIG. 3, the main control unit 21 receives, from the payout control unit 25, a prize ball counting signal indicating the payout operation of game balls, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN. there is The status signal CON includes, for example, a supply shortage signal, a dispensation shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after the power is turned on.

Also, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 32 . While receiving the switch signal of the detection switch built into each of the winning holes 16 to 18 on the game board, it drives solenoids such as an electric tulip. Solenoids and detection switches are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21 . In addition, each switch signal indicating the winning state to the symbol start port 15 is converted into a switch signal of TTL level or CMOS level by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V). After that, it is transmitted to the main control unit 21 .

As described above, the effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are integrated by connector connection. DC voltages (5 V, 12 V, 32 V) of various levels are received from the substrate 20 (see FIGS. 3 and 4(a)).

As shown in FIG. 3 , the effect interface board 22 receives the control command CMD and the strobe signal STB from the main control section 21 and transfers them to the effect control board 23 . More specifically, as shown in FIG. 4(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the effect control board 23 via the input buffer 40. .

Also, the CPU reset signal SYS generated by the reset circuit RST3 is supplied to the performance control board 23 and the audio circuit SND such as the audio processor 27 via the input buffer 40 and the OR circuit G1. As shown, the OR circuit G1 is also supplied with the underflow signal UF of the WDT circuit 58, and when either of the two signals SYS and UF becomes active level, the internal circuits of the composite chip 50 and the audio circuit SND are activated. synchronously enter the reset state (abnormal reset). The internal circuit of the composite chip 50 to be abnormally reset includes the CPU circuit 51 and the VDP circuit 52, and the audio circuit SND to be abnormally reset includes the audio processor 27 and the audio memory .

As shown in FIG. 4A, the input buffer 44 of the effect interface board 22 receives switch signals for the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and outputs each switch signal to the CPU of the effect control board 23. It is transmitting to circuit 51 . Specifically, the 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and the 1-bit length indicating the ON/OFF state of the chance button 11 are transmitted to the CPU circuit 51 .

The effect interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and . As shown, an output buffer 42 is arranged corresponding to the lamp driving board 30 , and an input buffer 43 a and an output buffer 43 b are arranged corresponding to the motor lamp driving board 31 . Note that in FIG. 4A, the input buffer 43a and the output buffer 43b are collectively referred to as an input/output buffer 43 for the sake of convenience. The input buffer 43a receives the outputs SN0 to SNn of the origin sensors for grasping the current positions of the characters as movable effects (rotational positions of the effect motors M1 to Mn), and transmits the outputs to the CPU circuit 51 of the effect control board 23. there is

The lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37 are equipped with driver ICs of the same kind. is forwarding to Specifically, the serial signals are a lamp (motor) drive signal SDATA and a clock signal CK. , the performance motors M1 to Mn perform a role performance.

In the case of this embodiment, the lamp effect is executed by three lamp groups CH0 to CH2, and the lamp drive board 37 outputs the lamp drive signal SDATA0 of CH0 via the frame relay boards 35 and 36 as a clock. It is received in synchronization with the signal CK0. A series of lamp drive signals SDATA0 transmitted as a serial signal are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting state all at once.

The above points also apply to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. , the lighting state of the lamp group CH1 is updated all at once.

On the other hand, the driver IC mounted on the motor lamp drive board 31 receives the lamp drive signal transmitted in clock synchronization to drive the lamp group CH2, and receives the motor drive signal transmitted in clock synchronization to A performance motor group M1 to Mn composed of a plurality of stepping motors is driven. The lamp driving signal and the motor driving signal are a series of serial signals SDATA2, which are serially transmitted in synchronism with the clock signal CK1. , the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Next, the audio circuit SND will be explained. As shown in FIG. 4(a), the effect interface board 22 includes a voice processor (voice synthesis circuit) 27 that reproduces voice signals based on instructions received from the CPU circuit 51 (performance control CPU 63) of the effect control board 23. , an audio memory 28 for storing compressed audio data, which is the original data of the audio signal to be reproduced, and a digital amplifier 29 for receiving the audio signal output from the audio processor 27 are mounted.

The voice processor 27 accesses the voice memory 28 based on the operating parameters (set values by voice commands) received from the performance control CPU 63 in the voice control register, which is a built-in register, and reproduces and outputs necessary voice signals. . As shown in FIG. 4A, the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, the audio memory 28 can store data of 1 Gbit (=2 ²⁶ *16).

In the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by a 13-bit length phrase number NUM (000H to 1FFFH), and is equivalent to a series of background music. A maximum of 8192 types (=213) of (BGM), a group of dramatic sounds (announcement sounds), etc. are stored corresponding to the phrase number NUM. This phrase number NUM is specified by the setting value (operation parameter) of the voice command transmitted from the performance control CPU 63 to the voice control register of the voice processor 27 .

As shown in FIG. 4(a), the data bus and address bus of the CPU circuit 51 of the effect control unit 23 are connected to a clock circuit (real time clock) 38 and effect data memory 39 mounted on the liquid crystal interface board 24. has also reached The clock circuit 38 is connected to the lower 4 bits of the address bus of the CPU circuit 51 and the lower 4 bits of the data bus, so that the CPU circuit 51 can arbitrarily access it. The performance data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed, and is connected to the 16-bit address bus of the CPU circuit 51 and the lower 16-bit data bus. The game performance information and other information stored in the game are appropriately R/W-accessed from the CPU circuit 51 .

The clock circuit 38 and the performance data memory 39 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is turned off, the timekeeping operation of the clock circuit 38 is continued, and the game performance information stored in the performance data memory 39 is permanently stored (imparted non-volatility).

As shown on the right side of FIG. 4A, the effect control board 23 includes a composite chip 50 containing a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 for storing a control program for the CPU circuit 51, A DRAM (Dynamic Random Access Memory) 54 capable of accessing a large amount of data at high speed, and a CGROM 55 storing a large amount of CG data required for control of effects are installed.

FIG. 5(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the effect control section 23, including related circuit elements. As shown, the composite chip 50 of the embodiment includes a built-in CPU circuit 51 that issues a display list DL at predetermined time intervals, and image data that is generated based on the issued display list DL to display the display devices DS1 and DS2. A VDP circuit 52 for driving is incorporated. The built-in CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays transmission/reception data between them.

Also connected to the CPUIF circuit 56 are a control memory (PROGRAM_ROM) 53 for storing control programs and necessary control data in a nonvolatile manner, and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes. It is configured to be accessible from the built-in CPU circuit 51 .

Note that the display list DL describes a series of instruction commands that specify one frame of each of the display devices DS1 and DS2. In the case of this embodiment, the series of instruction commands includes a texture load command such as a TXLOAD command for reading and decoding an image material (texture) from the CGROM 55, and a VRAM area (index space) to be decoded in advance. texture setting commands such as the SETINDEX command, primitive drawing commands such as the SPRITE command for placing the decoded image material at a predetermined position in the virtual drawing space, and drawing commands to create the virtual drawing space. Environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area to be actually drawn on the display device in the drawn image, and the index table control system command (WRIDXTBL) related to the index table IDXTBL that manages the index space. is included.

Note that FIG. 7C shows a virtual drawing space (±8192 in the X direction: ±8192 in the Y direction), a drawing area that can be arbitrarily set in the virtual drawing space, and images to be output to the display devices DS1 and DS2. The relationship between the actual drawing areas in the frame buffers FBa and FBb that temporarily store data is shown.

The built-in CPU circuit 51 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer. A watchdog timer (WDT) 58 for forced resetting, a RAM 59 having a storage capacity of about 16 kbytes and used as a work area for the CPU, and a DMAC (Direct Memory Access Controller) for realizing data transfer without going through the CPU. 60, a serial input/output port (SIO) 61 having a plurality of input ports Si and output ports So, and a parallel input/output port (PIO) 62 having a plurality of input ports Pi and output ports Po. It is

For the sake of convenience, the expression "input/output port" is used, but in the effect control unit 23, the input/output port includes an input port and an output port that operate independently. This point also applies to the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (effect interface board 22) through an input/output circuit 64p. It receives the switch signal of the button 11, the control command CMD, and the interrupt signal STB. A 3-bit encoder output and a 1-bit switch signal are supplied to a parallel input/output port (PIO) 62 via an input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the effect control CPU 63 via the input/output circuit 64p, thereby activating the reception interrupt process. Therefore, the effect control CPU 63, which grasps the control command CMD based on the reception interrupt process, controls the sound effect, the lamp effect, the motor effect, and the image effect corresponding to the control command CMD through the effect lottery and the like in a unified manner. will do.

Although not particularly limited, in this embodiment, the SMC (Serial Management Controller) 78 of the VDP circuit 52 is used for the lamp effect and the motor effect. The SMC unit 78 is a composite controller incorporating an LED controller and a motor controller, and is configured to output a serial signal in clock synchronization. Also, the motor controller is configured to output latch pulses at arbitrary timings based on the values set in the predetermined control register 70, and to input serial signals in a clock-synchronized manner.

Therefore, in this embodiment, while the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, the latch pulse is output as the operation control signal ENABLE at an appropriate timing. . Further, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are serially input in a clock synchronous manner.

As described with reference to FIG. 4A, clock signals CK0-CK2, drive signals SDATA0-SDATA2, and operation control signals ENABLE0-ENABLE2 pass through output buffers 41-43 to predetermined drive substrates 30, 31, . 37. Further, the origin sensor signals SN0 to SNn are serially input to the SMC section 78 from the motor lamp driving board 31 via the input/output buffer 43. FIG.

However, it is not essential to use the SMC unit 78 in this embodiment. That is, since the CPU circuit 51 has a built-in general-purpose serial input/output port SIO61, it is also possible to use these ports to execute lamp effects and motor effects.

Specifically, as shown by the dashed lines in FIG. 5A, in the configuration shown by the dashed lines, the clock signals CK0 to CK2, CK2, Drive signals SDATA0 to SDATA2 are output, and operation control signals ENABLE0 to ENABLE2 are output via the input/output circuit 64p. For convenience, they are expressed as input/output ports and input/output circuits, but what actually functions are output ports and output circuits.

Here, the serial output port SO is configured with a built-in 16-stage FIFO register. Then, the DMAC circuit 60 is activated upon receiving an operation start instruction (see FIG. 10(b) ST18) from the effect control CPU 63, and from the lamp/motor drive table (see FIG. 10(b)), the necessary drive data is sequentially and DMA transferred to the FIFO register of the serial output port SO. The drive data stored in the FIFO register are serially output from the serial output port SO in clock synchronization. The DMAC circuit has a plurality of (for example, 4) DMA channels. The first DMA channel is used for DMA transfer of lamp drive data, and the second DMA channel is used for DMA transfer of motor drive data. ing.

Next, a WDT circuit 58 provided in the built-in CPU circuit 51 has a WDT counter that performs a down-counting operation based on set values in a plurality of control registers (WDT control register, etc.) accessible from the effect control CPU 63. configured as follows. This WDT counter starts from a predetermined initial value and counts down toward zero in a predetermined operation cycle. When the counted down value reaches zero, an internal interrupt (WDT interrupt) is generated and the active level underflow signal UF.

As described above with reference to FIG. 4(a), the underflow signal UF is transmitted to each part via the OR circuit G1, and the composite chip 50 and the audio circuit SND are synchronously and abnormally reset. However, the effect control CPU 63 returns the counter value to the initial value by writing a predetermined 1-bit value to the initialization bit of the WDT control register every predetermined time (for example, 1/30 second). avoiding occurrence. Note that when the counter value of the WDT counter returns to the initial value, the initialization bit also returns to the original value.

Thus, in this embodiment, the effect control CPU 63 only needs to write-access the initialization bit (1 bit) of the WDT control register. Since there is no need to output a clear pulse to , the control load is reduced accordingly. In addition, since a WDT interrupt occurs when an underflow abnormality occurs, by starting an appropriate WDT interrupt processing program, it is possible to nonvolatilely store the occurrence time of the abnormal reset in the effect data memory 39. - 特許庁FIG. 4(b) shows a circuit configuration in such a case, and the effect control CPU 63 is reset by software reset processing after executing the WDT interrupt processing program.

The DMAC circuit 60 transfers data from a transfer source (Source) to a transfer destination (Destination) in a predetermined DMA transfer mode for each predetermined data transfer unit, a predetermined number of times, based on a set value in a predetermined operation control register. , is a circuit that repeats data transfer.

For example, in an embodiment in which the serial output port SO functions (see the dashed line in FIG. 5A), the operation control register of the CPU circuit 51 stores the head address of the lamp/motor drive table (the head value of the transfer source address) and , the address of the input register of the serial output port SO (fixed value of the transfer destination address), the data transfer unit (8 bits), and the number of transfers are specified. Then, the DMAC circuit 60, which has received the operation start instruction in the predetermined operation control register, DMA-transfers the driving data to the predetermined transfer destination address while updating the transfer source address.

This point is substantially the same in the case of the embodiment in which the DMAC circuit 60 issues the display list DL (FIGS. 13 and 17(c)). That is, the effect control CPU 63 stores the head address of the transfer source (DL buffer), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, and The number of transfers and other conditions are set. These points are further discussed below with respect to FIG.

Generally, DMA transfer modes include a cycle-steal transfer mode, a burst transfer mode (pipeline transfer), and a demand transfer mode. By passing the bus control right to the effect control CPU 63 each time the cycle is executed, the operation of the effect control CPU 63 is prevented from being hindered.

FIG. 6 is a diagram for explaining the cycle steal transfer operation and the pipeline transfer. The DMAC circuit 60 operates with at least one cycle between read access initiation and write access initiation for one data transfer. In this empty cycle, the performance control CPU 63 can use the bus. As is clear from the comparison in FIG. 6, in pipeline transfer, the bus is not released to the CPU until one cycle (one-operand transfer) is completed. Since the bus is released to the CPU, the operation of the CPU is not greatly delayed.

Then, for example, when the display list DL is issued to the VDP circuit 52, in an embodiment using the DMAC circuit 60, the data transfer unit (1 operand) of one cycle is set to 32×2 bits, and the display list DL is stored. While appropriately increasing the source address of the built-in RAM 59 (+8 for each operand transfer), the DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 8) of the data transfer circuit 72 specified by the fixed address. running

As will be described later, in the embodiment, by adding the required number of NOP (no operation) commands to the display list DL, the overall data size is set to a fixed value (for example, 4×64=256 bytes, or its integer 32 bits×2 times of one operand transfer is repeated 32 times (or an integer multiple thereof) to complete the issue of the display list DL. Note that execution of the NOP command by the drawing circuit 76 does not, in fact, cause any change.

Next, the VDP circuit 52 will be described. The VDP circuit 52 includes a CGROM 55 that stores compressed data that is a constituent element of still images and moving images that constitute an image effect, and an external DRAM (Dynamic Random Access Memory) having a storage capacity of about 4 Gbit. Random Access Memory) 54, the main display device DS1, and the sub display device DS2 are connected. The DRAM 54 is preferably configured with DDR (Double-Data-Rate SDRAM).

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory with a storage capacity of about 62 Gbits. is configured to obtain Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is resolved, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by the HSS (High Speed Serial) method conforming to SerialATA.

Regardless of whether or not the HSS method conforming to SerialATA is adopted, the NAND type flash memory is mechanically more stable than the hard disk and is capable of high-speed access. Compared with DRAM and SRAM (Static Random Access Memory), there is a problem in random accessibility. Therefore, in this embodiment, a group of compressed data (CG data) is preloaded into the DRAM 54 prior to the drawing operation, thereby realizing smooth random access of the CG data during the drawing operation. ing. Incidentally, the access speed decreases in the order of built-in VRAM>external DRAM>CGROM.

More specifically, the VDP circuit 52 includes a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by an effect control CPU 63, and image data to be displayed on the display devices DS1 and DS2. A built-in VRAM (video RAM) 71 of about 48 Mbytes used at the time of generation, a data transfer circuit 72 for executing data transmission/reception between each part inside the chip and data transmission/reception with the outside of the chip, and the built-in VRAM 71 have Source and Destination. An index table IDXTBL capable of specifying address information, a preloader 73 that performs a preload operation, a graphics decoder (GDEC) 75 that decodes (decodes and decompresses) compressed data read from the CGROM 55, and still image data and moving images after decoding. A rendering circuit 76 that generates image data for each one frame of the display devices DS1 and DS2 by appropriately combining data, and a geometry engine 77 that generates a stereoscopic image by appropriate coordinate transformation as part of the operation of the rendering circuit 76. , three systems (A/B/C) of display circuits 74A to 74C capable of reading image data generated by the drawing circuit from the frame buffers FBa and FBb and executing appropriate image processing in parallel, and three systems ( A/B/C) output selection unit 79 for appropriately selecting and outputting the output of the display circuit 74, an LVDS unit 80 for converting the image data output by the output selection unit 79 into an LVDS signal, and an SMC capable of serial data transmission/reception. 78, a CPUIF portion 81 that relays data transmission/reception with the CPUIF circuit 56, a CG bus IF portion 82 that relays data reception from the CGROM 55, a DRAMIF portion 83 that relays data transmission/reception with the external DRAM 54, and a built-in and a VRAMIF unit 84 that relays data transmission/reception with the VRAM 71 .

FIG. 5B shows the relationship between the CPUIF section 81, the CG bus IF section 82, the DRAMIF section 83, the VRAMIF section 84, the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. FIG. As shown, the CG data acquired from the CGROM 55 is transferred to the preload area of the external DRAM 54 via the data transfer circuit 72 and the DRAM IF unit 83 as preload data, for example.

However, the above-described preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54, and may be the built-in VRAM 71 as well. Therefore, for example, in an embodiment in which no preload operation is performed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and VRAMIF section 84 (FIG. 5(b)).

By the way, in this embodiment, the built-in VRAM 71 stores the image data specifying the expansion area of the compressed data read from the CGROM 55 and the ARGB information (32 bits=8×4) of each of W×H display pixels of the display device. A frame buffer area to store the depth information of each display pixel and a Z buffer area to store the depth information of each display pixel are required. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of three primary colors.

Here, each area of the built-in VRAM 71 is indirectly accessed based on various instruction commands (textures, sprites, etc. described above) described in the display list DL by the effect control CPU 63, but the READ/WRITE access , it is troublesome to specify the destination address and the source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after resetting the CPU, a one-dimensional or two-dimensional logical memory space (hereinafter referred to as an index space) required for the drawing operation is secured, and an index number is assigned to each index space. allows access based on the index number.

Specifically, after resetting the CPU, the built-in VRAM 71 is roughly divided into three types of memory areas, and the necessary number of index spaces are secured in each memory area. By constructing an index table IDXTBL (see FIG. 7A) that stores index spaces and index numbers in association with each other, subsequent operations based on the index numbers are realized.

This index space needs to be (1) added after initial processing, and conversely (2) freed. Therefore, when the addition/release effect control CPU 63 operates, a flag that can determine whether or not it is the timing at which the addition/release processing can be performed, and whether or not the processing such as addition/release has actually been completed. A region FG is provided in the index table IDXTBL. The built-in VRAM 71 is roughly divided into three types of memory areas: an AAC area (a), a page area (b), and an arbitrary area (c). Corresponding to (c), the index table IDXTBL is divided into three (FIG. 7(a)).

Although not particularly limited, in the case of this embodiment, the built-in VRAM 71 includes (a) an index space and its index number are automatically assigned by internal processing, and an AAC area having a memory cache function; is divided into a page area in which an index space can be secured within the range of integral multiples of the two-dimensional space, and (c) an arbitrary area in which the start address STx and horizontal size Hx can be set arbitrarily. (See FIG. 7(b)). However, the head address STx of the index space, which is arbitrarily set in the arbitrary area, must have 0 in the lower 8 bits and be in units of predetermined bits (2048 bits=256 bytes).

After resetting the CPU, the maximum value of the memory space required for each and the top address (lower 8 bits = 0) are defined, and the AAC area (a) and the page area (b) are secured, and the remaining memory The area becomes an arbitrary area (c). Then, the required number of index spaces are secured in each of the areas (a), (b), and (c). When the arbitrary area (c) is used, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 32 bytes (256 bits), while the vertical size is a fixed value (for example , 2048 lines).

In any case, since the AAC area (a) is automatically given an index space and an index number by the VDP circuit 52, the decoding destination is set to the AAC area (a) by, for example, the SETINDEX command of the texture setting command. , the TXLOAD (texture load) command for reading CG data from the CGROM 55 only needs to specify the source address of the CGROM 55 and the horizontal and vertical sizes after expansion (decoding). Therefore, in the present embodiment, still images (textures) such as characters that appear temporarily during an announcement effect, etc., and I-stream moving images are decoded to the ACC area (a).

This AAC area (a) is provided with a memory cache function. The decoded data cached in (a) can be used, and redundant READ accesses and decode processing can be suppressed. However, when the AAC area (a) is used up, old data is automatically destroyed. ) is virtually never effective.

By the way, the term "texture" generally refers to the texture and feel of the surface of an object. , is used as a concept including not only image data to be pasted on drawing primitives such as triangles and squares, but also image data after decoding. When image data is to be copied (hereinafter referred to as movement for convenience) within the built-in VRAM 71, the original image data is set as a texture by the SETINDEX command of the texture setting commands, and then the SPRITE command is executed. will be executed.

By executing the sprite command, the Source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 7(c). If the correspondence relationship between the area and the index space that becomes the frame buffer is set in advance by environment setting commands (SETDAVR, SETDAVF) and texture setting commands (SETINDEX), for example, the sprite command can be used to access the virtual drawing space. By drawing, the Source image data of the movement source is drawn in a predetermined index space (frame buffer) (see FIG. 7(c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a), a page area (b) and an arbitrary area (c), each of which has an appropriate number of index spaces. , each index space is specified by an independent index number for each region (a), (b), and (c). The index number is, for example, 1 byte long, and the effect control CPU 63 freely assigns index numbers in the range of 0 to 255 to the page area (b) and the arbitrary area (c) (excluding the AAC area). will do.

Therefore, in this embodiment, as shown in FIG. 7(a), a pair of frame buffers FBa are secured in an arbitrary area (c) for the display device DS1, and index numbers 255, 254 is given. That is, an index space 255 and an index space 254 that are toggled to be used are secured as the frame buffer FBa for the main display device DS1. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of pixels in the horizontal direction of the display device DS1. Since each pixel is specified by ARGB information of 32 bits, the horizontal size of 1280 means 32×1280=40960 bits.

For the display device DS2, another pair of frame buffers FBb are secured in the arbitrary area (c), and index numbers 252 and 251 are assigned to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of pixels in the horizontal direction of the display device DS2.

The reason why the frame buffers FBa and FBb are secured in the arbitrary area (c) is that the arbitrary horizontal size can be set in the arbitrary area (c) as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because if the number of horizontal pixels is matched with the number of horizontal pixels of the display devices DS1 and DS2, no waste occurs in the reserved area. On the other hand, in the page area (b), only horizontal/vertical sizes that are integral multiples of the unit space of 128 pixels×128 lines can be set.

However, the vertical size of the two-dimensional index space secured in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280×vertical size 1024 is the valid data area for the main display device DS1. This point is the same for the sub-display device DS2, and in the frame buffer FBb, only the area of horizontal size 480×vertical size 800 becomes an effective data area for the sub-display device DS2 (FIG. 7(c), FIG. 10(d)).

The above points will be further described later, but in any case, the frame buffers FBa and FBb are alternately used as the drawing areas for the drawing circuit 76, and the double buffers (255/254, 252/251) are alternately used. Each double buffer (255/254, 252/251) is alternately used as a display area for the display circuits 74A, 74B. In this embodiment, since the Z-buffer for storing the depth information of the display pixels is not used, a missing number (253) occurs. Index spaces 253 and 250 provide Z-buffers for display devices DS1 and DS2.

Also, in this embodiment, when an additional index space (memory area) is to be secured in the optional area (c) in which the frame buffers FBa and FBb are secured, an index number starting from 0 is given. . Although it is not limited in any way, in the present embodiment, an effect image composed of characters and other still images can be arbitrarily set as a work area for an advance notice effect that appears in a part of the screen in an appropriate rotational posture as necessary. An index space (0) is secured in the area (c).

However, the use of a work area is not essential, and an index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, it is possible to secure an index space with dimensions that are multiples of a square unit space of horizontal size 128 (=4096 bits)×vertical size 128, so it is suitable for handling small-sized effect images.

By the way, in this embodiment, the background image is composed of moving images, and the image effects are realized almost exclusively by moving images. In particular, a large number (usually 10 or more) moving images are drawn at the same time during the variable presentation. Each of these moving images is stored in the CGROM 55 in a compressed state as a series of moving image frames. and Here, an I frame (Intra coded frame) means a frame in which an input image is directly compressed independently of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame for which forward predictive coding is performed, and requires an I-frame or P-frame positioned in the past in terms of time.

Therefore, in this embodiment, the IP stream moving image is developed in the page area (b) instead of the AAC area (a) where there is a concern that the old data will be destroyed. In other words, a series of video frames are always the same by securing a large number of index spaces (IDX ₀ to IDX _N ) in the page area (b) that can secure index spaces with dimensions that are multiples of horizontal size 128 x vertical size 128. is decoded using the index space IDXi of . Specifically, the SETINDEX command specifies that "the decoding destination of the IP stream moving image MVi is the index space (i) of the index number i in the page area (b)", and then the TXLOAD command is executed. .

Then, one moving image frame (either of a series of moving image frames) on the CGROM 55 specified by the TXLOAD command is first acquired in the ACC area (a), and then automatically activated by the GDEC (graphics decoder) 75. , one frame of the acquired moving image is decoded and developed in the index space (i) of the page area (b).

On the other hand, in this embodiment, I-stream moving pictures are handled in the same way as still pictures. to run. As a result, the moving image frame is acquired in the AAC area (a), and then the GDEC 75, which is automatically activated, expands the decoded data in the ACC area (a). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), is TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Pre-specified by command.

In any case, the IP stream moving image MVi and the I stream moving image MVj are generally composed of N moving image frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 in which the k-th (1≤k≤N) video frame is stored and the horizontal/vertical size after development. In this embodiment, most of the memory space of 48 Mbytes (about 30 Mbytes) of the built-in VRAM 71 is allocated to the page area (b), though not limited thereto.

It is also conceivable to provide a dedicated GDEC (graphics decoder) circuit in order to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is incorporated in the VDP circuit 52, it is sufficient to instruct the GDEC circuit of the head address of the compressed moving image data in the decoding process of the compressed moving image data composed of N compressed moving image frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, incorporating a plurality of such dedicated GDEC circuits for each compression algorithm further complicates the internal configuration of the VDP circuit 52 . Therefore, in this embodiment, software GDEC is used, and decoding processing is realized by software processing corresponding to each compression algorithm for data such as IP stream moving images, I stream moving images, still images, and other α values. The processing time difference between the hardware processing and the software processing does not matter so much, and the processing time that matters is mainly the access (READ) time from the CGROM 55 .

Next, returning to FIG. 5A to continue the description, the data transfer circuit 72 uses the resource (storage medium) inside the VDP circuit and the external storage medium as a transfer source port or a transfer destination port, and transfers data between them. This is a circuit that performs data transfer operations in a DMA (Direct Memory Access) manner. FIG. 8 is a block diagram showing the internal configuration of this data transfer circuit 72 together with related circuit configurations.

As shown in FIG. 8, the data transfer circuit 72 is configured to transmit/receive data to/from the CGROM 55, DRAM 54, and built-in RAM 71 via an integrated connection bus ICM having a router function. The CGROM 55 and DRAM 54 are accessed via the CG bus IF section 82 and the DMAM IF section 83 .

On the other hand, the built-in CPU circuit 51 issues the display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT built into the data transfer circuit 72 . The built-in CPU circuit 51 and the data transfer circuit 72 are bi-directionally connected. When the display list DL is issued, the transfer port register TR_PORT is a data write port for receiving one unit of data constituting the display list DL. function as The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control section 72d.

As shown, the effect control CPU 63 can write-access the transfer port register TR_PORT via the CPUIF unit 81, while the DMAC circuit 60 directly accesses the transfer port register TR_PORT when the DMAC circuit 60 is utilized. Write access. A series of instruction commands written in the transfer port register TR_PORT (that is, a series of instruction commands forming the display list DL) are processed in 32-bit units by a CPU bus containing a FIFO buffer with a FIFO structure (32 bits x 130 stages). It is configured to be automatically stored in the control unit 72d.

In addition, the data transfer circuit 72 executes data transmission/reception operations on transmission paths of three channels ChA to ChC, and has a FIFO buffer of FIFO structure (64 bits×N stages) ChA control circuit 72a (N=130 stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

Then, the instruction command string (display list DL) accumulated in the CPU bus control unit 72d is sent to the drawing circuit 76 or It is transferred to the preloader 73 . As indicated by the arrow, the display list DL is transferred from the CPU bus control section 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and transferred to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. configured to be

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL. 72b or ChC control circuit 72c, respectively, to the drawing circuit 76 or the display list analyzer of the preloader 73 as part of the display list DL.

The drawing circuit 76 then starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 performs necessary preload operations based on the transferred display list DL. The CG data of the CGROM 55 is read ahead into the preload area secured in the DRAM 54 by the preload operation, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed in relation to the TXLOAD command etc. is secured in the DRAM 54. stored in the DL buffer area.

On the other hand, a ChA control circuit 72a and a connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in RAM 71. FIG. Further, the IDXTBL access arbitration circuit 72f functions when accessing the built-in RAM 71 that requires the address information of the index table IDXTBL. Here, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL.

In the embodiment in which the preloader 73 functions, the rewrite list DL' stored in the DL buffer area of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b. It will be.

As described above, the data transfer circuit 72 of this embodiment has a data transfer source arbitrarily selected from various storage resources and a data transfer destination arbitrarily selected from various storage resources. It provides high-speed data transfer between As can be seen from FIG. 8, the storage resources on which the data transfer circuit 72 functions include not only the built-in RAM 71 but also external devices via the CPUIF section 56, CG bus IF section 82, and DRAMIF section 83. FIG.

And, like the amount of data to be acquired at one time from the CGROM 55 (memory sequential read), the amount of data transfer with the external device in which the ChA control circuit 72a functions is the display in which the ChB control circuit 72b and the ChC control circuit 72c function. The list DL is huge compared to the case of the list DL, and the amount of data transfer is greatly different from each other.

Here, it is conceivable that the unit data amount and the total transfer data amount can be finely set for these various types of data transfer. inhibited. Therefore, in the present embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to an integral multiple of the minimum data amount DTmin, thereby achieving high-speed and smooth data transfer operations. Realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transfer data amount is limited to integral multiples of this.

Therefore, the instruction command string of the display list DL accumulated in the FIFO buffer of the CPU bus control section 72d for each 32 bits is sent to the ChB control circuit 72b and the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin. It will be transferred and accumulated in each FIFO buffer.

The display list DL consists of a series of instruction commands. In this embodiment, the command length of the display list DL is an integer N times 32 bits corresponding to the write unit (32 bits) of the transfer port register TR_PORT. It is composed only of (N>0) instruction commands. Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can quickly and smoothly start command analysis processing (DL analyze). It should be noted that the command length of 32-bit integer N times does not necessarily mean that all of them are significant bits, but that it is 32-bit integer N times including non-significant bits (Don't care bits).

Next, the preloader 73 will be explained. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b), and preloads the CG data on the CGROM 55 referenced by the TXLOAD command to the DRAM 54. It is a circuit that transfers to the preload area of . In addition, the preloader 73 stores in the DL buffer of the DRAM 54 a rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer in relation to this TXLOAD command. Note that the DL buffer and the preload area are secured in advance during the initial processing after CPU reset (ST3 in FIG. 10).

The rewrite list DL' is transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b when the drawing operation of the drawing circuit 76 is started. ).

In this embodiment, since the preload area is set in the external DRAM 54 having a sufficient storage capacity, it is possible to preload multiple frames of CG data at once, for example. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the read-ahead operation of the CG data is appropriately set within the range of integral multiples of the operation period δ during the intermittent operation of the VDP circuit 52. Multiple preloading is realized with

However, in the following description, for the sake of convenience, an embodiment without multiple preloading will be described, so the preloader 73 of the embodiment completes the preloading operation for one frame during one operation period (.delta.). As will be described later with reference to FIG. 10, in this embodiment, the operation cycle δ of the VDP circuit 52 during intermittent operation is 1/30 second, which is twice the cycle of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command strings of the display list DL and the rewrite list DL' transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like. This is a circuit for drawing an image of one frame of each of the display devices DS1 and DS2 in a frame buffer formed in the VRAM 71. FIG.

As described above, in the embodiment in which the preloader 73 functions, the reference destination of the CG data of the rewrite list DL' is not the CGROM 55 but the preload area set in the DRAM 54. FIG. Therefore, sequential access to CG data that occurs during execution of drawing by the drawing circuit 76 can be executed quickly, and high-resolution moving images with rapid motion can be drawn without problems. In other words, according to this embodiment, it is possible to use an inexpensive SATA module as the CGROM 55 and execute complex and advanced image effects.

As described with reference to FIG. 7, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a readout area, and the two areas are alternately used by switching their uses. . Also, in this embodiment, since two display devices DS1 and DS2 are connected, two partitions of frame buffers FBa/FBb are secured as shown in FIG. Therefore, the drawing circuit 76 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS1, and draws the drawing area (writing area) of the frame buffer FBa for the display device DS2. Then, one frame of image data is drawn. Note that when image data is written in the drawing area, the display circuit 74 reads the image data in the other read area (display area) and outputs it to each of the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads the image data in the frame buffers FBa and FBb, performs final image processing, and outputs the data (see FIG. 9). The final image processing includes, for example, scaling processing for enlarging/reducing the image, subtle color correction processing, and dithering processing for minimizing the quantization error of the entire image. After undergoing these image processes, digital RGB signals (total of 24 bits) are output together with horizontal synchronizing signals and vertical synchronizing signals. As shown in FIG. 9, this embodiment is provided with three systems of display circuits A/B/C for executing the above operations in parallel. The image data of FBa/FBb/FBc are read out and the final image processing described above is executed. However, since there are two display devices in this embodiment, the frame buffer FBc is not secured and the display circuit 74C does not function.

In relation to this operation, the output selection section 79 of this embodiment transmits the output signal of the display circuit 74A to the LVDS section 80a, and transmits the output signal of the display circuit 74B to the LVDS section 80b (Fig. 9). Then, the LVDS unit 80a converts the image data (24-bit digital RGB signals in total) into LVDS signals, adds a pair for transmitting a clock signal, and outputs all five pairs of differential signals to the main display device DS1. ing. The main display device DS1 incorporates an LVDS signal conversion/reception unit RV, which restores the RGB signals from the LVDS signals and displays an image corresponding to the output of the display circuit 74A.

In this respect, the LVDS section 80b is the same. For a total of 24 bits of each 8-bit digital RGB signal, a pair for transmitting a clock signal is added, and all five pairs of differential signals are output to the conversion receiving section RV. The display device DS2 realizes image display by a total of 24-bit RGB signals received from the conversion receiving unit RV. Therefore, the sub display device DS2 and the main display device DS1 have a resolution of ²⁸ * ²⁸ * ²⁸ .

Note that the LVDS signal is not necessarily required. For example, when the transmission distance is short, the digital RGB signal is directly transmitted to the display device via the digital RGB section 80c. converts a digital RGB signal into a V-By-one (registered trademark) signal in a conversion transmitting section TR', transmits the V-By-one (registered trademark) signal to a conversion receiving section RV', and converts it back to a digital RGB signal in a conversion receiving section RV'. is also suitable. Although the dashed lines in FIG. 9 indicate this mode of operation, the above operation is possible for any output signal of the display circuits 74A to 74C by appropriately setting the operation of the output selection section 79. becomes.

Next, the SMC section 78 (Serial Management Controller) is a composite controller containing an LED controller and a Motor controller. Then, it outputs an LED drive signal and a motor drive signal in synchronization with the clock signal to the LED/Motor driver (driver IC with a built-in shift register) mounted on the external board, while outputting the latch pulse at an appropriate timing. configured for output.

Regarding the internal circuit and its operation of the VDP circuit 52 described above, the operation contents to be executed by the internal circuit are defined by the operation parameters (set values) set in the control register group 70 by the effect control CPU 63, and the execution of the VDP circuit 52 The state can be specified by reading the operation status value of the control register group 70 . The control register group 70 means a large number of VDP registers mapped in a memory space (0 to FFFFFH) of about 1 Mbyte on the memory map of the effect control CPU 63, and the effect control CPU 63 operates via the CPUIF unit 81. A parameter WRITE (setting) operation and an operation status value READ operation are executed (see FIG. 5B).

The control register group 70 includes a "system control register" in which initial setting values related to system operations such as interrupt operations are written, an AAC area (a) and a page area (b) in the built-in VRAM, and an index table IDXTBL. "Index table register" for construction or modification, etc., "Data transfer register" in which set values for data transfer processing by the data transfer circuit 72 between the effect control CPU 63 and the internal circuit of the VDP circuit 52 are written, and graphics A "GDEC register" for specifying the execution status of the decoder 75, a "drawing register" in which instruction commands and setting values relating to the drawing circuit 76 are written, and a "preloader register" in which setting values relating to the operation of the preloader 73 are written. , a “display register” in which setting values relating to the operation of the display circuit 74 are written, an “LED control register” in which setting values relating to the LED controller (SMC section 78) are written, and settings relating to the motor controller (SMC section 78). It contains a "motor control register" into which values are written.

In the following description, one or more registers RGij included in the control register group 70 may be referred to by the individual names described above, or may be generically referred to as VDP registers RGij. The internal operation of the VDP circuit 52 is controlled by writing an appropriate set value to a predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on the display list DL updated at appropriate time intervals and the set value in the predetermined VDP register RGij. In this embodiment, since the effect control CPU 63 is in charge of the lamp effect and the motor effect, the VDP register RGij also includes an LED control register and a motor control register.

Next, a unified effect control operation for image effect, sound effect, motor effect, and lamp effect realized by the composite chip 50 containing the built-in CPU circuit 51 and the VDP circuit 52 will be described. FIG. 10 is a flow chart for explaining the control operation of the performance control CPU 63 of the built-in CPU circuit 51. As shown in FIG.

The operation of the effect control CPU 63 includes main processing (a) that is started after CPU reset, timer interrupt processing (b) that is started every 1 ms, reception interrupt processing (not shown) that is started in response to the control command CMD, and display. and a VBLANK interrupt process (c) that is activated in response to a VBLANK signal generated at the start timing of the V blank (vertical blanking period) of the device DS1.

In the reception interrupt process, the control command CMD received from the main control section 21 is stored in a predetermined reception buffer so that it can be referred to in the main process (ST13), and the process ends. In the VBLANK interrupt processing, the interrupt counter VCNT is incremented for each VBLANK interrupt, and at the start timing of the main processing, based on the value of the interrupt counter VCNT, the interrupt The counter VCNT is cleared to zero (ST4).

On the other hand, as shown in FIG. 10(b), the timer interrupt processing includes progress processing (ST18) for ramp effects and motor effects, and sensor signal acquisition processing for acquiring origin sensor signals SN0 to SNn signals, chance button signals, and the like. (ST19). The lamp effect and the motor effect are controlled based on the effect scenario that centrally manages all the effect operations, and when the effect start time managed by the effect counter EN is reached, the motor drive table and the motor drive table are changed in the effect scenario update process (ST11). A lamp drive table is specified.

After that, the motor effect progresses based on the specified motor drive table, and the lamp effect progresses based on the specified motor drive table. As explained above, in some embodiments, the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect progresses every 1 ms, but the ramp effect progresses at an appropriate timing longer than 1 ms.

Next, the main processing (a) will be described for an embodiment in which the preloader does not function. As shown in FIG. 10(a), the main processing is divided into initial processing (ST1 to ST3) executed after the CPU is reset, and then regular processing (ST4 to ST14) which is repeatedly executed every 1/30th of a second. be done.

Since the steady process is started at the timing when the interrupt counter VCNT becomes VCNT≧2 (ST4), the operation period δ of the steady process is 1/30 second. This operating cycle δ is nothing but the substantial operating cycle δ of the VDP circuit 52 that operates intermittently under the control of the effect control CPU 63 . The reason why the judgment condition is set to VCNT≧2 is to take into account the possibility that the steady process (ST4 to ST14) is abnormally prolonged and the timing of VCNT=2 is missed. is designed so that it does not occur.

Continuing the description of the main processing (FIG. 10(a)) based on the above, in the present embodiment, in the initial processing, the built-in VRAM 71 with a storage capacity of 48 Mbytes is stored in the ACC area (a) having an appropriate storage capacity, It is appropriately divided into a page area (b) and an arbitrary area (c) (ST1). Specifically, for the ACC area (a) and the page area (b), the start address and necessary total data size are set in a predetermined index table register RGij (ST1). As a result, the ACC area (a) secured in this manner and the remaining area not included in the page area (b) become the arbitrary area (c).

Also, necessary index spaces IDXi are secured for the page area (b) and the arbitrary area (c) (ST2). Specifically, by setting necessary address information in a predetermined index table register RGij, an index space IDXi for each area (b) and (c) is secured.

For example, when index space IDXi is provided in page area (b), address information of arbitrary horizontal size Hx and arbitrary vertical size Wx corresponding to arbitrary index number i is stored in a predetermined index table register RGij. (ST2).

As described above, the index space IDXi of the page area (b) has a horizontal size of 128×vertical size of 128 lines as a unit space, and one pixel is specified by 32-bit information. Based on the setting of the size Wx, an index space IDXi of data size (bit length)=32×128×Hx×128×Wx is secured. The start address of the index space IDXi of the page area (b) is automatically assigned internally.

When the index space IDXi is provided in the arbitrary area (c), address information of an arbitrary start address STx and an arbitrary horizontal size Hx corresponding to an arbitrary index number i is stored in a predetermined index table register RGij. (ST2). Arbitrary means that the horizontal size Hx is arbitrarily determined in units of 256 bits, the lower 8 bits of the start address STx are 0, and is arbitrarily determined in units of 2048 bits. As described above, the vertical size of the arbitrary area is fixed to 2048 lines, so based on the setting of the horizontal size Hx, after the start address STx, the data size (bit length) = 2048 × Hx index A space has been secured.

As described above, the necessary number of index spaces IDXi are generated by setting the necessary address information in the predetermined index table registers RGij for the page area (b) and the arbitrary area (c) (ST2). . In response to this setting process (ST2), an index table IDXTBL for specifying address information of each index space IDXi is automatically constructed. As shown in FIG. 7A, the index table IDXTBL stores the start address of each index space IDXi together with other necessary information. ) is referred to when acquiring data from (see FIG. 8). The index space IDXi of the AAC area (a) is automatically generated when necessary and is automatically deleted, so the setting process of step ST2 is unnecessary.

As shown in FIGS. 7(a) and 7(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and index numbers are assigned to each. In an embodiment that does not use the Z-buffer, a pair of index spaces 255 and 254 assigned index numbers 255 and 254 are reserved as the frame buffer FBa. A pair of index spaces 252 and 251 to which index numbers 252 and 251 are assigned are secured as the frame buffer FBb. In this embodiment, a work area with index number 0 (index space 0) is also secured in the arbitrary area (c).

Also, in this embodiment, the necessary number of index spaces IDXi for decoding IP stream moving images are secured in the page area (a), and the index number i is assigned. However, initially, only the index space IDX ₀ for the background moving image (IP stream moving image) is reserved. Then, according to the necessity of the image effect (fluctuation effect and advance notice effect), the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij and the instruction command of the display list DL, After that, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 7A shows the index table IDXTBL during steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command described in the display list DL. and other necessary information are automatically set. In this embodiment, this AAC area (a) is used as a decoding area for textures such as still images.

The above operation of securing the index space is realized mainly by setting the index table register RGij included in the control register group 70. Following the processing of steps ST1 and ST2, another VDP register RGij is set to: By executing the necessary setting operation, the steady operation (intermittent operation) of the VDP circuit 52 shown in FIGS. 18 and 19 is made possible.

For example, by writing predetermined operation parameters (the number of lines and the number of pixels) in a predetermined display register RGij that defines the operation of the display circuit 74, the number of display lines and the number of horizontal pixels are set for each of the display devices DS1 and SD2. (ST30). As a result, in each of the frame buffers FBa and FBb, the vertical and horizontal dimensions of the valid data area (broken line portion in FIG. 10(d)) to be read-accessed by the display circuit 74 are specified.

Next, a predetermined operation parameter (address value) is written in a predetermined display register RGij to specify the vertical display start position and horizontal display start position for each of the frame buffers FBa and FBb (ST31). As a result, the valid data area whose vertical and horizontal dimensions are specified in the process of step ST30 is determined on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and the display start position is (0, 0) in the example shown in FIG. 10(d).

Subsequently, the display register RGij (DSPAINDEX) relating to the display circuit 74A driving the main display device DS1 and the display register RGij (DSPBINDEX) relating to the display circuit 74B driving the sub-display device DS2 are respectively set to "display area (0)". and "display area (1)" are set to define each display area (ST32).

Here, the "display area" means an index space (frame buffers FBa, FBb) from which image data should be read in order for the display circuits 74A, 74B to drive the display devices DS1, DS2. means either one of the double buffers in the frame buffers FBa and FBb. However, the display circuits 74A and 74B actually read the image data only in the "effective data area" specified in steps ST30 to ST31 in the display area (0) or the display area (1).

Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of the index number 254 in the VRAM arbitrary area (c) is defined as "display area (0)", and the index number in the VRAM arbitrary area (c) 255 index space 255 is defined as "display area (1)" (ST32).

As for the frame buffer FBb, the index space 251 of the index number 251 in the VRAM arbitrary area (c) is designated as "display area (0)", and the index space 252 of the index number 252 in the VRAM arbitrary area (c) is designated as "display area ( 1)” (ST32). It should be noted that defining the "display area" in the initial processing (ST3) is not particularly limited. You can switch.

In this embodiment, when the above initial processing (ST30 to ST32) is completed, next, the set value of the predetermined system control register RGij is set to the first type prohibition setting so that it will not be changed due to the influence of noise or the like. A predetermined prohibition value is set in the register RGij (first prohibition setting ST33).

Here, the setting values for which future writing is prohibited include (1) setting values related to the display clocks of the display devices DS1 and DS2, (2) setting values related to the LVDS sampling clock, and (3) selection of the output selection circuit 79. (4) a synchronous relationship between the plurality of display circuits DS1 and DS2 (that the display circuit 74B is subordinate to the operation cycle of the display circuit 74A); Although there is software processing for canceling the first prohibition setting, it is not used in this embodiment. However, it is also suitable to use it as needed.

Next, by setting a predetermined prohibition value in the type 2 prohibition setting register RGij, the VDP register RGij of the initial setting system is write-prohibited (second prohibition setting ST34). Here, the prohibited registers include the VDP registers RGij related to steps ST30 to ST32.

On the other hand, by setting a predetermined prohibition value in the third type of prohibition setting register RGij, it is possible to prohibit many VDP registers, including the VDP registers related to the setting process of steps ST1 to ST3 (see the 3 prohibition setting). However, it is not used in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily released by writing a release value to a predetermined release register RGij, and the set value can be changed during steady operation. is also possible.

Since the initial setting process has been described above, next, before describing the steady process (ST4 to ST14), the steady operation (intermittent operation) of the VDP circuit 52 controlled by the effect control CPU 63 is shown in FIGS. A schematic description will be given based on FIG. 19(b).

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 18 and 19. In the embodiment in which the preloader 73 is not used, as shown in FIG. 18A, the display list DLi completed by the effect control CPU 63 is: In the operation cycle (T1), the drawing circuit 76 is issued, and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by the drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb are output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle T1+δ, so that the image data are displayed on the basis of the subsequent drawing operations of the display devices DS1 and DS2. , becomes a display screen that the player perceives.

On the other hand, in the embodiment using the preloader 73, as shown in FIG. 19(a), the display list DLi completed by the effect control CPU 63 is issued to the preloader 73 in its operation cycle (T1), and the preloader 73 , interprets the display list DLi, performs the necessary look-ahead operations, and rewrites a portion of the display list DLi to complete the rewrite list DL'. The pre-read CG data and rewrite list DL' are stored in appropriate locations in the DRAM 54. FIG.

Next, the drawing circuit 76 acquires the rewriting list DL' from the DRAM 54 in the next operation period (T1+.delta.), and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewriting list DL'. . Then, the image data completed in the frame buffers FBa and FBb are output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle (T1+2δ), thereby enabling subsequent drawing of the display devices DS1 and DS2. Based on the action, it becomes a display screen that the player perceives.

The intermittent operation of the VDP circuit 52 has been briefly described above, but in order to realize the operations of FIGS. is repeatedly referred to, until the operation start timing is reached, and when the operation start timing (V blank start timing skipped by one) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady operation is started. In this embodiment, first, it is determined whether or not an operation start condition for starting steady operation is satisfied (ST5). Note that this determination timing is the timing of T1, T1+δ, T1+2δ, . The display timing of the display device DS2 is set at the initial setting (ST3) so as to follow the display timing of the display device DS1.

Since the operation start condition determined by the start timing of the vertical blanking interval (VBLANK) differs depending on whether or not the preloader 73 is used, an embodiment (FIG. 10) in which the preloader 73 is not used will be described first. In this case, the circuit configuration and program are originally designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 18(a). That is, based on the display list DL1 completed in the operating cycle (T1), the drawing circuit 76 should finish the drawing operation during the operating cycle (T1 to T1+δ). However, for example, like the display list DL3 completed in the operation cycle (T1+2δ) of FIG.

The determination process of step ST5 takes this situation into consideration, and the effect control CPU 63 accesses the status register RGij (a kind of the control register group 70) indicating the operation state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether the necessary operations have been completed. In an embodiment that does not use the preloader 73, for example, at timing T1+.delta. in FIG. 18(a), read access is made to the status information of the drawing circuit 76 to confirm that the drawing operation based on the display list DL1 has ended.

Then, if the operation start condition is not satisfied (unsuitable), the abnormality flag ER that counts the number of times of abnormality is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER is determined in the processing of steps ST9 and ST10 together with other serious abnormality flags ABN. On the premise that the serious abnormality flag ABN is in a reset state, if the number of consecutive abnormalities is not large (ER≤2), Effect command analysis processing is executed in the same manner as in the normal state (ST13).

In the effect command analysis process (ST13), it is determined whether or not the control command CMD is received from the main control board 21. If the control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes start preparation processing for a new variable performance based on the control command CMD instructing the start of the variable performance, and error notification start processing based on the control command CMD indicating the occurrence of an error.

Subsequently, in order to return the WDT timer to its initial value, the specified 1 bit is written to the initial bit of the WDT control register (ST14), and then the process returns to step ST4. The effect control CPU 63 does not need to output a clear pulse to an external device, and has the advantage of simply executing a write command to the built-in register, as described above.

In the above, the case where the operation start condition is not satisfied and the abnormality flag ER is ER≦2 has been described. The process (ST6) and the display list creation process (ST7) are skipped, and the production scenario does not progress (see ST8 to ST12). This is to prevent output of image data in the frame buffers FBa and FBb that are incomplete. Therefore, for example, in the operation cycle (T1+3δ) of FIG. 18(a), the image effect does not progress, and the original screen (the screen based on DL2) is redisplayed, resulting in a dropped frame.

Here, in order to avoid dropping frames, a configuration of waiting until an operation start condition is satisfied is also conceivable. However, there are many control processes (ST6 to ST12) to be executed by the effect control CPU 63, and it is necessary to secure the processing time for each. there is

However, even if a frame drop occurs, the progress of the image rendering will only be delayed by about 1/30 to 2/30 of a second compared to the ramp rendering and motor rendering progressing by the interrupt processing (FIG. 10(b)). Yes, and the player is unaware of this. Moreover, when a frame is dropped, the effect scenario process (ST11) including the process of updating the effect counter EN and the sound progress process (ST12) are also skipped, so that the ready-to-win effect, the advance notice effect, and the accessory that are started after that are skipped. In the production, there is no possibility that the start timing of the image production, sound production, lamp production, motor production, etc. is shifted.

That is, in the production scenario, the start timing of image production, sound production, lamp production, and motor production and the content of production to be executed thereafter are centrally managed. Since the timing is controlled, the synchronization of various effects will not be lost. For example, when there is an effect operation that combines an explosion sound, an explosion image, a character object movement, and a lamp flash operation, each of the above effect operations is correctly started in synchronization even after a frame drop occurs. be.

In the above, a comparatively minor abnormality has been described, but when the serious abnormality flag ABN is set or when the number of consecutive abnormalities is large (ER>2), an infinite loop state is entered after the determination in step ST10. there is As a result, the down-count operation of the WDT timer progresses, the composite chip 50 including the effect control CPU 63 is abnormally reset, and then the initial processing (ST1 to ST3) is re-executed, thereby preventing the occurrence of an abnormal situation. It is hoped that the root cause will be eliminated.

As described with reference to FIG. 4, when this abnormality occurs, the sound circuit SND is also abnormally reset, so that the image effect, sound effect, lamp effect, and motor effect all return to their initial states. However, since these reset operations have no effect on the main control unit 21 and the payout control unit 25, there is no danger of disappearance of the big win state or disappearance of prize balls.

Abnormalities have been described above, but in reality, the abnormalities described above rarely occur, even if they are minor. Based on this, the "display areas" of the frame buffers FBa and FBb for storing the image data to be read by the display circuit 74A and the display circuit 74B are toggled (ST6). As described above, "display area (0)" and "display area (1)" are defined in advance in the initial processing (ST3). 'display area' specifies which of display area (0)/display area (1).

By executing step ST6, the display circuit 74A alternately outputs image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) at each operation cycle δ. The data is read out to drive the display device DS1. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) every operation cycle δ, and displays the sub display device DS2. will drive. As described above, the display circuit 74 actually performs READ access only to the effective data area in the display area (0)/display area (1).

In any case, in this embodiment, since the "display area" is switched for each operation cycle, the display circuits 74A and 74B display the image data completed by the drawing circuit 76 in the immediately preceding operation cycle on the display devices DS1 and DS2. will start the output process to However, since the process of step ST5 is started at the start of the vertical blanking period (V blank) of the main display device DS1, the image data output process actually starts after the vertical blanking period is completed. will be In FIG. 18(a), the arrows shown in the display circuit column indicate the operation cycle of this output process.

When the processing of step ST6 having the above significance is completed, the effect control CPU 63 subsequently completes the display list DL specifying the image data to be output to the display device by the display circuit 74 in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, a list buffer area (DL buffer) of the RAM 59 is secured and the display list DL is completed there (see FIG. 8).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all the instruction commands including the EODL command are set to an integer N times the command length of 32 bits (N>0). It is limited to only instruction commands for As described above, an instruction command composed of 32-bit integer N times may include a Don't care bit.

In this way, the display list DL of the embodiment is composed only of instruction commands whose command length is an integer N times 32 bits (N>0). It is always an integral multiple of the minimum command length unit (32 bits=4 bytes). Furthermore, in this embodiment, considering the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is set to an integer multiple (1 or more) of the minimum data amount Dmin and Adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin=256 bytes, the data volume value of the display list DL is adjusted to any value of 256 bytes, 512 bytes, and so on.

Here, depending on the complexity of the content of the presentation, it is also suitable to adjust to 256 bytes or 512 bytes as appropriate. The data volume value of the display list DL is always adjusted to 256 bytes in consideration of not executing such complicated image effects.

However, this method is not limited in any way, and if the number of display devices is three or more, or if the game machine executes complicated image effects including the sub-display device DS2, it is adjusted to 512 bytes or 768 bytes. be done. In addition, the data volume value of the display list DL is adjusted to 256 bytes at the time of normal rendering, and the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes only when executing a special rendering. is also preferred.

However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. As an adjustment method, after the 32-bit length EODL command, a simple method (A) that fills the missing area with a 32-bit length NOP (No Operation) command, or after filling the missing area with a 32-bit length NOP command , and finally a standard method (B) that describes a 32-bit long EODL command. The data volume value (total amount of data) of the display list DL is terminated by the EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72 to obtain an integral multiple of the minimum data amount Dmin. A non-adjustment method (C) that secures the transfer amount of is also conceivable.

Here, when adopting the standard method (B), first, the command counter CNT is initialized to a specified value (64-1 corresponding to 256 bytes), and every time a significant instruction command is written in the DL buffer area , the command counter CNT is appropriately decremented, and when a series of significant instruction commands are written, the NOP command is written until the command counter CNT becomes zero, and finally the EODL command is written. In the case of this embodiment, the instruction command is limited to a command length N times an integer of 32 bits (N>0). Subtraction processing corresponding to N is performed.

On the other hand, when adopting the simple method (A), it is sufficient to first fill the entire list buffer area (DL buffer) with NOP commands when creating the display list DL. It seems that Also, from the viewpoint of simplicity, the no-adjustment method (C) seems to be superior. However, in this embodiment, the standard method (B) is basically adopted, and the actual amount of data from the top of the display list DL to the EODL command, that is, the amount of data up to the EODL command is always transferred to the data transfer circuit 72. is adjusted to be an integral multiple of the minimum data amount Dmin.

This takes into consideration an embodiment that utilizes the preloader 73. If the simple method (A) or non-adjustment method (C) is adopted, the amount of actual data in the display list DL up to the EODL command will be random. This is because the transfer of the rewrite list DL′ rewritten by the preloader 73 to the DRAM 54 and the transfer of the rewrite list DL′ from the DRAM 54 to the drawing circuit 76 are hindered. The ChA control circuit 72a of the data transfer circuit 72 functions when the rewrite list DL' is transferred to the DRAM 54, and the ChB control circuit 72b functions when the rewrite list DL' is transferred to the drawing circuit 76 (FIG. 16). See), in either case, only the rewrite list DL' up to the EODL command is transferred.

The advantages of the standard method (B) for adjusting the data volume values of the display list DL have been described above. Therefore, the use of the simplified method (A) and the no-adjustment method (C) is not prohibited at all.

However, in the following explanation, the details of the display list DL will be explained with reference to FIG. 11 on the premise that the standard method (B) is adopted in principle regardless of whether or not the preloader 73 is used.

Although not particularly limited, in this embodiment, the display list DL first describes an instruction command string (L11 to L16) for the main display device DS1, and then writes an instruction command string (L17 to L20) for the sub display device DS2. I am trying to describe it. Also, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Incidentally, FIG. 11 actually shows the procedure by which the effect control CPU 63 writes the instruction command into the list buffer area of the RAM 59 and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 11, at the top of the display list DL, an environment setting instruction command (SETDAVR) is written to set the upper left base point address (X, Y) on the index space IDX for the frame buffer FBa of the display device DS1. Define (L11). As described with reference to FIG. 7(a), in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Usually, by setting the base point address (X, Y)=(0, 0) corresponding to the effective data area for the display circuit 74, the frame buffer FBa is used by the drawing circuit 76 from the head position. .

In FIG. 7(c), the actual drawing area on the lower left side is indicated by L11, which means that the actual drawing area on the frame buffer FBa is moved to the base address (0, 0) means specified starting from position. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies the actual drawing area are not yet determined, and are determined by an instruction command (SETINDEX) L13, which will be described later. The instruction command L11 also designates whether or not to use the Z buffer.

Next, the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) are set in the virtual drawing space by the instruction command (SETDAVF) of the environment setting system, and the W x H dimension is set. is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn by a drawing instruction command (such as a sprite command) (see FIG. 7(c)). .

By means of this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area in which drawing contents are actually reflected on the display device DS1 and other non-drawing areas. The instruction command L12 (SETDAVF) associates the actual drawing area whose starting position (base point address) is defined by the instruction command L11 with the drawing area in the virtual drawing space.

In other words, the instruction command L12 defines a W×H real drawing area starting from the base point address corresponding to the drawing area in the virtual drawing space in the frame buffer FBa (the index space is undecided). It will be. Therefore, the drawing area specified by the instruction command L12 must be equal to or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area and the actual drawing area are defined to have the same dimensions as the effective data area for the display circuit 74 (FIG. 10(d)).

After the drawing circuit 76 executes the instruction commands L11 and L12, of the drawing contents drawn in the virtual drawing space, only those included in the drawing area are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawn content of the part protruding from the drawing area and the part described as the work area in FIG. 7C is not directly reflected in the frame buffer. Note that when a work area is secured in the virtual drawing space, a non-drawing area in the virtual drawing space is used.

Next, in the current operation cycle, the drawing circuit 76 defines where the content to be drawn should be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the double-buffered display device DS1, an index space IDX that serves as a "writing area" for drawing content based on the current display list DL is specified (L13). Specifically, the SETINDEX command, which is a command of the texture setting system, requires that (1) the frame buffer FBa is secured in an arbitrary area, and (2) an arbitrary index space IDX _N serving as a "write area" is set. An index number N on the region is specified.

For example, when N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically would have been defined to be index space IDX ₂₅₅ .

In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 7(a)), and one of them is designated by switching in a toggle manner (L13). This index number is the index number other than the display area (0)/(1) specified in step ST6 of the main processing. For example, when the display area (0) is specified for the display circuit 74 in the process of step ST6, the display area (1) becomes the “write area” for the drawing circuit 76. FIG.

As described above, after the correspondence relationship between the actual drawing area (W×H logical space) and the drawing area (W×H virtual space) is generally defined by the instruction command L11 and the instruction command L12, The instruction command L13 (SETINDEX) specifically specifying the index space IDX associates the W×H virtual space with the W×H logical space in the specific index space IDX.

In other words, the contents to be virtually drawn in the W×H virtual space based on a series of instruction commands from now on are the internal VDP that defines the correspondence between the virtual space and the internal VRAM 71 real addresses. Based on the conversion table, it becomes the image data of the built-in VRAM 71 (frame buffer).

Subsequently, an instruction command for executing a frame buffer clear process for filling the specified index space IDX with black, for example, is described as a "write area" (ST14, ST15). This is nothing but erasing processing of the image data written in the frame buffer FBa two operation periods before.

Specifically, the SETFCOLOR command, which is a type of environment setting command, is used to select, for example, black color, and the RECTANGLE command, which is a primitive drawing command, is used to specify that the rectangular area should be filled. The RECTANGLE command specifies the XY coordinates of the upper left end point and the lower right end point of the drawing area set in the virtual drawing space (virtual space corresponding to the frame buffer FBa) (see FIG. 7(c)). .

With the above processing, the rendering preparation processing is completed. Next, instruction commands for rendering appropriate textures such as still images and one frame of moving images in the virtual rendering space are listed. Typically, first, the index space IDX to which the texture is to be developed is specified by the SETINDEX command of the texture setting system, and then the TXLOAD command, which is the instruction command of the texture load system, is written, and the predetermined Textures are described in the display list DL so as to be developed in a predetermined index space IDX.

As described above, in this embodiment, the background moving image is composed of IP stream moving images. Therefore, for example, the index space IDX in which the background video should be developed is specified as the index space IDX ₀ of the page area (b) by the SETINDEX command of the texture setting system, and then the TXLOAD command of the texture load system is described. do. In the TXLOAD command, it is necessary to specify the start address of the CGROM 55 (texture source address) and the data size after expansion (horizontal×vertical) for the video frame to be loaded this time.

When the TXLOAD command is executed in the VDP circuit 52, one moving image frame (texture) of the background moving image is first captured in the AAC area (a), and then transferred to the page area ( b) in the index space IDX ₀ . Next, this one animation frame will be drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set "the index space IDX ₀ of the page area (b) is the texture to be processed subsequently", but the If you do, you can omit this SETINDEX command.

In any case, in a state where "the index space IDX ₀ of the page area (b) is the texture to be processed later" is specified, next, parameters for alpha blend processing are set, and so on. Write an instruction command for an appropriate inter-rendering operation system. Note that the α-blending process relates to a transparent/semi-transparent process between an image already written in the drawing area (frame buffer FBa) and an image to be overwritten from now on. Therefore, like the moving image frame of the background moving image, in the drawing operation of the first frame, it is not necessary to use the instruction command of the inter-drawing arithmetic system.

Next, by using the sprite command, which is a primitive drawing system instruction command, "the texture of the index space IDX ₀ of the page area (b) (one video frame of the background video)" is placed in the appropriate place (rectangular destination area) in the virtual drawing space. Describe the sprite command to draw in. For the sprite command, it is necessary to specify the upper left corner point and the lower right corner point of the destination area of the virtual drawing space.

This destination area is the whole or a part of the drawing area (virtual space defined on the virtual drawing space) previously associated with the actual drawing area (FBa) by the instruction commands L11 and L12. However, since the background moving image is usually drawn on the entire display screen, the destination area in such a case is the entire drawing area or more. A case where the Destination area is larger than the entire rendering area is, for example, a case where the background moving image is zoomed up.

With the above processing, the drawing of the moving image frame of the background moving image is completed. The display list DL is configured to draw various textures superimposed on the background moving image. As described above, a large number of moving images are required during the variable rendering. The command (NEWPIX) will be described.

For example, regarding the second IP stream video, after allocating an additional index space IDX ₁ in the page area (b) with the NEWPIX command, this index space IDX ₁ is specified (SETINDEX), and the second Instruct the development of one frame of the video (TXLOAD), and place the developed texture in the appropriate place in the drawing area (SPRITE). Normally, the Destination area in this case will be part of the drawing area.

After that, the index space IDX _k is secured one after another by the NEWPIX command, and then, while executing appropriate α-blending processing, if a plurality of IP streams are drawn in the drawing area, the drawing contents in the drawing area are , is sequentially stored as image data in the frame buffer FBa, which is the actual drawing area. When a plurality of N IP stream moving images are rendered, a plurality of N index spaces are functioning in the page area (b).

Then, when a series of variable effects is completed, the DELPIX command is used to release the index space IDX that is deemed unnecessary among the many index spaces IDX ₁ to _IDXk secured in the page area (b). The unnecessary index space IDX should be deleted.

When drawing a still image or an I-stream video, use the SETINDEX command to specify that these textures are to be decoded in the AAC area (a), and then execute the TXLOAD command to load the AAC area. The texture acquired in (a) is then developed in the ACC area (a) by the automatically activated GDEC 75 . Then, the developed texture can be drawn in the proper place of the drawing area by the sprite command.

In the explanation so far, each texture is directly drawn in the drawing area of the main display device DS1, but the operation is not necessarily limited to this. For example, if an appropriate drawing area is provided so as not to overlap the drawing area already reserved for the display device DS1 (FIG. 7(c)), and this drawing area is associated with the work area of the built-in VRAM 71, an intermediate A suitable drawing area can be constructed to complete an appropriate effect image. Here, the reason why the drawing area for the display device DS1 does not overlap is that the later association setting is prioritized for the overlapping area, and the drawing contents for that area are not reflected in the frame buffer FBa.

As shown in FIG. 7(c), the work area in this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, at the rendering timing for using this working area, an instruction command for associating the rendering area for the rendering image (see FIG. 7C) with the working area (actual rendering area of index space IDX ₀ ) is issued first. Note the columns (SETDAVR, SETDAVF, SETINDEX). As described above and shown in FIG. 7C, the rendering area for the effect image is secured in an area that is not included in the rendering area for the main display device DS1.

After that, it is sufficient to list instruction commands similar to the instruction command string L16 regarding the frame buffer _FBa to complete an appropriate effect image in the index space IDX0. In the case of this embodiment, since the effect image is composed of a still image, an instruction command ( _SETINDEX ) is written so that the decoded data is developed in the AAC area (a). A primitive drawing system instruction command (SPRITE) with the appropriate place as the Destination will be used. It should be noted that such an operation is repeated once or multiple times according to the content of the effect.

Then, after positioning index space IDX ₀ , which completes the effect image, as a texture (SETINDEX), the effect image (texture) of index space IDX ₀ is drawn in the proper place of the drawing area of DS1 for the main display device by the sprite command. do it. In such a case, it is conceivable to decompose the effect image in the index space IDX ₀ into triangular drawing primitives, rotate them to an appropriate angle, and draw them in the drawing area. Note that the texture rotation angle is associated with, for example, the reliability of the advance notice effect.

The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above. It is the same. That is, the starting XY coordinates of the frame buffer FBb are specified, (L17) is defined (usually X=0, Y=0), and the sub-display device DS2 is displayed on the virtual drawing space shown in FIG. 7(c). A drawing area is defined (L18).

By the way, in this embodiment, after the generation of the image data for the main display device DS1 is completed, the process shifts to the generation processing for the sub display device DS2. You can freely set the drawing area without any problem even if it overlaps with the drawing area of . Therefore, when developing a display list DL generation program, for example, when pasting an appropriate texture to a newly set drawing area with the SPRITE command, the setting of the operation parameter (Destination area) of the SPRITE command, etc. It can be standardized to some extent.

After the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the double-buffered display device DS2, an index space that serves as a "write area" for drawing contents based on the current display list DL. Identify the IDX (L19). The index number of this index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0)/(1) specified in step ST6 of the main processing.

After that, instruction command strings L20 to L22 for the sub display device DS2 are listed in the same manner as the instruction command strings L14 to L16 for the main display device DS1. It is also possible to use the effect image completed in the index space _IDX0 .

As described above, the instruction commands L11 to L22 forming the display list DL are all limited to commands having an integral multiple of 32 bits in the present embodiment. As described above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and the necessary number of NOP commands (L23) as dummy commands are added. After that, it ends with the EODL command (L24). That is, the embodiment of FIG. 11 adopts the standard method (B) described above.

However, even if the standard method (B) is adopted, it is not essential to fix the total data amount of the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, if the total data amount of the display list DL excluding the NOP command exceeds 256 bytes (for example, during a special performance period), the total data amount of the display list DL may be added with the NOP command. , adjusted to N×256 bytes of 512 bytes or more. As described above, when the standard method (B) is adopted, the end of N×256 bytes is terminated with the EODL command.

The configuration of the display list DL has been described in detail above, and the effect control CPU 63 issues the completed display list DL of fixed byte length to the VDP circuit (ST7-ST8). FIG. 12 is a flow chart explaining the DL issuing process (ST8 in FIG. 10) in which the effect control CPU 63 directly write-accesses the transfer port register TR_PORT of the transfer circuit 72 and issues the display list DL to the drawing circuit 76. FIG. The transfer port register TR_PORT is a kind of data transfer register RGij that defines the operation contents of the data transfer circuit 72 .

In order to implement the DL issuing process, first, it is necessary to set necessary set values in a plurality of data transfer registers RGij that define the operation contents of the data transfer circuit 72 . Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are specified in a predetermined data transfer register RGij. Although the contents of the setting are not particularly limited, here, it is assumed that the data transfer operation is executed while checking the remaining amount of the FIFO buffer in relation to the CPU IF section 56 via the ChB control circuit 72b and the CPU bus control section 72d. Set (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in a predetermined data transfer register RGij. As described above, in this embodiment, the total data amount of the display list DL is adjusted to an integral multiple of 256 bytes, so that value is set. Note that the total amount of data=256×N is also integer N times the minimum data amount Dmin of the data transfer circuit 72 . Normally, the multiple N is 1 or 2, but in the following explanation, it will be explained as N=1.

Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit long register, the effect control CPU 63 executes a register write operation to the transfer port TR_PORT every 32 bits. It will be. Therefore, the value of the management counter CN that manages the number of register writes is initialized to 64 (ST21). If the non-adjustment method (C) is adopted, at this timing, the data transfer amount that is an integral multiple of the minimum data amount Dmin is determined and the management counter CN is set.

Since the initial setting is completed by the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and the predetermined drawing register RGij that defines the operation of the drawing circuit 76 is set. Based on the value, the drawing operation is started (ST23). As a result, after that, the effect control CPU 63 ensures quick and smooth Analyze processing by the drawing circuit 76 (display list analyzer) with respect to the instruction command sequence for the register write operation to the transfer port TR_PORT.

It should be noted that the fact that the instruction commands listed in the display list DL are limited to those with a command length of 32-bit integral multiples also effectively contributes to the quick and smooth Analyze processing. Timings t1, t2, t3, and t4 in FIG. 18(a) indicate the operation timings of step ST23. Since the display list DL issuing process (ST8) ends virtually instantaneously, the time span required for the issuing process is not shown in FIGS.

Subsequently, it is confirmed whether or not the setting in step ST22 has functioned (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes more processing time than the register write operation (setting operation) by the effect control CPU 63, so the data transfer circuit 72 in an incomplete state is given subsequent instructions. because there is no If the operation does not start even after waiting for a predetermined period of time, the serious abnormality flag ABN is set and the DL issuing process ends (ST25). As a result, the watchdog timer 58 then functions and the composite chip 50 is abnormally reset (ST10).

However, since the setting in step ST22 is normally completed quickly, the FIFO buffer (32 bits×130 stages) of the CPU bus control section 72d is confirmed not to be full (ST26). , the instruction command is written to the transfer port TR_PORT line by line from the top line constituting the display list DL (ST28).

Then, while decrementing the management counter CN (ST29), the processing of steps ST26 to ST29 is repeated until the management counter CN becomes zero (ST30). In the case of this embodiment, the minimum data amount Dmin is defined in the data transfer circuit 72, so the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer. transfer operation.

In any case, in this embodiment, the DL issuance processing (ST28) is quickly completed. In the determination, there may be cases where the FIFO buffer Full state is not resolved even after waiting for a predetermined time. In such a case, after setting initialization data in a predetermined VDP register RGij to initialize the drawing circuit 76 and the data transfer circuit 72, the serious abnormality flag ABN is set and DL issuance processing is started. Finish (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and have completed a certain amount of processing. (2) set all internal control circuits to their initial state; (3) initialize GDEC 75; (4) AAC It includes initializing the region's cache state. Similarly, the initialization processing of the data transfer circuit 72 includes initialization processing of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

In any case, as a result of setting the serious anomaly flag ABN, the watchdog timer 58 then functions and the composite chip 50 is abnormally reset (ST10), so the drawing circuit 76 and data transfer circuit 72 are initialized. Processing is not necessarily required. On the other hand, when the drawing circuit 76 and the data transfer circuit 72 are initialized, as a result, recovery from the abnormality can be expected. It is also preferred to do

This point is the same in the processing of step ST25, and after initializing the data transfer circuit 72 and the drawing circuit 76, it is preferable to return to the processing of step ST20 without setting the serious abnormality flag ABN. However, in such a case, the number of re-executions of the DL issuance process is counted, and if the number of re-executions exceeds the limit value, the serious abnormality flag ABN is set and the DL issuance process is terminated.

FIG. 12(b) is a confirmation illustration of a normal operating state. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and an operation based on each instruction command is executed.

For example, when the instruction command (TXLOAD) is executed, the necessary texture is read out from the CGROM 55 and acquired in the AAC area (a). Later data is expanded in a predetermined index space. Also, depending on the instruction command, the geometry engine 77 and others function, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of each part of the drawing circuit 76. will be

Next, the case where the display list DL is issued through the DMAC circuit 60 will be described with reference to FIG. Of the first to fourth DMA channels built in the DMAC circuit 60, the third DMA channel is used, although not limited in any way.

In the embodiment of FIG. 13, first, a predetermined data transfer register RGij and a predetermined drawing register RGij are each set to a clear value to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). Also in the case of FIG. 12, such an initialization process may be executed first.

In the process of FIG. 13, next, it is confirmed by reading a predetermined status register RGij that specifies the operating states of the data transfer circuit 72 and the drawing circuit 76 that the initialization process has been completed normally (ST21). If the initialization is not possible, the serious abnormality flag ABN is set and the process ends (ST22). However, such a situation almost never occurs in practice.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are set in a predetermined data transfer register RGij. Although the contents of the setting are not particularly limited, here, the transfer protocol from the CPUIF section 56 to the ChB control circuit 72b and the transfer protocol to the CPU bus control section 72d are set to follow the settings in the DMAC circuit 60 (ST23). ).

Next, the total transfer size is set in a predetermined data transfer register RGij. As in the case of FIG. 12, the data total amount=256. Note that when the non-adjustment method (C) is adopted, at this timing, the total transfer size that is an integer multiple of the minimum data amount Dmin is determined and set.
Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). Timings t1, t2, t3, and t4 in FIG. 18(a) are also operation timings of step ST25. Then, after starting the operation of the DMAC circuit 60 (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

The processing for starting the operation of the DMAC circuit 60 is as shown in FIG. ST40). The detailed contents of the operation are the same as the process shown in FIG. 14, and are divided into the process of prohibiting DMAC transfer (ST53) and the subsequent standby process (ST54).

Such processing is provided because (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in main processing and timer interrupt processing (FIG. 10); (2) In another embodiment in which the process of step ST5 in FIG. 10 is not provided, the DMAC circuit 60 that has started issuing the display list DL may not be able to complete the DL issuing operation within its operation period (δ). It is a consideration of what you can get.

In such an exceptional situation, if a new setting value (such as a contradictory setting value) is additionally set to the DMAC circuit 60 in operation, normal DMA operation cannot be ensured at all, and serious trouble may occur. Although it is a concern, providing the process of step ST40 ensures normal operation based on subsequent set values. That is, even in the modified embodiment that partially modifies the present embodiment, it is possible to realize normal DMA operation thereafter regardless of the preceding trouble.

After executing the processing of step ST40 having the above significance, next, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in FIG. 6, the cycle steal transfer mode is selected and one operand transfer is 32-bit transfer×2 times. Also, the Source address is the address of the list buffer area (DL buffer) of the RAM 59 and should be recognized as increasing sequentially, while the Destination address is the transfer port TR_PORT and should be a fixed value.

Next, the start address of the DL buffer of the RAM 59 is set in a predetermined operation control register that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). Also, after setting the total transfer size, that is, the total amount of data of the display list DL to 256 bytes (ST44), the DMA operation of the DMAC circuit 60 is started (ST45).

By the way, the explanation so far is based on the premise that the actual bit length of all instruction commands is an integral multiple of 32 bits. However, since the display list DL and the configuration of the instruction command are not necessarily limited, such a case will be described below.

For example, when the total data amount X of the display list DL is an arbitrary value X that is not an integer multiple of 32 bits, including the case of adopting the non-adjustment method (C), in the process of step ST44, this arbitrary value X is adjusted to an appropriate transfer amount MOD, and then the total transfer size setting process is executed. Here, an appropriate transfer amount MOD is defined based on the settings for one-operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72 .

Specifically, if the one-operand transfer setting is N bytes×M times, the transfer amount MOD is adjusted to an integer multiple of N×M (bytes) and an integer multiple of Dmin (bytes). be done. For example, if N×M=8×4 and Dmin=256, the arbitrary value X (=300) bytes is adjusted to the transfer amount MOD (=512) bytes.

As described above including the general theory, the DMA operation of the DMAC circuit 60 starts the cycle steal transfer operation as shown in FIG. In that case, every 32 bits are transferred to the transfer port TR_PORT. The transferred data is transferred to the drawing circuit 76 via the transfer circuit ChB.

In order to realize such an operation, in this embodiment, subsequent to the process of step ST45, the transfer operation of the data transfer circuit 72 is started and the process ends (ST27). After that, the data transfer circuit 72 receives the instruction command string of the display list DL from the DMAC circuit 60 in units of the minimum data amount Dmin, and transfers it to the drawing circuit 76 . The drawing circuit 76 then executes the drawing operation based on the instruction command of the display list DL. Therefore, after the process of step ST27, the effect control CPU 63 can start the process of step ST11 in FIG. , lamp effects and motor effects can be controlled.

FIG. 13(c) illustrates the content of this operation. Prior to DMA transfer, the operation of the drawing circuit is started (ST25), the display list analyzer of the drawing circuit 76 quickly and smoothly executes the Analyze processing, and other operations such as the GDEC 75 and the geometry engine 77 Based on this, one frame of image data is generated for each of the display devices DS1 and DS2 in the frame buffers FBa and FBb.

By the way, the configuration of FIG. 13 in which the DL issuing process ends with the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 20 and 21, when the sound effects, lamp effects, and motor effects are controlled by another CPU, normal operation of the DMAC circuit 60 and the data transfer circuit 72 is performed after the process of step ST27. It is preferable to check FIG. 14 is an operation following step ST27 in FIG. 13, and is a flowchart for explaining normal operation confirmation processing.

First, a predetermined status register is referred to confirm that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). It also confirms that the data transfer circuit 72 has completed the transfer operation (ST51). Normally, the DL issuing process of FIG. 13 is completed through such a route.

On the other hand, even if it waits for a predetermined time, . If the operation of the DMAC circuit 60 is not completed or the transfer operation of the data transfer circuit 72 is not completed, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72. to initialize the DL issuing process (ST52). This operation is based on the fact that the process of issuing the display list DL has not ended normally.

In this case as well, the rendering circuit 76 has already started operating and has completed a certain amount of processing. (2) Initialize all internal control circuits (3) Initialize the GDEC 75 (4) Initialize the cache state of the AAC area is included.

Next, after prohibiting a new DMA transfer operation (ST53), it waits for the completion of the transfer operation of one operand being executed (ST54). As described above, in this embodiment, 32-bit transfer×2 times is used as one operand to avoid abrupt initialization of the DMAC circuit 60 in operation.

Then, when this preparatory work is completed, a clear value is set in a predetermined operation control register that defines the operation of the DMAC circuit 60 to initialize the DMAC circuit 60 (ST52). Then, the serious anomaly flag ABN is set, and the DL issuing process ends. In this case, it is preferable to return to step ST20 in FIG. 13 and re-execute the DL issuance process without setting the serious abnormality flag ABN, because the process of steps ST52 and ST55 can be expected to restore the abnormality. be. However, if the number of re-executions of the DL issuance processing (ST23 to ST27) is counted and the number of re-executions exceeds the limit value, it is necessary to set the serious abnormality flag ABN and finish the DL issuance processing.

Next, main processing when using the preloader 73 will be described with reference to FIG. The process of FIG. 15 is similar to the process of FIG. 10, but first, the content of the start condition determination (ST5') is different. That is, in the embodiment using the preloader, at the start of each operation cycle, the status information of the drawing circuit 76 and the preloader 73 is read-accessed to confirm that the drawing operation based on the display list DL1 is completed and that the display list DL2 is completed. is completed (ST5').

As shown in the time chart of FIG. 19(a), the preloader 76, for example, based on the display list DL1 issued in the operation period (T1), performs a prefetch operation (preload operation) during the operation period (T1 to T1+δ). should have finished. Also, the drawing circuit 76 should have completed the drawing operation based on the display list DL1 during the operation cycle (T1+δ to T1+2δ) based on the operation start command specified in the operation cycle (T1+δ), for example.

Therefore, in the start condition determination (ST5'), read access is made to the status information of the VDP register RGij regarding the drawing circuit 76 and the preloader 73 to confirm the normal operation. FIG. 19(a) shows a state in which normal operation is confirmed at the determination timings of the operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but the preload operation is not completed at the determination timing of the operation cycle T1+3δ. .

Then, when such an abnormality occurs, the abnormality flag ER is incremented (ER=ER+1), and the process of step ST9 is performed. Therefore, as in the case of the embodiment of FIG. 10, frame drop occurs. That is, the same screen is displayed again because the display area switching process (ST6) is skipped. The operating period (T1+3δ to T1+4δ) shown in FIG. 18(a) indicates the operating state.

If the start condition is not satisfied in step ST5', the drawing circuit 76 is not operated because the drawing operation start instruction (PT10) based on the rewrite list DL' is not executed for the drawing circuit 76. state and no new display list is generated. In FIG. 19A, timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), more precisely, the timing of step ST26 in FIG.

The case where the judgment in step ST5' is not suitable has been described above, but in the normal case, after the display areas of the frame buffers FBa and FBb are toggled (ST6), the rewrite list DL is sent to the drawing circuit 76. ' is started (PT10). The specific contents are as shown in FIG. DL' is acquired and the drawing operation is executed.

Before explaining the flow chart of FIG. 16 which realizes this operation, the operation of the preloader 73 is confirmed. has been completed, and the prefetched data has already been stored in the preload area secured in the external DRAM 54 . Also, the source address of the texture load command (TXLOAD) described in the display list DL is rewritten to the address of the preload area, and stored in the DL buffer of the external DRAM 54 as the rewrite list DL'. .

In this rewriting process, the total data amount of the display list DL does not change, and the total data amount of the rewriting list DL' is the same as that of the display list DL. Also, the display list DL is created by the standard method (B), and the end of the rewrite list DL' is the EODL command as in the case of the display list DL.

16 based on the above, the effect control CPU 63 first sets a clear value in a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively, and activates the data transfer circuit 72 and the drawing circuit 76. Initialize (ST20). Next, it is confirmed that the initialization processing has been completed normally (ST21), and if the initialization is not completed even after a predetermined time has passed, the serious abnormality flag ABN is set and the processing ends (ST21). ST22).

Since the initialization of the data transfer circuit 72 and the drawing circuit 76 normally ends normally, the transmission route inside the data transfer circuit 72 is set to a predetermined data transfer register RGij (ST23). Specifically, data is set to be transferred from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the head address of the DL buffer of the external DRAM 54 storing the rewrite list DL' is set in a predetermined data transfer register RGij (ST24).

Also, for this rewrite list DL', the total transfer size is set in a predetermined data transfer register RGij (ST25). As described above, the total data amount of the rewrite list DL' is the same as the total data amount of the display list DL, specifically, 256 bytes, for example.

Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST26). Timings t1, t2, t3, and t4 in FIG. 18(a) are also operation timings of step ST26. Then, the data transfer circuit 60 is started to operate based on the set value in the predetermined data transfer register RGij, and the process is finished (ST27). After that, the effect control CPU 63 is not particularly concerned with the operation of the data transfer circuit 72 or the drawing circuit, and shifts to the display list generation process (ST7) that will be executed in the next operation cycle.

On the other hand, the drawing circuit 76, which starts operating at the timing of step ST26, executes a drawing operation based on the rewrite list DL' to generate image data based on the rewrite list DL' in the frame buffers FBa and FBb. In this operation, the drawing circuit 76 does not read-access the CGROM 55 but exclusively accesses the preload area, so that a series of drawing operations can be completed quickly.

Since the contents of the processing of step PT10 have been described above, returning to FIG. 15 to continue the description. It is created based on the standard method (B) (ST7). For example, in the operation period (T1) shown in FIG. 19A, the display list DL to be referred to by the drawing circuit 76 is created in the operation period (T1+.delta.), which is the next cycle.

Next, the effect control CPU 63 issues the created display list DL to the preloader 73 instead of the drawing circuit 76 (PT11). Specific operation contents are as shown in FIG. First, with respect to the embodiment (FIG. 10) that does not use the preloader 73, the effect control CPU 63 issues the display list DL directly to the drawing circuit 76 (FIG. 12) and via the DMAC circuit 60. 17(b) and 17(c) show almost the same operation except that the issue destination is the preloader 73. .

FIG. 17(a) is a flow chart for explaining the operation of FIG. 17(b), which is almost the same as the flow chart of FIG. However, it is set that data will be transferred from the CPUIF section 56 via the ChC control circuit 72c, and that the CPU bus control section 72d will perform the data transfer operation while checking the remaining capacity of the FIFO buffer (ST20). In the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set in a predetermined data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value in the preload register RGij that defines the operation of the preloader 73 (ST23).

As a result, after that, the preloader 73 executes necessary analysis (Analyze) processing for each instruction command written by the effect control CPU 63 to the transfer port TR_PORT, and detects an instruction command (TXLOAD) to read-access the CGROM 55. , the texture is preloaded and stored in the preload area of the DRAM 54 . Also, the rewrite list DL' in which the source address of the texture is changed is stored in the DL buffer area of the DRAM 54. FIG.

Timings t1, t3, and t5 in FIG. 19(a) actually indicate the operation timings of step ST23 in FIG. However, even in this embodiment, if some kind of abnormality occurs during the process of issuing the display list DL, the processes of steps ST25 and ST27 are executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the display list DL issuing process (ST20 to ST30) is re-executed within a possible range. The initialization processing of the preloader 73 includes erasing the incomplete rewrite list DL' and clearing the preload area in which the preload data is newly stored.

Although the case where the preloader 73 is used and the case where the preloader 73 is not used have been described in detail above, the specific operation contents are not particularly limited. FIG. 18(b) shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the drawing circuit 76 with a delay of one operation period δ instead of the generated operation period. In such an embodiment, rendering circuit 76 can use substantially the entire time of one operating period (.delta.), thereby reducing the possibility of frame dropping.

Also, FIG. 19(b) shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the preloader 73 with a delay of one operation cycle instead of the generated operation cycle. In this case, the preloader 73 can use substantially the entire time of one operation period (δ) to perform the preload operation, again reducing the possibility of frame dropping.

In the explanation so far, the composite chip 50 is used, but the effect control CPU 63 and the VDP circuit do not necessarily need to be integrated into one element. Furthermore, in the above embodiment, the entire production control is controlled by a single CPU (production control CPU 63), but the upstream CPU and the downstream production control CPU 63 cooperate with each other to produce A control action may be performed.

20-21 are block diagrams illustrating such embodiments. As illustrated, in this embodiment, the upstream effect control CPU controls the sound effect, the lamp effect, and the motor effect. On the other hand, the built-in CPU 50 on the downstream side controls only the image effect based on the control command CMD' received from the effect control CPU.

When adopting such a configuration, the built-in CPU 50 does not need to execute the processing of step ST12 in FIG. 10(a) and the processing of FIG. 10(b). DL can be generated, and more complex and advanced image effects such as 3D (Dimension) can be realized. In such a case, the display list becomes large, but in that case, the total amount of data in the display list DL is adjusted to 512 bytes or more N×256 bytes by adding dummy commands. .

Further, since the operation of the built-in CPU 50 on the downstream side is specialized for image effect control, it is possible to confirm that the drawing operation is completed after issuing the display list DL. The lower part of FIG. 12 shows an example of operation control in this case, and if the drawing operation is not completed even after the limit time is exceeded, the serious abnormality flag ABN is set and the process ends (ST32). Since the process of the built-in CPU 50 on the downstream side is only image effect control, it may simply wait for completion of the drawing operation in an infinite loop.

When adopting such a configuration, the start condition determination (ST5) of FIG. 10(a) can be repeated for a predetermined period of time. Even with this configuration, if the delay in completion of the drawing operation is not so long, the only problem that arises is the delay in switching between the display area (0) and the display area (1). That is, like the operation cycle T1+3δ shown in FIG. 22(a), in one operation cycle in which the display operation is repeated twice, only the first half is in a frame drop state, and the latter half is displayed as a normal frame.

This point is the same when using a preloader, and the start condition determination (ST5') of FIG. 15(a) can be repeated for a predetermined time. If there is a slight delay, only the first half of the operation cycle T1+3δ shown in FIG. However, if the completion of the drawing operation is significantly delayed, a complete frame drop will occur as in the operation cycle T1+3δ in FIG. 18(a). will start. Therefore, after that, based on the underflow signal UF, all or part of the effect control operation (only the image effect) should be abnormally reset. This point is the same when the preloader is not used.

Further, when the control operation of the built-in CPU 50 is specialized for image presentation control, in an embodiment employing DMA transfer, as shown in the lower part of FIG. Operation completion and operation completion of the DMAC circuit 60 are determined (ST50' to ST52'). If any of the operations does not end normally, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processes as those of steps ST53 to ST55 (ST55' to ST57') are executed. be. Also in this case, it is preferable to re-execute the DL issuing process a predetermined number of times.

Although various embodiments have been described in detail above, the specific description does not limit the present invention. For the sake of convenience, the pinball game machine is described, but the present invention can be suitably applied to other game machines such as a reel game machine.

GM gaming machine DL display list 51 CPU circuit 23 image control means 52 image generation means 77 drawing circuit 77
72 data transfer circuit 63 CPU
60 DMAC circuits ST41 to ST44 setting means ST40 setting preparation means

Claims (1)

An image control means having a CPU circuit for creating a display list specifying a display screen of a display device, a drawing circuit for generating image data based on an instruction command described in the display list, and configuration data of the display list, an image generation means having a data transfer circuit that receives data for each unit size , and a preloader capable of acquiring transfer data from the data transfer circuit ;
The image control means includes a DMAC circuit capable of executing a DMA (Direct Memory Access) operation based on instructions from the CPU of the CPU circuit, a control register in which setting values that define the operation of the DMAC circuit are set, and the CPU. a list buffer for storing the display list to be created,
The image control means is
setting means for setting DMA operation conditions, including the start address of the list buffer and the address of the data transfer circuit to which the display list is to be transferred by DMA, in one or more predetermined control registers with respect to the DMA operation; ,
preparation means for initializing the data transfer circuit prior to the start of the DMA operation,
The data transfer circuit of the image generating means collects the data transferred from the list buffer based on the DMA operation of the DMAC circuit into a predetermined transfer size that is an integer multiple of the unit size, and transfers the data to the drawing circuit. Or a gaming machine that transfers to the preloader.

Images