JP7135941B2 - radiography equipment - Google Patents

Description

The present invention relates to a radiation imaging apparatus.

Radiation imaging equipment (FPD: Flat Panel Detector) is required not only to capture still images, but also to support serial imaging in which radiation irradiation and image data generation are repeated multiple times with a single operation of the exposure switch. there is This is because serial imaging has the advantage of being able to visualize the movements of the lungs and circulatory system while suppressing the exposure dose compared to video imaging.
In addition, radiation imaging apparatuses are required to further reduce exposure dose, improve image quality, and speed up operation. However, as radiation imaging apparatuses have become more sophisticated, the influence of noise generated from circuits has increased. Since noise causes artifacts in radiographic images, its reduction is a problem.

Therefore, in recent years, various techniques for reducing noise have been proposed.
For example, in Patent Document 1, a horizontal shift register for transferring charges accumulated in a CCD, a driving circuit for driving the horizontal shift register, and a drive circuit which is supplied to the driving circuit when the driving circuit is not driven are disclosed. Imaging device having a dummy load circuit that consumes about an amount of power, and capable of suppressing sudden fluctuations in power supply voltage that occur when a horizontal shift register of an imaging device is driven to prevent noise from occurring Have been described.
In addition to these techniques, for example, a method of covering a readout circuit for reading radiographic images with a high magnetic permeability sheet or the like is conceivable.

JP-A-2005-177523

By the way, radiographic image artifacts may also be caused by circuit offsets. Therefore, in order to remove such an offset, recent radiation imaging apparatuses generally perform offset correction by subtracting the dark image read before exposure from the main image read after exposure. .
However, in serial imaging, moving image imaging, and the like, there is a demand for shortening the time from imaging to image display. may differ. Specifically, since it is necessary to perform many corrections such as offset correction and gain correction in parallel with the reading of the main image, the signal processing circuit that performs the correction, for example, as shown in FIG. This may be done more frequently than when reading a dark image.
When the memory access operation is executed, the power supply fluctuates in the apparatus, and the reading circuit generates noise corresponding to the fluctuation. Since there is a difference in the amount of noise generated between the dark image and the main image, the noise may not be completely removed by the offset correction, resulting in artifacts.

However, although the technique described in Patent Document 1 can reduce the power supply noise generated by the drive circuit in the imaging device as described above, it cannot deal with noise caused by differences in memory access operations. Can not.
Further, means for physically blocking noise, such as a high magnetic permeability sheet, has the problem of increasing the manufacturing cost and weight of the radiation imaging apparatus.

An object of the present invention is to provide a radiographic image generated due to the fact that the memory access operation of a signal processing circuit is different between when reading a dark image and when reading a main image, without increasing the manufacturing cost and weight of the radiation imaging apparatus. is to reduce the artifacts of

In order to solve the above problems, a radiographic imaging apparatus according to the present invention includes:
a sensor unit having a plurality of detecting elements arranged two-dimensionally and a plurality of switching elements respectively connected to the respective detecting elements;
a sensor driving unit for switching between a conducting state and a non-conducting state of each switch element of the sensor unit to output electric charge from each detection element;
an image generation unit that generates image data of a radiographic image based on the amount of charge output by each detection element of the sensor unit;
a memory that can store image data;
At least an operation of acquiring dark image data, which is image data of a dark image generated by the image generating unit before exposure, from the image generating unit, reading data from the memory, and writing data to the memory. a first operation comprising: a memory access operation to perform one;
At least one of an operation of acquiring from the image generating unit main image data, which is image data of a main image generated by the image generating unit after exposure, and reading data from the memory and writing data to the memory. a memory access operation for performing a second operation comprising:
When the memory access operation in the first operation and the memory access operation in the second operation do not match, the signal processing circuit performs memory access operation in the first operation and memory access operation in the second operation. At least one of them includes a dummy memory access operation imitating at least one of memory access operations included in the other memory access operation but not included in the one memory access operation. .

According to the present invention, a radiographic image generated due to the fact that the memory access operation of the signal processing circuit is different between when reading a dark image and when reading a main image can be achieved without increasing the manufacturing cost and weight of the radiation imaging apparatus. artifacts can be reduced.

1 is a perspective view of a radiographic apparatus according to a first embodiment of the present invention; FIG. 2 is a block diagram showing an equivalent circuit of the radiation imaging apparatus of FIG. 1; FIG. 2 is a block diagram showing an equivalent circuit for one pixel of a readout circuit provided in the radiation imaging apparatus of FIG. 1; FIG. It is a block diagram showing the functional composition of the signal processing circuit concerning a first embodiment. 4 is a diagram showing the operation of each part of the radiation imaging apparatus and the change over time of the output voltage V _out of the integrating circuit; FIG. It is a block diagram showing the functional composition of the signal processing circuit concerning a second embodiment. It is a figure explaining the problem in the conventional radiography apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of the present invention is not limited to what is described in the following embodiments and drawings.

<First embodiment>
First, a first embodiment of the present invention will be described with reference to FIGS. 1-5.

[Outline configuration]
A schematic configuration of a radiation imaging apparatus (hereinafter referred to as an imaging apparatus 100) according to this embodiment will be described. FIG. 1 is a perspective view of the imaging device 100, and FIG. 2 is a block diagram showing the electrical configuration of the imaging device 100. As shown in FIG.

As shown in FIGS. 1 and 2, the imaging apparatus 100 according to the present embodiment includes a housing 1, a scintillator 2, a sensor section 3, a sensor driving section 4, and an image pickup device 1, which are housed in the housing 1. A generation unit 5 , a control unit 6 , a memory 7 , a communication unit 8 , and a built-in power supply 9 are provided.
Here, a portable imaging apparatus 100 that can be carried around will be described, but the present invention can also be applied to a dedicated radiographic imaging apparatus installed indoors or on an imaging table, for example. is.

The housing 1 is formed in a panel shape as shown in FIG.
Further, the dimensions of the housing 1 are substantially equal to those of conventional medical radiation film cassettes.
A power switch 11, an operation switch 12, an indicator 13, a connector 82 of the communication section 8, and the like are provided on one side surface of the housing 1, as shown in FIG.

The scintillator 2 is a material (e.g., a columnar crystal of cesium iodide (CsI) that emits an electromagnetic wave (e.g., visible light) having a longer wavelength than radiation such as visible light when receiving radiation in an amount corresponding to the dose of the received radiation. ) and formed into a plate shape.
A reflective layer may be provided on the surface of the scintillator 2 corresponding to the sensor section 3 so that more electromagnetic waves are transmitted to the sensor section 3 .

As shown in FIG. 2, the sensor section 3 includes a substrate 31, a plurality of scanning lines 32, a plurality of signal lines 33, a plurality of detecting elements 34, a plurality of switching elements 35, and a plurality of bias lines 36. , and connection 37 .

The substrate 31 is formed in a plate shape and is arranged to face the scintillator 2 in parallel.
The plurality of scanning lines 32 in this embodiment are provided on the surface of the substrate 31 so as to extend parallel to each other at predetermined intervals.
The plurality of signal lines 33 in the present embodiment extend parallel to each other at predetermined intervals, are orthogonal to the scanning lines 32, and are provided so as not to be electrically connected at the intersections with the scanning lines.
That is, the plurality of scanning lines 32 and the plurality of signal lines 33 in this embodiment are provided in a grid pattern.

A plurality of detection elements 34 are arranged two-dimensionally on the surface of the substrate 31 and face the scintillators, respectively.
In the present embodiment, they are arranged in a matrix by being provided in a plurality of regions partitioned in a grid pattern by a plurality of scanning lines 32 and signal lines 33 .
Each detection element 34 is, for example, a photodiode or a phototransistor, and generates an amount of electric charge corresponding to the amount of electromagnetic waves generated by the scintillator 2 (the dose of radiation received).
A drain terminal of a switch element 35 is connected to one terminal 34a of each detection element 34, and a bias line 36 is connected to the other terminal 34b.

Here, the detection element 34 is configured to generate electric charge according to the amount of electromagnetic waves (light) generated by the scintillator 2, but it may be one that directly converts radiation into electric charge.
The scintillator 2 becomes unnecessary when the detection element 34 that converts the radiation directly into electric charge is used.

A plurality of switch elements 35 in this embodiment are provided in a plurality of regions partitioned by a plurality of scanning lines 32 and signal lines 33, similarly to the detection elements 34. As shown in FIG.
The switch element 35 in this embodiment is composed of a TFT (Thin Film Transistor), the gate electrode is connected to the adjacent scanning line 32, the source electrode is connected to the adjacent signal line 33, and the drain electrode is connected to the same region. It is connected to one terminal 34a of the detection element 34 inside.
Each switch element 35 is in a conductive state in which the detection element 34 and the signal line 33 (integration circuit 511) are electrically connected, or in a conductive state in which the detection element 34 and the signal line 33 (integration circuit 511) are electrically connected, depending on the voltage (on voltage/off voltage) applied to the gate electrode. It is possible to switch to a non-conducting state in which the signal line 33 is not conducting.

A plurality of bias lines 36 are connected to the other terminal 34 b of each sensing element 34 .
In this embodiment, the bias lines 36 are connected by the connection 37, but each bias line 36 may be directly connected to the bias power supply circuit 43, or the bias line 36 may be divided into a plurality of connections 37. may be connected. If the connection 37 is used, the current flowing through the bias line 36 concentrates and the voltage drop due to the wiring resistance becomes large.
In order to reduce the influence of wiring resistance, the bias line 36 may be spread out in a planar shape, or may be a parallel cross formed by connecting wirings arranged vertically and horizontally.
If the bias wire 36 is planar or grid-shaped, the wire connection 37 is not required.

The sensor driving section 4 includes a gate power supply circuit 41 , a gate driver 42 and a bias power supply circuit 43 .

The gate power supply circuit 41 generates an ON voltage and an OFF voltage, which are different voltages, and supplies them to the gate driver 42 .

The gate driver 42 is configured to selectively switch the scanning line 32 to which the ON voltage is applied.
An off voltage is applied to the scanning lines 32 to which the on voltage is not applied.

The bias power supply circuit 43 generates a reverse bias voltage and applies the reverse bias voltage to each detection element 34 via the connection 37 and the bias line 36 .

The sensor driving section 4 configured in this manner switches between the conducting state and the non-conducting state of each switch element 35 of the sensor section 3 to output charges from each detection element 34 .

The image generator 5 includes a plurality of readout circuits 51 , an analog multiplexer 52 and an A/D converter 53 .
Although one analog multiplexer 52 and one A/D converter 53 are shown in FIG. , an analog multiplexer 52, and an A/D converter 53, respectively.

A plurality of readout circuits 51 are connected to respective signal lines 33 respectively provided corresponding to respective columns of the detection elements 34 .
Each readout circuit 51 includes an integration circuit 511 and a correlated double sampling circuit (hereinafter referred to as a CDS circuit 512).
Each readout circuit 51 generates an analog signal value based on the amount of charge input from each signal line 33 and outputs it to the analog multiplexer 52 .
Details of the readout circuit 51 will be described later.

Each output terminal of a plurality of readout circuits 51 is connected to the analog multiplexer 52 .
Further, the analog multiplexer 52 selectively switches the readout circuit 51 connected to the A/D converter 53 from among the plurality of readout circuits 51, thereby converting the analog signal value input from each readout circuit 51 into one. They are output to the A/D converter 53 one by one.
Here, the analog multiplexer 52 is assumed to output analog signal values one by one. Multiplexer 52 may be configured to output two or more analog signal values to A/D converter 53 .

The A/D converter 53 sequentially converts input analog signal values into digital signal values.
Although one A/D converter is provided for the plurality of CDS circuits 512 here, the A/D converter 53 may be connected to each CDS circuit 512 .
In that case, the analog multiplexer 52 becomes unnecessary.

The image generating section 5 configured in this manner generates image data of a radiographic image based on the amount of charge output by each detecting element 34 of the sensor section 3 .

The control unit 6 according to this embodiment is configured to have a signal processing circuit 61 such as an FPGA (Field Programmable Gate Array).
The control unit 6 according to this embodiment also includes various control circuits (not shown) that control the sensor drive unit 4 and the image generation unit 5 .
The control unit 6 may be composed of a CPLD (Complex Programmable Logic Device), or may be composed of a microcomputer equipped with a CPU (Central Processing Unit), RAM (Random Access Memory), and ROM (Read Only Memory). You may make it

The memory 7 according to the present embodiment is a volatile memory (for example, a DRAM (Dynamic Random Access Memory)) that can store image data.
Note that the memory 7 may be composed of a non-volatile memory (for example, a flash memory or the like).

The communication unit 8 is composed of, for example, a communication module, and is capable of wireless or wired communication with other devices (console or radiation generator) via an antenna 81 and a connector 82 .

The built-in power supply 9 is composed of a lithium ion battery, a lithium ion capacitor, or the like, and supplies electric power to each part of the photographing apparatus 100 .

[Image generator]
Next, the details of the readout circuit 51 included in the image generation section 5 of the photographing apparatus 100 will be described. FIG. 3 is a circuit diagram showing a specific configuration of the readout circuit 51. As shown in FIG.

The readout circuits 51 each include an integration circuit 511 and a CDS circuit 512, as shown in FIG. 3, for example.

The integration circuit 511 includes an operational amplifier 511a, a capacitor 511b, and a reset switch 511c.
The operational amplifier 511a has an inverting input terminal connected to the signal line 33 and a non-inverting input terminal to which the reference voltage _V0 is applied. Therefore, the voltage applied to the signal line 33 is also the reference voltage _V0 .
When charges flow in from the signal line 33, an output voltage _Vout corresponding to the amount of charges is output.
Note that the GND potential may be applied as the reference voltage _V0 .

The capacitor 511b and the reset switch 511c are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 511a.
By being configured in this way, the integrating circuit 511 can time-integrate the amount of charge that has flowed in and output a voltage to the CDS circuit 512 .
Also, when the reset switch 511c is turned on, the electric charge accumulated in the capacitor 511b is released to reset the voltage.

The CDS circuit 512 includes a resistor 512a, a first sample and hold (CDS1) circuit 512b, a second sample and hold (CDS2) circuit 512c, and a difference circuit 512d.

The resistor 512a is connected in series with the output terminal of the operational amplifier 511a of the integrating circuit 511. FIG.

The first sample and hold circuit 512b includes a first capacitor Cr and a first switch Sr.
One electrode of the first capacitor Cr is connected between the resistor 512a and the inverting input terminal of the differential circuit 512d, and the other electrode is connected to GND.
A first switch Sr is provided between the resistor 512a and the first capacitor Cr.
Then, when the first switch Sr is turned on, the integration circuit 511 and the first capacitor Cr are connected, and the first capacitor Cr is charged.
After that, when the first switch Sr is turned off, the connection between the integration circuit 511 and the first capacitor Cr is released, and the voltage between the electrodes of the first capacitor Cr at that time (hereinafter referred to as the first voltage V _SHR ).

The second sample and hold circuit 512c has a second capacitor Cs and a second switch Ss.
The second capacitor Cs has one electrode connected between the resistor 512a and the non-inverting input terminal of the differential circuit 512d, and the other electrode connected to GND.
A second switch Ss is provided between the resistor 512a and the second capacitor Cs.
When the second switch Ss is turned on, the integration circuit 511 and the second capacitor Cs are connected, and the second capacitor Cs is charged.
After that, when the second switch Ss is turned off, the connection between the integration circuit 511 and the second capacitor Cs is released, and the voltage between the electrodes of the second capacitor Cs at that time (hereinafter referred to as the second voltage V _SHS ).

The differential circuit 512d has an inverting input terminal connected to the first sample-and-hold circuit 512b, and a non-inverting input terminal connected to the second sample-and-hold circuit 512c.
Then, the difference circuit 512d outputs the difference obtained by subtracting the first voltage V _SHR held by the first sample and hold circuit 512b from the second voltage V _SHS as the signal value held by the second sample and hold circuit 512c. It is designed to
This difference is output to the analog multiplexer 52 as the analog signal value ΔV described above.

[Signal processing circuit]
Next, the details of the signal processing circuit 61 included in the control unit 6 of the photographing apparatus 100 will be described. FIG. 4 is a block diagram showing the functional configuration of the signal processing circuit 61. As shown in FIG.

The signal processing circuit 61 is adapted to perform a first operation and a second operation.
This "first operation" is an operation as shown in FIG. It contains action A1.
Also, the “first operation” includes a memory access operation of at least one of reading data from the memory 7 and writing data to the memory 7 .
The first operation in this embodiment includes a memory access operation A2 for writing dark image data into the memory 7. FIG.

Further, the "second operation" is an operation as shown in FIG. It includes action B1.
Also, the “second operation” includes a memory access operation of at least one of reading data from the memory 7 and writing data to the memory 7 .
The second operation in this embodiment includes a memory access operation B2 for reading dark image data from the memory 7, an offset correction operation B3 for generating offset image data that is the difference between the dark image data and the main image data, and a A compression operation B4 for compressing the offset image data and a memory access operation B5 for writing the compressed offset image data to memory 7 are included.
Note that if the amount of offset image data is small, the compression operation B4 is unnecessary.

In this embodiment, the first operation is performed before the main image is captured, and then the main image including the second operation is captured. is not strictly required, the first operation may be performed after the main image including the second operation is captured.
In this case, many of the various corrections (described later in detail) applied to the main image data are performed in parallel with the first operation.

Further, the signal processing circuit 61 according to the present embodiment is included in (one) memory access operation in the first operation, in (the other) memory access operation in the second operation, and (one) in the first operation. A dummy memory access operation imitating a memory access operation not included in the memory access operation is included, and the (other) memory access operation in the second operation is included in the (one) memory access operation in the first operation. In addition, a dummy memory access operation imitating a memory access operation not included in the (other) memory access operation in the second operation is included.

This "dummy memory access operation" includes a dummy memory access operation of writing dummy image data, which is image data of a dummy image simulating a dark image or a main image, into the memory 7, and a dummy memory access operation of reading dummy image data from the memory 7. Behavior and includes.

In this embodiment, the first operation includes a dummy memory access operation DA3 for reading dummy image data, a dummy offset correction operation DA4 for generating dummy offset image data that is the difference between dark image data and dummy image data, and generating A dummy compression operation DA5 for compressing the compressed dummy offset image data and a dummy memory access operation DA6 for writing the compressed dummy offset image data to the memory 7 are included.
That is, the dummy memory access operation in the first operation imitates the memory access operation accompanying the offset correction operation in the second operation.

Further, in this embodiment, the second operation includes a dummy memory access operation DB6 for writing dummy image data into the memory 7. FIG.
Note that the second operation includes a plurality of memory access operations for respectively reading a plurality of correction data used for correcting the main image data (for example, gain correction, afterimage correction, defect correction, binning, etc.) from the memory 7, and A main image correction operation of performing a plurality of corrections on main image data using a plurality of correction data to generate corrected main image data may also be included.
These correction processes can be performed by relatively simple calculations, and the processing capacity of the signal processing circuit 61 is sufficient. time can be shortened.

By doing so, the memory access operation in the first operation and the memory access operation in the second operation in this embodiment will match.

It should be noted that the memory access operation in the first operation and the memory access operation in the second operation need not be completely matched, and at least one memory access operation may be brought closer to the other.
That is, the operation including the first dummy access operation may be either the first operation or the second operation.
Also, the dummy access operation may be either one of the operation of writing dummy image data in the memory 7 and the operation of reading it out.

In addition, the signal processing circuit 61 performs the mode of the memory access operation in the first operation and the mode of the memory access operation in the second operation, which are executed at timings overlapping the first sample-and-hold operation and the second sample-and-hold operation by the image generation unit 5. The dummy memory access operation is executed so that the mode and the are equal.
This "pattern" refers to the frequency (density) of memory access operations that are repeated in small steps, the length of the period in which the memory access operations are repeated, and the like.

〔motion〕
Next, the operation of the photographing device 100 will be described. FIG. 5 is a diagram showing the operation of each part of the photographing apparatus 100 and the temporal change of the output voltage V _out of the integration circuit 511 .
In the graph of the output voltage V _out in FIG. 5, the solid line indicates the case where no charge is accumulated in the detection element 34, and the dashed line indicates the case where charge is accumulated.

The control section 6 of the imaging device 100 operates each section of the imaging device 100 as follows.
When the power switch 11 is operated (turned ON), the control unit 6 first causes each readout circuit 51 to apply the reference voltage _V0 to each signal line 33, and causes the bias power supply circuit 43 to apply the connection 37 and the bias voltage. A reverse bias voltage is applied to each sensing element 34 via line 36 .

After that, the control unit 6 generates dark image data.
Specifically, first, the sensor driving section 4 is caused to apply an OFF voltage to all the scanning lines 32 to bring all the switch elements 35 into a non-conducting state. Then, the dark charge generated by each detection element is accumulated in each pixel.

Thereafter, as shown in FIG. 5, the control section 6 causes the reset switch 511c of each integrating circuit 511 to be turned on to reset the integrating circuit 511 (t1 to t2).
After each integration circuit 511 finishes resetting the voltage, the control unit 6 causes the image generation unit to perform the first sample-and-hold operation. That is, each first sample-and-hold circuit 512b samples the output voltage _Vout of each integration circuit 511 after the switch element 35 is turned off for a predetermined time. Specifically, the first switch Sr is turned on to charge the first capacitor Cr (t3 to t4).
In this embodiment, the plurality of integration circuits 511 output voltages to the first sample-and-hold circuits 512b, respectively. This will cause the _SHR to be held at the same time.
Then, the first voltage _VSHR after charging for a predetermined time is held (sampled and held) as a reference signal value (t4).

After that, the control section 6 causes the sensor driving section 4 to apply an on-voltage to one scanning line 32 to bring each switch element 35 connected to the scanning line 32 into a conductive state. Then, due to the voltage difference between the reference voltage _V0 applied to the signal line 33 and the reverse bias voltage applied to the bias line 36, each pixel connected to the scanning line 32 to which the ON voltage is applied The accumulated dark charge becomes a dark current and is emitted to each signal line 33 . Thus, the dark charge of one gate line is reset. Also, the output voltage V _out of the integration circuit rises or falls under the influence of the through current at the timing of switching the voltage applied to the scanning line 32 . After applying the ON voltage to the scanning line 32, _Vout drops (after t5). On the other hand, after the off-voltage is applied to the scanning line 32, _Vout rises (after t6). Since these falling and rising voltages are the same, the output voltage V _out of the integrating circuit when there is no charge stored in the sensor converges to the same reference voltage.

When the dark current is emitted to each signal line 33 , the integrating circuit 511 of each readout circuit 51 time-integrates the dark current flowing from the signal line 33 and outputs the obtained output voltage V _out to the CDS circuit 512 .
After that, the control section 6 causes the image generation section to perform the second sample hold operation. That is, each second sample-and-hold circuit 512c samples the output voltage V _out of each integration circuit 511 after the switch element 35 is turned on for a predetermined time. Specifically, the second switch Ss is turned on to charge the second capacitor Cs (t7 to t8).
In this embodiment, since the plurality of integration circuits 511 output voltages to the second sample-and-hold circuits 512c respectively, the control unit 6 supplies the plurality of second sample-and-hold circuits 512c with sampling and the second voltage V This will cause the _SHS to be held at the same time.
Then, the second voltage V _SHS after charging for a predetermined time is held (sampled and held) as a reference signal value (t8).

When the second voltage V _SHS is held in each second sample and hold circuit 512 c , each difference circuit 512 d outputs the analog signal value ΔV, which is the difference between the second voltage V _SHS and the first voltage V _SHR , to the analog multiplexer 52 . Output to
The analog multiplexer 52 sequentially outputs the input analog signal values ΔV to the A/D converter 53 .
Then, the A/D converter 53 sequentially converts the input analog signal value ΔV into a digital signal value.
By repeating the operation from the application of the ON voltage to one scanning line 32 to this while changing the target scanning line, one sheet of dark image data is generated.

After reading out the dark image data, the control unit 6 generates main image data.
The operation of the control unit 6 when generating the main image data is basically the same as when generating the dark image data. Therefore, the output voltage V _out after the switching element 35 is turned on changes at a higher value than when dark image data is generated (as shown by the dashed line in the graph).
It should be noted that when capturing a dynamic image, the generation of the main image data is repeated.

In addition, the signal processing circuit 61 executes various memory access operations in parallel with the generation of the dark image data and the main image data by the image generation section 5 .
Specifically, the dark image data is written to the memory 7, the dark image data is read from the memory 7, and the offset image data is written to the memory 7.
In this way, the offset image data subjected to offset correction can be transferred to another device (such as a console).

When the first and second sample-and-hold operations coincide with the execution timing of the memory access operation, the reference signal value (first voltage V _SHR ) and pixel signal value (second voltage V _SHS ) held in the CDS circuit 512 are fluctuate under influence.
Also, when the repetition cycle of various operations is short, such as when capturing a dynamic image, the execution timing of the first and second sample hold operations and the execution timing of the memory access operation often overlap.
However, as described above, the signal processing circuit 61 of the imaging device 100 according to the present embodiment performs at least one of the memory access operation in the first operation and the memory access operation in the second operation, and the other memory access operation. is included in the one memory access operation but not included in the one memory access operation. The difference between when data is generated and when main image data is generated is reduced or eliminated. Therefore, the offset can be removed more accurately.
In addition, since the imaging apparatus 100 according to the present embodiment suppresses noise caused by differences in memory access operations by the operation (software) of the signal processing circuit 61, the noise is physically cut off like a high magnetic permeability sheet. No need for tools.
As a result, without increasing the manufacturing cost and weight of the imaging apparatus 100, artifacts in radiographic images caused by different memory access operations of the signal processing circuit when reading a dark image and when reading a main image can be eliminated. can be reduced.

<Second embodiment>
Next, a second embodiment of the invention will be described with reference to FIGS. In addition, here, the same code|symbol is attached|subjected about the structure similar to said 1st embodiment, and the description is abbreviate|omitted.

A radiation imaging apparatus 100A (see FIGS. 1 and 2) according to the present embodiment differs from that of the first embodiment in the processing executed by the control unit 6A (see FIG. 2).

Specifically, the control unit 6 according to the present embodiment causes the image generation unit 5 to repeatedly generate dark images.

In the first operation executed by the signal processing circuit 61A according to the present embodiment, dark image data is corrected using correction data in addition to the operations A1 and A2 and the dummy operations DA4 to DA6. and a memory access operation A8 for writing the generated corrected dark image data into the memory 7.
Further, as shown in FIG. 6, the dark image correction operation A7 in this embodiment is an averaging process for generating average image data, which is an average of a plurality of dark image data. Therefore, the correction data in this embodiment is past dark image data or past average image data held by the signal processing circuit 61A.
The correction data may be read out from the memory 7 and the dark image correction operation may be executed.

Further, in the present embodiment, when performing the averaging process, dark image integrated data is generated by integrating dark image data. Therefore, in the present embodiment, the first operation also includes a memory access operation A9 for writing the dark image integrated data into the memory 7. FIG.

Also, in this embodiment, the dummy memory access operation DA3 (the operation of reading dummy image data from the memory 7) is omitted from the first operation.
This is because the operation of reading data from the memory 7 has less influence on the operation of the CDS circuit 512 than the operation of writing data to the memory 7 .
Note that the dummy memory access operation DA3 may be included in the first operation in this embodiment.

Further, the second operation executed by the signal processing circuit 61A according to the present embodiment includes, in addition to the operations B1 to B5 and the dummy operation of DB6, a dummy dark image correction operation ( averaging process) DB7; and dummy memory access operations DB8 and DB9 for writing the generated dummy corrected dark image data (past dummy dark image data or past dummy average image data and dummy dark image integrated data) into the memory 7; , is included.
In the present embodiment, all memory access operations for writing to the memory 7 are aligned, but only a portion of them (for example, the most influential memory access operations) may be aligned.

By doing so, also in this embodiment, the memory access operation in the first operation and the memory access operation in the second operation match.

As described above, according to the radiation imaging apparatus 100A according to the present embodiment, as in the imaging apparatus 100 according to the first embodiment, the memory access operation of the signal processing circuit can be performed without increasing the manufacturing cost and weight of the radiation imaging apparatus. It is possible to reduce the artifacts of the radiographic image caused by the difference between the reading of the dark image and the reading of the main image.
Moreover, power consumption can be suppressed by not performing a dummy memory access operation (read operation from the memory 7), which has a small effect, as in the present embodiment.

It goes without saying that the present invention is not limited to the above-described embodiments and the like, and can be modified as appropriate without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 100,100A Radiation imaging apparatus 1 housing 11 power switch 12 operation switch 13 indicator 2 scintillator 3 sensor part 31 substrate 32 scanning line 33 signal line 34 detection element 34a, 34b terminal 35 switch element 36 bias line 37 connection 4 sensor driving part 41 Gate power supply circuit 42 Gate driver 43 Bias power supply circuit 5 Image generation unit 51 Readout circuit 511 Integration circuit 511a Operational amplifier 511b Capacitor 511c Reset switch 512 Correlated double sampling circuit 512a Resistor 512b First sample hold circuit
Cr First condenser
Sr first switch 512c second sample and hold circuit
Cs second capacitor
Ss Second switch 512d Difference circuit 52 Analog multiplexer 53 A/D converter 6, 6A Control section 61, 61A Signal processing circuit 7 Memory 8 Communication section 81 Antenna 82 Connector 9 Built-in power supply A1 Acquisition operation A2, A8, A9 Memory access Operation A7 Dark image correction operation B1 Acquisition operation B2, B5 Memory access operation B3 Offset correction operation B4 Compression operation DA3, DA6 Dummy memory access operation DA4 Dummy offset correction operation DA5 Dummy compression operation DB6, DB8, DB9 Dummy memory access operation DB7 Dummy dark Image correction operation (averaging process)

Claims (7)

a sensor unit having a plurality of detecting elements arranged two-dimensionally and a plurality of switching elements respectively connected to the respective detecting elements;
a sensor driving unit for switching between a conducting state and a non-conducting state of each switch element of the sensor unit to output electric charge from each detection element;
an image generation unit that generates image data of a radiographic image based on the amount of charge output by each detection element of the sensor unit;
a memory that can store image data;
At least an operation of acquiring dark image data, which is image data of a dark image generated by the image generating unit before exposure, from the image generating unit, reading data from the memory, and writing data to the memory. a first operation comprising: a memory access operation to perform one;
At least one of an operation of acquiring from the image generating unit main image data, which is image data of a main image generated by the image generating unit after exposure, and reading data from the memory and writing data to the memory. a memory access operation for performing a second operation comprising:
When the memory access operation in the first operation and the memory access operation in the second operation do not match, the signal processing circuit performs memory access operation in the first operation and memory access operation in the second operation. At least one of them includes a dummy memory access operation imitating at least one of memory access operations included in the other memory access operation but not included in the one memory access operation. Radiography equipment. In the image generation unit,
a first sample-and-hold operation of holding a reference signal value after the switch element becomes non-conductive;
a second sample-and-hold operation for holding the pixel signal value after the switch element is turned on,
The signal processing circuit is
A mode of the memory access operation in the first operation and a mode of the memory access operation in the second operation, which are executed at timings overlapping the first sample-and-hold operation and the second sample-and-hold operation by the image generation unit. 2. The radiation imaging apparatus according to claim 1, wherein said dummy memory access operation is executed so that , and are equal to each other. the first operation includes a memory access operation for writing the dark image data to the memory;
The second action includes:
a memory access operation for reading the dark image data from the memory;
an offset correction operation for generating offset image data that is a difference between the dark image data and the main image data;
a memory access operation to write the generated offset image data to memory;
3. The radiography according to claim 1, wherein the dummy memory access operation in the first operation imitates the memory access operation accompanying the offset correction operation in the second operation. Device. The dummy memory access operation is a dummy memory access operation of writing dummy image data, which is image data of a dummy image simulating the dark image or the main image, into the memory , or a dummy memory access operation of reading the dummy image data from the memory. 4. The radiation imaging apparatus according to claim 1, wherein the operation is a memory access operation. The second action includes:
a plurality of memory access operations for respectively reading a plurality of correction data used for correcting the main image data from the memory;
and a main image correction operation of applying a plurality of corrections to the main image data using the plurality of read correction data to generate corrected main image data. 5. The radiographic apparatus according to any one of 4. The first operation includes:
a dark image correcting operation for correcting the dark image data using the correction data to generate corrected dark image data;
6. The radiation imaging apparatus according to any one of claims 1 to 5, further comprising: a memory access operation for writing the generated corrected dark image data into a memory. 7. The radiation imaging apparatus according to claim 6, wherein the dark image correction operation is an averaging process for generating average image data that is an average of a plurality of dark image data.

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