JP7132723B2 - Transmitting device, receiving device, LDPC encoder and LDPC decoder - Google Patents

Description

The present invention relates to the technical fields of satellite broadcasting, terrestrial broadcasting, fixed communication and mobile communication, and more particularly to a digital data transmitter, receiver, LDPC encoder and LDPC decoder.

As a technique for improving transmission performance under white noise, a coded modulation technique has been proposed in digital modulation that enables improved transmission performance by appropriately combining the strength of the error correction code and the bits of the modulation mapping. (For example, see Non-Patent Document 1).

The coding modulation technique described in this non-patent document 1 etc. is also adopted in the Japanese satellite digital broadcasting standard ISDB-S (see, for example, non-patent document 2), and has been proven as a technique that contributes to the improvement of transmission performance. There is

The basic principle of the technique described in Non-Patent Document 1 is to consider the Euclidean distance between signal points after mapping bits to symbols, and , strong error correction is applied to bits in which 1/0 is inverted between signal points with short Euclidean distances, and weak error correction is performed on bits in which 1/0 is inverted between signal points with long Euclidean distances. By performing error correction or not performing coding processing, noise tolerance is improved while maintaining overall information efficiency.

Also, Non-Patent Document 1 proposes a method of assigning symbols to signal points called a set partitioning method using 8PSK (phase-shift keying) as an example. In the set partitioning method, a plurality of code sequences that can be divided for each bit are used as an input symbol sequence, and the symbol-constituting bits of the input symbol sequence are divided so that the minimum Euclidean distance between signal points is uniformly expanded, This is a transmission method that allocates symbols to signal points used for modulation. As an example, a method of allocating symbols to 8PSK signal points by the set partitioning method will be described with reference to FIG.

In FIG. 26, 3-bit symbols (000, 001, . . . , 111) assigned to each signal point of 8PSK are already described. is obtained as a result of symbol assignment to , and has not yet been determined at the time of set partitioning.

In the first division, the eight signal points are divided into two signal point groups of four signal points so that the Euclidean distance (minimum Euclidean distance) between adjacent signal points is maximized. Here, for one of the two signal point groups, a1=0 is assigned to the first bit (most significant bit) of the symbol configuration bits, and a1=1 is assigned to the other.

Next, the two signal point groups composed of four signal points obtained in the first division are divided into four signal point groups each composed of two signal points so that the minimum Euclidean distance is maximized. . Here, when a signal point group composed of four signal points is divided into two signal point groups, a2=0 is assigned to the second bit of the symbol configuration bits to one signal point group, and a2=0 is assigned to the other. assigns a2=1.

Furthermore, although omitted in FIG. 26, the four signal point groups composed of two signal points obtained in the second division are divided into eight signal point groups each composed of one signal point. Here, when dividing a signal point group composed of two signal points into one signal point, one of the signal point groups has a3=0 in the third bit (least significant bit) of the symbol configuration bits. assign a3=1 to the other.

As a result of the above three stages of set partitioning, each of the eight signal points is assigned a unique 3-bit symbol.

By assigning symbols to such signal points, in the case of 8PSK, the first bit (corresponding to a1 in FIG. 26) is the minimum Euclidean distance in 8PSK, and the second bit (corresponding to a2 in FIG. 26) is QPSK. (Quadrature Phase Shift Keying) minimum Euclidean distance, the third bit (equivalent to a3 in FIG. 26) can be decoded under the condition of BPSK (Binary Phase-Shift Keying) minimum Euclidean distance. becomes.

27 and 28 show examples of symbol allocation methods when the set partitioning method is applied to 16QAM (Quadrature Amplitude Modulation) and 32QAM. As in the case of 8PSK, it can be confirmed that the minimum Euclidean distance is increased by advancing the division. 27 and 28 show examples of division up to the first bit (a1: most significant bit) and the second bit (a2). It can be split to expand.

According to such a set division method transmission system, the transmission and reception share the assignment of symbols to the signal points obtained by the set division method in advance, and the transmitting side controls the data to be transmitted by each bit constituting the symbol. , encodes and modulates with an error correcting code with correction capability suitable for the minimum Euclidean distance between corresponding signal points, and after demodulation, the receiving side performs decoding corresponding to the encoding on the transmitting side, resulting in high noise immunity. A transmission system can be realized.

On the other hand, when the set partitioning method is applied to multilevel modulation, the minimum Euclidean distance increases for each divided bit, and the error correction capability differs for each bit, so the transmission performance is improved at a predetermined coding rate. requires optimization of the error correction code according to the error correction capability of each bit.

By the way, DVB-S2 (see non-patent document 3), DVB-S2X (see non-patent document 4), which is a European satellite digital broadcasting system, and advanced wideband satellite digital broadcasting transmission system described in ARIB STD-B44 (hereinafter referred to as In the advanced satellite broadcasting system (see, for example, Non-Patent Document 5), the Gray code is adopted as a technique for allocating symbols to signal points.

The Gray code has uniform bit-by-bit correction capability in BPSK and QPSK, but in multilevel modulation of 8PSK or more, the error correction capability between bits included in a symbol is uneven. This is an obstacle to improving the transmission performance at the coding rate.

For this reason, in order to improve the above-mentioned problem of the Gray code, a technique for further improving the transmission system by the set partitioning method and improving the transmission performance when the correction ability of each bit is different has been disclosed (for example, patent Reference 1).

In addition, a new signal point arrangement for 64APSK coded modulation in a transmission system using the Gray code or the set partitioning method has been proposed. and performance improvement of error correcting codes based on bit allocation (see Non-Patent Documents 6 to 9, for example).

More specifically, representatively, in the technique of Non-Patent Document 9, as a new signal point arrangement for 64APSK, the number of signal points arranged on four concentric circles is optimized from the viewpoint of expanding the Euclidean distance. The amplitude value of each signal point is approximately matched with one of the concentric circles, and the phase value of each signal point is adjusted.

Then, in the technique of Non-Patent Document 9, as bit allocation by the set partitioning method using the new 64APSK signal point arrangement, a predetermined signal power to noise power ratio is obtained from bit allocation optimized based on a predetermined calculation method. It is assumed that bits are exchanged so as to satisfy

Furthermore, in the technique of Non-Patent Document 9, based on the new signal point arrangement of the 64APSK and the bit allocation by the new set partitioning method, the slot configuration of 6 slots as the concatenated code by the LDPC code and the BCH code as the error correction code , the average coding rate of the entire LDPC code satisfies 4/5, the LDPC coding rate of each slot in the six slots is defined, and the parity check matrix initial value table of the LDPC code in the set partitioning method is It is optimized.

JP 2014-155195 A

G. Ungerboeck, "Channel coding with multilevel/phase signals", IEEE Transaction Information Theory, Vol.IT-28, No.1, January 1982, pp.55-67 "Transmission method standard for satellite digital broadcasting ARIB STD-B20 Version 3.0", revised on May 31, 2001, ARIB Digital Video Broadcasting (DVB), ``Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)'', Final draft ETSI EN 302 307 V1.2.1(2009- 04) Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; Part2: DVB-S2 Extensions(DVB-S2X)”, Draft ETSI EN 302 307 -2 V1.1.1(2014-10) "Advanced Wideband Digital Satellite Broadcast Transmission System Standard ARIB STD-B44 Version 2.1", revised on March 25, 2016, ARIB Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Kyoichi Saito, Shoji Tanaka, "Study on 64APSK coded modulation (Part 1) -Study on 64APSK signal point arrangement-", The Institute of Electronics, Information and Communication Engineers, 2016 Society Conference Proceedings, B-5-21, 2016, p291, announced on September 20, 2016 Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Kyoichi Saito, Shoji Tanaka, “Study on 64APSK Coded Modulation -Study on Bit Allocation of 64APSK Coded Modulation-”, The Institute of Image Information and Television Engineers, Annual Conference Proceedings, 32C- 1, 2016, announced on September 2, 2016 Yoichi Suzuki, Yuki Koizumi, Masaaki Kojima, Kyoichi Saito, Shoji Tanaka, “Study of 64APSK coded modulation (Part 2) - Performance improvement by LDPC coding rate optimization -”, Institute of Electronics, Information and Communication Engineers, 2016 Society Conference Lecture Proceedings, B-5-22, 2016, p292, announced on September 20, 2016 Yuki Koizumi, Yoichi Suzuki, Masaaki Kojima, Kyoichi Saito, Shoji Tanaka, “A study on 64APSK Coded Modulation”, [online], IEICE Tech. Rep., vol. 116, no. 243, SAT2016- 55, pp. 51-56, October 6, 2016, [searched on August 1, 2017], Internet <URL: http://www.ieice.org/ken/paper/20161013cblh/eng/>

As described above, in the set partitioning method, since the correction capability differs for each bit, in order to improve the transmission performance at a predetermined coding rate, it is necessary to optimize the error correction code according to the error correction capability for each bit. Is required.

For this reason, Patent Document 1 discloses a technique for improving transmission performance when the correction capability of each bit differs depending on the transmission method based on the set partitioning method, but only for 8PSK, a specific example thereof is disclosed. . On the other hand, what values should be adopted for the LDPC (Low Density Parity Check) coding rate in 64APSK (Amplitude and Phase Shift Keying) and the parity check matrix of the LDPC code to improve the frequency utilization efficiency and improve the transmission performance? has not been disclosed. Therefore, when adopting a transmission method based on the set partitioning method, there is a possibility that a broadcaster may use an LDPC coding rate (or a parity check matrix of an LDPC code) that does not improve transmission performance in some cases.

Therefore, a plurality of code sequences that can be divided for each bit are used as an input symbol sequence, and the symbol-constituting bits of the input symbol sequence are divided so that the minimum Euclidean distance between signal points is uniformly increased. In the system, a specific LDPC coding rate in 64APSK and a specific numerical value for a parity check matrix of the LDPC code have been desired.

Furthermore, it is necessary to improve the information bit rate in order to meet the needs for higher image quality for ultra-high-definition video such as 4K and 8K. It is necessary to reduce the number of bits and raise the average coding rate, and at the same time, raise the C/N ratio so that the error-correcting code satisfies pseudo-errors. Normally, a bit error rate of 1.0×10 ⁻¹¹ is often used as a pseudo-error-free evaluation point for a required C/N.

FIG. 29 shows an example of bit allocation to symbols applied to coding rates 7/9, 4/5, and 5/6 in the DVB-S2X standard (see Non-Patent Document 4), which is a conventional technique for 64APSK. The 6 bits are assigned in order from left to right: 1st bit (a1), 2nd bit (a2), . . . , 6th bit (a6). 100). DVB-S2X employs Gray code as a bit allocation technique for symbols. In multi-level modulation of 8PSK or more, the Gray code is an obstacle to improving transmission performance at a predetermined coding rate because the error correction capability between bits included in a symbol is uneven.

In particular, in the future, as the resolution of images to be transmitted increases, digital data will be transmitted using 64APSK while satisfying the available bandwidth of 34.5MHz for each satellite transponder in 12GHz band satellite broadcasting, for example. There is a demand for a transmission system with a transmission bit rate of 150 Mbps or higher, and a technique that improves performance over 64APSK of DVB-S2X is desired. desired.

On the other hand, Non-Patent Documents 6 to 9 disclose performance improvement of error correcting code based on new signal point arrangement and bit allocation as a technique to improve the problem of the Gray code. There is room for further improvement in the performance of non-linear transmission paths through repeaters. Non-Patent Documents 6-9 are techniques for improving the required C/N of 64APSK coded modulation under white noise. On the other hand, in satellite transmission, nonlinear distortion caused by a satellite transponder is a factor that degrades the required C/N ratio. Also, it is effective to perform adaptive equalization processing based on the minimum square error criterion in the receiving apparatus for the signal subjected to nonlinear distortion.

For example, typical equipment for nonlinear transmission paths in 12 GHz band satellite broadcasting includes an input filter (IMUX filter), a power amplifier (TWTA), and an output filter ( OMUX filter).

The IMUX filter is a band-pass filter corresponding to each channel frequency, extracts only one-channel band component from the modulated wave signals of a plurality of channels received from the terrestrial broadcasting station, and outputs it to each TWTA. In the terrestrial broadcasting station, the modulated wave signal from the transmitting device is power-amplified by a high power amplifier (HPA) and uplinked to the satellite transponder.

The TWTA amplifies the power of the extracted modulated wave signal for one channel and outputs it to the OMUX filter.

The OMUX filter is a band-pass filter corresponding to each channel frequency, extracts only the band component for one channel from the modulated wave signal power-amplified by the TWTA, suppresses unnecessary frequency components, and outputs the modulated wave signal as a broadcast wave. It is generated as a signal and output to the receiver on the ground.

Originally, it is desirable for the TWTA to perform power amplification processing with input/output characteristics in which the amplitude and phase relationships between the input signal and the output signal are proportional. However, this input/output characteristic actually has nonlinearity (AM-AM characteristic) in which the gain of the output signal decreases as the gain of the input signal increases. (AM-PM characteristics). Therefore, if the gain of the input signal is within a certain level, the gain of the output signal also becomes a substantially linear output level. . An operating point immediately before such a decrease in output level is generally called an output saturation point. In addition, the case where the input level is lowered from this output saturation point is called input back off (IBO). ). Especially in the case of APSK, since there are signal points with multiple amplitudes in the amplitude/phase signal point arrangement, the required C/N is more likely to deteriorate due to the nonlinearity of TWTA compared to PSK modulation.

In addition, from the viewpoint of extracting band components and generating waveforms, IMUX filters and OMUX filters have amplitude differences (frequency-amplitude characteristics) and group delay differences (frequency-group delay characteristics) at frequencies within the modulated wave band. . These differences are non-uniform in in-band frequencies, resulting in different delays depending on symbol transitions when viewed on the time axis. As a result, inter-symbol interference (ISI) is caused and signal points are spread out, resulting in deterioration of the required C/N ratio.

In order to compensate for the nonlinear distortion that occurs in this nonlinear transmission line, adaptive equalization processing is performed on the received signal. Adaptive equalization calculates the ideal signal point arrangement determined by a known modulation method and the error vector of the received signal subjected to nonlinear distortion, and updates the filter coefficients of the adaptive equalizer using the LMS (Least Mean Square) method. , performs nonlinear distortion compensation.

However, when performing adaptive equalization processing on 64APSK coded modulation subjected to nonlinear distortion, the equalization performance differs according to the amplitude of the signal point. Therefore, in a satellite transmission system that adaptively equalizes a received signal affected by nonlinear distortion, the 64APSK coded modulation of Non-Patent Documents 6 to 9 designed under white noise is the optimum transmission system for the satellite transmission system. is not.

Therefore, in a transmission device that transmits digital data via a nonlinear transmission path, optimization of signal point arrangement and bit allocation related to mapping at the time of modulation, and corresponding coding rate for each bit constituting a symbol (particularly, It is also necessary to optimize the coding rate of the LDPC code and the parity check matrix related to error correction by the LDPC code. Similarly, a receiving device that receives digital data via a nonlinear transmission path demodulates according to the signal point arrangement and bit allocation related to the optimized mapping, performs adaptive equalization processing, and converts the optimized symbols into It is necessary to perform likelihood determination and decoding using the optimized parity check matrix according to the coding rate for each bit constituting bits (in particular, the coding rate of the LDPC code).

SUMMARY OF THE INVENTION Therefore, in view of the above problems, an object of the present invention is to reduce the influence of nonlinear distortion in a nonlinear transmission line and improve the required C/N when transmitting digital data using 64APSK through a nonlinear transmission line. Another object of the present invention is to provide a transmitting device, a receiving device, an LDPC encoder, and an LDPC decoder, which preferably enable a transmission bit rate of 150 Mbps or more.

In the transmitter and receiver according to the present invention, the overall coding rate of the LDPC code is set to 4/5 (=96/120) in order to achieve a transmission bit rate of 150 Mbps or higher when transmitting digital data using 64APSK. , for symbols after encoding by the LDPC code, a 64APSK signal point arrangement considering nonlinear distortion in a nonlinear transmission line and adaptive equalization performance on the receiving side, and an IQ signal ( a complex signal consisting of an in-phase component I and a quadrature-phase component Q). Further, in the transmitting apparatus and the receiving apparatus according to the present invention, the LDPC code parameters related to the parity check matrix of the LDPC coding rate for each bit are also optimized. In addition, in the present invention, the LDPC code parameters for each bit having steep error correction capability are optimized at C/N=16 dB.

In particular, in the transmission device and the reception device according to the present invention, the mapping method by the set partitioning method that can improve the above problems of the mapping method of the Gray code (also referred to as "Gray coding" in this specification) is multi-valued modulation. , the minimum Euclidean distance increases as signal point division progresses, enabling error correction with less parity. In the case of 64APSK, error correction of the first bit (a1) is performed by LDPC decoding using LDPC code for a1 using 64 signal points. The error correction of the second bit (a2) is performed in the same manner using 32 signal points divided by the decoding result of a1 and the LDPC code for a2. After that, for the third bit (a3) to the sixth bit (a6), signal point division and LDPC decoding based on the decoding result of the previous stage are repeated (multistage decoding). Also, in order to correct residual bit errors after LDPC decoding, a BCH outer code is concatenated to all bits.

Characteristic items of the transmitting device and the receiving device according to the present invention are listed below.

The first feature is
In a transmission device that transmits digital data, the symbols after encoding by the LDPC code with the overall average coding rate of 4/5 are shown in Tables 11 and 12, which will be described later, as a signal point arrangement in the 64APSK modulation scheme. Alternatively, it is configured to include mapping means for mapping the IQ signals shown in Tables 15 and 16. This signal point arrangement takes into consideration nonlinear distortion in a nonlinear transmission line and adaptive equalization performance on the receiving side. This makes it possible to improve resistance to nonlinear distortion due to a nonlinear transmission line compared to 64APSK of Non-Patent Document 9.

The second feature is
Bit allocation of each bit constituting the symbol for the signal constellation is configured as shown in Table 13 based on Tables 11 and 12, or Table 17 based on Tables 15 and 16, which will be described later.

The third feature is
In a transmission device that transmits digital data that constitutes the signal point arrangement and the bit allocation of each bit that constitutes the symbol, the average coding rate of the entire LDPC code is 96/120 for 64APSK as the modulation scheme (that is, 4/5) is applied, and a concatenated code composed of a BCH code including an LDPC code as a part is assigned to a signal point used for modulation, and the concatenated code is each bit constituting a symbol has a predetermined number of coding rates determined according to the required correction capability of the set division method, and in encoding the LDPC code for each bit of the symbol configuration bits in the set partitioning method, the first bit (most significant bit ) to the 6th bit (least significant bit), for the 1st, 2nd, 3rd, 4th, and 6th bits, LDPC having a coding rate according to the BER characteristics of each bit code, and the 5th bit is coded by a predetermined BCH code without applying the LDPC code, or in order from the 1st bit (most significant bit) to the 6th bit (least significant bit), The 1st, 2nd, 3rd, 4th, and 5th bits are encoded by an LDPC code having a coding rate according to the BER characteristics of each bit, and the 6th bit is encoded by the LDPC code. The present invention is configured to perform encoding with a predetermined BCH code without applying. This makes it possible to improve the frequency utilization efficiency in the set partitioning method.

The fourth feature is
In the LDPC code, the code length of the LDPC code is set to 44880 bits. This enables transmission highly compatible with MPEG-2 TS (Motion Pictures Expert Group 2 Transport Stream).

The fifth feature is
In the concatenated code, the BCH code is a BCH (65535, 65343) shortened code or a BCH (65535, 65167) shortened code. As a result, sufficient error resistance can be obtained even when the inner code parity is not added in order to improve frequency utilization efficiency.

The sixth feature is
When the BCH code is a BCH (65535, 65343) shortened code, the information bits constituting the code sequence are all configured in units of bytes. As a result, it is possible to delimit variable-length packets such as TLV in units of bytes even in the information bit area of the code sequence in units of bytes.

The seventh feature is
The LDPC code is 57/120 for the first bit, 64/120 for the second bit, and 105/120 for the 4th bit, 117/120 for the 4th bit, 120/120 for the 5th bit (no LDPC parity), and 113/120 for the 6th bit, or 61/120 for the 1st bit, The coding rate is 63/120 for the 2nd bit, 101/120 for the 3rd bit, 115/120 for the 4th bit, 116/120 for the 5th bit, and 120/120 for the 6th bit (no LDPC parity). That's what it is. Having a coding rate determined according to the required correction capability for each bit in this way makes it possible to increase the frequency utilization efficiency in the set partitioning method.

The eighth feature is
In the transmitting apparatus having the features of the third to seventh points, information about one or more coding rates of the LDPC code and the BCH code used on the transmitting apparatus side is transmitted by a transmission multiplex control signal. As a result, it is possible to provide a transmitting apparatus and a receiving apparatus in which encoding and decoding are matched according to the coding rate used.

The ninth feature is
In a receiving device that receives a signal transmitted by a transmitting device configured according to the features of the third to seventh points, when LDPC decoding each bit that constitutes the symbol, the first bit, the second bit, the LDPC decoding processing is performed using a parity check matrix used for the LDPC code according to the correction capability of each bit in the order of 3 bits, 4th bits, 5th bits, and 6th bits.

The tenth feature is
In a receiving device that receives a signal transmitted by a transmitting device configured according to the characteristics of the third to seventh points, decoding corresponding to the LDPC code and BCH code at the coding rate used for encoding on the transmitting side is performed. That's what it is. This enables efficient error correction decoding.

The eleventh feature is
In a receiving device that receives a signal transmitted by a transmitting device configured according to the eighth characteristic, one or more coding rate information of the LDPC code and the BCH code is discriminated based on the transmission multiplex control signal. be. As a result, it is possible to provide a transmitting apparatus and a receiving apparatus in which encoding and decoding are matched according to the coding rate used.

By incorporating the above techniques into the transmitting device and the receiving device, it is possible to improve the transmission performance in 64APSK.

That is, a transmission device according to a first aspect of the present invention is a transmission device for transmitting digital data,
error correction coding means for applying a concatenated code composed of a BCH code partially including an LDPC code to the digital data to generate a symbol having an overall average coding rate of 4/5;
Define four concentric circles as the 1st, 2nd, 3rd, and 4th circles in ascending order of radius as the signal point arrangement in the 64APSK modulation system for the symbols encoded by the error correction encoding means. 12 signal points on the first circle, 16 signal points on the second circle, 16 signal points on the third circle, and 20 signal points on the fourth circle. mapping means for mapping the IQ signal of the modulus;
a quadrature modulation means for modulating the symbols mapped by the mapping means using a 64APSK modulation method and transmitting a modulated wave signal to a receiving device that performs adaptive equalization processing via a nonlinear transmission path;
The mapping means sets the phase angles in the signal point constellation for the first circle at intervals of 30 degrees from a position 22 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis, and for the second circle on the I axis. 22.5 degrees from the position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees of the I axis, and the third circle is 22 degrees from the position of 11.45 degrees counterclockwise from the reference phase of 0 degrees of the I axis. .5 degree intervals, and the fourth circle is set at 18 degree intervals from a position 11.3 degrees counterclockwise with respect to the reference phase of 0 degree of the I axis, and the radius ratio in the signal point arrangement is the first circle, The radii of the second, third, and fourth circles are defined as r1, r2, r3, and r4, respectively, and the ratios of the radii to r1 are γ1=r2/r1, γ2=r3/r1, and γ3=r4. /r1, in order to reduce the influence of nonlinear distortion that occurs in a nonlinear transmission path , set division is performed for the signal point arrangement with γ1 = 2.02, γ2 = 2.98, and γ3 = 4.14. Based on the method, bit allocation is performed so that the transmission line capacity after signal division is maximized in a predetermined calculation method and a predetermined signal power to noise power ratio, and then the BER of each bit of 64 APSK symbols is LDPC. Mapping the IQ signal by allocating the bits constituting the symbol according to the bit allocation in which the bits are exchanged so that the error can be corrected within the code application range or only with the BCH code ,
The LDPC code is 57/120 for the first bit, which is the most significant bit, 64/120 for the second bit, and It has a coding rate of 105/120, 117/120 in the 4th bit, 120/120 (no LDPC parity) in the 5th bit, and 113/120 in the 6th bit, which is the least significant bit.

Further, in the transmission device of the first aspect according to the present invention, the bit assignment of each bit constituting the symbol for the signal point arrangement is
For the first circle, "001100 (14 in octal notation)" is placed at a position of 22 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"011100 (34 in octal notation)" at the position of 52 degrees,
"101100 (54 in octal notation)" at the position of 82 degrees,
"111100 (74 in octal notation)" at the position of 112 degrees,
"000101 (05 in octal notation)" at the position of 142 degrees,
"010100 (24 in octal notation)" at the position of 172 degrees,
"100101 (45 in octal notation)" at the position of 202 degrees,
"110101 (65 in octal notation)" at the position of 232 degrees,
"001101 (15 in octal notation)" at the position of 262 degrees,
"011001 (31 in octal notation)" at the position of 292 degrees,
"101001 (51 in octal notation)" at the position of 322 degrees,
"111001 (71 in octal notation)" at the position of 352 degrees,
For the second circle, "111000 (70 in octal notation)" is placed at a position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"000001 (01 in octal notation)" at the position of 45.05 degrees,
"010000 (20 in octal notation)" at the position of 67.55 degrees,
"100001 (41 in octal notation)" at the position of 90.05 degrees,
"110001 (61 in octal notation)" at the position of 112.55 degrees,
"001001 (11 in octal notation)" at the position of 135.05 degrees,
"011101 (35 in octal notation)" at the position of 157.55 degrees,
"101101 (55 in octal notation)" at the position of 180.05 degrees,
"111101 (75 in octal notation)" at the position of 202.55 degrees,
"000000 (00 in octal notation)" at the position of 225.05 degrees,
"010001 (21 in octal notation)" at the position of 247.55 degrees,
"100000 (40 in octal notation)" at the position of 270.05 degrees,
"110000 (60 in octal notation)" at the position of 292.55 degrees,
"001000 (10 in octal notation)" at the position of 315.05 degrees,
"011000 (30 in octal notation)" at the position of 337.55 degrees,
"101000 (50 in octal notation)" at the position of 360.05 degrees,
For the third circle, "001111 (17 in octal notation)" is placed at a position of 11.45 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"011111 (37 in octal notation)" at the position of 33.95 degrees,
"101111 (57 in octal notation)" at the position of 56.45 degrees,
"111111 (77 in octal notation)" at the position of 78.95 degrees,
"000100 (04 in octal notation)" at the position of 101.45 degrees,
"010101 (25 in octal notation)" at the position of 123.95 degrees,
"100100 (44 in octal notation)" at the position of 146.45 degrees,
"110100 (64 in octal notation)" at the position of 168.95 degrees,
"001110 (16 in octal notation)" at the position of 191.45 degrees,
"011110 (36 in octal notation)" at the position of 213.95 degrees,
"101110 (56 in octal notation)" at the position of 236.45 degrees,
"111110 (76 in octal notation)" at the position of 258.95 degrees,
"000111 (07 in octal notation)" at the position of 281.45 degrees,
"010110 (26 in octal notation)" at the position of 303.95 degrees,
"100111 (47 in octal notation)" at the position of 326.45 degrees,
"110111 (67 in octal notation)" at the position of 348.95 degrees,
For the fourth circle, "000010 (02 in octal notation)" is placed at a position of 11.3 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"010011 (23 in octal notation)" at the position of 29.3 degrees,
"100010 (42 in octal notation)" at the position of 47.3 degrees,
"110010 (62 in octal notation)" at the position of 65.3 degrees,
"001010 (12 in octal notation)" at the position of 83.3 degrees,
"011010 (32 in octal notation)" at the position of 101.3 degrees,
"101010 (52 in octal notation)" at the position of 119.3 degrees,
"111010 (72 in octal notation)" at the position of 137.3 degrees,
"000011 (03 in octal notation)" at the position of 155.3 degrees,
"010010 (22 in octal notation)" at the position of 173.3 degrees,
"100011 (43 in octal notation)" at the position of 191.3 degrees,
"110011 (63 in octal notation)" at the position of 209.3 degrees,
"001011 (13 in octal notation)" at the position of 227.3 degrees,
"011011 (33 in octal notation)" at the position of 245.3 degrees,
"101011 (53 in octal notation)" at the position of 263.3 degrees,
"111011 (73 in octal notation)" at the position of 281.3 degrees,
"000110 (06 in octal notation)" at the position of 299.3 degrees,
"010111 (27 in octal notation)" at the position of 317.3 degrees,
"100110 (46 in octal notation)" at the position of 335.3 degrees,
"110110 (66 in octal notation)" at the position of 353.3 degrees,
It is characterized by being configured as follows.

Further, in the transmitting apparatus according to the first aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length consisting of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 57/120, It has a means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 1) of the coding rate 57/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the first aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length consisting of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 64/120, It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 2) of the coding rate 64/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the first aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length consisting of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length according to the coding rate 105/120, It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 3) of the coding rate 105/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the first aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 113/120, It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 9) with the coding rate of 113/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the first aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 117/120, It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 5) with the coding rate of 117/120 is as follows. It is characterized by comprising a table.

On the other hand, a transmission device according to a second aspect of the present invention is a transmission device for transmitting digital data,
error correction coding means for applying a concatenated code composed of a BCH code partially including an LDPC code to the digital data to generate a symbol having an overall average coding rate of 4/5;
Define four concentric circles as the 1st, 2nd, 3rd, and 4th circles in ascending order of radius as the signal point arrangement in the 64APSK modulation system for the symbols encoded by the error correction encoding means. 8 signal points on the first circle, 16 signal points on the second circle, 20 signal points on the third circle, and 20 signal points on the fourth circle. mapping means for mapping the IQ signal of the modulus;
a quadrature modulation means for modulating the symbols mapped by the mapping means using a 64APSK modulation method and transmitting a modulated wave signal to a receiving device that performs adaptive equalization processing via a nonlinear transmission path;
The mapping means sets the phase angles in the signal point constellation for the first circle at intervals of 45 degrees from a position of 58.4 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis, and for the second circle 22.5 degree intervals from the position of 14.55 degrees counterclockwise with respect to the I-axis reference phase of 0 degrees, and the third circle is 18 degrees from the position of 18 degrees counterclockwise with respect to the I-axis reference phase of 0 degrees. The fourth circle is set at intervals of 18 degrees from the position 9 degrees counterclockwise with respect to the reference phase of 0 degrees of the I-axis. The radii of the third circle and the fourth circle are defined as r1, r2, r3, and r4, respectively, and the radius ratio to r1 is defined as γ1=r2/r1, γ2=r3/r1, and γ3=r4/r1. Then, in order to reduce the influence of nonlinear distortion that occurs in the nonlinear transmission path, first, based on the set partitioning method, for the signal point arrangement with γ1 = 2.10, γ2 = 3.16, and γ3 = 4.49. , bit allocation is performed so that the transmission path capacity after signal division is maximized in a predetermined calculation method and a predetermined signal power to noise power ratio. Or mapping the IQ signal by allocating the bits that make up the symbol according to the bit allocation in which the bits are exchanged so that the error can be corrected only with the BCH code ,
The LDPC code is 61/120 for the first bit, which is the most significant bit, 63/120 for the second bit, and It has a coding rate of 101/120, 115/120 for the 4th bit, 116/120 for the 5th bit, and 120/120 (no LDPC parity) for the 6th bit, which is the least significant bit.

Further, in the transmission device of the second aspect according to the present invention, bit allocation of each bit constituting the symbol for the signal point arrangement is as follows:
Regarding the first circle, "101000 (50 in octal notation)" is placed at a position of 58.4 degrees counterclockwise with respect to the reference phase of 0 degree of the I axis,
"111010 (72 in octal notation)" at the position of 103.4 degrees,
"000010 (02 in octal notation)" at the position of 148.4 degrees,
"010010 (22 in octal notation)" at the position of 193.4 degrees,
"100010 (42 in octal notation)" at the position of 238.4 degrees,
"111100 (74 in octal notation)" at the position of 283.4 degrees,
"001000 (10 in octal notation)" at the position of 328.4 degrees,
"011100 (34 in octal notation)" at the position of 373.4 degrees,
For the second circle, "100100 (44 in octal notation)" is placed at a position of 14.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"010100 (24 in octal notation)" at the position of 37.05 degrees,
"000110 (06 in octal notation)" at the position of 59.55 degrees,
"110110 (66 in octal notation)" at the position of 82.05 degrees,
"101110 (56 in octal notation)" at the position of 104.55 degrees,
"011110 (36 in octal notation)" at the position of 127.05 degrees,
"001100 (14 in octal notation)" at the position of 149.55 degrees,
"111000 (70 in octal notation)" at the position of 172.05 degrees,
"101100 (54 in octal notation)" at the position of 194.55 degrees,
"011000 (30 in octal notation)" at the position of 217.05 degrees,
"001110 (16 in octal notation)" at the position of 239.55 degrees,
"111110 (76 in octal notation)" at the position of 262.05 degrees,
"100110 (46 in octal notation)" at the position of 284.55 degrees,
"010110 (26 in octal notation)" at the position of 307.05 degrees,
"000000 (00 in octal notation)" at the position of 329.55 degrees,
"110000 (60 in octal notation)" at the position of 352.05 degrees,
For the third circle, "101010 (52 in octal notation)" is placed at a position of 18 degrees counterclockwise with respect to the reference phase of 0 degree of the I axis,
"110010 (62 in octal notation)" at the position of 36 degrees,
"001111 (17 in octal notation)" at the position of 54 degrees,
"011010 (32 in octal notation)" at the position of 72 degrees,
"101101 (55 in octal notation)" at the position of 90 degrees,
"111101 (75 in octal notation)" at the position of 108 degrees,
"000100 (04 in octal notation)" at the position of 126 degrees,
"010000 (20 in octal notation)" at the position of 144 degrees,
"100111 (47 in octal notation)" at the position of 162 degrees,
"111111 (77 in octal notation)" at the position of 180 degrees,
"000111 (07 in octal notation)" at the position of 198 degrees,
"010111 (27 in octal notation)" at the position of 216 degrees,
"100000 (40 in octal notation)" at the position of 234 degrees,
"110100 (64 in octal notation)" at the position of 252 degrees,
"001101 (15 in octal notation)" at the position of 270 degrees,
"011101 (35 in octal notation)" at the position of 288 degrees,
"101111 (57 in octal notation)" at the position of 306 degrees,
"110111 (67 in octal notation)" at the position of 324 degrees,
"001010 (12 in octal notation)" at the position of 342 degrees,
"011111 (37 in octal notation)" at the position of 360 degrees,
For the fourth circle, "000001 (01 in octal notation)" is placed at a position of 9 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"010001 (21 in octal notation)" at the position of 27 degrees,
"100001 (41 in octal notation)" at the position of 45 degrees,
"110001 (61 in octal notation)" at the position of 63 degrees,
"000011 (03 in octal notation)" at the position of 81 degrees,
"010011 (23 in octal notation)" at the position of 99 degrees,
"100011 (43 in octal notation)" at the position of 117 degrees,
"110011 (63 in octal notation)" at the position of 135 degrees,
"001001 (11 in octal notation)" at the position of 153 degrees,
"011001 (31 in octal notation)" at the position of 171 degrees,
"101001 (51 in octal notation)" at the position of 189 degrees,
"111001 (71 in octal notation)" at the position of 207 degrees,
"001011 (13 in octal notation)" at the position of 225 degrees,
"011011 (33 in octal notation)" at the position of 243 degrees,
"101011 (53 in octal notation)" at the position of 261 degrees,
"111011 (73 in octal notation)" at the position of 279 degrees,
"000101 (05 in octal notation)" at the position of 297 degrees,
"010101 (25 in octal notation)" at the position of 315 degrees,
"100101 (45 in octal notation)" at the position of 333 degrees,
"110101 (65 in octal notation)" at the position of 351 degrees,
It is characterized by being configured as follows.

Further, in the transmitting apparatus according to the second aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding With a code length consisting of 44880 bits and a predetermined parity check matrix initial value table for each coding rate as an initial value, the unit 1 element of the submatrix corresponding to the information length corresponding to the coding rate 61/120 is It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 6) with the coding rate of 61/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the second aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 63/120, It has a means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 7) of the coding rate 63/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the second aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 101/120, It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 8) with the coding rate of 101/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the second aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding With a code length consisting of 44880 bits and a predetermined parity check matrix initial value table for each coding rate as an initial value, the unit 1 element of the submatrix corresponding to the information length corresponding to the coding rate 115/120 is It has means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 9) with the coding rate of 115/120 is as follows. It is characterized by comprising a table.

Further, in the transmitting apparatus according to the second aspect of the present invention, the error correction encoding means includes an encoder that LDPC-encodes the digital data using a parity check matrix unique to each encoding rate, and the encoding The unit uses a parity check matrix initial value table predetermined for each coding rate with a code length consisting of 44880 bits as an initial value, and 1 element of the submatrix corresponding to the information length corresponding to the coding rate 116/120, It has a means for performing LDPC encoding using a parity check matrix arranged in a column direction with a period of every 374 columns, and the parity check matrix initial value table (Table 10) of the coding rate 116/120 is as follows. It is characterized by comprising a table.

Also, in the transmitting apparatus according to the first or second aspect of the present invention, the BCH code is a BCH (65535, 65167) shortened code or a BCH (65535, 65167) shortened code.

Further, in the transmitting device according to the first or second aspect of the present invention, when the BCH code is a BCH (65535, 65343) shortened code, the information bits constituting the code sequence are all configured in byte units. Characterized by

Further, the receiving apparatus of the present invention receives, via a nonlinear transmission path, a modulated wave signal based on the 64APSK IQ signal transmitted from the transmitting apparatus of the first or second aspect of the present invention, and Orthogonal demodulation means for performing orthogonal demodulation processing corresponding to the 64APSK signal point arrangement to generate a demodulated signal, and adaptive equalization processing for the demodulated signal to compensate for distortion caused by the nonlinear transmission path. adaptive equalization means for outputting a received signal point sequence; and symbol configuration bits made up of a plurality of code sequences divisible by 6 bits constituting said 64APSK are acquired from said received signal point sequence, and LDPC determined for each bit. Decoding means for performing LDPC decoding processing using the coding rate of the code and performing BCH decoding processing, wherein the coding rate of the LDPC code determined for each bit is from the most significant bit of the symbol constituent bits. It is determined for each bit according to the required correction capability of the symbols divided by the set partitioning method in bit order from the least significant bit, and the average coding rate of the entire LDPC code determined for each bit is 4/ 5, and when the decoding means LDPC-decodes each bit constituting the symbol, the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit In order, LDPC decoding processing is performed using the parity check matrix used for the LDPC code according to the correction capability for each bit, and one or more coding rate information of the LDPC code and BCH code is determined based on the transmission multiplexing control signal. It is characterized by comprising a coding rate discriminating means.

Further, in the receiving apparatus of the present invention, the decoding means is based on the coding rate of the LDPC code and the parity check matrix individually set for each bit of the symbol configuration bits for 64APSK in the set partitioning method. It is characterized by decoding.

Then, the LDPC encoder of one aspect according to the present invention is provided in the error correction encoding means in the transmitting apparatus of the present invention, and for each bit of the symbol configuration bits for 64APSK with the average coding rate of 4/5, An LDPC encoder that LDPC-encodes digital data using a parity check matrix unique to each coding rate in encoding an LDPC code with a code length of 44880 bits in advance for each coding rate Using the defined parity check matrix initial value table as an initial value, the submatrix corresponding to the information length for the coding rate of the LDPC code individually set for each bit of the symbol configuration bits for 64APSK in the set partitioning method A means for performing LDPC encoding using a parity check matrix constructed by arranging elements of 1 in the column direction at intervals of every 374 columns.

Further, in the LDPC encoder according to one aspect of the present invention, the encoding rates 57/120, 61/120, 63/120, 64/120, 101/120, 105/120, 113/120, 115/120, Each parity check matrix initial value table for 116/120 and 117/120 consists of Table 1, Table 6, Table 7, Table 2, Table 8, Table 3, Table 4, Table 9, Table 10 and Table 5. characterized by

Further, the LDPC decoder of one aspect of the present invention provides digital data to which the parity of the LDPC code has been added by the LDPC encoder of one aspect of the present invention, and each of the symbol configuration bits for 64APSK in the set partitioning method. Decoding is performed based on the coding rate of the LDPC code set individually for each bit and the parity check matrix.

According to the present invention, for example, a transmission bit rate of 150 Mbps or more when transmitting digital data using 64APSK while satisfying 34.5 MHz, which is a usable bandwidth per satellite transponder in 12 GHz band satellite broadcasting. It becomes possible to realize a transmission system that Furthermore, according to the present invention, it is possible to improve the performance of coded modulation in a combination of error correcting code and multilevel modulation (64APSK), and to improve the transmission performance in a nonlinear transmission line.

It is a figure which shows the structural example of the transmitter of 1st Embodiment by this invention, and a receiver. (a) is a diagram showing a constellation of transmission signal points according to the technique of Non-Patent Document 9 and reception signal points via a nonlinear transmission path, and (b) is a diagram showing transmission signal points and reception signal points according to the first embodiment according to the present invention. FIG. 4 is a diagram showing a constellation of received signal points via a nonlinear transmission path; 1 is a diagram showing an overview of 64APSK signal point constellation design according to a first embodiment of the present invention; FIG. FIG. 10 is a diagram showing bit allocation results of the first bit to the sixth bit based on the transmission line capacity of 64APSK according to the first embodiment of the present invention; FIG. 4 is a diagram showing C/N vs. bit error rate characteristics before error correction for each bit of 64APSK according to the first embodiment of the present invention; FIG. 10 is a diagram showing bit allocation results of the 1st bit to the 6th bit after 64APSK bit permutation according to the first embodiment of the present invention; FIG. 4 is a diagram showing C/N vs. bit error rate characteristics before error correction for each bit after bit permutation of 64APSK according to the first embodiment according to the present invention; FIG. 4 is a diagram illustrating a division process of 1st to 6th bits after 64APSK bit permutation according to the first embodiment of the present invention; As Example 1 according to the first embodiment of the present invention, the first bit LDPC coding rate is 57/120, the second bit LDPC coding rate is 64/120, the third bit LDPC coding rate is 105/120, and the fourth bit is Slot configuration example for LDPC coding rate 117/120, 5th bit LDPC coding rate 120/120 (no LDPC parity), 6th bit LDPC coding rate 113/120, and BCH (65535, 65343) shortened code It is a figure which shows. As Example 2 according to the first embodiment of the present invention, information bits are configured in units of bytes in all code sequences, and the first bit LDPC coding rate is 57/120, the second bit LDPC coding rate is 64/120, 3rd bit LDPC coding rate 105/120, 4th bit LDPC coding rate 117/120, 5th bit LDPC coding rate 120/120 (no LDPC parity), 6th bit LDPC coding rate 113/120, and FIG. 10 is a diagram showing an example of slot configuration in the case of BCH (65535, 65343) shortened code; As Example 3 according to the first embodiment of the present invention, 1st bit LDPC coding rate 57/120, 2nd bit LDPC coding rate 64/120, 3rd bit LDPC coding rate 105/120, 4th bit Slot configuration example for LDPC coding rate 117/120, 5th bit LDPC coding rate 120/120 (no LDPC parity), 6th bit LDPC coding rate 113/120, and BCH (65535, 65167) shortened code It is a figure which shows. FIG. 10 is a diagram showing C/N vs. bit error rate characteristics comparing Example 3 according to the first embodiment of the present invention with the technique of Non-Patent Document 9; It is a figure which shows the required C/N comparison result which compares Example 3 which concerns on 1st Embodiment by this invention, and the technique of a nonpatent literature 9. FIG. It is a figure which shows the structural example of the transmitter of 2nd Embodiment by this invention, and a receiver. (a) is a diagram showing a constellation of transmission signal points according to the technique of Non-Patent Document 9 and reception signal points via a nonlinear transmission path, and (b) is a diagram showing transmission signal points and reception signal points according to the second embodiment according to the present invention. FIG. 4 is a diagram showing a constellation of received signal points via a nonlinear transmission path; FIG. 10 is a diagram showing bit allocation results of the first bit to the sixth bit based on the transmission line capacity of 64APSK according to the second embodiment of the present invention; FIG. 9 is a diagram showing C/N vs. bit error rate characteristics before error correction for each bit of 64APSK according to the second embodiment of the present invention; FIG. 10 is a diagram showing bit allocation results of the 1st to 6th bits after 64APSK bit permutation according to the second embodiment of the present invention; FIG. 10 is a diagram showing C/N vs. bit error rate characteristics before error correction for each bit after bit permutation of 64APSK according to the second embodiment according to the present invention; FIG. 7 is a diagram illustrating a division process of 1st to 6th bits after 64APSK bit permutation according to the second embodiment of the present invention; As Example 1 of the second embodiment according to the present invention, the first bit LDPC coding rate is 61/120, the second bit LDPC coding rate is 63/120, the third bit LDPC coding rate is 101/120, and the fourth bit is Slot configuration example for LDPC coding rate 115/120, 5th bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and BCH (65535, 65343) shortened code It is a figure which shows. As Example 2 according to the second embodiment of the present invention, information bits are configured in units of bytes in all code sequences, and the first bit LDPC coding rate is 61/120, the second bit LDPC coding rate is 63/120, 3rd bit LDPC coding rate 101/120, 4th bit LDPC coding rate 115/120, 5th bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and FIG. 10 is a diagram showing an example of slot configuration in the case of BCH (65535, 65343) shortened code; As Example 3 according to the second embodiment of the present invention, the first bit LDPC coding rate is 61/120, the second bit LDPC coding rate is 63/120, the third bit LDPC coding rate is 101/120, and the fourth bit is Slot configuration example for LDPC coding rate 115/120, 5th bit LDPC coding rate 116/120, 6th bit LDPC coding rate 120/120 (no LDPC parity), and BCH (65535, 65167) shortened code It is a figure which shows. FIG. 10 is a diagram showing C/N vs. bit error rate characteristics comparing Example 3 according to the second embodiment of the present invention with the technology of Non-Patent Document 9; It is a figure which shows the required C/N comparison result which compares Example 3 which concerns on 2nd Embodiment by this invention, and the technique of a nonpatent literature 9. FIG. FIG. 10 is a diagram showing an example of division by a conventional set division method in 8PSK; It is a figure which shows the division example of the set division method in conventional 16QAM. It is a diagram showing a division example of a set division method in the conventional 32QAM. Fig. 2 shows the bit allocation of prior art DVB-S2X;

The transmission system of the first embodiment will be described below with reference to FIGS. 1 to 13, and the transmission system of the second embodiment will be described with reference to FIGS. 14 to 25. FIG.

[First embodiment]
First, the transmission device 10 and the reception device 20 in the transmission system of the first embodiment will be described. FIG. 1 is a block diagram of a transmitting device 10 and a receiving device 20 of a first embodiment according to the present invention. The actual transmitter 10 has a function of multiplexing a synchronization signal with a modulated wave signal in order to identify the head of an error correction code, and information such as the setting of a transmission method used in ISDB-S etc. is sent to a receiver. It has a function of multiplexing a transmission multiplexing control signal (also called a TMCC signal) for advance notice into a modulated wave signal. The actual receiver 20 also has a synchronization detection function for detecting the synchronous signal multiplexed in the modulated wave signal to detect the beginning of the error correction code, and a function for detecting information such as the setting of the transmission system from the transmission multiplex control signal. It has a control function for setting the modulation method, coding rate, etc., but its detailed illustration is omitted.

(Device configuration)
[Transmitter]
Referring to FIG. 1, the transmission device 10 of the first embodiment is a forward error correction transmission device, and includes a serial/parallel conversion unit 11, an error correction coding unit 12, and a coding rate setting unit 13. , a mapping unit 14 , an orthogonal modulation unit 15 , and a coding rate determination signal multiplexing unit 16 . That is, the functional block configuration of the transmission device 10 is the same as that of the coding modulation transmission device using the set partitioning method, but the processing of the error correction coding unit 12, the coding rate setting unit 13, and the accompanying mapping unit 14 are the same as those of the conventional technique. different from

The serial/parallel conversion unit 11 converts a 1-bit transmission data sequence into a data sequence of M=log ₂ L bits, where L is the multilevel number of the modulation scheme used (M=log ₂ 64= in the case of 64-level modulation). 6-bit sequence) and sent to the error correction coding unit 12 .

The error correction coding unit 12 is composed of a first error correction coding unit 12-1 to a sixth error correction coding unit 12-6, and is coded by a predetermined error correction code (for example, BCH code and LDPC code). 6 code sequences are generated.

Each of the first error correction encoding unit 12-1 to the sixth error correction encoding unit 12-6 uses a BCH (65535, 65343) shortened code as an outer code as Example 1 described later, and the inner code has a code length of 44880 LDPC codes. Further, when the coding rate applied to the LDPC code described later is 120/120, the LDPC parity is not added, and error correction coding is performed only with the BCH (65535, 65343) shortened code as Example 1 described later. .

The coding rate setting unit 13 individually sets the coding rate of the LDPC code for each symbol-constituting bit in the set partitioning method. In particular, the LDPC code according to the present invention has an average coding rate of 96/120 (that is, 4/5), and in each bit of 64APSK modulation based on the set partitioning method, the coding rate setting unit of the first embodiment 13 will be described later in detail with reference to FIGS. 64/120, 105/120 for the 3rd bit, 117/120 coding rate for the 4th bit, 120/120 coding rate for the 5th bit (no LDPC parity), coding rate for the 6th bit A coding rate of 113/120 is set.

As a result, the error correction coding unit 12 can perform LDPC coding with sufficient correction ability by setting the coding rate in consideration of the correction ability of the symbol constituent bits by the set partitioning method. Therefore, it is possible to improve the frequency utilization efficiency in the set partitioning method.

In the example of the first embodiment, the LDPC code length is 44880, which is the same code length as the advanced satellite broadcasting system (see Non-Patent Document 5). It is also possible to apply the same assignment starting with the slot header in the slot configuration of each embodiment to be described later. Also, the mapping unit 14, which will be described later, can perform mapping that does not cause excess or deficiency in bit allocation when 64APSK is applied.

The mapping unit 14 uses the six code sequences as an input symbol sequence, and outputs the amplitude values of the I-axis and Q-axis signal points corresponding to the symbols to the quadrature modulation unit 15 as a signal point sequence of the IQ signal. Here, as will be described later with reference to FIG. 2, the 64APSK signal point arrangement by the mapping unit 14 of the first embodiment is the signal of Non-Patent Document 9 in consideration of non-linear distortion and the adaptive equalization performance of the receiving apparatus. This is a signal point arrangement in which two signal points on the third circle are allocated to the fourth circle from the point arrangement. As an example of bit allocation based on this signal point arrangement, FIG. 6 shows an example of bit allocation to symbols when the set partitioning method in 64APSK according to the first embodiment of the present invention is applied. FIG. 8 shows the set partitioning process of 64APSK when the set partitioning method by mapping shown in FIG. 6 is applied. That is, the correspondence relationship between symbols and signal points used for mapping according to the present invention is set division, which is assigned while proceeding with the division of each bit in the symbol-constituting bits in the order shown in FIGS. use the law.

Therefore, the mapping unit 14 functions as symbol/signal point conversion means for converting an input symbol sequence composed of a plurality of code sequences into a signal point sequence based on the correspondence relationship.

The quadrature modulation unit 15 performs roll-off filter processing on the IQ signal generated by the mapping unit 14, generates a modulated wave signal that is quadrature-modulated, and transmits the modulated wave signal to an external transmission line. The transmission line in this case is a non-linear transmission line via a 12 GHz band satellite transponder, for example.

The coding rate determination signal multiplexing unit 16 receives coding rate information for each bit of the symbol-constituting bits set for the error correction coding unit 12 by the coding rate setting unit 13 from the coding rate setting unit 13. It has a function of multiplexing the modulated wave signal in the quadrature modulator 15 so as to be transmitted by a transmission multiplexing control signal (that is, a TMCC signal).

[Receiving device]
The receiving device 20 of the first embodiment is a forward error correction receiving device, and includes an orthogonal demodulator 21, first to sixth bit log-likelihood ratio calculators 22-1 to 22-6, and first ˜6th bit error correction decoding units 23-1 to 23-6, a parallel/serial conversion unit 24, an encoding rate determination unit 25, and an adaptive equalization unit 26. That is, the functional block configuration of the receiver 20 is the same as that of the coded modulation receiver using the set partitioning method, but the processing of the orthogonal demodulator 21 and the 1st to 6th bit error correction decoders 23-1 to 23-6 is different from conventional techniques.

The quadrature demodulator 21 modulates the signal point sequence of the IQ signal based on the correspondence relationship between the symbols and the signal points obtained by the set division method according to the present invention, and outputs the modulated wave signal of 64APSK through the nonlinear transmission line. Then, the modulated wave signal is subjected to orthogonal demodulation processing corresponding to the 64APSK signal point arrangement to generate a demodulated signal, which is output to the adaptive equalizer 26 . Received signal point sequences corresponding to the symbols of the main signal are output to the first to sixth bit log-likelihood ratio calculators 22-1 to 22-6, respectively. Therefore, the quadrature demodulation unit 21 restores and outputs the signal point sequence of the IQ signal modulated based on the correspondence relationship between the symbols and the signal points obtained by the set partitioning method according to the present invention by quadrature demodulation. act as a means.

The adaptive equalization unit 26 applies adaptive equalization processing to the demodulated signal, thereby generating a received signal point sequence in which the distortion caused by the nonlinear transmission path is compensated for by the first to sixth bit log-likelihood ratio calculation units 22. -1 to 22-6.

The first bit log-likelihood ratio calculator 22-1 calculates 1 and 0 for the first bit constituting the symbol based on the correspondence relationship between the symbol and the signal point obtained by the set partitioning method according to the present invention. Then, the natural logarithm (LLR: log-likelihood ratio) of the ratio P11/P10 is calculated and sent to the first bit error correction decoding section 23-1.

The first bit error correction decoding unit 23-1 uses the log-likelihood ratio of the first bit by the first bit log-likelihood ratio calculation unit 22-1 to encode the first bit constituting the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 57/120, which is the coding rate information for the first bit obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the first bit is sent to the second bit log-likelihood ratio calculation unit 22-2 and the parallel/serial conversion unit 24.

The second bit log-likelihood ratio calculation unit 22-2 calculates the log-likelihood ratio of the second bit constituting the symbol in the same way as the first bit, based on the correspondence between the symbol and the signal point obtained by the set partitioning method according to the present invention. The degree ratio is calculated and sent to the second bit error correction decoding section 23-2.

The second bit error correction decoding unit 23-2 uses the second bit log-likelihood ratio calculated by the second bit log-likelihood ratio calculation unit 22-2 to encode the second bit constituting the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 64/120, which is the coding rate information for the second bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the second bit is sent to the third bit log-likelihood ratio calculation unit 22-3 and the parallel/serial conversion unit 24.

The third bit log-likelihood ratio calculator 22-3 calculates the third bit constituting the symbol based on the correspondence relationship between the symbol and the signal point obtained by the set partitioning method of the present invention. Then, the log-likelihood ratio is calculated and sent to the third bit error correction decoding unit 23-3.

The third bit error correction decoding unit 23-3 uses the third bit log-likelihood ratio calculated by the third bit log-likelihood ratio calculation unit 22-3 to encode the third bit forming the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 105/120, which is the coding rate information for the third bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the decoded result of the 3rd bit is sent to the 4th bit log-likelihood ratio calculation unit 22-4 and the parallel/serial conversion unit 24.

A fourth-bit log-likelihood ratio calculator 22-4 calculates first, second, and second The log-likelihood ratio is calculated in the same manner as for the 3 bits, and sent to the 4th bit error correction decoding unit 23-4.

The fourth bit error correction decoding unit 23-4 uses the log-likelihood ratio of the fourth bit by the fourth-bit log-likelihood ratio calculation unit 22-4 to encode the fourth bit forming the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 117/120, which is the coding rate information for the fourth bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. Outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the decoded result of the 4th bit is sent to the parallel/serial converter 24 .

A fifth bit log-likelihood ratio calculator 22-5 calculates the first, second, and second 3. Similar to the 4th bit, the logarithmic likelihood ratio is calculated and sent to the 5th bit error correction decoding unit 23-5.

The fifth bit error correction decoding unit 23-5 uses the log-likelihood ratio of the fifth bit by the fifth-bit log-likelihood ratio calculation unit 22-5 to encode the fifth bit forming the symbol. Outer code error correction according to, for example, the BCH (65535, 65343) shortened code generation polynomial of Embodiment 1, which corresponds to the coding rate 120/120, which is the coding rate information for the fifth bit obtained from the rate discriminating unit 25 is executed, and the decoded result of the fifth bit is sent to the parallel/serial converter 24 .

The 6th bit log-likelihood ratio calculator 22-6 calculates first, second, and second Similar to the 3rd, 4th and 5th bits, the logarithmic likelihood ratio is calculated and sent to the 6th bit error correction decoding section 23-6.

The 6th bit error correction decoding unit 23-6 uses the log-likelihood ratio of the 6th bit by the 6th bit log-likelihood ratio calculation unit 22-6 to encode the 6th bit constituting the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 113/120, which is the coding rate information for the 6th bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. Outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the decoded result of the 6th bit is sent to the parallel/serial converter 24 .

In this way, the first to sixth bit log-likelihood ratio calculation units 22-1 to 22-6 and the first to sixth bit error correction decoding units 23-1 to 23-6 are obtained by the set partitioning method. Sequential decoding is performed using the decoding result obtained for each bit and the logarithmic likelihood ratio based on the correspondence between symbols and signal points. Therefore, the 1st to 6th bit log-likelihood ratio calculators 22-1 to 22-6 and the 1st to 6th bit error correction decoders 23-1 to 23-6 perform the above-described set partitioning to obtain signal points. It functions as decoding means for decoding each symbol-constituting bit based on the correspondence relationship between the symbol-assigned signal point and the symbol.

The parallel/serial conversion unit 24 parallel/serial converts the decoded result of the data series corresponding to the bits constituting the symbols obtained from the first to sixth bit error correction decoding units 23-1 to 23-6, and converts the result into 1 bit. Sends out the received data sequence of

The coding rate discriminating unit 25 notifies the receiving device 20 of information such as the function of multiplexing the synchronization signal with the modulated wave signal to identify the head of the error correction code obtained from the orthogonal demodulation unit 21 and the setting of the transmission method. A transmission multiplexing control signal is input to determine the coding rate information for the 1st to 6th bits used in the 1st to 6th bit error correction decoding units 23-1 to 23-6 from the transmission multiplexing control signal. and sent to the 1st to 6th bit error correction decoders 23-1 to 23-6, respectively.

(64APSK signal point arrangement and bit allocation)
Here, the 64APSK signal point arrangement and bit allocation in the mapping unit 14 will be described in detail. As described above as a problem to be solved, in the satellite transmission system, by designing the signal point arrangement in consideration of the non-linear distortion caused by the satellite repeater and the adaptive equalization performance of the receiving device, The transmission performance can be improved more than when the optimized constellation is applied under white noise.

Therefore, in order to improve the performance of the 64APSK coded modulation in the satellite transmission system, we decided to study the design of the signal point arrangement in consideration of the nonlinear distortion and the adaptive equalization performance of the receiver. FIG. 2(a) shows reception signal points and transmission signal points shown in Non-Patent Document 9 when passing through a nonlinear transmission path. This received signal point is subjected to adaptive equalization processing after being affected by nonlinear distortion. Here, when the four concentric circles are defined as 1st, 2nd, 3rd, and 4th circles in ascending order of radius, focusing on the received signal points of the 2nd and 3rd circles, the transmission A large number of received signal points that are out of the vicinity of the signal points are confirmed. It can be seen that the signal points of the second and third circles are affected by the equalization error, deteriorating the MER, which is one of the indices for evaluating the reception performance. Therefore, in the first embodiment according to the present invention, as shown in FIG. 2B, two signal points of the third circle of Non-Patent Document 9 are distributed to the fourth circle with less equalization error. After that, the phase and radius ratios were designed so as to maximize the transmission line capacity, which will be described later. As described above, it is possible to improve the performance of a nonlinear transmission line by applying a signal point arrangement that considers nonlinear distortion and the adaptive equalization performance of a receiving apparatus.

As a design criterion for the phase and radius ratios, the transmission line capacity T (equation (1)), which is the Shannon limit for the limited modulation scheme, is used. The transmission line capacity T is defined by the equation (1) when x is a transmission symbol and y is a reception symbol in an AWGN transmission line. M is the number of signal points, p(y|x) is a transition probability density function determined from the minimum Euclidean distance between signal points and the C/N shown in Equation ( ² ), and σ2 is white noise power. The first term of equation (1) is the average amount of information of the received symbol y and is determined from the number of signal points M. The second term in equation (1) indicates the average amount of information for which the received symbol is y when a certain transmission symbol x is transmitted.

Considering maximizing the transmission line capacity T, the value of the second term in the equation (1) should be minimized when the number of signal points M and C/N are fixed. At this time, the second term in equation (1) becomes a function of the minimum Euclidean distance between signal points, and the larger the minimum Euclidean distance, the smaller the second term. Therefore, maximizing the transmission line capacity T in equation (1) is equivalent to expanding the minimum Euclidean distance between signal points. By increasing the minimum Euclidean distance between signal points, it is possible to reduce the possibility that a certain received symbol is erroneously received as an adjacent symbol, leading to an improvement in the error rate after reception.

From the above, by designing the signal point arrangement in consideration of the nonlinear distortion and the adaptive equalization performance of the receiving device, it is possible to reduce the number of signal points in the third circle, where equalization errors are likely to occur. transmission performance improvement. As a specific signal point constellation design method, the number of signal points to be arranged on a circle is divided into two signal points on the third circle and two signal points on the fourth circle in the signal point constellation of Non-Patent Document 9, and the phase of the signal points is , and the radius ratio between the circumferences, each value was designed so as to maximize the transmission line capacity shown in Equation (1).

More specifically, in the 64APSK signal point arrangement design of the present invention, the number of signal points to be arranged on the circle is designed in consideration of nonlinear distortion and the adaptive equalization performance of the receiving apparatus, and the phase and radius ratio are was designed so that the number of signal points M=64, design C/N=16 dB, and the transmission line capacity calculated by the equation (1) was maximized. The design C/N was C/N=16 dB with a gap of about 1 dB as the performance target for the theoretical limit C/N=14.9 dB of 64APSK (LDPC coding rate 4/5).

As shown in FIG. 3, the design parameters are (a) the number of signal points on the signal point arrangement of each of the first to fourth circles, and (b) the phase of each signal point on each of the first to fourth circles ( First phase θ ₀ 1 to θ ₀ 4 and phase interval θ 1 to θ 4) in each circle counterclockwise with respect to the reference phase 0 degree of the I axis, (c) Radius ratio between the circumferences of the first circle to the fourth circle (γ1 to γ3), and each design parameter was determined so as to maximize the transmission line capacity. The radii of the first to fourth circles are r1 to r4, respectively, and the radius ratios are defined as γ1=r2/r1, γ2=r3/r1, and γ3=r4/r1 with r1 as a reference.

Table 11 shows the designed signal point constellation of 64APSK. Table 11 shows the signal point coordinates of the IQ signal normalized by the transmission power 1 generated by this design. Also, each design parameter and transmission line capacity optimized for the signal point arrangement in Table 11 are shown in Table 12 so that they can be compared with DVB-S2X.

Next, bit allocation to the above 64APSK signal point constellation is also optimized. Multi-level coded modulation to which the set partitioning method is applied, which is conventional technology, divides the signal points according to the decoding result of the previous bit based on the set partitioning method, and demodulates each bit. For example, for the demodulation of the second bit (a2), the result of demodulation of the first bit (a1) is divided into signal points a1=0 and a1=1, respectively, and then demodulated. Signal points are divided and demodulated. As the signal points are divided in this manner, the minimum Euclidean distance between signal points can be increased, and the BER characteristic of each bit is It is possible to improve the transmission characteristics as a whole.

In order to apply the set partitioning method in this way, it is necessary to allocate bits to each signal point so that the minimum Euclidean distance of the signal points after partitioning becomes as large as possible. In QAM, where the signal points are arranged in a lattice, it is possible to allocate bits to expand the minimum Euclidean distance between geometrically adjacent signal points. It is geometrically difficult to extend the minimum Euclidean distance for such a modulation scheme.

Therefore, in the mapping of 64APSK according to the present invention, bits are assigned to each signal point based on the above-described transmission channel capacity T (equation (1)). As described above, maximizing the transmission line capacity is equivalent to increasing the minimum Euclidean distance. Therefore, by performing bit allocation that maximizes the transmission line capacity after signal point division, it is possible to extend the minimum Euclidean distance after signal point division when the set division method is applied to 64APSK.

Specifically, the transmission line capacity formula (1) is applied as an evaluation function when bit allocation is performed on the 64APSK signal point arrangement based on the set division method, and the transmission line capacity after signal division at C/N = 16 dB is the maximum bit allocation. As a result of allocating the 1st to 6th bits to the signal points based on the transmission channel capacity, the results shown in FIG. 4 are obtained. In FIG. 4, the 6 bits assigned to the signal points are defined as the 1st bit (a1), the 2nd bit (a2), . is written in Also, FIG. 5 shows the BER characteristics before error correction for each bit, which corresponds to the output of the quadrature demodulator 21 on the receiver 20 side.

However, in order to apply a concatenated code consisting of an LDPC code (inner code) and a BCH code (outer code) for each bit as a 64APSK error correction code based on the set partitioning method, the current standard (ISDB-S3: non-patent document The LDPC code adopted in 5) can be designed to keep the randomness of the code in the range of BER before error correction from 1.5×10 ⁻¹ to 2.0×10 ⁻³ . Also, when BCH (65535, 65167, t = 23) code is applied as the outer code, the BER before error correction can be expected to be pseudo-error-free (1 × 10 ^-11 ) is 1.2 × 10 ^-4 or less. . Here, focusing on C/N=16 dB in FIG. 5, the BER of the first bit is 1.96×10 ⁻¹ , which is outside the LDPC code design range.

Therefore, by performing bit replacement from the bit allocation in FIG. 4, bit allocation was performed such that the BER of the 1st to 6th bits is within the LDPC code application range or error correction is possible only with the BCH code. FIG. 6 shows the bit allocation result at that time, and FIG. 7 shows the BER characteristic before error correction for each bit. FIG. 8 shows the division result of the set division method for the 1st to 6th bits after this bit permutation. For the sake of simplicity, FIG. 8 shows cases where a1=0, a2=0, a3=0, a4=0, and a5=0, and other division results are omitted.

That is, the mapping unit 14 of the first embodiment performs mapping as shown in Table 13 as bit allocation of each bit constituting a symbol for the 64APSK signal point arrangement shown in FIG.

(Code parameters of LDPC codes of Examples 1 to 3)
Here, from the BER characteristics in FIG. 7, the BER of the fifth bit (a5) at C/N=16 dB is 1.17×10 ⁻⁴ , and error-free operation can be achieved only with the BCH outer code. Finally, in the present invention, the LDPC coding rate applied to the first bit (a1) to the fourth bit (a4) and the sixth bit (a6) while satisfying the overall average coding rate of 4/5 of the LDPC code and designed an LDPC code that minimizes the required C/N (defined as C/N corresponding to BER=1×10 ⁻¹¹ ) under white noise.

At this time, the structure of the LDPC parity check matrix was the same as ISDB-S3. That is, the error correction coding unit 12 is configured to include an encoder for LDPC-encoding the digital data using a parity check matrix unique to each coding rate. 1 element of the submatrix corresponding to the information length according to the coding rate is arranged in the column direction at intervals of every 374 columns, using the parity check matrix initial value table predetermined for each coding rate as the initial value. LDPC encoding is performed using the parity check matrix configured as above.

As the specifications of the designed LDPC code, the coding rate for each bit shown in Table 14 satisfies the average coding rate of 4/5 of the entire LDPC code, and Examples 1 to 3 shown in FIGS. slot configuration. Also, the initial value table of the parity check matrix in the LDPC code for each bit shown in Table 14 is as shown in Tables 1 to 5 described above.

In addition, in the slot configuration of the first embodiment shown in FIG. 9, it is assumed that the slot header area is used to accommodate variable-length packets such as TLV packets configured in units of bytes. In the slot configuration of , when looking at each code sequence that constitutes the slot, the information bits are not configured in units of bytes, making it difficult to write the byte information indicating the breaks of the variable-length packets into the slot header area. It is expected that.

Therefore, as in the second embodiment shown in FIG. 10, by using a slot configuration in which information bits are configured in byte units for each bit code sequence, information indicating breaks in variable-length packets configured in byte units can be obtained. to the slot header area.

In addition, in order to apply a BCH code with a higher correction capability as an outer code, a slot with a code length of 44880 bits is converted to a slot of Example 3 as shown in FIG. can be configured.

That is, in the slot configuration of the first embodiment shown in FIG. 9, a slot header of 176 bits and stuff bits of 6 bits are provided, like the slot configuration of the conventional advanced satellite broadcasting system. However, in the target required C/N, if the bit error of the 5th bit (a5) among the bits constituting the symbol is large enough to be corrected only by the BCH (65535, 65343) shortened code Furthermore, it is desirable to enhance the correction capability without changing the code length of 44880 bits. In addition, by applying the BCH (65535, 65167) shortening code to each bit from the 1st to 4th bits and the 6th bit (a6), the effect of error propagation when decoding sequentially from the 1st bit is reduced. It becomes possible to

Therefore, as shown in FIG. 11, in the slot configuration of the third embodiment, the slot header area is deleted, the deleted 176 bits are assigned to the parity of the BCH code, and the BCH (65535, 65343) with a correction capability of 12 bits is shortened. The code is enhanced to a BCH (65535, 65167) shortened code with a correction capability of 23 bits. Even if the slot header is deleted in this way, no problem arises in terms of signal identification by providing the transmission multiplex control signal with information capable of identifying both.

As a result, when the target required C/N is sufficiently high (that is, when the target value is higher than the required C/N determined by the BCH (65535, 65343) shortened code), the slot configuration of the third embodiment (FIG. 11) can be adopted, and therefore, depending on the target required C/N, the slot configuration of Example 1 or 2 (FIGS. 9 and 10) and the slot configuration of Example 3 (FIG. 11 ) can be switched and adopted.

Incidentally, the generator polynomial of the BCH (65535, 65167) shortened code is as disclosed in Patent Document 1. Also, the generator polynomial of the BCH (65535, 65343) shortened code is as disclosed in Non-Patent Document 5.

As an effect of the present invention, transmission performance (simulation results) when using the slot configuration of FIG. 11 in the transmitting device 10 and the receiving device 20 of FIG. 1 will be described. The transmission model assumed white noise, the BCH outer code was a BCH (65535, 65167, t=23) code, and the decoding iteration count of the LDPC code was set to a maximum of 50 per stage.

According to Table 14, FIG. 12 shows C/N vs. BER characteristics obtained by computer simulation in a non-linear transmission line assuming that a 12 GHz band satellite repeater is used in this example. In FIG. 12, the simulation results of Non-Patent Document 9 when the same nonlinear transmission model is propagated are also plotted. The computer simulation was performed up to BER=10 ⁻⁸ order and extrapolated up to BER=1×10 ⁻¹¹ by linear interpolation. The results obtained from FIG. 12 are shown in FIG. From FIG. 13, the required C/N of the technology of the present invention is 17.18 dB in a non-linear transmission path assuming a 12 GHz band satellite repeater, and a performance improvement of 0.34 dB is possible according to Non-Patent Document 9. .

In particular, in the technique of Non-Patent Document 9, as a new 64APSK signal point arrangement, the number of signal points arranged on four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and each The amplitude values of the signal points are almost matched, and the phase value of each signal point is adjusted. On the other hand, in the new signal point arrangement of 64APSK according to the first embodiment according to the present invention, as a signal point arrangement considering non-linear distortion and adaptive equalization performance of the receiving apparatus, Equalization from signal point arrangement in Non-Patent Document 9 Two signal points on the third circle, where errors are likely to occur, are assigned to the fourth circle.

In addition, in the bit allocation by the set partitioning method using the new signal point arrangement of 64APSK according to the present invention, the predetermined signal power to noise The bit error rate can be further reduced by performing bit permutation so as to satisfy the power ratio.

Furthermore, in the error correction code based on the new signal point arrangement of the 64APSK according to the present invention and the bit allocation by the new set partitioning method, the entire slot configuration of 6 slots as a concatenated code by the LDPC code and the BCH code is The average coding rate of the LDPC code of satisfies 4/5, the LDPC coding rate of each slot in the six slots is defined as shown in Table 14, and the initial value of the parity check matrix of the LDPC code in the set partitioning method By optimizing the table, transmission performance can be further improved.

As a result, in the configuration of the transmitting device 10 and the receiving device 20 according to one embodiment of the present invention, for example, a performance improvement of 0.34 dB over the technique of Non-Patent Document 9 is achieved in a non-linear transmission path via a 12 GHz band satellite repeater. It is possible.

[Second embodiment]
Next, the transmitting device 10 and the receiving device 20 in the transmission system of the second embodiment will be described. The same reference numerals are given to the same components as in the first embodiment. FIG. 1 is a block diagram of a transmitting device 10 and a receiving device 20 of a first embodiment according to the present invention. The actual transmitter 10 has a function of multiplexing a synchronization signal with a modulated wave signal in order to identify the head of an error correction code, and information such as the setting of a transmission method used in ISDB-S etc. is sent to a receiver. It has a function of multiplexing a transmission multiplexing control signal (also called a TMCC signal) for advance notice into a modulated wave signal. The actual receiver 20 also has a synchronization detection function for detecting the synchronous signal multiplexed in the modulated wave signal to detect the beginning of the error correction code, and a function for detecting information such as the setting of the transmission system from the transmission multiplex control signal. It has a control function for setting the modulation method, coding rate, etc., but its detailed illustration is omitted.

(Device configuration)
[Transmitter]
Referring to FIG. 14, the transmission device 10 of the second embodiment is a forward error correction transmission device, and includes a serial/parallel conversion unit 11, an error correction coding unit 12, and a coding rate setting unit 13. , a mapping unit 14 , an orthogonal modulation unit 15 , and a coding rate determination signal multiplexing unit 16 . That is, the functional block configuration of the transmission device 10 is the same as that of the coding modulation transmission device using the set partitioning method, but the processing of the error correction coding unit 12, the coding rate setting unit 13, and the accompanying mapping unit 14 are the same as those of the conventional technique. different from

The serial/parallel conversion unit 11 converts a 1-bit transmission data sequence into a data sequence of M=log ₂ L bits, where L is the multilevel number of the modulation scheme used (M=log ₂ 64= in the case of 64-level modulation). 6-bit sequence) and sent to the error correction coding unit 12 .

The error correction coding unit 12 is composed of a first error correction coding unit 12-1 to a sixth error correction coding unit 12-6, and is coded by a predetermined error correction code (for example, BCH code and LDPC code). 6 code sequences are generated.

Each of the first error correction encoding unit 12-1 to the sixth error correction encoding unit 12-6 uses a BCH (65535, 65343) shortened code as an outer code as Example 1 described later, and the inner code has a code length of 44880 LDPC codes. Further, when the coding rate applied to the LDPC code described later is 120/120, the LDPC parity is not added, and error correction coding is performed only with the BCH (65535, 65343) shortened code as Example 1 described later. .

The coding rate setting unit 13 individually sets the coding rate of the LDPC code for each symbol-constituting bit in the set partitioning method. In particular, the LDPC code according to the present invention has an average coding rate of 96/120 (that is, 4/5), and in each bit of 64APSK modulation based on the set partitioning method, the coding rate setting unit of the second embodiment 13 will be described in detail later with reference to FIGS. 63/120, 101/120 for the 3rd bit, 115/120 coding rate for the 4th bit, 116/120 coding rate for the 5th bit, 120/120 coding rate for the 6th bit (LDPC (no parity) coding rate.

As a result, the error correction coding unit 12 can perform LDPC coding with sufficient correction ability by setting the coding rate in consideration of the correction ability of the symbol constituent bits by the set partitioning method. Therefore, it is possible to improve the frequency utilization efficiency in the set partitioning method.

In the example of the second embodiment, the LDPC code length is 44880, which is the same code length as the advanced satellite broadcasting system (see Non-Patent Document 5). It is also possible to apply the same assignment starting with the slot header in the slot configuration of each embodiment to be described later. Also, the mapping unit 14, which will be described later, can perform mapping that does not cause excess or deficiency in bit allocation when 64APSK is applied.

The mapping unit 14 uses the six code sequences as an input symbol sequence, and outputs the amplitude values of the I-axis and Q-axis signal points corresponding to the symbols to the quadrature modulation unit 15 as a signal point sequence of the IQ signal. Here, the 64APSK signal point arrangement by the mapping unit 14 of the second embodiment differs from that of the first embodiment, and in consideration of nonlinear distortion and adaptive equalization performance of the receiving apparatus, the transmission performance in the nonlinear transmission line is It is a signal point arrangement designed to improve the phase and radius ratio of signal points, and as an example of bit allocation based on this signal point arrangement, FIG. It shows an example of bit allocation to symbols when applied. FIG. 20 shows the set partitioning process of 64APSK when the set partitioning method by mapping shown in FIG. 18 is applied. That is, the correspondence relationship between symbols and signal points used for mapping according to the present invention is set division, which is assigned while proceeding with the division of each bit in the symbol-constituting bits in the order shown in FIGS. use the law.

Therefore, the mapping unit 14 functions as symbol/signal point conversion means for converting an input symbol sequence composed of a plurality of code sequences into a signal point sequence based on the correspondence relationship.

The quadrature modulation unit 15 performs roll-off filter processing on the IQ signal generated by the mapping unit 14, generates a modulated wave signal that is quadrature-modulated, and transmits the modulated wave signal to an external transmission line. The transmission line in this case is a non-linear transmission line via a 12 GHz band satellite transponder, for example.

The coding rate determination signal multiplexing unit 16 receives coding rate information for each bit of the symbol-constituting bits set for the error correction coding unit 12 by the coding rate setting unit 13 from the coding rate setting unit 13. It has a function of multiplexing the modulated wave signal in the quadrature modulator 15 so as to be transmitted by a transmission multiplexing control signal (that is, a TMCC signal).

[Receiving device]
The receiving apparatus 20 of the second embodiment is a forward error correction receiving apparatus, and includes an orthogonal demodulator 21, first to sixth bit log-likelihood ratio calculators 22-1 to 22-6, and first ˜6th bit error correction decoding units 23-1 to 23-6, a parallel/serial conversion unit 24, an encoding rate determination unit 25, and an adaptive equalization unit 26. That is, the functional block configuration of the receiver 20 is the same as that of the coded modulation receiver using the set partitioning method, but the processing of the orthogonal demodulator 21 and the 1st to 6th bit error correction decoders 23-1 to 23-6 is different from conventional techniques.

The quadrature demodulator 21 modulates the signal point sequence of the IQ signal based on the correspondence relationship between the symbols and the signal points obtained by the set division method according to the present invention, and outputs the modulated wave signal of 64APSK through the nonlinear transmission line. Then, the modulated wave signal is subjected to orthogonal demodulation processing corresponding to the 64APSK signal point arrangement to generate a demodulated signal, which is output to the adaptive equalizer 26 . Received signal point sequences corresponding to the symbols of the main signal are output to the first to sixth bit log-likelihood ratio calculators 22-1 to 22-6, respectively. Therefore, the quadrature demodulation unit 21 restores and outputs the signal point sequence of the IQ signal modulated based on the correspondence relationship between the symbols and the signal points obtained by the set partitioning method according to the present invention by quadrature demodulation. act as a means.

The adaptive equalization unit 26 applies adaptive equalization processing to the demodulated signal, thereby generating a received signal point sequence in which the distortion caused by the nonlinear transmission path is compensated for by the first to sixth bit log-likelihood ratio calculation units 22. -1 to 22-6.

The first bit log-likelihood ratio calculator 22-1 calculates 1 and 0 for the first bit constituting the symbol based on the correspondence relationship between the symbol and the signal point obtained by the set partitioning method according to the present invention. Then, the natural logarithm (LLR: log-likelihood ratio) of the ratio P11/P10 is calculated and sent to the first bit error correction decoding section 23-1.

The first bit error correction decoding unit 23-1 uses the log-likelihood ratio of the first bit by the first bit log-likelihood ratio calculation unit 22-1 to encode the first bit constituting the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 61/120, which is the coding rate information for the first bit obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the first bit is sent to the second bit log-likelihood ratio calculation unit 22-2 and the parallel/serial conversion unit 24.

The second bit log-likelihood ratio calculation unit 22-2 calculates the log-likelihood ratio of the second bit constituting the symbol in the same way as the first bit, based on the correspondence between the symbol and the signal point obtained by the set partitioning method according to the present invention. The degree ratio is calculated and sent to the second bit error correction decoding section 23-2.

The second bit error correction decoding unit 23-2 uses the second bit log-likelihood ratio calculated by the second bit log-likelihood ratio calculation unit 22-2 to encode the second bit constituting the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 63/120, which is the coding rate information for the second bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the decoding result of the second bit is sent to the third bit log-likelihood ratio calculation unit 22-3 and the parallel/serial conversion unit 24.

The third bit log-likelihood ratio calculator 22-3 calculates the third bit constituting the symbol based on the correspondence relationship between the symbol and the signal point obtained by the set partitioning method of the present invention. Then, the log-likelihood ratio is calculated and sent to the third bit error correction decoding unit 23-3.

The third bit error correction decoding unit 23-3 uses the third bit log-likelihood ratio calculated by the third bit log-likelihood ratio calculation unit 22-3 to encode the third bit forming the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 101/120, which is the coding rate information for the third bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, later described. In the first embodiment, outer code error correction is performed according to the BCH (65535, 65343) shortened code generation polynomial, and the decoded result of the 3rd bit is sent to the 4th bit log-likelihood ratio calculation unit 22-4 and the parallel/serial conversion unit 24.

A fourth-bit log-likelihood ratio calculator 22-4 calculates first, second, and second The log-likelihood ratio is calculated in the same manner as for the 3 bits, and sent to the 4th bit error correction decoding unit 23-4.

The fourth bit error correction decoding unit 23-4 uses the log-likelihood ratio of the fourth bit by the fourth-bit log-likelihood ratio calculation unit 22-4 to encode the fourth bit forming the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 115/120, which is the coding rate information for the fourth bit obtained from the rate discriminating unit 25, and the LDPC decoding result is input, for example, as described later. Outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the decoded result of the 4th bit is sent to the parallel/serial converter 24 .

A fifth bit log-likelihood ratio calculator 22-5 calculates the first, second, and second 3. Similar to the 4th bit, the logarithmic likelihood ratio is calculated and sent to the 5th bit error correction decoding section 23-5.

The fifth bit error correction decoding unit 23-5 uses the log-likelihood ratio of the fifth bit by the fifth-bit log-likelihood ratio calculation unit 22-5 to encode the fifth bit forming the symbol. Inner code error correction is performed according to the LDPC code parity check matrix corresponding to the coding rate of 116/120, which is the coding rate information for the fifth bit obtained from the rate discriminating unit 25, and the LDPC decoding result is used as an input. Outer code error correction is executed according to the BCH (65535, 65343) shortened code generation polynomial of the first embodiment, and the decoded result of the 5th bit is sent to the parallel/serial converter 24 .

The 6th bit log-likelihood ratio calculator 22-6 calculates first, second, and second Similar to the 3rd, 4th and 5th bits, the logarithmic likelihood ratio is calculated and sent to the 6th bit error correction decoding section 23-6.

The 6th bit error correction decoding unit 23-6 uses the log-likelihood ratio of the 6th bit by the 6th bit log-likelihood ratio calculation unit 22-6 to encode the 6th bit constituting the symbol. Outer code error correction according to, for example, the BCH (65535, 65343) shortened code generation polynomial of Embodiment 1, which corresponds to the coding rate 120/120, which is the coding rate information for the fifth bit obtained from the rate discriminating unit 25 is executed, and the decoded result of the 6th bit is sent to the parallel/serial conversion unit 24 .

In this way, the first to sixth bit log-likelihood ratio calculation units 22-1 to 22-6 and the first to sixth bit error correction decoding units 23-1 to 23-6 are obtained by the set partitioning method. Sequential decoding is performed using the decoding result obtained for each bit and the logarithmic likelihood ratio based on the correspondence between symbols and signal points. Therefore, the 1st to 6th bit log-likelihood ratio calculators 22-1 to 22-6 and the 1st to 6th bit error correction decoders 23-1 to 23-6 perform the above-described set partitioning to obtain signal points. It functions as decoding means for decoding each symbol-constituting bit based on the correspondence relationship between the symbol-assigned signal point and the symbol.

The parallel/serial conversion unit 24 parallel/serial converts the decoded result of the data series corresponding to the bits constituting the symbols obtained from the first to sixth bit error correction decoding units 23-1 to 23-6, and converts the result into 1 bit. Sends out the received data sequence of

The coding rate discriminating unit 25 notifies the receiving device 20 of information such as the function of multiplexing the synchronization signal with the modulated wave signal to identify the head of the error correction code obtained from the orthogonal demodulation unit 21 and the setting of the transmission method. A transmission multiplexing control signal is input to determine the coding rate information for the 1st to 6th bits used in the 1st to 6th bit error correction decoding units 23-1 to 23-6 from the transmission multiplexing control signal. and sent to the 1st to 6th bit error correction decoders 23-1 to 23-6, respectively.

(64APSK signal point arrangement and bit allocation)
Here, the 64APSK signal point arrangement and bit allocation in the mapping unit 14 will be described in detail. As described above as a problem to be solved, in the satellite transmission system, by designing the signal point arrangement in consideration of the non-linear distortion caused by the satellite repeater and the adaptive equalization performance of the receiving device, The transmission performance can be improved more than when the optimized constellation is applied under white noise.

Therefore, in order to improve the performance of the 64APSK coded modulation in the satellite transmission system, we decided to study the design of the signal point arrangement in consideration of the nonlinear distortion and the adaptive equalization performance of the receiver. FIG. 11(a) shows reception signal points and transmission signal points shown in Non-Patent Document 9 when the non-linear transmission path is passed. This received signal point is subjected to adaptive equalization processing after being affected by nonlinear distortion. Here, when the four concentric circles are defined as 1st, 2nd, 3rd, and 4th circles in ascending order of radius, focusing on the received signal points of the 2nd and 3rd circles, the transmission A large number of received signal points that are out of the vicinity of the signal points are confirmed. It can be seen that the signal points of the second and third circles are affected by the equalization error, deteriorating the MER, which is one of the indices for evaluating the reception performance. Therefore, in the second embodiment according to the present invention, as shown in FIG. designed. As described above, it is possible to improve the performance of a nonlinear transmission path by applying a signal point arrangement that considers nonlinear distortion and the adaptive equalization performance of a receiving apparatus.

As described above, the transmission path capacity T (equation (1) and equation (2)), which is the Shannon limit that limits the modulation scheme as a design criterion for the phase and radius ratios, and MER, and the downlink to the output signal of the satellite repeater Equation (3) using the required C/N (required C/Nsat) that takes into account the white noise received in the receiver and the required C/N (required C/Nall) of the entire satellite transmission path that is finally input to the receiver is use.

For each signal point arrangement pattern, the required C/Nsat is calculated by equation (3), and the signal point arrangement that minimizes the required C/Nsat is set as the signal point arrangement that can improve the transmission performance in the linear transmission line. . The required C/Nall is the transmission line capacity of each signal point constellation pattern based on the achievable transmission line capacity Ts=5.0839 bps/Hz of the signal point constellation that maximizes the transmission line capacity T when C/N=16 dB. Td was converted to required C/Nall (required C/Nall=16×Ts/Td), and the value after adaptive equalization was used for MER.

From the above, considering the nonlinear distortion, the performance of the adaptive equalizer, and the transmission line capacity of the signal point constellation, the value of the phase of the signal point constellation and the radius ratio between the circumferences that improve the transmission performance in the nonlinear transmission line designed.

More specifically, in the 64APSK signal point arrangement design of the present invention, the number of signal points to be arranged on the circle is designed in consideration of nonlinear distortion and the adaptive equalization performance of the receiving apparatus, and the phase and radius ratio are was designed so that the number of signal points M=64, design C/N=16 dB, and the transmission line capacity calculated by the equation (1) was maximized. The design C/N was C/N=16 dB with a gap of about 1 dB as the performance target for the theoretical limit C/N=14.9 dB of 64APSK (LDPC coding rate 4/5).

The design parameters are, as shown in FIG. Phase (first phase θ ₀ 1 to θ ₀ 4 and phase interval θ 1 to θ 4 in each circle counterclockwise with respect to the reference phase of 0 degrees on the I axis), (c) the circumference of the first circle to the fourth circle The radius ratios (γ1 to γ3) were used to determine each design parameter so as to maximize the transmission line capacity. The radii of the first to fourth circles are r1 to r4, respectively, and the radius ratios are defined as γ1=r2/r1, γ2=r3/r1, and γ3=r4/r1 with r1 as a reference.

Table 15 shows the designed signal point constellation of 64APSK. Table 15 shows the signal point coordinates of the IQ signal normalized with a transmission power of 1 generated by this design. Also, each design parameter and transmission line capacity optimized for the signal point arrangement in Table 15 are shown in Table 16 so that they can be compared with DVB-S2X.

Next, bit allocation to the above 64APSK signal point constellation is also optimized. Multi-level coded modulation to which the set partitioning method is applied, which is conventional technology, divides the signal points according to the decoding result of the previous bit based on the set partitioning method, and demodulates each bit. For example, for the demodulation of the second bit (a2), the result of demodulation of the first bit (a1) is divided into signal points a1=0 and a1=1, respectively, and then demodulated. Signal points are divided and demodulated. As the signal points are divided in this manner, the minimum Euclidean distance between signal points can be increased, and the BER characteristic of each bit is It is possible to improve the transmission characteristics as a whole.

In order to apply the set partitioning method in this way, it is necessary to allocate bits to each signal point so that the minimum Euclidean distance of the signal points after partitioning becomes as large as possible. In QAM, where the signal points are arranged in a lattice, it is possible to allocate bits to expand the minimum Euclidean distance between geometrically adjacent signal points. It is geometrically difficult to extend the minimum Euclidean distance for such a modulation scheme.

Therefore, in the 64APSK mapping according to the second embodiment of the present invention, bits are assigned to each signal point based on the transmission line capacity T (equation (1)) as in the first embodiment. As described above, maximizing the transmission line capacity is equivalent to increasing the minimum Euclidean distance. Therefore, by performing bit allocation that maximizes the transmission line capacity after signal point division, it is possible to extend the minimum Euclidean distance after signal point division when the set division method is applied to 64APSK.

Specifically, the transmission line capacity formula (1) is applied as an evaluation function when bit allocation is performed on the 64APSK signal point arrangement based on the set division method, and the transmission line capacity after signal division at C/N = 16 dB is the maximum bit allocation. As a result of allocating the 1st to 6th bits to the signal points based on the transmission channel capacity, the results shown in FIG. 16 are obtained. In FIG. 16, the 6 bits assigned to the signal points are defined as the 1st bit (a1), the 2nd bit (a2), . is written in Also, FIG. 17 shows the BER characteristics before error correction for each bit, which corresponds to the output of the quadrature demodulator 21 on the receiving device 20 side.

However, in order to apply a concatenated code consisting of an LDPC code (inner code) and a BCH code (outer code) for each bit as a 64APSK error correction code based on the set partitioning method, the current standard (ISDB-S3: non-patent document The LDPC code adopted in 5) can be designed to keep the randomness of the code in the range of BER before error correction from 1.5×10 ⁻¹ to 2.0×10 ⁻³ . Also, when BCH (65535, 65167, t = 23) code is applied as the outer code, the BER before error correction can be expected to be pseudo-error-free (1 × 10 ^-11 ) is 1.2 × 10 ^-4 or less. . Here, focusing on C/N=16 dB in FIG. 17, the BER of the first bit is 1.97×10 ⁻¹ , which is outside the LDPC code design range.

Therefore, by performing bit replacement from the bit allocation in FIG. 16, bit allocation was performed such that the BER of the 1st to 6th bits is within the LDPC code application range or error correction is possible only with the BCH code. FIG. 18 shows the bit allocation result at that time, and FIG. 19 shows the BER characteristic before error correction for each bit. FIG. 20 shows the division result of the set division method for the 1st to 6th bits after this bit permutation. For the sake of simplicity, FIG. 20 shows cases where a1=0, a2=0, a3=0, a4=0, and a5=0, and other division results are omitted.

That is, the mapping unit 14 of the second embodiment performs mapping as shown in Table 17 as bit allocation of each bit constituting a symbol for the 64APSK signal point arrangement shown in FIG.

(Code parameters of LDPC codes of Examples 1 to 3)
Here, from the BER characteristics of FIG. 19, the BER of the sixth bit (a6) at C/N=16 dB is 1.07×10 ⁻⁶ , and error-free can be achieved only with the BCH outer code. Finally, in the present invention, the LDPC coding rate applied to the first bit (a1) to the fifth bit (a5) is adjusted while satisfying the overall average coding rate of 4/5 of the LDPC code, and white noise is reduced. We designed an LDPC code that minimizes the required C/N (defined as C/N corresponding to BER=1×10 ⁻¹¹ ) below.

At this time, the structure of the LDPC parity check matrix was the same as ISDB-S3. That is, the error correction coding unit 12 is configured to include an encoder for LDPC-encoding the digital data using a parity check matrix unique to each coding rate. 1 element of the submatrix corresponding to the information length according to the coding rate is arranged in the column direction at intervals of every 374 columns, using the parity check matrix initial value table predetermined for each coding rate as the initial value. LDPC encoding is performed using the parity check matrix configured as above.

As the specifications of the designed LDPC code, the coding rate for each bit shown in Table 18 satisfies the average coding rate of 4/5 of the entire LDPC code, and Examples 1 to 3 shown in FIGS. slot configuration. Also, the initial value table of the parity check matrix in the LDPC code for each bit shown in Table 18 is as shown in Tables 6 to 10 described above.

In addition, in the slot configuration of the first embodiment shown in FIG. 21, it is assumed that the slot header area is used to accommodate variable-length packets such as TLV packets configured in units of bytes. In the slot configuration of , when looking at each code sequence that constitutes the slot, the information bits are not configured in units of bytes, making it difficult to write the byte information indicating the breaks of the variable-length packets into the slot header area. It is expected that.

Therefore, as in the second embodiment shown in FIG. 22, by using a slot configuration in which information bits are configured in byte units for each bit code sequence, information indicating breaks in variable-length packets configured in byte units can be obtained. to the slot header area.

In addition, in order to apply a BCH code with a higher correction capability as an outer code, a slot with a code length of 44880 bits is converted to a slot of Example 3 as shown in FIG. can be configured.

That is, in the slot configuration of the first embodiment shown in FIG. 21, a slot header of 176 bits and stuff bits of 6 bits are provided, like the slot configuration of the conventional advanced satellite broadcasting system. However, in the target required C/N, if the bit error of the 6th bit (a6) among the bits constituting the symbol is large enough to be corrected only by the BCH (65535, 65343) shortened code Furthermore, it is desirable to enhance the correction capability without changing the code length of 44880 bits. Also, by applying the BCH (65535, 65167) shortening code to each bit from the 1st bit to the 5th bit, it is possible to reduce the influence of error propagation when decoding sequentially from the 1st bit.

Therefore, as shown in FIG. 23, in the slot configuration of the third embodiment, the slot header area is deleted, the deleted 176 bits are assigned to the parity of the BCH code, and the BCH (65535, 65343) with a correction capability of 12 bits is shortened. The code is enhanced to a BCH (65535, 65167) shortened code with a correction capability of 23 bits. Even if the slot header is deleted in this way, no problem arises in terms of signal identification by providing the transmission multiplex control signal with information capable of identifying both.

As a result, when the target required C/N is sufficiently high (that is, when the target value is higher than the required C/N determined by the BCH (65535, 65343) shortened code), the slot configuration of the third embodiment (FIG. 23) can be adopted, and therefore, depending on the target required C/N, the slot configuration of Example 1 or 2 (FIGS. 21 and 22) and the slot configuration of Example 3 (FIG. 23 ) can be switched and adopted.

Incidentally, the generator polynomial of the BCH (65535, 65167) shortened code is as disclosed in Patent Document 1. Also, the generator polynomial of the BCH (65535, 65343) shortened code is as disclosed in Non-Patent Document 5.

As an effect of the present invention, transmission performance (simulation results) when using the slot configuration of FIG. 23 in the transmitting device 10 and the receiving device 20 of FIG. 14 will be described. The transmission model assumed white noise, the BCH outer code was a BCH (65535, 65167, t=23) code, and the decoding iteration count of the LDPC code was set to a maximum of 50 per stage.

According to Table 14, FIG. 24 shows C/N vs. BER characteristics obtained by computer simulation in a non-linear transmission line assuming that a 12 GHz band satellite repeater is used in this example. FIG. 24 also plots the simulation results of Non-Patent Document 9 when the same nonlinear transmission model is propagated. The computer simulation was performed up to BER=10 ⁻⁸ order and extrapolated up to BER=1×10 ⁻¹¹ by linear interpolation. The results obtained from FIG. 24 are shown in FIG. From FIG. 25, the required C/N of the technology of the present invention is 17.14 dB in a non-linear transmission path assuming a 12 GHz band satellite repeater, and a performance improvement of 0.38 dB is possible according to Non-Patent Document 9. .

In particular, in the technique of Non-Patent Document 9, as a new 64APSK signal point arrangement, the number of signal points arranged on four concentric circles is optimized from the viewpoint of expanding the Euclidean distance, and each The amplitude values of the signal points are almost matched, and the phase value of each signal point is adjusted. On the other hand, in the new 64APSK signal point arrangement according to the second embodiment of the present invention, as a signal point arrangement in consideration of nonlinear distortion and adaptive equalization performance of the receiving apparatus, the signal points are distributed.

In addition, in the bit allocation by the set partitioning method using the new signal point arrangement of 64APSK according to the present invention, the predetermined signal power to noise The bit error rate can be further reduced by performing bit permutation so as to satisfy the power ratio.

Furthermore, in the error correction code based on the new signal point arrangement of the 64APSK according to the present invention and the bit allocation by the new set partitioning method, the entire slot configuration of 6 slots as a concatenated code by the LDPC code and the BCH code is The average coding rate of the LDPC code of satisfies 4/5, and the LDPC coding rate of each slot in the six slots is defined as shown in Table 18, and the initial value of the parity check matrix of the LDPC code in the set partitioning method By optimizing the table, transmission performance can be further improved.

As a result, in the configuration of the transmitting device 10 and the receiving device 20 of the second embodiment according to the present invention, for example, a performance improvement of 0.38 dB can be achieved over the technique of Non-Patent Document 9 in a nonlinear transmission path via a 12 GHz band satellite repeater. It is possible.

Note that the parity check matrix initial value table used to generate a parity check matrix for each LDPC coding rate according to each embodiment of the present invention is not limited to the use of the above-described set partitioning method, and other set partitioning methods and Gray code mapping It is also effective when applying the LDPC code to the bits forming the symbols related to .

Although the present invention has been described with reference to specific embodiments, the present invention is not limited to the above-described embodiments, and can be modified in various ways without departing from the technical idea thereof. Therefore, the transmitter and receiver according to the invention are not limited to the above-described embodiment examples, but only by the description of the claims.

According to the present invention, for example, a transmission bit rate of 150 Mbps or more when transmitting digital data using 64APSK while satisfying 34.5 MHz, which is a usable bandwidth per satellite transponder in 12 GHz band satellite broadcasting. and improve the performance of coded modulation in the combination of error correction code and multilevel modulation (64APSK), and improve the transmission performance in non-linear transmission paths via, for example, 12 GHz band satellite transponders. is possible, it is useful for any application that utilizes error correcting code and multilevel modulation (64APSK).

10 Transmitter 11 Serial/Parallel Converter 12 Error Correction Encoder 12-1 First Error Correction Encoder 12-2 Second Error Correction Encoder 12-3 Third Error Correction Encoder 12-4 Fourth Error correction coding section 12-5 Fifth error correction coding section 12-6 Sixth error correction coding section 13 Coding rate setting section 14 Mapping section 15 Quadrature modulation section 16 Coding rate determination signal multiplexing section 20 Receiver 21 Orthogonal demodulator 22-1 1st bit log-likelihood ratio calculator 22-2 2nd bit log-likelihood ratio calculator 22-3 3rd bit log-likelihood ratio calculator 22-4 4th bit log-likelihood ratio calculator Unit 22-5 5th bit log-likelihood ratio calculation unit 22-6 6th bit log-likelihood ratio calculation unit 23-1 1st bit error correction decoding unit 23-2 2nd bit error correction decoding unit 23-3 3rd Bit error correction decoding unit 23-4 4th bit error correction decoding unit 23-5 5th bit error correction decoding unit 23-6 6th bit error correction decoding unit 24 Parallel/serial conversion unit 25 Coding rate determination unit 26 Adaptation etc. Kabe

Claims (15)

A transmitting device for transmitting digital data,
error correction coding means for applying a concatenated code composed of a BCH code partially including an LDPC code to the digital data to generate a symbol having an overall average coding rate of 4/5;
Define four concentric circles as the 1st, 2nd, 3rd, and 4th circles in ascending order of radius as the signal point arrangement in the 64APSK modulation system for the symbols encoded by the error correction encoding means. 12 signal points on the first circle, 16 signal points on the second circle, 16 signal points on the third circle, and 20 signal points on the fourth circle. mapping means for mapping the IQ signal of the modulus;
a quadrature modulation means for modulating the symbols mapped by the mapping means using a 64APSK modulation method and transmitting a modulated wave signal to a receiving device that performs adaptive equalization processing via a nonlinear transmission path;
The mapping means sets the phase angles in the signal point constellation for the first circle at intervals of 30 degrees from a position 22 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis, and for the second circle on the I axis. 22.5 degrees from the position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees of the I axis, and the third circle is 22 degrees from the position of 11.45 degrees counterclockwise from the reference phase of 0 degrees of the I axis. .5 degree intervals, and the fourth circle is set at 18 degree intervals from a position 11.3 degrees counterclockwise with respect to the reference phase of 0 degree of the I axis, and the radius ratio in the signal point arrangement is the first circle, The radii of the second, third, and fourth circles are defined as r1, r2, r3, and r4, respectively, and the ratios of the radii to r1 are γ1=r2/r1, γ2=r3/r1, and γ3=r4. /r1, in order to reduce the influence of nonlinear distortion that occurs in a nonlinear transmission path , set division is performed for the signal point arrangement with γ1 = 2.02, γ2 = 2.98, and γ3 = 4.14. Based on the method, bit allocation is performed so that the transmission line capacity after signal division is maximized in a predetermined calculation method and a predetermined signal power to noise power ratio, and then the BER of each bit of 64 APSK symbols is LDPC. Mapping the IQ signal by allocating the bits constituting the symbol according to the bit allocation in which the bits are exchanged so that the error can be corrected within the code application range or only with the BCH code ,
The LDPC code is 57/120 for the first bit, which is the most significant bit, 64/120 for the second bit, and 105/120, 117/120 for the 4th bit, 120/120 (no LDPC parity) for the 5th bit, and 113/120 for the 6th bit which is the least significant bit. . Bit assignment of each bit constituting the symbol for the signal constellation,
For the first circle, "001100 (14 in octal notation)" is placed at a position of 22 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"011100 (34 in octal notation)" at the position of 52 degrees,
"101100 (54 in octal notation)" at the position of 82 degrees,
"111100 (74 in octal notation)" at the position of 112 degrees,
"000101 (05 in octal notation)" at the position of 142 degrees,
"010100 (24 in octal notation)" at the position of 172 degrees,
"100101 (45 in octal notation)" at the position of 202 degrees,
"110101 (65 in octal notation)" at the position of 232 degrees,
"001101 (15 in octal notation)" at the position of 262 degrees,
"011001 (31 in octal notation)" at the position of 292 degrees,
"101001 (51 in octal notation)" at the position of 322 degrees,
"111001 (71 in octal notation)" at the position of 352 degrees,
For the second circle, "111000 (70 in octal notation)" is placed at a position of 22.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"000001 (01 in octal notation)" at the position of 45.05 degrees,
"010000 (20 in octal notation)" at the position of 67.55 degrees,
"100001 (41 in octal notation)" at the position of 90.05 degrees,
"110001 (61 in octal notation)" at the position of 112.55 degrees,
"001001 (11 in octal notation)" at the position of 135.05 degrees,
"011101 (35 in octal notation)" at the position of 157.55 degrees,
"101101 (55 in octal notation)" at the position of 180.05 degrees,
"111101 (75 in octal notation)" at the position of 202.55 degrees,
"000000 (00 in octal notation)" at the position of 225.05 degrees,
"010001 (21 in octal notation)" at the position of 247.55 degrees,
"100000 (40 in octal notation)" at the position of 270.05 degrees,
"110000 (60 in octal notation)" at the position of 292.55 degrees,
"001000 (10 in octal notation)" at the position of 315.05 degrees,
"011000 (30 in octal notation)" at the position of 337.55 degrees,
"101000 (50 in octal notation)" at the position of 360.05 degrees,
For the third circle, "001111 (17 in octal notation)" is placed at a position of 11.45 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"011111 (37 in octal notation)" at the position of 33.95 degrees,
"101111 (57 in octal notation)" at the position of 56.45 degrees,
"111111 (77 in octal notation)" at the position of 78.95 degrees,
"000100 (04 in octal notation)" at the position of 101.45 degrees,
"010101 (25 in octal notation)" at the position of 123.95 degrees,
"100100 (44 in octal notation)" at the position of 146.45 degrees,
"110100 (64 in octal notation)" at the position of 168.95 degrees,
"001110 (16 in octal notation)" at the position of 191.45 degrees,
"011110 (36 in octal notation)" at the position of 213.95 degrees,
"101110 (56 in octal notation)" at the position of 236.45 degrees,
"111110 (76 in octal notation)" at the position of 258.95 degrees,
"000111 (07 in octal notation)" at the position of 281.45 degrees,
"010110 (26 in octal notation)" at the position of 303.95 degrees,
"100111 (47 in octal notation)" at the position of 326.45 degrees,
"110111 (67 in octal notation)" at the position of 348.95 degrees,
For the fourth circle, "000010 (02 in octal notation)" is placed at a position of 11.3 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"010011 (23 in octal notation)" at the position of 29.3 degrees,
"100010 (42 in octal notation)" at the position of 47.3 degrees,
"110010 (62 in octal notation)" at the position of 65.3 degrees,
"001010 (12 in octal notation)" at the position of 83.3 degrees,
"011010 (32 in octal notation)" at the position of 101.3 degrees,
"101010 (52 in octal notation)" at the position of 119.3 degrees,
"111010 (72 in octal notation)" at the position of 137.3 degrees,
"000011 (03 in octal notation)" at the position of 155.3 degrees,
"010010 (22 in octal notation)" at the position of 173.3 degrees,
"100011 (43 in octal notation)" at the position of 191.3 degrees,
"110011 (63 in octal notation)" at the position of 209.3 degrees,
"001011 (13 in octal notation)" at the position of 227.3 degrees,
"011011 (33 in octal notation)" at the position of 245.3 degrees,
"101011 (53 in octal notation)" at the position of 263.3 degrees,
"111011 (73 in octal notation)" at the position of 281.3 degrees,
"000110 (06 in octal notation)" at the position of 299.3 degrees,
"010111 (27 in octal notation)" at the position of 317.3 degrees,
"100110 (46 in octal notation)" at the position of 335.3 degrees,
"110110 (66 in octal notation)" at the position of 353.3 degrees,
2. The transmitting device according to claim 1, characterized in that it is configured such that: A transmitting device for transmitting digital data,
error correction coding means for applying a concatenated code composed of a BCH code partially including an LDPC code to the digital data to generate a symbol having an overall average coding rate of 4/5;
Define four concentric circles as the 1st, 2nd, 3rd, and 4th circles in ascending order of radius as the signal point arrangement in the 64APSK modulation system for the symbols encoded by the error correction encoding means. 8 signal points on the first circle, 16 signal points on the second circle, 20 signal points on the third circle, and 20 signal points on the fourth circle. mapping means for mapping the IQ signal of the modulus;
a quadrature modulation means for modulating the symbols mapped by the mapping means using a 64APSK modulation method and transmitting a modulated wave signal to a receiving device that performs adaptive equalization processing via a nonlinear transmission path;
The mapping means sets the phase angles in the signal point constellation for the first circle at intervals of 45 degrees from a position of 58.4 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis, and for the second circle 22.5 degree intervals from the position of 14.55 degrees counterclockwise with respect to the I-axis reference phase of 0 degrees, and the third circle is 18 degrees from the position of 18 degrees counterclockwise with respect to the I-axis reference phase of 0 degrees. The fourth circle is set at intervals of 18 degrees from the position 9 degrees counterclockwise with respect to the reference phase of 0 degrees of the I-axis. The radii of the third circle and the fourth circle are defined as r1, r2, r3, and r4, respectively, and the radius ratio to r1 is defined as γ1=r2/r1, γ2=r3/r1, and γ3=r4/r1. Then, in order to reduce the influence of nonlinear distortion that occurs in the nonlinear transmission path, first, based on the set partitioning method, for the signal point arrangement with γ1 = 2.10, γ2 = 3.16, and γ3 = 4.49. , bit allocation is performed so that the transmission path capacity after signal division is maximized in a predetermined calculation method and a predetermined signal power to noise power ratio. Or mapping the IQ signal by allocating the bits that make up the symbol according to the bit allocation in which the bits are exchanged so that the error can be corrected only with the BCH code ,
The LDPC code is 61/120 for the first bit, which is the most significant bit, 63/120 for the second bit, and 101/120, 115/120 for the 4th bit, 116/120 for the 5th bit, and 120/120 (no LDPC parity) for the 6th bit, which is the least significant bit. A transmitting device characterized by: Bit assignment of each bit constituting the symbol for the signal constellation,
Regarding the first circle, "101000 (50 in octal notation)" is placed at a position of 58.4 degrees counterclockwise with respect to the reference phase of 0 degree of the I axis,
"111010 (72 in octal notation)" at the position of 103.4 degrees,
"000010 (02 in octal notation)" at the position of 148.4 degrees,
"010010 (22 in octal notation)" at the position of 193.4 degrees,
"100010 (42 in octal notation)" at the position of 238.4 degrees,
"111100 (74 in octal notation)" at the position of 283.4 degrees,
"001000 (10 in octal notation)" at the position of 328.4 degrees,
"011100 (34 in octal notation)" at the position of 373.4 degrees,
For the second circle, "100100 (44 in octal notation)" is placed at a position of 14.55 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"010100 (24 in octal notation)" at the position of 37.05 degrees,
"000110 (06 in octal notation)" at the position of 59.55 degrees,
"110110 (66 in octal notation)" at the position of 82.05 degrees,
"101110 (56 in octal notation)" at the position of 104.55 degrees,
"011110 (36 in octal notation)" at the position of 127.05 degrees,
"001100 (14 in octal notation)" at the position of 149.55 degrees,
"111000 (70 in octal notation)" at the position of 172.05 degrees,
"101100 (54 in octal notation)" at the position of 194.55 degrees,
"011000 (30 in octal notation)" at the position of 217.05 degrees,
"001110 (16 in octal notation)" at the position of 239.55 degrees,
"111110 (76 in octal notation)" at the position of 262.05 degrees,
"100110 (46 in octal notation)" at the position of 284.55 degrees,
"010110 (26 in octal notation)" at the position of 307.05 degrees,
"000000 (00 in octal notation)" at the position of 329.55 degrees,
"110000 (60 in octal notation)" at the position of 352.05 degrees,
For the third circle, "101010 (52 in octal notation)" is placed at a position of 18 degrees counterclockwise with respect to the reference phase of 0 degree of the I axis,
"110010 (62 in octal notation)" at the position of 36 degrees,
"001111 (17 in octal notation)" at the position of 54 degrees,
"011010 (32 in octal notation)" at the position of 72 degrees,
"101101 (55 in octal notation)" at the position of 90 degrees,
"111101 (75 in octal notation)" at the position of 108 degrees,
"000100 (04 in octal notation)" at the position of 126 degrees,
"010000 (20 in octal notation)" at the position of 144 degrees,
"100111 (47 in octal notation)" at the position of 162 degrees,
"111111 (77 in octal notation)" at the position of 180 degrees,
"000111 (07 in octal notation)" at the position of 198 degrees,
"010111 (27 in octal notation)" at the position of 216 degrees,
"100000 (40 in octal notation)" at the position of 234 degrees,
"110100 (64 in octal notation)" at the position of 252 degrees,
"001101 (15 in octal notation)" at the position of 270 degrees,
"011101 (35 in octal notation)" at the position of 288 degrees,
"101111 (57 in octal notation)" at the position of 306 degrees,
"110111 (67 in octal notation)" at the position of 324 degrees,
"001010 (12 in octal notation)" at the position of 342 degrees,
"011111 (37 in octal notation)" at the position of 360 degrees,
For the fourth circle, "000001 (01 in octal notation)" is placed at a position of 9 degrees counterclockwise with respect to the reference phase of 0 degrees on the I axis,
"010001 (21 in octal notation)" at the position of 27 degrees,
"100001 (41 in octal notation)" at the position of 45 degrees,
"110001 (61 in octal notation)" at the position of 63 degrees,
"000011 (03 in octal notation)" at the position of 81 degrees,
"010011 (23 in octal notation)" at the position of 99 degrees,
"100011 (43 in octal notation)" at the position of 117 degrees,
"110011 (63 in octal notation)" at the position of 135 degrees,
"001001 (11 in octal notation)" at the position of 153 degrees,
"011001 (31 in octal notation)" at the position of 171 degrees,
"101001 (51 in octal notation)" at the position of 189 degrees,
"111001 (71 in octal notation)" at the position of 207 degrees,
"001011 (13 in octal notation)" at the position of 225 degrees,
"011011 (33 in octal notation)" at the position of 243 degrees,
"101011 (53 in octal notation)" at the position of 261 degrees,
"111011 (73 in octal notation)" at the position of 279 degrees,
"000101 (05 in octal notation)" at the position of 297 degrees,
"010101 (25 in octal notation)" at the position of 315 degrees,
"100101 (45 in octal notation)" at the position of 333 degrees,
"110101 (65 in octal notation)" at the position of 351 degrees,
4. The transmitting device according to claim 3, characterized in that it is configured such that: receiving a modulated wave signal based on the 64APSK IQ signal transmitted from the transmitting device according to any one of claims 1 to 4 via a nonlinear transmission path, and receiving the 64APSK signal point arrangement for the modulated wave signal; Quadrature demodulation means for performing quadrature demodulation processing corresponding to to generate a demodulated signal;
adaptive equalization means for outputting a received signal point sequence in which distortion caused by the nonlinear transmission path is compensated by performing adaptive equalization processing on the demodulated signal;
Symbol configuration bits composed of a plurality of code sequences that can be divided into 6 bits constituting the 64APSK are obtained from the received signal point sequence, and LDPC decoding processing is performed using the coding rate of the LDPC code determined for each bit. and decoding means for performing BCH decoding processing,
The coding rate of the LDPC code determined for each bit is according to the required correction capability of the symbol divided by the set partitioning method in bit order from the most significant bit to the least significant bit of the symbol constituent bits. and configured so that the overall average coding rate of the LDPC code determined for each bit is 4/5,
When the decoding means LDPC-decodes each bit constituting the symbol, the correction capability for each bit is in the order of the 1st bit, the 2nd bit, the 3rd bit, the 4th bit, the 5th bit, and the 6th bit. A receiver, characterized in that it performs an LDPC decoding process using a parity check matrix used for an LDPC code according to a. 5. An LDPC code for each bit of the symbol configuration bits for 64APSK with the average coding rate of 4/5, provided in the error correction coding means in the transmitting apparatus according to any one of claims 1 to 4. An LDPC encoder that LDPC-encodes digital data using a parity check matrix unique to each coding rate in encoding,
A parity check matrix initial value table predetermined for each coding rate with a code length consisting of 44880 bits is used as an initial value. With respect to the coding rate, it is characterized by having means for performing LDPC coding using a parity check matrix configured by arranging 1 elements of a submatrix corresponding to the information length in the column direction at intervals of every 374 columns. LDPC encoder. The parity check matrix initial value table with the coding rate of 57/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 1 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 64/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 1 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 105/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 1 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 113/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 1 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 61/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 3 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 63/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 3 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 101/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 3 , characterized in that it consists of: The parity check matrix initial value table with the coding rate of 115/120 is

7. An LDPC encoder as claimed in claim 6, when citing claim 3 , characterized in that it consists of: For the digital data to which the parity of the LDPC code is added by the LDPC encoder according to any one of claims 6 to 14, individually for each bit of the symbol configuration bits for 64APSK in the set partitioning method An LDPC decoder for decoding based on the set coding rate of the LDPC code and the parity check matrix.

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