JP7131451B2 - PHASE MODULATION DEVICE AND PHASE MODULATION METHOD - Google Patents

Description

The present invention relates to a phase modulation device and a phase modulation method.

Conventionally, a phase modulation device using LCOS (Liquid Crystal On Silicon) has been proposed as disclosed in Patent Document 1, for example. Paragraph [0015] of Patent Document 1 and the like disclose controlling the voltage applied to each pixel of the LCOS element to phase-modulate the incident light.

JP 2014-56004 A

Devices that handle infrared light must sufficiently modulate long-wavelength light. Therefore, as a means to secure a high modulation factor, it is basically possible to use a liquid crystal material having a high refractive index anisotropy. For example, the applied voltage of is increased. The method of increasing the thickness of the liquid crystal layer has the disadvantage that the orientation of the liquid crystal tends to be disturbed.

On the other hand, in the technique disclosed in the above-mentioned Patent Document 1, since the voltage supplied to each pixel from the drive circuit is limited, the amount of modulation when modulating the phase cannot be increased. If the voltage output from the drive circuit is increased, it is necessary to increase the withstand voltage of the circuit elements, which causes a problem of increased power consumption.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such conventional problems. An object of the present invention is to provide a phase modulation device and a phase modulation method capable of securing a sufficient phase modulation amount even for infrared light by increasing the voltage applied to the liquid crystal without increasing the voltage.

In order to achieve the above object, a phase modulation device according to the present invention is a phase modulation device for reflecting incident light at a desired angle, wherein a plurality of column data lines and a plurality of row scanning lines orthogonal to each other intersect each other. a plurality of pixel circuits and a plurality of reflective pixels provided at positions corresponding to the reflective pixels; wherein the column data line outputs a control voltage to the pixel circuit that varies up to a predetermined maximum voltage, the pixel circuit having a charge pump that adds the maximum voltage to the control voltage; , when the drive voltage supplied to the liquid crystal is equal to or less than the maximum voltage, the control voltage is output to the liquid crystal without being amplified; and when the drive voltage supplied to the liquid crystal exceeds the maximum voltage, is characterized by comprising a charge pump control unit for controlling the charge pump to add the maximum voltage to the control voltage and output the result to the liquid crystal.

A phase modulation method according to the present invention is a phase modulation method for reflecting incident light at a desired angle. a step of outputting a control voltage that varies within a range up to a predetermined maximum voltage to the pixel circuit of (1); outputting the control voltage to the liquid crystal without amplifying it when the driving voltage supplied to the liquid crystal is less than or equal to the maximum voltage; and when the driving voltage supplied to the liquid crystal exceeds the maximum voltage, and outputting a voltage obtained by adding the maximum voltage to the control voltage by a charge pump to the liquid crystal.

According to the present invention, it is possible to set a large amount of phase modulation of reflected light without increasing the control voltage supplied from the column data line to the pixel circuit. As a result, it is possible to suppress the thickening of the liquid crystal layer for securing the phase modulation amount and the disturbance of the liquid crystal alignment due to the thickening of the liquid crystal layer.

FIG. 1 is a plan view showing the configuration of a phase modulation device according to an embodiment of the invention. FIG. 2 is a side sectional view showing the configuration of the phase modulation device according to the embodiment of the present invention. FIG. 3 is a circuit diagram of a phase modulation device according to an embodiment of the invention. FIG. 4 is a circuit diagram showing the configuration of each pixel circuit provided in the phase modulation device according to the embodiment of the invention. FIG. 5 is an explanatory diagram showing the direction of reflected light reflected by the pixel circuit, where sa1 indicates the case when the charge pump is off and sb1 indicates the case when the charge pump is on. FIG. 6(a) shows pixel circuits arranged in a matrix, and FIG. 6(b) is a graph showing drive voltages supplied from each pixel circuit to the liquid crystal. FIG. 7A is a graph showing the relationship between the gradation set in the liquid crystal and the control voltage supplied to the pixel circuit. FIG. 7B is a graph showing the relationship between the gradation set to the liquid crystal and the driving voltage supplied to the liquid crystal. FIG. 8 is a timing chart showing operations of transistors Q1, Q2, Q3 and switches S1 to S4 provided in each pixel circuit of the phase modulation device according to the embodiment of the present invention. FIG. 9 is an explanatory diagram showing a modification of the pixel circuit provided in the phase modulation circuit according to this embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a phase modulation device according to an embodiment of the present invention, and FIG. 2 is a side cross-sectional view. As shown in FIGS. 1 and 2, a phase modulation device 101 according to this embodiment has an LCOS panel structure including a reflective substrate 11, a liquid crystal layer 12, and a counter substrate 13. FIG. Then, the light incident from the counter substrate 13 side (the direction of the arrow Y1 in FIG. 2) is reflected and separated into a plurality of reflected lights having different phases. In the following, the surfaces of the reflecting substrate 11 and the opposing substrate 13 on which light is incident are referred to as "light incident surfaces".

A plurality of reflective pixels made of a metal that reflects light (for example, aluminum) is provided on the light incident surface of the reflective substrate 11, and a pixel circuit is provided for each reflective pixel. A plurality of pixel circuits 21 are arranged in the horizontal direction and the vertical direction, respectively, as will be described later with reference to FIG. Each pixel circuit 21 operates under the control of the control circuit 22 .

The opposing substrate 13 is arranged parallel to the light incident surface side of the reflecting substrate 11 at a constant interval, and is made of a transparent member (for example, a transparent glass material). That is, the counter substrate 13 has a function as a transparent substrate. Furthermore, the counter substrate 13 is provided with a transparent electrode. Therefore, the light incident from the light incident surface side of the opposing substrate 13 passes through the transparent member and the transparent electrode and enters the liquid crystal layer 12 and the reflective substrate 11 .

The liquid crystal layer 12 is arranged in a space sandwiched between the reflective substrate 11 and the opposing substrate 13, and the periphery thereof is sealed with a sealing material 14. As shown in FIG. Also, for convenience of the following description, the liquid crystal layer 12 is considered to be liquid crystal 42 (see FIG. 4 described later) divided on each reflective pixel (that is, each pixel circuit 21). The liquid crystal 42 includes a pixel electrode having light reflectivity (q1 shown in FIG. 4 to be described later, i.e., reflective pixel) and a common electrode (q2 shown in FIG. 4 to be described later, i.e., transparent electrode ) and are filled and sealed. A voltage output from the pixel circuit 21 (hereinafter referred to as "driving voltage") is supplied to the pixel electrode q1, and a preset common electrode voltage is supplied to the common electrode q2.

Therefore, the potential difference between the driving voltage applied by each pixel circuit 21 and the common electrode voltage applied to the common electrode q2 changes the refractive index of the liquid crystal 42 on each reflective pixel with respect to the incident light to the individual liquid crystal. By changing every 42 or every predetermined number of groups, the incident light incident from the light incident surface side of the counter substrate 13 can be reflected in a desired direction.
By changing the refractive index of the liquid crystal 42 on a plurality of continuous reflective pixels stepwise from large to small (or from small to large), the speed of the incident light (advance or delay in phase) will change. Because of the difference, the incident light travels in a curved manner, and reflected light with a certain angle can be obtained.

Next, the configuration of each pixel circuit 21 and the control circuit 22 that controls each pixel circuit 21 will be described with reference to the block diagram shown in FIG. 3 and the circuit diagram shown in FIG. 3, the control circuit 22 includes a plurality of pixel circuits 21 (m columns, n rows) arranged in a matrix, a horizontal scanning circuit 23, a vertical scanning circuit 24, and a charge pump control section 25. ing. Then, the control circuit 22 outputs an electric signal to each pixel circuit 21 to drive each pixel circuit 21 and applies a driving voltage to the liquid crystal 42 from each pixel circuit 21 . Therefore, the refractive index for incident light of the liquid crystal 42 on each reflective pixel is controlled to a desired value.

A plurality of pixel circuits 21 (m ×n) are arranged. The plurality of pixel circuits 21 are all configured identically. Further, drive lines (L1 to Ln) and control lines (K1 to Kn) are provided in parallel with the row scanning lines (G1 to Gn). The drive lines (L1-Ln) and the control lines (K1-Kn) are connected to the charge pump controller 25. FIG.

The drive lines (L1 to Ln) are wires for transmitting control signals for switching on and off of the transistor Q2 (short-circuit switch; see FIG. 4) provided in each pixel circuit 21. FIG. Further, the control lines (K1 to Kn) are control signals for switching ON/OFF of the switches S1 to S4 (see FIG. 4) provided in each pixel circuit 21, and for switching ON/OFF of the transistor Q3. This wiring is used to transmit control signals for As shown in FIG. 4, a plurality of control lines (K1-Kn) are provided (three lines K1-1, K1-2, and K1-3 in the figure), but only one line is shown in FIG. is simplified by a control line K1.

The column data lines (D1 to Dm) are wirings for supplying analog voltages (hereinafter referred to as “control voltages”) output from the voltage supply line X1 to the respective pixel circuits 21 .

[Description of Pixel Circuit 21]
The configuration of the pixel circuit 21 will be described below. FIG. 4 is a circuit diagram showing a detailed configuration of the pixel circuit 21. As shown in FIG. Here, the configuration of the pixel circuit 21 (referred to as pixel circuit 21a) arranged at the intersection of the column data line D1 and the row scanning line G1 shown in FIG. 3 will be described. As shown in FIG. 4, the pixel circuit 21a includes transistors Q1, Q2, Q3, a charge pump 31, and an output capacitor C2.

The transistor Q1 is a switching transistor, and is composed of, for example, an N-channel MOSFET (field effect transistor). One terminal (eg, drain) of the transistor Q1 is connected to the column data line D1, and the other terminal (eg, source) is connected to the input terminal p1 of the charge pump 31. FIG. A control terminal (for example, gate) of the transistor Q1 is connected to the row scanning line G1. Therefore, when the row scanning line G1 is selected and the control voltage is input from the column data line D1, this control voltage is supplied to the input terminal p1 of the charge pump 31. FIG.

Similar to the transistor Q1, the transistor Q2 is also a switching transistor, and is composed of, for example, an N-channel MOSFET (field effect transistor). One terminal (eg, drain) of the transistor Q2 is connected to the input terminal p1 of the charge pump 31, and the other terminal (eg, source) is connected to the output terminal p2 of the charge pump 31. FIG.

A control terminal (for example, a gate) is connected to the drive line L1. Therefore, when a voltage of "H" level is supplied to the drive line L1, the transistor Q2 is turned on and the input terminal p1 and the output terminal p2 of the charge pump 31 are short-circuited. That is, the function of the charge pump 31 can be stopped. On the contrary, when drive line L1 is supplied with a voltage of "L" level, transistor Q2 is turned off. Therefore, the input terminal p1 and the output terminal p2 of the charge pump 31 are opened, and the charge pump 31 can be operated.

That is, the transistor Q2 functions as a short-circuit switch for short-circuiting the input terminal p1 for supplying the control voltage to the charge pump 31 and the output terminal p2 for outputting the voltage (driving voltage) from the charge pump 31 to the liquid crystal 42. ing. When the drive voltage for setting the liquid crystal 42 to a desired refractive index is equal to or lower than the maximum voltage VLC supplied from the column data line D1, the charge pump controller 25 (see FIG. 3) controls the transistor. Q2 is shorted. When the drive voltage exceeds the maximum voltage VLC, the transistor Q2 is opened and the charge pump 31 can be driven.

Similar to the transistors Q1 and Q2, the transistor Q3 is also a switching transistor such as a MOSFET. One terminal is connected to the input terminal p1 of the charge pump 31, and the other terminal outputs a voltage Vdd (maximum voltage is VLC). It is connected to a power supply (not shown) that A control terminal (for example, a gate) is connected to the control line K1-3.

The charge pump 31 includes four switches S1 to S4 and a capacitor C1 (first capacitor) for storing charges, amplifies a control voltage supplied to the input terminal p1, and outputs the amplified control voltage to the output terminal p2.

The switch S1 (first switch) and switch S3 (third switch) are connected in series with each other, the end on the switch S1 side is connected to the input terminal p1, and the end on the switch S3 side is connected to the output terminal p2. . Also, the switch S2 (second switch) and the switch S4 (fourth switch) are connected in series with each other, the end on the switch S2 side is connected to the input terminal p1, and the end on the switch S4 side is connected to the ground. .

Furthermore, a capacitor C1 is provided between the connection point of the switches S1 and S3 and the connection point of the switches S2 and S4. The output terminal p2 is connected to the ground via the output capacitor C2 and further connected to the pixel electrode q1 of the liquid crystal 42. FIG. That is, one end of the capacitor C1 is connected to the switches S1 and S3, and the other end of the capacitor C1 is connected to the switches S2 and S4. Further, as described above, the common electrode q2 of the liquid crystal 42 is a transparent electrode provided on transparent glass. A common electrode voltage is applied to the transparent electrode.

The liquid crystal 42 is driven according to the potential difference between the drive voltage applied to the pixel electrode q1 from the pixel circuit 21 and the common electrode applied to the common electrode q2. Therefore, the incident light incident on the liquid crystal 42 is phase-modulated according to the potential difference and reflected.

[Description of Reflected Light by Reflective Substrate]
FIG. 5 is an explanatory diagram schematically showing angles of incident light incident on each reflective pixel 20 provided on the reflective substrate 11 and reflected light reflected by the reflective pixel 20 . In FIG. 5, symbol st indicates incident light incident from a direction orthogonal to the reflective pixel 20 (the light incident surface of the reflective substrate 11) corresponding to each pixel circuit 21, and symbol sa1 indicates the light incident on the reflective pixel 20 at an angle θa. Reflected light is shown, and symbol sb1 indicates reflected light reflected at an angle θb. The same phase plane of the incident light st (a plane normal to the direction of the incident light st) is r1, the phase plane of the reflected light sa1 is ra1, and the same phase plane of the reflected light sb1 is rb1.

As shown in FIG. 5, incident light st is irradiated from a direction substantially orthogonal to the reflective pixel 20, and when incident on the reflective pixel 20, according to the driving voltage applied to the liquid crystal 42 by the pixel circuit 21, The refractive index of the liquid crystal 42 changes. For example, when the maximum driving voltage in the conventional art is voltage Va, the reflection angle of the reflected light sa1 obtained when the voltage is changed stepwise from the minimum voltage Vmin to voltage Va in consecutive pixels is θa. Therefore, when the charge pump 31 is driven, the maximum driving voltage becomes Vb (Vb>Va), and reflected light sb1 reflected at a larger reflection angle θb is obtained.

At this time, although Vmin is applied, the liquid crystal on the pixel has a large refractive index nmax, and the liquid crystal on the pixel to which the maximum voltage Va is applied changes to a small refractive index na. Since the light incident on the liquid crystal with the refractive index na travels faster than the light incident on the liquid crystal with the refractive index nmax, the reflected light is emitted at an angle θa. On the other hand, since the liquid crystal on the pixel to which the voltage Vb is applied has a refractive index nb smaller than na, the incident light travels even faster. Therefore, the reflected light is emitted at a larger angle θb.

Returning to FIG. 3, the horizontal scanning circuit 23 provided in the control circuit 22 includes a shift register circuit 26 and a switch circuit 27 including switches SW1 to SWm.

The shift register circuit 26 inputs a horizontal synchronization signal (HST) and horizontal scanning clock signals (HCK1, HCK2). The shift register circuit 26 sequentially shifts the clock signal based on the horizontal synchronizing signal and the clock signal for horizontal scanning, thereby outputting switching signals (which are referred to as "SD1 to SDm") to the switch circuit 27. It is generated in a cycle of one horizontal scanning period.

The switch circuit 27 includes m switches SW1 to SWm for switching ON/OFF of each column data line (D1 to Dm). The switches SW1 to SWm are controlled to be on or off based on switching signals (SD1 to SDm) output from the shift register circuit . The switches SW1 to SWm are provided corresponding to the column data lines (D1 to Dm), and sequentially input the control voltage "d" corresponding to each column data line.

The switches SW1 to SWm selectively apply control voltages corresponding to the respective column data lines (D1 to Dm) to the column data lines. For example, the switch SW1 is turned on when the switching signal SD1 is at high level, selects a control voltage corresponding to the column data line D1, and outputs the selected control voltage to the column data line D1.

The control voltage "d" supplied from the voltage supply line X1 to each column data line (D1 to Dm) is an analog voltage from "0" (minimum voltage) to "VLC" (maximum voltage). In this embodiment, a double voltage (2*VLC) that is twice the maximum voltage VLC is set, and k gradations ( However, k is an integer of 3 or more). By switching between driving and stopping the charge pump 31, the control voltage (voltage in the range of 0 to VLC) supplied from the column data line is changed to the voltage of the k gradation (voltage in the range of 0 to 2*VLC). voltage).

A detailed description will be given below with reference to FIG. 7A. FIG. 7A is a graph in which the horizontal axis indicates the above-mentioned k gradation (5 gradations in this example), and the vertical axis indicates the control voltage supplied from the voltage supply line X1 to the pixel circuit 21 via the column data line. be.

Graph R1 shown in FIG. 7A shows characteristics when the driving voltage supplied to the liquid crystal 42 is equal to or lower than the maximum voltage VLC, and graph R2 shows characteristics when the driving voltage supplied to the liquid crystal 42 is equal to or higher than the maximum voltage VLC. showing. Although the graphs R1 and R2 show an example in which the voltage changes linearly, the change may be a monotonically increasing change within the range of 0 to VLC.

In FIG. 7A, for example, when the number of gradations of the driving voltage supplied to the liquid crystal 42 is set to "5" (that is, k=5), the double voltage (2*VLC) is equally divided into five gradations. Set tone 1 to tone 5. Therefore, the voltage doubled (2*VLC) is divided into 5 equal parts, the voltage of (1/5)*2*VLC as gradation 1, the voltage of (2/5)*2*VLC as gradation 2, and the gradation A voltage of (3/5)*2*VLC for 3, a voltage of (4/5)*2*VLC for gradation 4, and a voltage of (5/5)*2*VLC for gradation 5 are used as control voltages. It suffices to supply it to the pixel circuit 21 .

However, since the control voltage corresponding to the gradation 3 to gradation 5 exceeds the maximum voltage VLC, the control voltage corresponding to the gradation 3 to 5 is applied to the pixel circuit 21 from the voltage supply line X1 shown in FIG. cannot supply. In this embodiment, for gradations 3 to 5, voltages obtained by subtracting the voltage VLC from the respective control voltages are output, and then the voltage VLC is added by the charge pump 31 . That is, (1/5)*VLC for gradation 3, (3/5)*VLC for gradation 4, and VLC for gradation 5 are output. 31 adds the voltage VLC and outputs it to the liquid crystal 42 .

That is, when the control voltage for obtaining a desired gradation is equal to or lower than the maximum voltage VLC (in the case of gradations 1 and 2), as shown in the graph R1 in FIG. 7A, the control voltage is driven without being amplified. It is output to the liquid crystal 42 as a voltage.

On the other hand, when the voltage for obtaining the desired gradation exceeds the maximum voltage VLC (for gradations 3, 4 and 5), the voltage VLC is subtracted from this voltage as shown in graph R2 in FIG. 7A. A desired drive voltage is obtained by supplying the voltage as a control voltage to the pixel circuit 21 and then adding the voltage VLC in the charge pump 31 . Therefore, the slope of graph R2 is the same as the slope of graph R1.

That is, the charge pump control unit 25 selects a voltage corresponding to an arbitrary gradation among a plurality of gradations set in advance in a range up to a voltage (double voltage in this example) that is higher than the maximum voltage (VLC). When the voltage is less than the maximum voltage (VLC), the control voltage is output to the liquid crystal without being amplified. On the other hand, if the voltage corresponding to an arbitrary gradation out of a plurality of gradations exceeds the maximum voltage (VLC), the voltage obtained by subtracting the maximum voltage (VLC) from the voltage corresponding to this gradation is used as the control voltage. After that, the voltage VLC (maximum voltage) is added by the charge pump 31 and controlled to be output to the liquid crystal 42 .

In this way, by controlling the on/off of each of the switches SW1 to SWm provided in the switch circuit 27 and controlling the driving of the charge pump 31, the pixel circuit 21 has k gradations (5 gradations in the above example). It is possible to generate a drive signal corresponding to the gradation) and supply it to the liquid crystal 42 . That is, as shown in the graph R3 of FIG. 7B, it is possible to output to the liquid crystal 42 drive voltages of gradations 1 to 5 obtained by equally dividing the voltage doubled (2*VLC) into five. .

Returning to FIG. 3, the vertical scanning circuit 24 is connected to row scanning lines (G1 to Gn). The vertical scanning circuit 24 inputs a vertical synchronization signal (VST) and vertical scanning clock signals (VCK1, VCK2). The vertical scanning circuit 24 sequentially supplies row selection signals (scanning signals), for example, from the row scanning line G1 to the row scanning line Gn at a cycle of one horizontal scanning period based on the vertical synchronization signal and the clock signal for vertical scanning. .

The charge pump control unit 25 outputs a drive signal to each drive line (L1 to Ln) shown in FIG. Specifically, when the voltage corresponding to an arbitrary gradation among a plurality of gradations preset in a range up to twice the voltage higher than the maximum voltage (VLC) is equal to or lower than the maximum voltage (VLC), A signal of "H" level is output to the drive line. Further, when the voltage corresponding to an arbitrary grayscale out of a plurality of grayscales exceeds the maximum voltage (VLC), an "L" level signal is output to the drive line.

Further, the charge pump control unit 25 does not drive the charge pump 31 when a signal of "H" level is supplied to the drive line, and does not charge the charge pump 31 when a signal of "L" level is supplied to the drive line. It controls to drive the pump 31 . The operation of the charge pump 31 will be described below.

When driving the charge pump 31, the charge pump control unit 25 outputs control signals for controlling ON/OFF of the switches S1 to S4 shown in FIG. 4 to the control lines K1-1 and K1-2. . Specifically, when the charge pump 31 is driven, the switches S1 and S4 are first turned on and the switches S2 and S3 are turned off when the control voltage is input from the column data line D1.

Therefore, the control voltage is stored on capacitor C1. After a predetermined time has elapsed, the switches S1 and S4 are turned off and the switches S2 and S3 are turned on. At this time, the transistor Q1 is turned off and the transistor Q3 is turned on. As a result, the maximum voltage (VLC) supplied from the transistor Q3 and the voltage stored in the capacitor C1 are added, and the added voltage is stored in the output capacitor C2. Therefore, a voltage obtained by adding the maximum voltage (VLC) to the control voltage supplied from the column data line D1 is accumulated in the output capacitor C2 and output to the pixel electrode q1.

Then, in the phase modulation device 101 according to the present embodiment, blocks made up of some of the (n×m) pixel circuits 21 shown in FIG. 3 are set. For example, as shown in FIG. 6A, a block composed of (5 rows×6 columns) pixel circuits 21 is set. In FIG. 6A, the suffix "-mn" is added to specify the row (n) and column (m) of each pixel circuit 21, respectively. Therefore, the pixel circuit of column 1 and row 1 shown in FIG. 6(a) is 21-11, and the pixel circuit of column 5 and row 6 is 21-56.

In FIG. 6A, the same voltage is supplied to the six pixel circuits 21-11 to 21-16 in the same row. For example, the pixel circuits 21-11 to 21-16 are supplied with a voltage of gradation 1 among gradations 1 to 5. FIG. Also, the gradation is set so that the gradation gradually increases from top to bottom in the horizontal direction, and the voltage of gradation 5 is supplied to the pixel circuits 21-51 to 21-56 in the bottom row. .

Specifically, as shown in FIG. 6B, in each of the pixel circuits 21-11 to 21-51 arranged in the horizontal direction, the voltages supplied to the pixel circuits 21-11 to 21-51 are changed stepwise. voltage is applied. Accordingly, six pixel circuits 21 are grouped into one group, and the reflectance can be changed in five ways, and thus it is possible to obtain reflected light phase-modulated in five ways.

[Explanation of operation of the present embodiment]
Next, the operation of the phase modulation device 101 according to this embodiment configured as described above will be described with reference to the graphs shown in FIGS. 7A and 7B and the timing chart shown in FIG. An example in which the pixel circuits 21 are arranged in a matrix of 5 rows and 6 columns as shown in FIG. 6A will be described below.

The horizontal scanning circuit 23 shown in FIG. 3 controls the ON/OFF of each switch SW1 to SWm (here, m=6) provided in the switch circuit 27 to control the control voltage supplied from the voltage supply line X1. to the desired column data lines.

Furthermore, by driving the vertical scanning circuit 24, the scanning line corresponding to the desired pixel circuit 21 is selected from the scanning lines (G1 to Gn) (here, n=5). As a result, the desired pixel circuit 21 can be supplied with the control voltage.

That is, as described above, the range "0 to 2*VLC" from "0" to double voltage is divided into five gradations, and the pixel circuits 21-11 to 21-11 of the first row shown in FIG. 21-16 is supplied with a gradation 1 voltage "(1/5)*2*VLC", and a gradation 2 voltage "(2/5)*" is supplied to the pixel circuits 21-21 to 21-26 of the second row. 2*VLC".

Furthermore, the voltage of gradation 3 is supplied to the pixel circuits 21-31 to 21-36 of the third row. In this case, the voltage supplied to the pixel circuit is "(3/5)*2*VLC", which exceeds the maximum voltage VLC. is subtracted to output "(1/5)*VLC" as the control voltage.

Likewise, the pixel circuits 21-41 to 21-46 in the fourth row and the pixel circuits 21-51 to 21-56 in the fifth column output voltages obtained by subtracting the voltage VLC as control voltages. After that, the charge pump 31 adds the voltage VLC to generate voltages of gradations 3 to 5. FIG.

Next, the operation of the pixel circuit 21 will be described with reference to the timing chart shown in FIG. As an example, the operation of the charge pump 31 in the pixel circuit 21a connected to the column data line D1 and the row scanning line G1 will be described.

When the pixel circuit 21a is set to the gradation 1 and the gradation 2 described above, the charge pump 31 is not operated. In this case, the charge pump control unit 25 outputs an H level signal to the drive line L1, as shown from time t0 to time t1 in FIG. Furthermore, the switches S1 to S4 are all controlled to be turned off, and the transistor Q3 is controlled to be turned off. Also, the transistor Q1 is turned on. As a result, the transistor Q2 shown in FIG. 4 is turned on, the transistor Q3 is turned off, and the input terminal p1 and the output terminal p2 of the charge pump 31 are short-circuited. It is output to the liquid crystal 42 without being amplified by the pump 31 . Therefore, desired driving voltages can be supplied to the liquid crystal 42 as indicated by symbols z1 and z2 in FIG. 7B.

On the other hand, when the pixel circuit 21 is set to the gradation 3, the voltage "(1/5)" obtained by subtracting the voltage VLC from the voltage "(6/5)*VLC" corresponding to the gradation 3 is applied to the column data line D1. )*VLC” as the control voltage. Further, the charge pump 31 adds the voltage VLC to this control voltage.

Specifically, at time t1 in FIG. 8, the charge pump control unit 25 switches the signal supplied to the drive line L1 from H level to L level. As a result, transistor Q2 is turned off. Further, at time t1, the charge pump control unit 25 sends a control signal to the control line K1 (K1-1, K1-2) to turn on the switches S1 and S4 and turn off the switches S2 and S3 shown in FIG. ).

As a result, the control voltage supplied from the column data line is accumulated in the capacitor C1. After that, at time t2, switches S1, S4 and transistor Q1 are turned off, and at time t3, switches S2, S3 and transistor Q3 are turned on. As a result, a voltage obtained by adding the maximum voltage (VCL) to the control voltage is accumulated in the output capacitor C2. Therefore, as indicated by symbols z3 to z5 in FIG. 7B, the liquid crystal 42 can be supplied with the driving voltage of gradation 3. FIG.

[Description of effects of the present embodiment]
Thus, in the phase modulation device 101 according to this embodiment, each pixel circuit 21 is provided with the charge pump 31 . When setting an arbitrary gradation among a plurality of gradations preset in the range from "0" to double voltage (2*VLC), the voltage corresponding to this arbitrary gradation is the maximum. When the voltage is less than the voltage (VLC), the control voltage supplied from the column data line to the pixel circuit 21 is output to the liquid crystal 42 without being amplified.

Further, when the voltage corresponding to an arbitrary gradation out of a plurality of gradations exceeds the maximum voltage (VLC), the charge pump 31 outputs a voltage obtained by adding the maximum voltage (VCL) to the control voltage to the liquid crystal 42. do.

Therefore, when the maximum value of the control voltage supplied to the pixel circuit 21 from the column data line is the maximum voltage (VLC), the voltage supplied to the liquid crystal 42 is doubled (2*VLC). It becomes possible to set the driving voltage to be used. Therefore, the magnitude of the refractive index of the liquid crystal 42 can be changed in a wider range, an increase in the thickness of the liquid crystal layer 12 can be suppressed, and the precision of phase modulation can be improved.

Furthermore, since the gradation can be set in a wide voltage range without increasing the maximum voltage VLC of the control voltage supplied to the pixel circuit 21, there is no need to increase the breakdown voltage of each component constituting the control circuit 22, and the device can be made smaller. , it becomes possible to achieve weight reduction.

Further, since the voltage range for setting the drive voltage of the liquid crystal 42 is set to a voltage that is twice the maximum voltage VLC, a desired drive voltage can be obtained by a simple process of doubling the control voltage. can be obtained, and the circuit configuration can be simplified.

Further, in this embodiment, the refractive index of the liquid crystal 42 is set to change in one of the directions orthogonal to each other, ie, the column direction and the row direction shown in FIG. 3, and changes in the other direction. , drive lines (L1 to Ln) for switching the charge pump on and off. Therefore, it is possible to prevent the alignment of the liquid crystal from being disturbed due to the change in the refractive index.

In this embodiment, the drive voltage range is set to twice the maximum voltage (2*VLC), but the present invention is not limited to this, as long as it is greater than the maximum voltage VLC.

[Description of modification of the present embodiment]
Next, a modified example of this embodiment will be described. FIG. 9 is a circuit diagram showing the configuration of a pixel circuit 21' according to a modification. As shown in FIG. 9, in the pixel circuit 21' according to the modification, the drive lines L1 are arranged in the vertical direction. Therefore, the charge pump 31 can be turned on or off in the vertical direction of each pixel circuit 21' arranged in a matrix. Therefore, the direction in which the refractive index changes is the lateral direction.

That is, in the examples shown in FIGS. 6A and 6B, the refractive index of the liquid crystal 42 changes in the vertical direction, whereas in the modified example shown in FIG. , the refractive index of the liquid crystal 42 is set to change. In this case, the voltage supplied to the pixel circuit 21' is set so that the control voltage reaches the maximum voltage VLC in one vertical scanning period.

Although embodiments of the present invention have been described above, the statements and drawings forming part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

11 reflective substrate 12 liquid crystal layer 13 counter substrate 14 sealing material 21, 21a, 21' pixel circuit 22 control circuit 23 horizontal scanning circuit 24 vertical scanning circuit 25 charge pump control unit 26 shift register circuit 27 switch circuit 31 charge pump 42 liquid crystal q1 pixel Electrode q2 Common electrode p1 Input terminal p2 Output terminal L1 to Ln Drive lines D1 to Dm Column data lines G1 to Gn Row scanning lines L1 to Ln Drive lines K1 to Kn Control lines

Claims (6)

A phase modulation device that reflects incident light at a desired angle,
a plurality of pixel circuits provided at positions where a plurality of column data lines and a plurality of row scanning lines that are orthogonal to each other intersect, and a plurality of reflective pixels;
a liquid crystal provided corresponding to the reflective pixel and having a refractive index with respect to incident light that changes according to a driving voltage supplied from the pixel circuit;
the column data line outputs a control voltage to the pixel circuit that varies up to a predetermined maximum voltage;
the pixel circuit has a charge pump that adds the maximum voltage to the control voltage;
Further, when the driving voltage supplied to the liquid crystal is equal to or less than the maximum voltage, the control voltage is output to the liquid crystal without being amplified, and when the driving voltage supplied to the liquid crystal exceeds the maximum voltage a charge pump control unit for controlling the charge pump to add the maximum voltage to the control voltage and output the result to the liquid crystal. setting the refractive index of the liquid crystal to change in one of the directions orthogonal to each other, and arranging a driving line for switching on and off of the charge pump in the other direction; The phase modulation device according to claim 1, characterized by: the pixel circuit includes a short-circuit switch that short-circuits an input terminal for supplying the control voltage to the charge pump and an output terminal for outputting a voltage from the charge pump to the liquid crystal;
The charge pump controller short-circuits the short-circuit switch when the drive voltage output to the liquid crystal is equal to or less than the maximum voltage, and closes the short-circuit switch when the drive voltage output to the liquid crystal exceeds the maximum voltage. 3. The phase modulation device according to claim 1, wherein the phase modulation device is open. The pixel circuit includes an output capacitor that stores a voltage supplied to the liquid crystal,
The charge pump is
a first capacitor that stores electric charge;
a first switch provided between one end of the first capacitor and an input terminal to which the control voltage is supplied;
a second switch provided between the other end of the first capacitor and the input terminal;
a third switch provided between the one end of the first capacitor and one end of the output capacitor;
a fourth switch provided between the other end of the first capacitor and the other end of the output capacitor;
The phase modulation device according to any one of claims 1 to 3, characterized by comprising: 5. The phase modulation device according to any one of claims 1 to 4, wherein the maximum voltage of the driving voltage supplied to the liquid crystal is set to twice the maximum voltage. A phase modulation method for reflecting incident light at a desired angle,
a step of outputting a control voltage that varies within a range up to a predetermined maximum voltage to a plurality of pixel circuits provided at intersections of a plurality of column data lines and a plurality of row scanning lines that are orthogonal to each other;
When the drive voltage supplied to the liquid crystal, which is provided corresponding to each pixel circuit and whose refractive index for incident light changes according to the input drive voltage, is equal to or lower than the maximum voltage, the control voltage is not amplified. a step of outputting to the liquid crystal at
outputting to the liquid crystal a voltage obtained by adding the maximum voltage to the control voltage using a charge pump when the drive voltage supplied to the liquid crystal exceeds the maximum voltage;
A phase modulation method, comprising:

Images