JP7128694B2 - Monitoring device for parallel-serial conversion circuit - Google Patents

Description

The present invention relates to a monitoring device for a parallel-serial conversion circuit.

2. Description of the Related Art Parallel-serial conversion circuits are used in communication devices such as network switches to monitor status signals output from a large number of optical transceivers. In this case, the parallel-serial conversion circuit converts a large number of status signals input as parallel signals into serial signals and outputs the serial signals. By configuring in this way, in a monitoring device that monitors status signals, it is possible to efficiently monitor the status signals of many optical transceivers with one input port (input pin). Parallel-serial conversion circuits are also used to monitor switching states of analog switches.

A parallel-serial conversion circuit is generally configured by connecting a plurality of shift registers in multiple stages. A shift register is a digital circuit consisting of cascaded flip-flops. The parallel-to-serial conversion circuit is configured to hold a bit string input as a parallel signal and shift (move) the bit string within the circuit each time a clock signal is input.

In addition, there exists patent document 1 as prior art document information relevant to the invention of this application.

JP-A-9-311159

When a randomly changing signal such as the status signal described above is input as a parallel signal, the monitoring device side must determine whether the signal change is due to a fault in the parallel-to-serial conversion circuit or is a normal signal change. There is a problem that it is not possible to

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a parallel-serial conversion circuit monitoring apparatus capable of detecting a failure of a parallel-serial conversion circuit.

To solve the above problems, the present invention provides a monitoring device for a parallel-to-serial conversion circuit that uses one or more shift registers to convert an input parallel signal into a serial signal and outputs the parallel signal. a monitoring shift register which is connected to the rear stage of the shift register constituting the serial conversion circuit and outputs a serial signal to the final stage shift register of the parallel-serial conversion circuit; A dummy signal input unit for inputting a dummy signal and the dummy signal added to the end of the serial signal output from the parallel-serial conversion circuit are monitored, and based on whether the dummy signal matches the input value, the a failure determination unit for determining a failure of the parallel- serial conversion circuit, wherein the parallel-serial conversion circuit is configured by connecting a plurality of shift registers in multiple stages, and a serial signal output from the parallel-serial conversion circuit; By monitoring the signal monitoring unit for detecting a change in the parallel signal input to each of the shift registers; a faulty shift register estimator for estimating the faulty shift register based on the changed parallel signal when a change in the parallel signal is detected in .

In order to solve the above-mentioned problems, the present invention also provides a monitoring device for a parallel-serial conversion circuit which is configured by connecting a plurality of shift registers in multiple stages and which converts an input parallel signal into a serial signal and outputs the serial signal. a dummy signal input unit for inputting a predetermined dummy signal as a parallel signal to the final stage shift register constituting the parallel-serial conversion circuit; a failure determination unit that monitors the dummy signal received and determines failure of the parallel-serial conversion circuit based on whether the dummy signal matches an input value , wherein the parallel-serial conversion circuit includes a plurality of a signal monitoring unit configured by connecting the shift registers in multiple stages, and detecting a change in the parallel signal input to each of the shift registers by monitoring the serial signal output from the parallel-serial conversion circuit; At the same time that the dummy signal is determined to be inconsistent with the input value in the failure determining section, and at the same time when the change in the parallel signal is detected in the signal monitoring section, the shift register in which the failure has occurred is selected based on the changed parallel signal. and a faulty shift register estimator for estimating .

According to the present invention, it is possible to provide a monitoring device for a parallel-serial conversion circuit that can detect a failure of the parallel-serial conversion circuit.

1(a) is a schematic configuration diagram showing a monitoring device for a parallel-serial conversion circuit according to an embodiment of the present invention, and FIG. 1(b) schematically shows a serial signal output from the parallel-serial conversion circuit; It is an explanatory diagram. FIG. 4 is a diagram showing an example of a circuit configuration of a dummy signal input section; FIG. 11 is a schematic configuration diagram showing a modified example of a monitoring device for a parallel-serial conversion circuit;

[Embodiment]
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1(a) is a schematic configuration diagram showing a monitoring device for a parallel-serial conversion circuit according to the present embodiment, and FIG. 1(b) schematically shows a serial signal output from the parallel-serial conversion circuit. It is a diagram.

As shown in FIG. 1A, the parallel-serial conversion circuit 2 converts an input parallel signal into a serial signal and outputs the serial signal, and is configured using one or more shift registers 3 . Here, a case where the parallel-serial conversion circuit 2 is configured by connecting a plurality of shift registers 3 in multiple stages will be described.

The shift register 3 has a plurality of (for example, eight) parallel signal input ports 3a to which parallel signals are input, a serial signal output port 3b to output serial signals, and a serial signal input port 3c to input serial signals. have. The serial signal output port 3b of each shift register 3 is connected to the serial signal input port 3c of the shift register 3 in the preceding stage, and the serial signal output port 3b of the shift register 3 in the foremost stage is connected to the monitoring device 9 described later. It is A serial signal output port 5b of a monitoring shift register 5, which will be described later, is connected to the serial signal input port 3c of the shift register 3 at the last stage.

Each shift register 3 is a digital circuit in which a plurality of flip-flops are cascaded. Although not shown, each shift register 3 is provided with a port for inputting a clock signal. Each shift register 3 holds a bit string input as a parallel signal, sequentially shifts (moves) the bit string within the circuit each time a clock signal is input, and outputs the overflowed most significant bit as a serial signal. It is configured to output from the port 3b and take in the least significant bit input from the serial signal input port 3c.

In this embodiment, a parallel signal input to each shift register 3 is a status signal representing the state of a device or device (normal, abnormal, etc.). A parallel signal input port 3a of each shift register 3 is connected to a status signal output port (not shown) in a device or device (for example, an optical transceiver) 4 to be monitored.

The parallel-serial conversion circuit monitoring device 1 is a device that monitors whether the parallel-serial conversion circuit 2 is operating normally, that is, whether the parallel-serial conversion circuit 2 has a failure. A monitoring device 1 for a parallel-serial conversion circuit includes a monitoring shift register 5 , a dummy signal input section 6 , and a failure determination section 7 .

As the monitoring shift register 5, the same one as the shift register 3 of the parallel-to-serial conversion circuit 2 can be used. It is of course possible to use a shift register different from the shift register 3 of the parallel-serial conversion circuit 2 as the monitoring shift register 5 . The monitoring shift register 5 includes a plurality of (for example, eight) parallel signal input ports 5a to which parallel signals are input, a serial signal output port 5b to output serial signals, and a serial signal input port (not shown).

The monitoring shift register 5 is connected after the shift register 3 forming the parallel-serial conversion circuit 2 . That is, the serial signal output port 5b of the monitoring shift register 5 is connected to the serial signal input port 3c of the final stage shift register 3 of the parallel-serial conversion circuit 2. FIG. As a result, the serial signal from the monitoring shift register 5 is output to the last-stage shift register 3 of the parallel-serial conversion circuit 2 .

The dummy signal input section 6 inputs a predetermined dummy signal as a parallel signal to the shift register 5 for monitoring. As the dummy signal input unit 6, for example, as shown in FIG. 2, it is preferable to use a circuit in which high (1) or low (0) input is fixed in terms of hardware. In this example, the parallel signal input port 5a for inputting a low signal is connected to ground, and the parallel signal input port 5a for inputting a high signal is connected to a voltage source (Vcc) via a resistor.

Note that the specific circuit configuration of the dummy signal input section 6 is not limited to that shown in FIG. A signal generator or the like that generates a desired dummy signal can also be used as the dummy signal input unit 6 . However, since it is conceivable that the signal generator or the like may fail, it is more desirable to use a circuit in which the input value is fixed by hardware as the dummy signal input section 6, as shown in FIG.

By the way, when a failure occurs in the shift register 3, all bits after the bit where the failure occurred often become high (1) or low (0). Therefore, the dummy signal preferably includes both high and low signals, and preferably has at least two bits. In this embodiment, an 8-bit dummy signal (10101010) alternating between high (1) and low (0) is used.

By connecting the monitoring shift register 5 and the dummy signal input unit 6 to the parallel-serial conversion circuit 2, the serial signal output from the parallel-serial conversion circuit 2 is converted into a status signal ( D0 to Dn) are added with a dummy signal (10101010).

The output from the parallel-serial conversion circuit 2 is output to a monitoring device 9 that monitors status signals. The monitoring device 9 is composed of, for example, an FPGA (Field-Programmable Gate Array). The monitoring device 9 monitors the status signal portion (bits other than the dummy signal) in the serial signal output from the parallel-to-serial conversion circuit, thereby monitoring the status signal (parallel signal) input to each shift register 3. It has a signal monitor 8 for detecting changes.

The signal monitoring unit 8 stores the content of the status signal in a register in the monitoring device 9 when detecting that the status signal has changed a predetermined number of times (three times in this case) in succession. An interrupt signal indicating that the status has changed (hereinafter referred to as a status change notification signal) is output to the arithmetic unit 10 .

Arithmetic device 10 is equipped with a status monitoring unit 11 that monitors the status of equipment or devices to be monitored. When the status change notification signal is received from the monitoring device 9, the status monitoring unit 11 refers to the register of the monitoring device 9 to identify the port where the status signal has changed, and determines the state of the equipment or device corresponding to the port. Detect what has changed. The status monitoring unit 11 may have a function of notifying an administrator or the like that the state of the equipment or device has changed.

The failure determination unit 7 is mounted on the monitoring device 9 . The failure determination unit 7 monitors the dummy signal added to the end of the serial signal output from the parallel-serial conversion circuit 2 and determines whether the dummy signal matches the input value. and a determination unit 72 that determines failure of the parallel-serial conversion circuit based on the determination result of the signal monitoring unit 71 .

In this embodiment, since the dummy signal is a fixed value, the dummy signal monitoring unit 71 determines whether the dummy signal input as a serial signal matches a preset fixed value (here, 10101010). . Note that it is preferable to set in advance how to separate the status signal and the dummy signal (from which bit of the serial signal the dummy signal starts).

When the dummy signal monitoring unit 71 determines that the dummy signal does not match the input value (fixed value) consecutively for a predetermined number of times (three times in this case), the determination unit 72 determines that the parallel-to-serial conversion circuit 2 has failed. judge. When determining that the parallel-to-serial conversion circuit 2 has failed, the determination unit 72 sends an interrupt signal (hereinafter referred to as a failure notification signal) indicating that the parallel-to-serial conversion circuit 2 has failed to the arithmetic unit 10 above the monitoring device 9. Output.

The arithmetic device 10 is equipped with a faulty shift register estimator 12 for estimating the faulty shift register 3 . The faulty shift register estimator 12 mounted on the arithmetic device 10 and the above-described status monitor 11 are realized by appropriately combining arithmetic elements such as CPUs, memories, software, interfaces, and the like.

When the failure determination unit 7 determines that the dummy signal does not match the input value (fixed value) and the signal monitoring unit 8 detects a change in the status signal (parallel signal), the failure shift register estimation unit 12 It is configured to estimate the faulty shift register 3 based on the changed bit position of the status signal (parallel signal). That is, when the failure shift register estimator 12 receives both the status change notification signal and the failure notification signal at the same timing (for example, at an interval shorter than the time for receiving one cycle of the serial signal), It is determined that the change in the status signal is caused by the failure of the shift register 3, and the shift register 3 in which the failure has occurred is estimated.

Specifically, for example, in the serial signal, if all bits after a certain bit of the status signal are high (1), the faulty shift register estimation unit 12 is assumed to be the shift register 3 in which the failure has occurred. By estimating the shift register 3 in which the failure has occurred, repair work becomes easier. The failure shift register estimator 12 may be configured to store the estimation result of the failed shift register 3 in a predetermined storage area of the arithmetic unit 10, or may be configured to notify an administrator or the like. may be

(Actions and effects of the embodiment)
As described above, in the parallel-serial conversion circuit monitoring device 1 according to the present embodiment, the shift register 3 forming the parallel-serial conversion circuit 2 is connected to the rear stage of the shift register 3, and the last-stage shift register of the parallel-serial conversion circuit 2 A monitoring shift register 5 for outputting a serial signal to 3, a dummy signal input unit 6 for inputting a predetermined dummy signal as a parallel signal to the monitoring shift register 5, and an end of the serial signal output from the parallel-serial conversion circuit 2. and a failure determination unit 7 that monitors the dummy signal given to the parallel-serial conversion circuit 2 and determines a failure of the parallel-serial conversion circuit 2 based on whether the dummy signal matches the input value.

With this configuration, a failure of the parallel-to-serial conversion circuit 2 can be detected with a simple configuration such as adding the monitoring shift register 5 and the dummy signal input section 6 to the existing circuit and mounting the failure determination section 7 on the monitoring device 9 . can be detected. As a result, it becomes possible to improve the reliability of the entire device using the parallel-serial conversion circuit 2 . Further, since the monitoring device 1 of the parallel-serial conversion circuit according to the present embodiment can be realized by adding the monitoring shift register 5 and the dummy signal input section 6 as hardware, almost all the existing circuit configuration is changed. It is easy to apply to existing equipment.

(Modification)
In the above embodiment, the case of adding the monitoring shift register 5 to the existing circuit has been described. 3 can also be used as a monitoring shift register 5 . That is, as shown in FIG. 3, the shift register 3 at the final stage of the parallel-serial conversion circuit 2 may be configured to receive a dummy signal from the dummy signal input section 6 as a parallel signal. In other words, the monitoring shift register 5 in the monitoring device 1 of the parallel-serial conversion circuit of FIG.

It should be noted that it is also possible to configure the parallel-serial conversion circuit 2 so that a dummy signal is input to the shift register 3 other than the final stage. However, in this case, it becomes impossible to detect the failure of the shift register 3 at the stage after the shift register 3 to which the dummy signal is input. Therefore, it is desirable to input a dummy signal to the last-stage shift register 3 (monitoring shift register 5). By inputting a dummy signal into the final shift register 3 (monitoring shift register 5) and the shift registers 3 other than the final stage, it is possible to monitor which dummy signal causes a mismatch with the input value. , it is also possible to configure the faulty shift register estimator 12 so as to detect the faulty shift register 3 .

(Summary of embodiment)
Next, technical ideas understood from the embodiments described above will be described with reference to the reference numerals and the like in the embodiments. However, each reference numeral and the like in the following description do not limit the constituent elements in the claims to the members and the like specifically shown in the embodiment.

[1] A monitoring device for a parallel-serial conversion circuit (2) that uses one or more shift registers (3) to convert an input parallel signal into a serial signal and outputs the serial signal, the parallel-serial conversion circuit (2) ), a monitoring shift register (5) for outputting a serial signal to the last stage shift register (3) of the parallel-to-serial conversion circuit (2); A dummy signal input unit (6) for inputting a predetermined dummy signal as a parallel signal to a monitoring shift register (5), and the dummy signal added to the end of the serial signal output from the parallel-serial conversion circuit (2) and a failure judgment unit (7) for judging a failure of the parallel-serial conversion circuit (2) based on whether the dummy signal matches the input value. (1).

[2] A monitoring device for a parallel-to-serial conversion circuit (2) configured by connecting a plurality of shift registers (3) in multiple stages, converting an input parallel signal into a serial signal and outputting the serial signal,
a dummy signal input section (6) for inputting a predetermined dummy signal as a parallel signal to the final stage shift register (3) constituting the parallel-serial conversion circuit (2); a failure determination unit (7) that monitors the dummy signal added to the end of the output serial signal and determines failure of the parallel-serial conversion circuit (2) based on whether the dummy signal matches the input value; ), and a monitoring device (1) for a parallel-to-serial conversion circuit.

[3] The parallel-serial conversion circuit (2) is configured by connecting a plurality of shift registers (3) in multiple stages, and by monitoring the serial signal output from the parallel-serial conversion circuit (2), At the same time when the dummy signal is determined to be inconsistent with the input value in the signal monitoring unit (8) for detecting a change in the parallel signal input to each shift register (3) and the failure determining unit (7), the a faulty shift register estimator (12) for estimating the faulty shift register (3) based on the changed parallel signal when the signal monitor (8) detects a change in the parallel signal; A monitoring device (1) for a parallel-to-serial conversion circuit according to [1] or [2].

[4] A monitoring apparatus (1) for a parallel-to-serial conversion circuit according to [3], wherein the parallel signal input to the shift register (3) is a status signal representing the state of the equipment or device (4).

[5] The monitoring device (1) for a parallel-to-serial conversion circuit according to any one of [1] to [4], wherein the dummy signal has at least two bits and includes both high and low signals.

[6] The failure determination unit (7) determines that the parallel-to-serial conversion circuit (2) has failed when the dummy signal does not match the input value for a predetermined number of times consecutively, [1] to [5]. A monitoring device (1) for a parallel-to-serial conversion circuit according to any one of Claims 1 to 3.

Although the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the scope of claims. Also, it should be noted that not all combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

The present invention can be appropriately modified and implemented without departing from the gist thereof. For example, in the above-described embodiment, the dummy signal is set to a fixed value. A signal may be input.

Further, in the above-described embodiment, the dummy signal input section 6 is provided separately from the monitoring device 9 , but the monitoring device 9 may be provided with the function of the dummy signal input section 6 . In this case, the dummy signal output from the monitoring device 9 is input to the monitoring shift register 5 as a parallel signal.

REFERENCE SIGNS LIST 1 Parallel-serial conversion circuit monitoring device 2 Parallel-serial conversion circuit 3 Shift register 4 Equipment or device 5 Monitoring shift register 6 Dummy signal input unit 7 Failure determination unit 8 Signal monitoring unit 9 Monitoring device 10... Arithmetic unit 11... Status monitoring unit 12... Failure shift register estimating unit

Claims (5)

A monitoring device for a parallel-serial conversion circuit that converts an input parallel signal into a serial signal and outputs the serial signal using one or more shift registers,
a monitoring shift register connected to the rear stage of the shift register constituting the parallel-serial conversion circuit and outputting a serial signal to the last-stage shift register of the parallel-serial conversion circuit;
a dummy signal input unit for inputting a predetermined dummy signal as a parallel signal to the monitoring shift register;
failure determination for determining a failure of the parallel-serial conversion circuit by monitoring the dummy signal added to the end of the serial signal output from the parallel-serial conversion circuit and determining whether the dummy signal matches an input value; and
The parallel-serial conversion circuit is configured by connecting a plurality of shift registers in multiple stages,
a signal monitoring unit that detects a change in the parallel signal input to each of the shift registers by monitoring the serial signal output from the parallel-serial conversion circuit;
At the same time that the dummy signal is determined to be inconsistent with the input value in the failure determining section, and at the same time when the change in the parallel signal is detected in the signal monitoring section, the shift register in which the failure has occurred is selected based on the changed parallel signal. a faulty shift register estimator for estimating,
A monitoring device for a parallel-to-serial conversion circuit. A monitoring device for a parallel-to-serial conversion circuit configured by connecting a plurality of shift registers in multiple stages, converting an input parallel signal into a serial signal and outputting the serial signal,
a dummy signal input unit for inputting a predetermined dummy signal as a parallel signal to the final stage shift register constituting the parallel-serial conversion circuit;
failure determination for determining a failure of the parallel-serial conversion circuit by monitoring the dummy signal added to the end of the serial signal output from the parallel-serial conversion circuit and determining whether the dummy signal matches an input value; and
The parallel-serial conversion circuit is configured by connecting a plurality of shift registers in multiple stages,
a signal monitoring unit that detects a change in the parallel signal input to each of the shift registers by monitoring the serial signal output from the parallel-serial conversion circuit;
At the same time that the dummy signal is determined to be inconsistent with the input value in the failure determining section, and at the same time when the change in the parallel signal is detected in the signal monitoring section, the shift register in which the failure has occurred is selected based on the changed parallel signal. a faulty shift register estimator for estimating,
A monitoring device for a parallel-to-serial conversion circuit. the parallel signal input to the shift register is a status signal representing the state of the equipment or device;
3. A monitoring device for a parallel-to-serial conversion circuit according to claim 1 . The dummy signal is at least 2 bits or more and includes both high and low signals,
4. A monitoring device for a parallel-to-serial conversion circuit according to claim 1 . The failure determination unit determines that the parallel-serial conversion circuit has failed when the dummy signal does not match the input value for a predetermined number of consecutive times.
5. A monitoring device for a parallel-to-serial conversion circuit according to claim 1 .

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