JP7124803B2 - power circuit - Google Patents

Description

The technology disclosed in this specification relates to a power supply circuit.

A regulator circuit disclosed in Patent Document 1 boosts and outputs an input voltage using a switching element. The regulator has multiple resistors connected in series between the output terminal and ground. Therefore, a potential obtained by dividing the output potential of the regulator circuit is generated at the midpoint of the resistors. This regulator circuit controls the output potential by feedback-controlling the gate voltage of the switching element using the midpoint potential.

JP-A-2004-126922

In a circuit that divides an output potential by a plurality of resistors and detects the divided potential, as in Patent Document 1, the correlation between the potential at the midpoint of the resistors and the output potential may be lost due to failure of the resistors. In this case, the output potential cannot be controlled accurately. This specification proposes a technique that can accurately control an output potential even if a failure occurs in a resistor in a power supply circuit that controls the output potential based on a potential obtained by dividing the output potential.

A power supply circuit disclosed in this specification has an input terminal, an output terminal, and a switching element, and switches the switching element to apply an output potential different in magnitude from an input potential applied to the input terminal to the output terminal. a detection terminal; a reference terminal to which a potential lower than the output potential is applied; a first resistor connected between the output terminal and the detection terminal; a second resistor connected between terminals; an adjustment circuit connected to the output terminal and the detection terminal; applying a gate signal to the gate of the switching element; and a gate control circuit that changes the duty ratio of the signal. This power supply circuit has a first operation in which the potential of the detection terminal becomes a potential obtained by dividing the output potential by the first resistor and the second resistor, and A second action of controlling the potential can be performed. This power supply circuit executes the second operation when the output potential rises or falls continuously for a predetermined period in the first operation.

In this power supply circuit, in the first operation, the potential of the detection terminal becomes a potential obtained by dividing the output potential by the first resistor and the second resistor. Therefore, in the first operation, the gate control circuit controls the duty ratio of the gate signal based on the potential obtained by dividing the output potential by the first resistor and the second resistor. Therefore, the output potential can be controlled accurately. Further, if either the first resistor or the second resistor fails in the first operation, the output potential rises or falls continuously for a predetermined period. Then, the power supply circuit performs the second operation. In the second operation, the adjustment circuit controls the potential of the detection terminal according to the output potential. Therefore, the gate control circuit controls the duty ratio of the gate signal based on the potential controlled by the adjustment circuit (that is, the potential controlled according to the output potential). Therefore, the output potential can be controlled accurately. Thus, in this power supply circuit, even if either the first resistor or the second resistor fails, the output potential can be controlled accurately.

2 is a circuit diagram of the power supply circuit 10; FIG. 4 is a graph showing changes in output potential Vout and potential Vfb during normal operation; Flowchart of resistance fault operation. 5 is a graph illustrating changes in the output potential Vout and the potential Vb when the output potential Vout rises due to failure of the resistor; 5 is a graph illustrating changes in the output potential Vout and the potential Vb when the output potential Vout is lowered due to failure of the resistor; Flowchart of low potential operation. 5 is a graph illustrating changes in output potential Vout and potential Vb during low potential operation;

A power supply circuit 10 of the embodiment shown in FIG. 1 is mounted on a vehicle. The power supply circuit 10 has a converter circuit 20 . The converter circuit 20 boosts the input potential Vin and outputs it as an output potential Vout. An output potential Vout of the converter circuit 20 is supplied to a resolver (rotational angle sensor) (not shown). The resolver detects the rotation angle of the driving motor. By supplying the output potential Vout of the power supply circuit 10 to the resolver, the resolver is excited and the rotation angle can be detected.

The converter circuit 20 has an input terminal 22 , an input smoothing capacitor 24 , a reactor 26 , a switching element 28 , a diode 30 , an output smoothing capacitor 32 and an output terminal 34 . An input potential Vin is applied to the input terminal 22 from a DC power supply (not shown). The input-side smoothing capacitor 24 is connected between the input terminal 22 and ground. One end of the reactor 26 is connected to the input terminal 22 . The other end of reactor 26 is connected to the drain of switching element 28 . The switching element 28 is an n-channel FET (field effect transistor). The source of switching element 28 is connected to the ground. The anode of diode 30 is connected to the drain of switching element 28 . The cathode of diode 30 is connected to output terminal 34 . The output-side smoothing capacitor 32 is connected between the output terminal 34 and the ground. When the switching element 28 is repeatedly turned on and off, the input potential Vin applied to the input terminal 22 is boosted, and the boosted potential is output to the output terminal 34 as the output potential Vout.

The converter circuit 20 has a detection terminal 36 , a reference terminal 38 , a first resistor 41 and a second resistor 42 . A first resistor 41 is connected between the output terminal 34 and the detection terminal 36 . A second resistor 42 is connected between the sense terminal 36 and the reference terminal 38 . The reference terminal 38 is connected to ground. The detection terminal 36 is connected to an adjustment circuit 60 which will be described later. The adjustment circuit 60 can control the potential Vfb of the detection terminal 36 , or the potential of the detection terminal 36 can be made floating from the adjustment circuit 60 . When the potential of the detection terminal 36 is floating from the adjustment circuit 60 , the potential Vfb of the detection terminal 36 is a potential obtained by dividing the output potential Vout by the first resistor 41 and the second resistor 42 . That is, in this case, the potential Vfb satisfies the relationship of Vfb=Vout·R2/(R1+R2). However, R1 is the electrical resistance of the first resistor 41, and R2 is the electrical resistance of the second resistor 42.

The converter circuit 20 has a gate control IC 44 . The gate control IC 44 has a comparator 46 and a PWM signal generator 48 . A reference potential Vref1 is applied to the non-inverting input terminal of the comparator 46 . An inverting input terminal of the comparator 46 is connected to the detection terminal 36 . A comparator 46 outputs a signal indicating which of the reference potential Vref1 and the potential Vfb is larger. The output signal of the comparator 46 is input to the PWM signal generator 48 . The PWM signal generator 48 is connected to the gate of the switching element 28 . The PWM signal generator 48 applies a PWM signal to the gate of the switching element 28 . A PWM signal is a pulse signal that changes between a gate-on potential and a gate-off potential. When a gate-on potential is applied to the gate of the switching element 28, the switching element is turned on, and when a gate-off potential is applied to the gate of the switching element 28, the switching element is turned off. Since the PWM signal repeatedly changes between the gate-on potential and the gate-off potential, the switching element 28 is repeatedly turned on and off. The PWM signal generator 48 can change the duty ratio of the PWM signal. The duty ratio of the PWM signal means the ratio of the period during which the gate-on potential is applied. The duty ratio D satisfies the relationship D=Ton/(Ton+Toff), where Ton is the length of the period for applying the gate-on potential and Toff is the length of the period for applying the gate-off potential. The PWM signal generator 48 changes the duty ratio according to the signal input from the comparator 46 . Comparator 46 increases the duty ratio when potential Vfb is lower than reference potential Vref1. Increasing the duty ratio increases the output potential Vout of the converter circuit 20 . Further, the comparator 46 reduces the duty ratio when the potential Vfb is higher than the reference potential Vref1. When the duty ratio is lowered, the output potential Vout of converter circuit 20 is lowered. Thus, the output potential Vout is controlled by feedback control based on the potential Vfb.

The power supply circuit 10 has an adjustment circuit 60 . The adjustment circuit 60 has a microcomputer 62 , a third resistor 63 , a fourth resistor 64 , an intermediate terminal 66 and a reference terminal 68 . A third resistor 63 is connected between the output terminal 34 and the intermediate terminal 66 of the converter circuit 20 . A fourth resistor 64 is connected between the intermediate terminal 66 and the reference terminal 68 . The reference terminal 68 is connected to ground. Therefore, the potential Vs obtained by dividing the output potential Vout by the third resistor 63 and the fourth resistor 64 is applied to the intermediate terminal 66 . The microcomputer 62 is composed of an IC and has a control section 62a and a D/A converter 62b. The controller 62 a detects the potential Vs of the intermediate terminal 66 . The control unit 62a transmits a potential command value to the D/A converter 62b according to the potential Vs. The D/A converter 62b, upon receiving the potential command value from the control unit 62a, applies to the detection terminal 36 a potential Vdac corresponding to the potential command value. In this case, the potential Vfb of the detection terminal 36 matches the potential Vdac output from the D/A converter 62b. The controller 62a can also command the D/A converter 62b not to output the potential Vdac. In this case, the potential of the detection terminal 36 becomes floating with respect to the D/A converter 62b. In this state, the potential Vfb of the detection terminal 36 is a potential obtained by dividing the output potential Vout by the first resistor 41 and the second resistor 42 . As described above, the microcomputer 62 detects the potential Vs of the intermediate terminal 66 and operates according to the potential Vs. Since the potential Vs is proportional to the output potential Vout, the microcomputer 62 is equivalent to operating according to the output potential Vout. Therefore, in the following description, it is assumed that the microcomputer 62 operates according to the output potential Vout.

Power supply circuit 10 is capable of normal operation, resistive fault operation, and low potential operation. Each operation will be described below.

The power supply circuit 10 performs normal operation when the first resistor 41 and the second resistor 42 are not malfunctioning and the resolver is operated with high precision. In normal operation, the microcomputer 62 does not control the potential Vfb of the detection terminal 36 . That is, in normal operation, the potential Vfb of the detection terminal 36 is floating with respect to the D/A converter 62b. Therefore, the potential Vfb becomes a potential obtained by dividing the output potential Vout by the first resistor 41 and the second resistor 42 . In this case, the comparator 46 compares whether or not the potential Vfb (=Vout·R2/(R1+R2)) is greater than the reference potential Vref1. to control.

FIG. 2 illustrates changes in the output potential Vout and the potential Vfb during normal operation. Note that the target potential Vt1 in FIG. 2 indicates the control target value of the output potential Vout corresponding to the reference potential Vref1. During the period T1 in FIG. 2, the output potential Vout is stable at the target potential Vt1. In the subsequent period T2, the output potential Vout rises due to the decrease in the load on the resolver. Then, as the output potential Vout rises, the potential Vfb also rises. The comparator 46 then detects that the potential Vfb is higher than the reference potential Vref1. Then, the PWM signal generator 48 reduces the duty ratio of the PWM signal. Then, the output potential Vout drops to the target potential Vt1 in the subsequent period T3. In the subsequent period T4, the output potential Vout is stabilized at the target potential Vt1 by feedback-controlling the duty ratio of the PWM signal based on the potential Vfb.

Further, in the period T5 in FIG. 2, the output potential Vout decreases due to the increased load on the resolver. Then, the potential Vfb also drops as the output potential Vout drops. Comparator 46 then detects that potential Vfb is lower than reference potential Vref1. Then, the PWM signal generator 48 increases the duty ratio of the PWM signal. Then, the output potential Vout rises to the target potential Vt1 in the subsequent period T6. In the subsequent period T7, the output potential Vout is stabilized at the target potential Vt1 by feedback-controlling the duty ratio of the PWM signal based on the potential Vfb.

As described above, in normal operation, the potential Vfb of the detection terminal 36 is a potential obtained by dividing the output potential Vout. That is, the potential Vfb is proportional to the output potential Vout. Therefore, by feedback-controlling the switching element 28 based on the potential Vfb, the output potential Vout can be controlled to the target potential Vt1.

Next, resistance failure operation will be described. A resistance failure operation is performed when the first resistor 41 or the second resistor 42 fails. For example, when the resistors 41 and 42 are open (disconnected) due to a solder crack or the like, or when the electrical resistance of the resistors 41 and 42 fluctuates due to a resistance drift failure, the resistance failure operation is executed. First, detection of a failure in the first resistor 41 or the second resistor 42 will be described.

During normal operation, if the first resistor 41 becomes open or if the electrical resistance of the first resistor 41 increases, the potential Vfb of the detection terminal 36 decreases. Also, when the electrical resistance of the second resistor 42 decreases during normal operation, the potential Vfb of the detection terminal 36 also decreases. When the potential Vfb of the detection terminal 36 decreases, the PWM signal generator 48 increases the duty ratio to increase the output potential Vout. When the output potential Vout rises, the microcomputer 62 (that is, the control section 62a) detects the rise of the output potential Vout. A rise in the output potential Vout due to a resistor failure occurs over a longer period of time than a normal rise in the output potential Vout (for example, a rise in the output potential Vout during the period T2 in FIG. 2). The microcomputer 62 determines that a resistance failure has occurred when the output potential Vout continues to rise for a certain period of time or longer.

Further, when the second resistor 42 becomes open or the electrical resistance of the second resistor 42 increases during normal operation, the potential Vfb of the detection terminal 36 increases. Also, when the electrical resistance of the first resistor 41 decreases during normal operation, the potential Vfb of the detection terminal 36 increases. When the potential Vfb of the detection terminal 36 rises, the PWM signal generator 48 lowers the duty ratio to lower the output potential Vout. When the output potential Vout drops, the microcomputer 62 detects the drop in the output potential Vout. The drop in the output potential Vout due to the failure of the resistor occurs over a longer period of time than the normal drop in the output potential Vout (for example, the drop in the output potential Vout during the period T5 in FIG. 2). The microcomputer 62 determines that a resistor failure has occurred when the output potential Vout continues to drop for a certain period of time or more.

In this way, the microcomputer 62 determines that a resistor failure has occurred when the output potential Vout continues to rise or fall for a certain period of time. The microcomputer 62 performs resistance failure operation when a resistance failure occurs. In resistance failure operation, the microcomputer 62 controls the potential Vfb of the detection terminal 36 . In this case, the potential Vfb of the detection terminal 36 is controlled independently of the output potential Vout. In resistance failure operation, the microcomputer 62 repeatedly executes the flow chart of FIG.

In step S2, the microcomputer 62 detects the output potential Vout and determines the output potential Vout.

When it is determined in step S2 that the output potential Vout is higher than the target potential Vt1, in step S4 the microcomputer 62 controls the potential Vfb of the detection terminal 36 to a potential VH higher than the reference potential Vref1. Then, the PWM signal generator 48 reduces the duty ratio to reduce the output potential Vout.

When it is determined in step S2 that the output potential Vout is equal to the target potential Vt1, the microcomputer 62 controls the potential Vfb of the detection terminal 36 to the same value as the reference potential Vref1 in step S6. Then, the PWM signal generator 48 maintains the duty ratio and maintains the output potential Vout.

When it is determined in step S2 that the output potential Vout is lower than the target potential Vt1, in step S8 the microcomputer 62 controls the potential Vfb of the detection terminal 36 to a potential VL lower than the reference potential Vref1. Then, the PWM signal generator 48 increases the duty ratio to raise the output potential Vout.

FIG. 4 illustrates changes in the output potential Vout and the potential Vb when the output potential Vout rises due to failure of the resistor. In this case, a resistive fault action is performed. In period T11, the output potential Vout is higher than the target potential Vt1. Therefore, during the period T11, the microcomputer 62 repeatedly executes steps S2 and S4. Therefore, during the period T11, the microcomputer 62 controls the potential Vfb to a potential VH higher than the reference potential Vref1, and the PWM signal generator 48 reduces the duty ratio of the PWM signal. Therefore, the output potential Vout decreases during the period T11. When the output potential Vout drops to the target potential Vt1 at the end of the period T11, the microcomputer 62 determines in step S2 that the output potential Vout is equal to the target potential Vt1. Therefore, the microcomputer 62 controls the potential Vfb to the reference potential Vref1 in step S6. Therefore, the PWM signal generator 48 maintains the current duty ratio. As a result, the output potential Vout stops decreasing. In a period T12 after the period T11, the microcomputer 62 repeatedly executes steps S2 and S6. Therefore, during the period T12, the potential Vfb is maintained at the reference potential Vref1, and the output potential Vout is maintained at the target potential Vt1.

FIG. 5 illustrates changes in the output potential Vout and the potential Vb when the output potential Vout drops due to failure of the resistor. In this case, a resistive fault action is performed. In period T21, the output potential Vout is lower than the target potential Vt1. Therefore, during the period T21, the microcomputer 62 repeatedly executes steps S2 and S8. Therefore, during the period T21, the microcomputer 62 controls the potential Vfb to a potential VL lower than the reference potential Vref1, and the PWM signal generator 48 increases the duty ratio of the PWM signal. Therefore, the output potential Vout rises during the period T21. When the output potential Vout rises to the target potential Vt1 at the end of the period T21, the microcomputer 62 determines in step S2 that the output potential Vout is equal to the target potential Vt1. Therefore, the microcomputer 62 controls the potential Vfb to the reference potential Vref1 in step S6. Therefore, the PWM signal generator 48 maintains the current duty ratio. As a result, the output potential Vout stops rising. In a period T22 after the period T21, the microcomputer 62 repeatedly executes steps S2 and S6. Therefore, during the period T22, the potential Vfb is maintained at the reference potential Vref1, and the output potential Vout is maintained at the target potential Vt1.

Moreover, after the output potential Vout is stabilized by the resistance failure operation, the output potential Vout may rise or fall due to load fluctuations in the resolver. For example, the output potential Vout may rise or fall after period T12 in FIG. 4 or after period T22 in FIG. Also in this case, the microcomputer 62 operates according to the flowchart of FIG. 3 to return the output potential Vout to the target potential Vt1. Thus, in this power supply circuit 10, even if the first resistor 41 or the second resistor 42 fails, the output potential Vout can be appropriately controlled.

As described above, when the resistor fails, the microcomputer 62 controls the potential Vb so that the output potential Vout is controlled to the target potential Vt1.

Next, the low potential operation will be explained. Low potential operation is performed when high detection accuracy is not required in the resolver. In the low potential operation, the output potential Vout is controlled to a target value (target potential Vt2) lower than the normal target value (target potential Vt1). Power consumption in the resolver can be suppressed by lowering the output potential Vout. A low potential operation is started by inputting a command to the microcomputer 62 from the outside. In the low potential operation, the microcomputer 62 repeatedly executes the flowchart of FIG.

In step S12, the microcomputer 62 detects the output potential Vout and determines whether the output potential Vout is higher than the target potential Vt2. As described above, the target potential Vt2 is lower than the target potential Vt1.

When it is determined in step S12 that the output potential Vout is higher than the target potential Vt2, in step S14 the microcomputer 62 controls the potential Vfb of the detection terminal 36 to a potential VH higher than the reference potential Vref1. Then, the PWM signal generator 48 reduces the duty ratio to reduce the output potential Vout.

When it is determined in step S12 that the output potential Vout is equal to the target potential Vt2, the microcomputer 62 controls the potential Vfb of the detection terminal 36 to the same value as the reference potential Vref1 in step S16. Then, the PWM signal generator 48 maintains the duty ratio and maintains the output potential Vout.

When it is determined in step S12 that the output potential Vout is lower than the target potential Vt2, in step S18 the microcomputer 62 controls the potential Vfb of the detection terminal 36 to a potential VL lower than the reference potential Vref1. Then, the PWM signal generator 48 increases the duty ratio to raise the output potential Vout.

FIG. 7 illustrates changes in the output potential Vout and the potential Vfb during low potential operation. At the beginning of the period T31, the output potential Vout matches the target potential Vt1 during normal operation. In period T31, the output potential Vout is higher than the target potential Vt2. Therefore, during the period T31, the microcomputer 62 repeatedly executes steps S12 and S14. Therefore, during the period T31, the microcomputer 62 controls the potential Vfb to a potential VH higher than the reference potential Vref1, and the PWM signal generator 48 reduces the duty ratio of the PWM signal. Therefore, the output potential Vout decreases during the period T31. When the output potential Vout drops to the target potential Vt2 at the end of the period T31, the microcomputer 62 determines in step S12 that the output potential Vout is equal to the target potential Vt2. Therefore, the microcomputer 62 controls the potential Vfb to the reference potential Vref1 in step S16. Therefore, the PWM signal generator 48 maintains the current duty ratio. As a result, the output potential Vout stops decreasing. In a period T32 after the period T31, the microcomputer 62 repeatedly executes steps S12 and S16. Therefore, during the period T32, the potential Vfb is maintained at the reference potential Vref1, and the output potential Vout is maintained at the target potential Vt2.

Further, after the output potential Vout stabilizes at the target potential Vt2 due to the low potential operation, the output potential Vout may rise or fall due to load fluctuations in the resolver. For example, the output potential Vout may rise or fall after the period T32 in FIG. Also in this case, the microcomputer 62 operates according to the flowchart of FIG. 6 to return the output potential Vout to the target potential Vt2.

As described above, during low potential operation, the microcomputer 62 controls the potential Vb so that the output potential Vout is controlled to a low potential (target potential Vt2).

As described above, according to the power supply circuit 10, even when the first resistor 41 or the second resistor 42 fails, the output potential Vout can be controlled to an appropriate value.

In addition, according to the power supply circuit 10, power consumption can be suppressed by supplying a low potential to the resolver when high-precision detection by the resolver is not required.

Further, since the configuration of the adjustment circuit 60 can be obtained only by partially changing the configuration of the circuit for monitoring the output potential Vout, the adjustment circuit 60 can be configured at low cost.

Further, in the power supply circuit 10, the microcomputer 62 does not control the potential Vfb when there is no resistance failure, so power consumption in the microcomputer 62 can be suppressed.

In the above-described embodiments, the power supply circuit that boosts the input potential has been described, but the same technology as the embodiment may be applied to a power supply circuit that steps down the input potential.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: Power supply circuit 20: Converter circuit 22: Input terminal 24: Input side smoothing capacitor 26: Reactor 28: Switching element 30: Diode 32: Output side smoothing capacitor 34: Output terminal 36: Detection terminal 38: Reference terminal 41: First resistor 42 : Second resistor 46 : Comparator 48 : PWM signal generator 60 : Adjustment circuit 62 : Microcomputer 62a : Control unit 62b : D/A converter 63 : Third resistor 64 : Fourth resistor 66 : Intermediate terminal 68 : Reference terminal

Claims (1)

a power circuit,
a converter circuit having an input terminal, an output terminal, and a switching element, and outputting an output potential different in magnitude from an input potential applied to the input terminal to the output terminal by switching the switching element;
a detection terminal;
a reference terminal to which a potential lower than the output potential is applied;
a first resistor connected between the output terminal and the detection terminal;
a second resistor connected between the detection terminal and the reference terminal;
an adjustment circuit connected to the output terminal and the detection terminal;
a gate control circuit that applies a gate signal to the gate of the switching element and changes the duty ratio of the gate signal according to the potential of the detection terminal;
has
a first operation in which the potential of the detection terminal becomes a potential obtained by dividing the output potential by the first resistor and the second resistor; and a second operation in which the adjustment circuit controls the potential of the detection terminal according to the output potential. 2 operations are executable,
performing the second operation when the output potential continuously rises or falls for a predetermined period in the first operation;
power circuit.

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