JP7101530B2 - Imaging display device and electronic equipment - Google Patents

Description

One aspect of the present invention relates to an image pickup display device.

It should be noted that one aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, image pickup devices, and the like. The driving method or the manufacturing method thereof can be given as an example.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Further, the storage device, the display device, the image pickup device, and the electronic device may have a semiconductor device.

Attention is being paid to a technique for constructing a transistor using an oxide semiconductor thin film formed on a substrate. For example, Patent Document 1 discloses an image pickup apparatus having an oxide semiconductor and using a transistor having an extremely low off-current in a pixel circuit.

In addition, the image pickup device is incorporated in various electronic devices together with the display device, and the captured image can be confirmed on the spot. In addition, a technique called augmented reality (AR) that displays a combination of an image actually captured and additional data such as character information acquired from a server or computer graphics (CG) is also used. ..

Japanese Unexamined Patent Publication No. 2011-119711

Since the image data acquired by the image pickup device is analog data, it is converted into digital data and transmitted to a recording medium or a display device. Then, the display device converts the digital data into analog data again to drive the display element. Therefore, even when the captured image is displayed in real time, the image actually displayed on the display device has a delay from the reality.

Further, in the AR display, the display of the additional data requires the communication time with the server and the data processing time. Therefore, in order to obtain consistency with reality, it is effective to speed up communication with the server, reduce the server load, and apply a high-performance data processing device.

In addition, a method has been proposed in which a see-through type display is used to make a real image that actually passes through the display and only additional data is displayed on the display. However, since the positional relationship between the position of the viewer and the position of the display is not always constant, it is necessary to adjust the position of the display of the actual and additional data. For example, when the display is viewed from the front, even if an object and additional data such as characters can be displayed so as to overlap each other, when the display is viewed from an angle, the overlap will be shifted.

Therefore, one of the objects of the present invention is to provide an image pickup display device capable of transmitting analog data acquired by the image pickup unit to the display unit without converting it into digital data. Alternatively, one of the purposes is to provide an image pickup display device capable of acquiring additional data used for AR display at high speed. Another object of the present invention is to provide an image pickup display device that does not require adjustment of the position of the display of reality and additional data in AR display.

Alternatively, one of the purposes is to provide an image pickup display device having low power consumption. Another object of the present invention is to provide an image pickup display device capable of taking an image with less noise. Another object of the present invention is to provide an image pickup display device capable of high-sensitivity image pickup. Alternatively, one of the purposes is to provide a highly reliable image pickup display device. Alternatively, one of the purposes is to provide a new image pickup display device or the like. Alternatively, one of the purposes is to provide a method for driving the image pickup display device. Alternatively, one of the purposes is to provide a new semiconductor device or the like.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

One aspect of the present invention relates to an image pickup display device having an image pickup unit on a first surface and a display unit on a second surface opposite to the first surface.

One aspect of the present invention has an image pickup unit on a first surface, a display unit on a second surface opposite to the first surface, and the image pickup unit has light irradiated to the first surface. The photoelectric conversion element has a light emitting element that emits light in the direction opposite to the first surface, and the photoelectric conversion element is electrically connected to the gate of the transistor. The light emitting element is an image pickup display device that is electrically connected to one of the source and drain of the transistor.

Further, it can be configured to have a data processing unit. The data processing unit has a neural network that estimates the type of subject. Further, the data processing unit can be provided between the photoelectric conversion element and the light emitting element.

Further, another aspect of the present invention includes a first layer, a second layer, and a third layer, and the second layer is a first layer and a third layer. Provided between them, the first layer has a light emitting element, the second layer has a first transistor and a second transistor, and the third layer has a photoelectric conversion element and emits light. The element is electrically connected to the first transistor, the photoelectric conversion element is electrically connected to the second transistor, and the first transistor and the second transistor are electrically connected to each other. It is a display device.

Further, it has a fourth layer, the fourth layer is provided between the second layer and the third layer, and the fourth layer has a third transistor, and the third transistor and the third layer. The second transistor may be electrically connected, the first and second transistors may have a metal oxide in the channel forming region, and the third transistor may have silicon in the channel forming region.

The metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

The photoelectric conversion element preferably has selenium or a compound containing selenium.

Further, another aspect of the present invention is an image pickup display device including a first transistor, a second transistor, a third transistor, a photoelectric conversion element, and a light emitting element. One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the transistor, and one of the source or drain of the second transistor is electrically connected to one of the electrodes of the photoelectric conversion element. The gate of the third transistor is electrically connected to the other of the source or drain of the second transistor, and one electrode of the light emitting element is electrically connected to one of the source or drain of the third transistor. It is an image pickup display device.

Further having a fourth transistor, one of the source or drain of the fourth transistor is electrically connected to the other of the source or drain of the second transistor, and the other of the source or drain of the fourth transistor is. It can be configured to be electrically connected to the gate of the third transistor.

By using one aspect of the present invention, it is possible to provide an image pickup display device capable of transmitting analog data acquired by the image pickup unit to the display unit without converting it into digital data. Alternatively, it is possible to provide an image pickup display device capable of acquiring additional data used for AR display at high speed. Alternatively, it is possible to provide an image pickup display device that does not require position adjustment of the display of reality and additional data in AR display.

Alternatively, it is possible to provide an image pickup display device having low power consumption. Alternatively, it is possible to provide an image pickup display device capable of taking an image with less noise. Alternatively, it is possible to provide an image pickup display device capable of high-sensitivity image pickup. Alternatively, a highly reliable image pickup display device can be provided. Alternatively, a new image pickup display device or the like can be provided. Alternatively, it is possible to provide a method for driving the image pickup display device. Alternatively, a new semiconductor device or the like can be provided.

The figure explaining the image pickup display device. Block diagram of the image pickup display device. A flowchart illustrating the operation of displaying information about a subject. The figure explaining the configuration example of the image pickup display device. The figure explaining the configuration example of the image pickup display device. The figure explaining the electrical connection of the element which an image pickup display device has. The figure explaining the electrical connection of a pixel circuit and other circuits. Diagrams and timing charts illustrating pixel circuits. Diagrams and timing charts illustrating pixel circuits. Diagrams and timing charts illustrating pixel circuits. The figure explaining the pixel circuit. The figure explaining the pixel circuit. Diagrams and timing charts illustrating pixel circuits. Diagrams and timing charts illustrating pixel circuits. The figure explaining the example of the image displayed on the display part. The figure explaining the operation of estimating the category of a subject by a neural network. The figure which shows the structural example of a neural network. The figure which shows the structural example of the semiconductor device. The figure which shows the structural example of the storage circuit. The figure which shows the configuration example of the memory cell. The figure which shows the structural example of a circuit. A timing chart explaining the operation of a semiconductor device. The figure explaining the composition of the pixel of the image pickup apparatus. The figure explaining the composition of the pixel of the image pickup apparatus. The figure explaining the composition of the pixel of the image pickup apparatus. The figure explaining the structure of the image pickup apparatus. The figure explaining the electronic device.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals may be used in common among different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. The hatching of the same element constituting the figure may be omitted or changed as appropriate between different drawings.

(Embodiment 1)
In the present embodiment, the image pickup display device according to one aspect of the present invention will be described with reference to the drawings.

One aspect of the present invention is an image pickup display device having an image pickup unit and a display unit. The image pickup display device includes an image pickup unit on a first surface and a display unit on a second surface opposite to the first surface. Since the surface that detects light and the surface that emits light are opposite to each other, the configuration is suitable for smart glasses, telescopes, binoculars, monoculars, microscopes, night-vision scopes, and the like.

The image pickup display device has pixels in each of the image pickup unit and the display unit, and the pixels of the image pickup unit and the pixels of the display unit are electrically connected to each other. Alternatively, it can be said that one pixel has a portion that functions as an image pickup unit and a portion that functions as a display unit. With this configuration, the image signal acquired by the image pickup unit can be directly input to the display unit. Therefore, the delay time associated with the data conversion can be eliminated, and the captured image can be displayed instantly.

FIG. 1 is a diagram illustrating an image pickup display device according to an aspect of the present invention. The image pickup display device 100 has an image pickup unit (IS) 101 and a display unit (DIS) 102. A lens 103 may be provided between the image pickup unit 101 and the subject 105. Further, a lens 104 may be provided between the display unit 102 and the viewer 106.

For example, the lens 103 has a function of reducing and projecting the subject 105 onto the image pickup unit 101. Further, the lens 104 has a function of magnifying and projecting the image displayed on the display unit 102 onto the viewer 106. Although the lenses 103 and 104 are each represented by one convex lens in FIG. 1, the configuration and function are arbitrary, and a combination lens or the like may be used. Further, a mirror for adjusting the optical path may be provided between the display unit 102 and the subject 105.

Each of the pixels of the image pickup unit 101 is electrically connected to the corresponding pixel of the display unit 102 on a one-to-one basis. Therefore, the analog data acquired as an image signal by the pixels of the image pickup unit 101 is transmitted to the pixels of the display unit 102 without being converted into digital data, and is displayed.

Therefore, in the image pickup display device of one aspect of the present invention, the delay of the actual display can be made extremely small.

FIG. 2 shows an example of a block diagram of the image pickup display device 100. The image pickup display device 100 includes a data processing unit 200 in addition to the image pickup unit 101 and the display unit 102. The data processing unit 200 includes, for example, a calculation unit (CPU) 201, an image processing unit (GPU) 202, a position sensor (GPS) 203, an input / output unit (I / O) 204, and a storage unit (MEM) 205. Has.

The elements of the image pickup unit 101, the display unit 102, and the data processing unit 200 are electrically connected to each other, and signals and data can be exchanged as needed. In some cases, one of the elements is not electrically connected to any of the other elements. In addition, another element may have the function of one of the elements. In addition, the function of one element may be distributed to a plurality of elements.

The image pickup unit 101 has a function of capturing image data, and an image pickup device such as a CMOS image sensor can be used. The display unit 102 has a function of displaying image data. For example, it is preferable to use a display device using a light emitting element such as an organic EL element.

The calculation unit 201 has a function of performing calculations related to the operation of the entire image pickup display device 100, and for example, a central processing unit (CPU: Central Processing Unit) or the like can be used.

The image processing unit 202 has a function of processing data related to an image, and for example, an image processing unit (GPU: Graphics Processing Unit) or the like can be used. Further, the image processing unit 202 can have a neural network (NN) 207 for analyzing an image.

The position sensor 203 has a function of specifying the position of the image pickup display device 100, and for example, a GPS (Global Positioning System) receiver can be used. Further, a gyro sensor, an acceleration sensor, an optical sensor, a temperature sensor and the like may be provided.

The input / output unit 204 has a function of acquiring information from the outside or a function of outputting information to the outside. For example, the input / output unit 204 can be connected to a wired or wireless network, and can input / output information to / from the server (SV) 206 via the network. Further, a medium in which information for collating with the acquired image data may be stored may be connected to the input / output unit 204.

The storage unit 205 has a function of storing programs and setting items related to the operation in the image pickup display device 100. It also has a function of storing image data captured by the image pickup unit 101. A removable storage medium (MEM) 208 that also functions as a part of the storage unit 205 may be used.

Here, the neural network 207 performs an operation of estimating a category such as whether the subject imaged by the imaging unit 101 is a building, a plant, or a person. For example, when it is desired to obtain information on a subject by AR display, it has been possible to obtain information on buildings, roads, etc. using the position sensor 203 in the past, but it has been difficult to obtain information on a subject that is not specified by the position. ..

When only the image information of the subject is transmitted to the server 206 to obtain the information, it is necessary for the server 206 to analyze what the subject is from the category. Therefore, the load on the server 206 side becomes large, and it takes time to search. In addition, it may not be possible to analyze due to lack of information, or more information may be requested for analysis.

By estimating the category with the neural network 207 and transmitting the estimation result of the category in addition to the image data, the burden of analysis on the server 206 can be significantly reduced. Further, the information acquired by the position sensor 203 may be added and transmitted to the server 206. By transmitting the information to the server 206 after the category is confirmed, the search result can be obtained from the server 206 at high speed.

Therefore, in the image pickup display device of one aspect of the present invention, AR display with high consistency with reality can be performed by category estimation of a subject using a neural network.

Here, the flowchart shown in FIG. 3 shows an example of an operation of performing AR display at an arbitrary timing when the image pickup operation of the image pickup unit 101 and the display operation of the display unit 102 are repeatedly performed in the image pickup display device 100. It will be explained using. It is assumed that the acquisition of the position information by the position sensor 203 and the acquisition of various environmental information when the other sensors are provided are also performed at the same time as the imaging operation and the like.

First, a subject is extracted from the images captured by the calculation unit 201, the image processing unit 202, and the like, and image analysis is performed. Here, the number, shape, color, and the like of the subjects in the image are classified (S1).

Next, a subject for which information is to be displayed is selected (S2). It should be noted that it may be preset so that all the subjects included in the image are selected.

Next, for the selected subject, the neural network 207 estimates the subject category using the already acquired position information of the subject and the information obtained by the image analysis of S1 (S3).

Next, the image of the subject, the information used for the category estimation of S3, and the category estimation result are transmitted to the server 206, and the server 206 searches for the information about the subject (S4).

Then, the information about the subject is received from the server 206 (S5), and the information is AR-displayed on the display unit 102 (S6).

If you want to change the subject for which information is displayed, return to S2 and select the subject again.

Next, a configuration example applicable as the image pickup display device 100 will be described with reference to FIGS. 4A to 7. The symbols of the elements common to FIGS. 4 (A) to 7 are the same.

The image pickup display device 110 shown in FIG. 4A has a structure in which a layer 111, a layer 112, and a layer 113 are sequentially laminated. In the image pickup display device 110, the elements of the image pickup unit 101 can be provided on the layer 111 and the layer 112. Further, the elements of the display unit 102 can be provided on the layer 112 and the layer 113.

FIG. 4C is a diagram illustrating each layer of the image pickup display device 110. Layer 111 has a region 153 provided with a photodiode. As the photodiode, it is preferable to use a pn-type photodiode or a pin-type photodiode having a silicon substrate as a photoelectric conversion layer.

The layer 112 has a region 151 and a region 152 provided on the silicon substrate. Regions 151 and 152 have transistors with silicon as the channel forming region. It should be noted that there are a plurality of regions 152, and circuits having different functions can be provided in each region.

The region 151 has a configuration in which the pixel circuit of the image pickup unit 101 (excluding the photoelectric conversion element) and the pixel circuit of the display unit 102 (excluding the display element) are mixed. The region 152 may be provided with a drive circuit, a readout circuit, or the like of the pixel circuit of the image pickup unit 101 or the pixel circuit of the display unit 102.

The layer 113 has a region 150 provided with a display element. It is preferable to use a light emitting element having an organic EL layer as the display element.

The area 153, the area 151, and the area 150 have almost the same area.

FIG. 6A is a diagram illustrating the electrical connection of the elements constituting one pixel in the image pickup display device 110. The region 153 has a photoelectric conversion element 161. Region 151 has transistors 162a and 162b. The region 150 has a display element 163.

The transistors 162a and 162b are a part of the pixel circuit 162 of the image pickup unit 101 and the display unit 102. The photoelectric conversion element 161 and the transistors 162a and 162b and the display element 163 are arranged in a matrix in the region 153, the region 151, or the region 150, respectively.

The photoelectric conversion element 161 is arranged so as to have a region overlapping with the transistors 162a and 162b. One electrode of the photoelectric conversion element 161 is electrically connected to one of the source and the drain of the transistor 162a.

The transistors 162a and 162b are arranged so as to have a region overlapping with the display element 163. One of the source or drain of the transistor 162b is electrically connected to one of the electrodes of the display element 163.

Although the details of the circuit corresponding to the pixel circuit 162 will be described later, the gate of the transistor 162b is electrically connected to the other of the source or drain of the transistor 162a.

Further, FIG. 7A is a diagram illustrating an electrical connection between the pixel circuit 162 in the image pickup display device 110 and the circuits 152a, 152b, 152c, and 152d provided in the region 152. The circuits 152a, 152b, 152c, and 152d can have a function of driving the pixel circuit 162, a function of reading a signal from the pixel circuit 162, and the like.

The circuit 152a can have a function as a low driver of the image pickup unit 101. The circuit 152a is electrically connected to the elements of the pixel circuit 162 via wiring. The circuit 152b can have a function as a column driver of the image pickup unit 101. Further, the circuit 152b may have a function of a CDS (colored double sampling) circuit for removing noise and an A / D converter. The circuit 152b is electrically connected to the elements of the pixel circuit 162 via wiring.

The circuit 152c can have a function as a low driver of the display unit 102. The circuit 152c is electrically connected to the elements of the pixel circuit 162 via wiring. The circuit 152d can have a function as a column driver of the display unit 102. The circuit 152d is electrically connected to the elements of the pixel circuit 162 via wiring.

Further, as shown in the explanatory diagram of each layer in FIG. 4D, the relative area of the region 152 in the layer 112 can be increased by reducing the relative area of the region 151 in the layer 112. At this time, in addition to providing the drive circuit and the like described above, the region 152 may be provided with any element of the data processing unit 200 or a part of the circuit included in the element.

Further, the image pickup display device 100 may have the configuration of the image pickup display device 120 shown in FIG. 4 (B). The image pickup display device 120 has a configuration in which the photoelectric conversion element is different from that of the image pickup display device 110, and has a layer 115.

The photoelectric conversion element provided on the layer 115 preferably has selenium or a compound of selenium. In a photoelectric conversion element using a selenium-based material, the photodetection sensitivity at low illuminance can be increased by utilizing the avalanche multiplication effect. Further, it may be a photodiode in which an organic semiconductor is used for the photoelectric conversion layer.

Further, the image pickup display device 100 may have the configuration of the image pickup display device 130 shown in FIG. 5 (A). The image pickup display device 130 has a configuration in which the layer 111, the layer 112, the layer 114, and the layer 113 are sequentially laminated.

In the image pickup display device 130, the elements of the image pickup unit 101 can be provided on the layer 111, the layer 112, and the layer 114. Further, the elements of the display unit 102 can be provided on the layer 112, the layer 114, and the layer 113.

As shown in the explanatory diagram of each layer in FIG. 5C, the layer 114 has a region 154 and a region 155. The region 154 and the region 155 have a transistor having a metal oxide as a channel forming region. It should be noted that there are a plurality of regions 155, and circuits having different functions can be provided in each region.

The region 154 has a configuration in which elements of the pixel circuit of the image pickup unit 101 (excluding the photoelectric conversion element) and elements of the pixel circuit of the display unit 102 (excluding the display element) are mixed. The region 155 may be provided with a pixel circuit of the image pickup unit 101, a drive circuit of the pixel circuit of the display unit 102, or the like.

FIG. 6B is a diagram illustrating an example of electrical connection of elements constituting one pixel in the image pickup display device 130. The region 153 has a photoelectric conversion element 161. Region 151 includes transistors 165a, 165b, and a connection 166. Region 154 has transistors 167a and 167b. The region 150 has a display element 163.

The transistors 165a, 165b, 167a, and 167b are part of the pixel circuit 167 of the image pickup unit 101 and the display unit 102. The connection portion 166 can be a through hole or the like formed on a silicon substrate.

The photoelectric conversion element 161 and the transistors 165a and 165b, the transistors 167a and 167b, and the display element 163 are arranged in a matrix in the region 153, the region 151, the region 154, or the region 150, respectively.

The photoelectric conversion element 161 is arranged so as to have a region overlapping with the transistors 165a and 165b. One electrode of the photoelectric conversion element 161 is electrically connected to one of the source or drain of the transistor 167a via the connection portion 166.

Any of the transistors 165a and 165b is arranged so as to have a region overlapping with any of the transistors 167a and 167b. The gate of transistor 165a is electrically connected to the other of the source or drain of transistor 167a.

The transistors 167a and 167b are arranged so as to have a region overlapping with the display element 163. One of the source or drain of the transistor 167b is electrically connected to one of the electrodes of the display element 163.

The details of the circuit corresponding to the pixel circuit 167 will be described later, but the gate of the transistor 167b is electrically connected to the other of the source or drain of the transistor 167a.

Further, FIG. 7B is a diagram illustrating the electrical connection between the pixel circuit 167 in the image pickup display device 130, the circuits 155a and 155b provided in the region 155, and the circuits 152e, 152f, 152g and 152h. be. The circuits 155a, 155b, 152e, 152f, 152g, 152h can have a function of driving the pixel circuit 167, a function of reading a signal from the pixel circuit 167, and the like.

The circuits 155a and 155b provided on the layer 114 can have a function as a low driver of the display unit 102. The circuits 155a and 155b can be electrically connected to the elements of the pixel circuit 167 provided in the layer 114 via wiring.

The circuit 152h provided on the layer 112 can have a function as a column driver for the display unit 102. The circuit 152h can be electrically connected to the element of the pixel circuit 167 provided in the layer 114 via wiring.

The circuits 152e and 152g provided on the layer 112 can have a function as a low driver of the image pickup unit 101. The circuit 152e can be electrically connected to the element of the pixel circuit 167 provided in the layer 112 via wiring. The circuit 152g can be electrically connected to the element of the pixel circuit 167 provided in the layer 114 via wiring.

The circuit 152f provided on the layer 112 can have a function as a column driver of the imaging unit 101. Further, the circuit 152f may have a function of a CDS circuit and an A / D converter for removing noise. The circuit 152f is electrically connected to the element of the pixel circuit 167 provided in the layer 112 via wiring.

Further, as shown in the explanatory diagram of each layer in FIG. 5D, the relative area of the region 155 in the layer 114 can be increased by reducing the relative area of the region 154 in the layer 114. At this time, in addition to the drive circuit described above, the region 155 may be provided with any element of the data processing unit 200 or a part of the circuit included in the element.

Further, the image pickup display device 100 may have the configuration of the image pickup display device 140 shown in FIG. 5 (B). The image pickup display device 140 has a configuration in which the photoelectric conversion element is different from that of the image pickup display device 130, and has a layer 115 provided with a photoelectric conversion element having selenium or a compound of selenium.

Although the embodiment in which the circuit electrically connected to the image pickup unit 101 and the display unit 102 is provided in the area 152 or the area 155 has been described above, the circuit may be provided in an external IC chip.

A configuration example of a pixel circuit that can be used as the pixel circuit 162 or the pixel circuit 167 described above will be described with reference to FIGS. 8 (A) to 14 (B). In FIGS. 8A to 14B, the reference numerals of elements such as transistors having a common function are the same. Although it cannot be strictly separated, the portion that mainly operates as a pixel of the display unit 102 is referred to as the circuit unit 102a.

The pixel circuit 171 shown in FIG. 8A is one of the basic configurations of one aspect of the present invention. The pixel circuit 171 has a function of determining the potential of the charge detection unit ND with a photoelectric conversion element and causing the display element to emit light according to the potential of the charge detection unit ND. Therefore, the operation from imaging to display can be performed at high speed without going through steps such as data conversion.

The pixel circuit 171 includes a photoelectric conversion element 10, a transistor 51, a transistor 52, a transistor 53, a display element 11, and a capacitive element 60.

The photoelectric conversion element 10 corresponds to the photoelectric conversion element 161 shown in FIGS. 6A and 6B. The transistor 52 corresponds to the transistor 162a or the transistor 167a shown in FIGS. 6A and 6B. The transistor 53 corresponds to the transistor 162b or the transistor 167b shown in FIGS. 6A and 6B. The display element 11 corresponds to the display element 163 shown in FIGS. 6A and 6B.

One of the source and drain of the transistor 51 is electrically connected to one electrode (anode) of the photoelectric conversion element 10. One electrode of the photoelectric conversion element 10 is electrically connected to one of the source and drain of the transistor 52. The other of the source or drain of the transistor 52 is electrically connected to the gate of the transistor 53. One of the source and drain of the transistor 53 is electrically connected to one electrode (anode) of the display element 11. The gate of the transistor 53 is electrically connected to one of the electrodes of the capacitive element 60. It should be noted that the configuration may be such that the capacitive element 60 is not provided.

The other electrode (cathode) of the photoelectric conversion element 10 is electrically connected to the wiring 72. The gate of the transistor 51 is electrically connected to the wiring 76. The gate of the transistor 52 is electrically connected to the wiring 75. The other of the source or drain of the transistor 51 is electrically connected to the wiring 73. The other of the source or drain of the transistor 53 is electrically connected to the wiring 74. The other electrode (cathode) of the display element 11 is electrically connected to the wiring 86. The other electrode of the capacitive element 60 is electrically connected to the wiring 77.

Wiring 72, 73, 74, 77, 86 can have a function as a power line. For example, the wiring 73, 77, 86 can function as a low-potential power line, and the wiring 74 can function as a high-potential power line. The wirings 75 and 76 can function as signal lines for controlling the on / off of each transistor.

As the photoelectric conversion element 10, a photoelectric conversion element that produces an avalanche multiplication effect may be used in order to increase the photodetection sensitivity at low illuminance. In order to generate the avalanche multiplication effect, a relatively high potential HSiO (for example, a potential of 10 V or more and higher than VDD) is required. Therefore, it is preferable that the wiring 72 is electrically connected to a power source capable of supplying the potential H VDD. The photoelectric conversion element 10 can also be used by applying a potential that does not cause the avalanche multiplication effect. Further, as the photoelectric conversion element 10, an element that does not generate an avalanche multiplication effect can also be used.

The transistor 51 can have a function of initializing the potential of the charge detection unit ND. The transistor 52 can have a function of controlling the charge detection unit ND. The transistor 53 can have a function of controlling the current flowing through the display element 11 according to the potential of the charge detection unit ND.

As shown in the pixel circuit 172 shown in FIG. 8B, one of the source and drain of the transistor 54 is electrically connected to the gate of the transistor 53, and one electrode of the capacitive element 60 is connected to the other of the source and drain. It may be configured to be electrically connected. At this time, a wiring 87 that can function as a signal line is electrically connected to the gate of the transistor 54.

By configuring the pixel circuit 172, the capacitance value of the charge detection unit ND can be made variable. Therefore, high-sensitivity imaging can be performed by turning off the transistor 54 in a low-light environment. Further, in a high illuminance environment, by turning on the transistor 54, it is possible to perform low-sensitivity imaging.

In the pixel circuits 171 and 172, the sensitivity can be adjusted for imaging by making the potential supplied to the wiring 74 variable. In particular, by increasing the potential supplied to the wiring 74, the brightness of the display element 11 can be increased, which is suitable for applications such as a night-vision scope.

When a high voltage is applied to the photoelectric conversion element 10, it is necessary to use a transistor having a high withstand voltage as the transistor connected to the photoelectric conversion element 10. As the high withstand voltage transistor, for example, a transistor using a metal oxide in the channel forming region (hereinafter referred to as an OS transistor) can be used. Specifically, it is preferable to apply an OS transistor to the transistor 51 and the transistor 52.

Further, due to the low off-current characteristics of the transistor 51 and the transistor 52, the period during which the charge can be held by the charge detection unit ND can be made extremely long. Therefore, it is possible to apply the global shutter method that simultaneously accumulates charges in all pixels without complicating the circuit configuration and operation method.

Therefore, when a high voltage is applied to the photoelectric conversion element 10, it is preferable to use the configuration of the image pickup display device 130 or the image pickup display device 140. When the pixel circuits 171 and 172 are applied to the image pickup display device 130 or the image pickup display device 140, the transistors 165a and 165b are not required.

When the photoelectric conversion element 10 is used without applying a high voltage, a transistor using silicon in the active layer or active region (hereinafter, Si transistor) may be applied to the transistor 51 and the transistor 52. Therefore, the configuration of the image pickup display device 110 or the image pickup display device 120 can also be used.

It is preferable to use a light emitting element as the display element 11. As the light emitting element, an organic EL element (OLED) including a light emitting layer of an organic substance can be used. The organic EL element exhibits diode characteristics, and a current can be passed by applying a forward bias. Further, the brightness can be changed by adjusting the current with a transistor.

Next, the basic operation of the pixel circuits 171 and 172 will be described with reference to the timing chart of FIG. 8C. In the operation of the example described below, it is assumed that the potentials of VDD are supplied as "H" and the potential of GND is supplied as "L" to the wirings 75 and 76. It is assumed that the potential of VDD is supplied to the wirings 72 and 74. It is assumed that the potential of GND is supplied to the wirings 73, 77, 86. In addition, it is also possible to supply a potential other than the above to each wiring.

At time T1, the wiring 76 is set to "H" and the wiring 75 is set to "H", and the potential of the charge detection unit ND is set to the reset potential (GND) (reset operation). At this time, since the transistor 53 is non-conducting, the display element 11 does not emit light.

By setting the wiring 76 to "L" and the wiring 75 to "H" at time T2, the potential of the charge detection unit ND begins to change (accumulation operation). The potential of the charge detection unit ND changes from GND to VDD at the maximum depending on the intensity of the light incident on the photoelectric conversion element 10.

At time T3, the wiring 75 is set to "L", and the potential of the charge detection unit ND is determined. At this time, if the potential of the charge detection unit ND is larger than the threshold voltage of the transistor 53, the transistor 53 conducts, and the display element 11 emits light according to the current value (display operation).

After that, the display is continued for a certain period of time, and the reset operation is performed again at time T4. By repeating the above operation, the image pickup and display operations can be performed at high speed. Further, since the black display is appropriately inserted during the reset operation, afterimages of moving images can be reduced.

When the pixel circuits 171 and 172 are used, since imaging and display can be performed with simple control as described above, a pixel selection circuit such as a shift register is not required, and reset operation is performed for all pixels at the same time. Accumulation operation and display operation can be performed.

Further, one aspect of the present invention may be the configuration of the pixel circuit 173 shown in FIG. 9A. The pixel circuit 173 differs from the pixel circuit 171 in that the imaging data can be output to the outside of the pixel.

The pixel circuit 173 includes the configuration of the pixel circuit 171 and the transistor 55 and the transistor 56. The gate of the transistor 55 is electrically connected to the other of the source or drain of the transistor 52. One of the source or drain of the transistor 55 is electrically connected to one of the source or drain of the transistor 56.

The transistor 55 corresponds to the transistor 165a shown in FIG. 6 (B). The transistor 53 corresponds to the transistor 165b shown in FIG. 6 (B). The transistors 55 and 56 can also be provided in the region 151 of the image pickup display device 110 and 120.

The other of the source or drain of the transistor 55 is electrically connected to the wiring 79. The other of the source or drain of the transistor 56 is electrically connected to the wiring 71. The gate of the transistor 56 is electrically connected to the wiring 78.

The wiring 79 can have a function as a power line. For example, the wiring 79 can function as a high potential power line. The wiring 71 can have a function as an output line that outputs a signal from the pixel. The wiring 78 can function as a signal line for controlling the on / off of the transistor.

The transistor 55 can have a function of outputting a signal corresponding to the potential of the charge detection unit ND. The transistor 56 can have a function of selecting a pixel for reading a signal.

Since the transistor 55 is desired to have excellent amplification characteristics, it is preferably a transistor having a high on-current. Therefore, it is preferable to apply Si transistors to the transistors 55 and 56. Of course, OS transistors may be applied to the transistors 55 and 56.

Next, the basic operation of the pixel circuit 173 will be described with reference to the timing chart of FIG. 9B. In the operation of the example described below, it is assumed that the potentials of VDD are supplied as "H" and the potential of GND is supplied as "L" to the wirings 75, 76, and 78. It is assumed that the potential of VDD is supplied to the wirings 72, 74, and 79. It is assumed that the potential of GND is supplied to the wirings 73, 77, 86. In addition, it is also possible to supply a potential other than the above to each wiring.

For the operations at times T1 to T3, the description in FIG. 8B can be referred to.

By setting the wiring 78 to "H" at time T4, the transistor 56 is made conductive, and an image signal corresponding to the potential of the charge detection unit ND is output to the wiring 71.

After that, the reset operation is performed again at time T5. By repeating the above operation, the image pickup and display operations can be performed at high speed, and the image data can be output to the outside.

When the pixel circuit 173 is used, a low driver for selecting pixels for imaging and a column driver are required. The low driver and the column driver can be provided in the area 152 or the like.

Further, one aspect of the present invention may be the configuration of the pixel circuit 174 shown in FIG. 10 (A). The pixel circuit 174 differs from the pixel circuit 173 in that an arbitrary image different from the captured image can be superimposed and displayed.

The pixel circuit 174 includes a configuration of the pixel circuit 173, a transistor 57, a transistor 58, and a display element 12.

One of the source or drain of the transistor 57 is electrically connected to one of the electrodes of the display element 12. The gate of transistor 57 is electrically connected to either the source or drain of transistor 58. The other of the source or drain of the transistor 57 is electrically connected to the wiring 74. The other electrode of the display element 12 is electrically connected to the wiring 86. The other of the source or drain of the transistor 58 is electrically connected to the wiring 81. The gate of the transistor 58 is electrically connected to the wiring 80.

The transistors 57 and 58 can be provided in the area 151 of the image pickup display devices 110 and 120 or the area 154 of the image pickup display devices 130 and 140. The same element as the display element 11 can be used for the display element 12, and the display element 12 can be provided in the region 150.

The wirings 80 and 81 can have a function as a signal line. For example, the wiring 80 can function as a signal line for controlling the on / off of the transistor 58. The wiring 81 can function as a signal line for supplying an image signal.

The transistor 57 can have a function of controlling the current flowing through the display element 12 according to the potential supplied from the wiring 81. The transistor 58 can have a function of selecting a pixel to perform an arbitrary display.

Since the image pickup display device using the pixel circuit 174 can display an arbitrary image by using the transistors 57 and 58 and the display element 12, it is possible to perform AR display in which information is superimposed on reality.

Next, the basic operation of the pixel circuit 173 will be described with reference to the timing chart of FIG. 10B. In the operation of the example described below, it is assumed that the wirings 75, 76, 78, and 80 are supplied with the potential of VDD as “H” and GND as “L”. It is assumed that the potential of VDD is supplied to the wirings 72, 74, and 79. It is assumed that the potential of GND is supplied to the wirings 73, 77, 86. It is assumed that an arbitrary potential (image signal) is supplied to the wiring 81. In addition, it is also possible to supply a potential other than the above to each wiring.

For the operation at time T1, the description of FIG. 8B can be referred to.

When the wiring 76 is set to "L", the wiring 75 is set to "H", and the wiring 80 is set to "H" at time T2, the potential of the charge detection unit ND begins to change (accumulation operation). The potential of the charge detection unit ND changes from GND to VDD at the maximum depending on the intensity of the light incident on the photoelectric conversion element 10. Further, the image signal supplied from the wiring 81 is written to the gate of the transistor 57.

At time T3, the wiring 75 is set to "L" and the wiring 80 is set to "L", and the potential of the charge detection unit ND is determined. At this time, if the potential of the charge detection unit ND is larger than the threshold voltage of the transistor 53, the transistor 53 conducts, and the display element 11 emits light according to the current value. Further, if the potential of the gate of the transistor 57 is larger than the threshold voltage of the transistor 57, the transistor 57 conducts, and the display element 12 emits light according to the current value (display operation).

For the operation after the time T4, the description of FIG. 9B can be referred to.

When the pixel circuit 174 is used, a low driver for selecting pixels for imaging and display and a column driver are required. The low driver and the column driver can be provided in the areas 152, 155 and the like.

Further, one aspect of the present invention may be the configuration of the pixel circuit 175 shown in FIG. 11 (A). The pixel circuit 175 has a configuration in which the display element 12 is omitted from the pixel circuit 174, and the other of the source or drain of the transistor 57 is electrically connected to one electrode of the display element 11.

In the configuration shown in FIG. 10 (A), whichever of the display element 11 and the display element 12 has the higher emission intensity is superior and appears on the display. Therefore, in order to display an arbitrary image on the display element 12, the emission intensity must be increased so as to overwrite the display on the display element 11. Even with the configuration of FIG. 11A, since the signal can be input from the wiring 81 so as to overwrite the original display of the display element 11, the display element 12 can be omitted.

Further, one aspect of the present invention may be the configuration of the pixel circuit 176 shown in FIG. 11B. The pixel circuit 176 has the configuration shown in FIG. 11A, a transistor 59, and a transistor 63.

One of the source or drain of the transistor 59 is electrically connected to the other of the source or drain of the transistor 52. The other of the source or drain of the transistor 59 is electrically connected to the gate of the transistor 53. The gate of transistor 59 is electrically connected to either the source or drain of transistor 63. The gate of the transistor 63 is electrically connected to the wiring 85. The other of the source or drain of the transistor 63 is electrically connected to the wiring 82.

The wiring 82 can function as a signal line for controlling the on / off of the transistor 59. The wiring 85 can function as a signal line for selecting pixels. It is also possible to electrically connect the gate of the transistor 59 and the wiring 82 without providing the transistor 63.

By making the transistor 59 non-conducting, it is possible to stop the image display at the same time as the image pickup. If the transistor 59 is made non-conducting in all the pixels, arbitrary image data supplied from the wiring 81 can be displayed in the entire display unit 102. Further, the data taken out to the outside via the wiring 71 and processed can be supplied from the wiring 81 and displayed. For example, it is possible to perform an enlarged display or a processed display of the captured image.

Further, if a pixel is selected and the transistor 59 is made non-conducting, the image display at the same time as the imaging can be stopped at the selected pixel. Further, if the transistor 59 is made non-conducting during the reset period, the transistor 53 becomes non-conducting and can be displayed in black. By displaying arbitrary image data supplied from the wiring 81 against the background of the black display pixel, a clear AR display can be performed.

If a low-potential power supply line is electrically connected to the gate of the transistor 53 via a switch (transistor or the like), the transistor 53 can be made non-conducting at any timing regardless of the reset period, and is displayed in black. can do.

Further, one aspect of the present invention may be the configuration of the pixel circuit 177 shown in FIG. 12 (A). The pixel circuit 177 has a configuration in which a back gate is provided in each transistor. By applying a constant voltage to the back gate, the threshold voltage of each transistor can be adjusted. Further, the same potential as that of the front gate may be applied to control the on current and the off current. Although FIG. 12A shows a configuration in which a back gate is provided in all the transistors, a transistor without a back gate may be provided.

Further, one aspect of the present invention may be the configuration of the pixel circuit 178 shown in FIG. 12 (B). The pixel circuit 178 is an example of a configuration in which the charge detection unit ND can be reset to a high potential and operated.

In the pixel circuit 178, the connection direction of the photoelectric conversion element 10 is reversed, and the transistor 53 is of the p-ch type, which is different from the pixel circuit described above. At this time, the transistor 53 is preferably a Si transistor. Further, in the operation of the pixel circuit 178, the wiring 72 has a low potential and the wiring 73 has a high potential.

In the pixel circuit 178, the potential of the charge detection unit ND is relatively low when the light intensity is high, and relatively high when the light intensity is low. Therefore, the transistor 53 is of the p-ch type, and is operated so that the light emission of the display element 11 becomes bright when the potential of the charge detection unit ND is low.

Further, one aspect of the present invention may be the configuration of the pixel circuit 179 shown in FIG. 13 (A). The pixel circuit 179 can also be operated by resetting the charge detection unit ND to a high potential.

The pixel circuit 179 includes a transistor 62 and a capacitive element 64 in addition to the configuration of the pixel circuit 175. One of the source or drain of the transistor 62 is electrically connected to the gate of the transistor 55. One electrode of the capacitive element 64 is electrically connected to the other of the source or drain of the transistor 52. The other electrode of the capacitive element 64 is electrically connected to the gate of the transistor 55. Further, the direction of connection of the photoelectric conversion element 10 is opposite to that of the pixel circuit 175.

The other of the source or drain of the transistor 62 is electrically connected to the wiring 85 and the gate is electrically connected to the wiring 84. The wiring 85 can have a function as a power supply line and can supply a high potential. The wiring 84 can have a function as a signal line for controlling the on / off of the transistor 62.

The wiring connecting one electrode of the photoelectric conversion element 10 and one of the source or drain of the transistor 52 is referred to as a charge storage unit RD1. Further, the wiring connecting the other of the source or drain of the transistor 52 and the capacitive element 64 is referred to as the charge storage unit RD2.

Next, the basic operation of the pixel circuit 179 will be described with reference to the timing chart of FIG. 13 (B). In the operation of the example described below, it is assumed that the wirings 75, 76, 78, 80, 84 are supplied with the potential of VDD as “H” and GND as “L”. It is assumed that the potential of GND is supplied to the wirings 72, 77, and 85. It is assumed that the potential of VDD is supplied to the wirings 73, 74, and 79. It is assumed that an arbitrary potential (image signal) is supplied to the wiring 81. In addition, it is also possible to supply a potential other than the above to each wiring.

At time T1, the wiring 76 is set to "H", the wiring 75 is set to "H", and the potentials of the charge storage units RD1 and RD2 are set to the first reset potential (SiO). At this time, since the potential of the charge detection unit ND rises due to the capacitive coupling by the capacitive element 64, the transistor 53 may be in a conductive state, and the display element 11 may emit light.

By setting the wiring 75 to "L" at the time T2 and the wiring 76 to "L" at the time T3, the potential of the charge storage unit RD1 begins to change. The potential of the charge storage unit RD1 changes from VDD to GND at the minimum depending on the intensity of the light incident on the photoelectric conversion element 10.

Assuming that the wiring 75 is "H" and the wiring 84 is "H" at time T4, the potential of the charge storage unit RD2 becomes the same as the potential of the charge storage unit RD1. Further, the potential of the charge detection unit ND is set to the second reset potential.

When the wiring 84 is set to "L" at time T5, the potential of the charge detection unit ND is lowered due to the capacitive coupling by the capacitive element 64.

When the wiring 76 is set to "H" at time T6, the potential of the charge storage unit RD1 becomes the first reset potential (SiO). In other words, the potentials of the charge storage units RD1 and RD2 increase by the amount of decrease during the exposure period (between time T3 and time T6). At this time, the potential of the charge detection unit ND increases in response to the increase in the potentials of the charge storage units RD1 and RD2 due to the capacitive coupling by the capacitive element 64. That is, the charge detection unit ND has a potential that reflects the exposure period, and the display element 11 emits light according to the potential.

In this operation, the higher the intensity of light, the smaller the potentials of the charge storage portions RD1 and RD2 during the exposure period, so that the difference from the first reset potential becomes larger. Therefore, the potential of the charge detection unit ND is relatively high when the light intensity is high, and relatively low when the light intensity is low.

Therefore, even if the transistor 53 is an n-ch type, the pixel circuit 179 can be operated so that the light emission of the display element 11 becomes bright when the potential of the charge detection unit ND is high.

In addition, T6 corresponds to T1, and by repeating the above operation, the operation of imaging and display can be performed at high speed.

Further, one aspect of the present invention may be the configuration of the pixel circuit 180 shown in FIG. 14 (A). The pixel circuit 180 is an example of a pixel circuit for performing correlated double sampling that cancels out noise of elements constituting a circuit such as a transistor. The CDS circuit that performs the correlated double sampling is provided by being electrically connected to the wiring 71. Correlated double sampling is performed by subtracting the reset signal from the image signal taken out by the wiring 71.

The pixel circuit 180 has a configuration in which the capacitive element 64 of the pixel circuit 179 is replaced with the transistor 61. Further, the direction of connection of the photoelectric conversion element is opposite to that of the pixel circuit 179. One of the source or drain of the transistor 61 is electrically connected to the other of the source or drain of the transistor 52. The other of the source or drain of the transistor 61 is electrically connected to the gate of the transistor 55.

The gate of the transistor 61 is electrically connected to the wiring 83. The wiring 83 can have a function as a signal line for controlling the on / off of the transistor 61.

The wiring connecting the other of the source or drain of the transistor 52 and one of the source or drain of the transistor 61 is referred to as a charge storage unit RD.

Next, the basic operation of the pixel circuit 180 will be described with reference to the timing chart of FIG. 14 (B). In the operation of the example described below, it is assumed that the wirings 75, 76, 78, 80, 84 are supplied with the potential of VDD as “H” and GND as “L”. It is assumed that the potential of VDD is supplied to the wirings 72, 74, and 79. It is assumed that the potential of GND is supplied to the wirings 73, 77, and 85. It is assumed that an arbitrary potential (image signal) is supplied to the wiring 81. In addition, it is also possible to supply a potential other than the above to each wiring.

At time T1, the wiring 76 is set to "H" and the wiring 75 is set to "H", and the potential of the charge storage unit RD is set to the reset potential (GND) (reset operation).

By setting the wiring 76 to "L" at time T2, the potential of the charge storage unit RD begins to change (storage operation). The potential of the charge storage unit RD changes from GND to VDD at the maximum depending on the intensity of the light incident on the photoelectric conversion element 10.

When the wiring 75 is set to "L" at time T3, the potential of the charge storage unit RD is fixed.

When the wiring 78 is set to "H" and the wiring 84 is set to "H" at time T4, the potential of the charge detection unit ND becomes the reset potential (GND), and the wiring 71 contains the reset potential (GND) including a noise signal such as a transistor. ) Is read out. At this time, the reset potential (GND) is stored in the CDS circuit. Further, at time T4, the display element 11 does not emit light.

When the wiring 84 is set to "L" at the time T5 and the wiring 83 is set to "H" at the time T6, the potential of the charge detection unit ND becomes the potential of the charge storage unit RD, and the wiring 71 contains a noise signal such as a transistor. The image signal potential is read out. Further, at time T5, the display element 11 emits light according to the potential of the charge detection unit ND.

In the CDS circuit, the operation of subtracting the reset potential (GND) including the noise signal of the transistor or the like stored earlier from the image signal potential containing the noise signal of the transistor or the like is performed, and the net image signal is taken out. ..

By setting the wiring 83 to "L" at the time T7 and the wiring 78 to "L" at the time T8, the extraction of the image data from which the noise has been removed is completed. Further, the time T8 corresponds to the time T1, and by repeating the above operation, it is possible to perform high-speed operation of imaging and display and extraction of image data from which noise has been removed.

The configurations of the pixel circuits 171 to 180 shown above as one aspect of the present invention can be arbitrarily combined.

15 (A), (B), and (C) are diagrams illustrating an example of an image displayed on the display unit 102. For example, suppose that an image is taken of a flower blooming on a hill or an airship floating in the sky as shown in FIG. 15 (A).

FIG. 15B is an example in which the subject information is added by the time and AR display. As described above, in order to add information and display it on the display unit, an operation such as overwriting the background image is performed. When the background image is dark, visibility is good if the information is displayed in light color, but when the background is light, visibility is improved even if the brightness of the information display is increased. Becomes difficult.

In such cases, it is preferable to display the information using complementary colors of the background color. For example, the characters "Airship" and "Sunflower" are preferably displayed in a complementary color to blue in the sky or in orange or yellow close to it. In addition, it is preferable that the time numbers are displayed in red or purple, which is a complementary color to the green of the hill or close to it.

Further, by using the configuration shown in the pixel circuit 176, it is possible to stop the image display at the same time as the imaging at the selected pixel. Therefore, as shown in FIG. 15C, visibility can be improved by hiding (black display) the captured image of the background of the area for displaying information such as characters and displaying the information in bright color. ..

Further, in the image pickup display device of one aspect of the present invention, unlike the see-through type display, the AR display can be added to the captured image, so that it is not necessary to adjust the position of the AR display with respect to the position of the viewer.

When the subject information as shown in FIG. 15A is obtained from the server, for an unknown subject, the image of the subject and the surrounding information are uploaded to the server, and a huge amount of information such as shape, color, place, and time is obtained. Search results must be obtained by collating with the database. Therefore, when obtaining information from the server, it is preferable to narrow down the subject categories as described above and then perform the search on the server.

In order to narrow down such categories, it is preferable to perform estimation using a neural network.

FIG. 16 is a diagram illustrating an operation of estimating a subject category by a neural network. The input data E ₁ to E _i (i is a natural number) correspond to features such as shape, color, and size extracted from the image P of the subject, as well as information such as position and time that can be acquired by the image pickup display device.

The input data E ₁ to E _i are input to the nodes F ₁ to _Fi of the input layer 501, respectively, and the weighted information is input to the first layer G ₁ of the intermediate layer 502. Here, the intermediate layer 502 has an arbitrary number of layers from G ₁ to G _j (j is a natural number). Further, each layer of the intermediate layer 502 has an arbitrary number of nodes. Then, the information output from the final layer _Gj of the intermediate layer 502 is input to the output layer 503. The output layer 503 outputs any one of H ₁ to H _k (k is a natural number) which is the estimation result of the category of the subject, or some of the category estimation results with high probability.

The estimation results of the categories, H ₁ to H _k , are at any level, from a rough category such as whether the subject is a natural object, an artificial object, or a living thing to a detailed category to the extent that the subject is identified. good.

Then, the image P of the subject, the input data _E1 to _Ei , and the estimation result of the category are transmitted to the server 505, and the information of the subject is searched. The more detailed the estimation result, the narrower the database required for the search on the server 505, so that the search time can be shortened.

However, since the image pickup display device has restrictions on the chip area and processing speed of the neural network, it is preferable to estimate the category to the minimum necessary and use it in cooperation with the server 505. For example, assuming that the database of the server 505 has information, if the subject is a building, the estimation result that the category is a building, the image, and the position information are obtained at high speed with sufficiently high accuracy. be able to. Also, if the subject is a person, the estimation result that the category is a person (including information such as gender, height, age) and the image (preferably including a face) can identify the individual at high speed. It is also possible.

Next, a configuration example of a neural network that can be used in one aspect of the present invention will be described in detail with reference to FIGS. 17A to 17C. The neural network NN is composed of a neuron circuit and a synaptic circuit provided between the neuron circuits.

FIG. 17A is a configuration example of the neuron circuit NC and the synapse circuit SC constituting the neural network NN. Input data x ₁ to x _L (L is a natural number) are input to the synapse circuit SC. Further, the synapse circuit SC has a function of storing a weighting coefficient w _k (k is an integer of 1 or more and L or less). The weighting factor w _k corresponds to the strength of the connection between the neuron circuits NC.

When the input data x ₁ to x _L are input to the synaptic circuit SC, the neuron circuit NC is the product of the input data x _k input to the synaptic circuit SC and the weighting coefficient w _k stored in the synaptic circuit SC. (X _k w _k ) is obtained by adding up values (x ₁ w ₁ + x ₂ w ₂ + ... + x _L w _L ) for k = 1 to L, that is, by a product-sum operation using x _k and w _k . The given value is supplied. When this value exceeds the threshold value θ of the neuron circuit NC, the neuron circuit NC outputs a high-level signal y. This phenomenon is called firing of the neuron circuit NC.

FIG. 17B shows an example of a model of the neural network NN. The neural network NN has a hierarchical perceptron configuration using a neuron circuit NC and a synaptic circuit SC, and has an input layer IL, a hidden layer (intermediate layer) HL, and an output layer OL.

The input layer IL can output the input data x ₁ to x _L to the hidden layer HL. The hidden layer HL has a hidden synaptic circuit HS and a hidden neuron circuit HN. The output layer OL has an output synapse circuit OS and an output neuron circuit ON.

The hidden neuron circuit HN is supplied with a value obtained by a product-sum operation using the input data x _k and the weighting coefficient w _k held in the hidden synapse circuit HS. Then, the output of the hidden neuron circuit HN and the value obtained by the product-sum operation using the weighting coefficient _wk held in the output synapse circuit OS are supplied to the output neuron circuit ON. Then, the output data _y1 to _yL are output from the output neuron circuit ON.

As described above, the neural network NN to which the predetermined input data is given has a function of outputting the weighting coefficient held in the synapse circuit SC and the value corresponding to the threshold value θ of the neuron circuit as output data.

Further, the neural network NN can perform supervised learning by inputting teacher data. FIG. 17C shows a model of a neural network NN that performs supervised learning using the backpropagation method.

The error back propagation method is a method of changing the weighting coefficient _wk of the synaptic circuit so that the error between the output data of the neural network and the teacher signal becomes small. Specifically, the weighting coefficient w _k of the hidden synaptic circuit HS is changed according to the error δ _O determined based on the output data y ₁ to y _L and the teacher data t ₁ to t _L. Further, the weighting coefficient _wk of the synaptic circuit SC in the previous stage is further changed according to the amount of change of the weighting coefficient _wk of the hidden synaptic circuit HS. In this way, the neural network NN can be learned by sequentially changing the weighting coefficient of the synaptic circuit SC based on the teacher data t ₁ to t _L.

The neural network configuration shown in FIG. 17 can be used for the neural network 207 in FIG. Further, the above error back propagation method can be used for learning the neural network 207.

Although FIGS. 17B and 17C show one hidden layer HL, the number of hidden layer HL can be two or more. Deep learning can be performed by using a neural network (deep neural network (DNN)) having two or more hidden layers HL. This makes it possible to improve the accuracy of image generation.

As described above, by using one aspect of the present invention, information on the subject can be quickly obtained, and AR display with good consistency with reality can be performed.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 2)
In this embodiment, a configuration example of a semiconductor device that can be used for the neural network described in the above embodiment will be described.

When the neural network is configured by hardware, the product-sum operation in the neural network can be performed by using the product-sum calculation element. In this embodiment, a configuration example of a semiconductor device that can be used as a product-sum calculation element in the neural network 207 will be described.

<Semiconductor device configuration example>
An example of the configuration of the semiconductor device 600 is shown in FIG. The semiconductor device 600 shown in FIG. 18 includes a storage circuit 610 (MEM), a reference storage circuit 620 (RMEM), a circuit 630, and a circuit 640. The semiconductor device 600 may further include a current source circuit 650 (CREF).

The storage circuit 610 (MEM) has a memory cell MC exemplified by the memory cell MC [i, j] and the memory cell MC [i + 1, j]. Further, each memory cell MC has an element having a function of converting an input potential into a current. As an element having the above function, an active element such as a transistor can be used. FIG. 18 illustrates a case where each memory cell MC has a transistor Tr11.

Then, the first analog potential is input to the memory cell MC from the wiring WD exemplified by the wiring WD [j]. The first analog potential corresponds to the first analog data. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr11 obtained when the first analog potential is supplied to the gate of the transistor Tr11 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC [i, j] is referred to as I [i, j], and the current flowing through the memory cell MC [i + 1, j] is referred to as I [i + 1, j].

When the transistor Tr11 operates in the saturation region, its drain current does not depend on the voltage between the source and drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is desirable to operate the transistor Tr11 in the saturation region. In order to operate the transistor Tr11 in the saturation region, it is assumed that the gate voltage and the voltage between the source and the drain are appropriately set to the voltage in the range in which the transistor Tr11 operates in the saturation region.

Specifically, in the semiconductor device 600 shown in FIG. 18, the first analog potential Vx [i, j] or the first analog potential Vx [i, j] is connected to the memory cell MC [i, j] from the wiring WD [j]. ] The potential corresponding to is input. The memory cell MC [i, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i, j]. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the first analog current.

Specifically, in the semiconductor device 600 shown in FIG. 18, the first analog potential Vx [i + 1, j] or the first analog potential Vx [i + 1] from the wiring WD [j] to the memory cell MC [i + 1, j]. , J], the potential is input. The memory cell MC [i + 1, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i + 1, j]. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the first analog current.

The memory cell MC has a function of holding the first analog potential. That is, it can be said that the memory cell MC has a function of holding the first analog current corresponding to the first analog potential by holding the first analog potential.

Further, a second analog potential is input to the memory cell MC from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The second analog potential corresponds to the second analog data. The memory cell MC has a function of adding a potential corresponding to a second analog potential or a second analog potential to the already held first analog potential, and a third analog potential obtained by the addition. It has a function to hold. Then, the memory cell MC has a function of generating a second analog current corresponding to the third analog potential. That is, it can be said that the memory cell MC has a function of holding a second analog current corresponding to the third analog potential by holding the third analog potential.

Specifically, in the semiconductor device 600 shown in FIG. 18, the second analog potential Vw [i, j] is input from the wiring RW [i] to the memory cell MC [i, j]. The memory cell MC [i, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i, j] and the second analog potential Vw [i, j]. The memory cell MC [i, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the second analog current.

Further, in the semiconductor device 600 shown in FIG. 18, a second analog potential Vw [i + 1, j] is input from the wiring RW [i + 1] to the memory cell MC [i + 1, j]. The memory cell MC [i + 1, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the second analog current.

Then, the current I [i, j] flows between the wiring BL [j] and the wiring VR [j] via the memory cell MC [i, j]. The current I [i + 1, j] flows between the wiring BL [j] and the wiring VR [j] via the memory cells MC [i + 1, j]. Therefore, the current I [j] corresponding to the sum of the current I [i, j] and the current I [i + 1, j] passes through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. It will flow between the wiring BL [j] and the wiring VR [j].

The reference storage circuit 620 (RMEM) has a memory cell MCR exemplified by the memory cell MCR [i] and the memory cell MCR [i + 1]. The first reference potential VPR is input to the memory cell MCR from the wiring WDREF. Then, the memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR [i] is referred to as IREF [i], and the current flowing through the memory cell MCR [i + 1] is referred to as IREF [i + 1].

Specifically, in the semiconductor device 600 shown in FIG. 18, the first reference potential VPR is input from the wiring WDREF to the memory cell MCR [i]. The memory cell MCR [i] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the first reference current.

Further, in the semiconductor device 600 shown in FIG. 18, the first reference potential VPR is input from the wiring WDREF to the memory cell MCR [i + 1]. The memory cell MCR [i + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the first reference current.

The memory cell MCR has a function of holding the first reference potential VPR. That is, it can be said that the memory cell MCR has a function of holding the first reference current corresponding to the first reference potential VPR by holding the first reference potential VPR.

Further, a second analog potential is input to the memory cell MCR from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MCR holds the second reference potential obtained by adding the potential corresponding to the second analog potential or the second analog potential to the already held first reference potential VPR and adding the potentials. Has the function of Then, the memory cell MCR has a function of generating a second reference current according to the second reference potential. That is, it can be said that the memory cell MCR has a function of holding the second reference current corresponding to the second reference potential by holding the second reference potential.

Specifically, in the semiconductor device 600 shown in FIG. 18, the second analog potential Vw [i, j] is input from the wiring RW [i] to the memory cell MCR [i]. The memory cell MCR [i] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i, j]. The memory cell MCR [i] has a function of generating a second reference current according to the second reference potential. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the second reference current.

Further, in the semiconductor device 600 shown in FIG. 18, a second analog potential Vw [i + 1, j] is input from the wiring RW [i + 1] to the memory cell MCR [i + 1]. The memory cell MCR [i + 1] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i + 1, j]. The memory cell MCR [i + 1] has a function of generating a second reference current according to the second reference potential. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the second reference current.

Then, the current IREF [i] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i]. The current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i + 1]. Therefore, the current IREF corresponding to the sum of the current IREF [i] and the current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1]. Become.

The current source circuit 650 has a function of supplying the wiring BL with a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF. Then, when setting the offset current described later, the current flowing between the wiring BL [j] and the wiring VR [j] via the memory cells MC [i, j] and the memory cells MC [i + 1, j]. If I [j] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1], the differential current will flow in circuit 630 or circuit 640. The circuit 630 has a function as a current source circuit, and the circuit 640 has a function as a current sink circuit.

Specifically, when the current I [j] is larger than the current IREF, the circuit 630 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. Further, the circuit 630 has a function of supplying the generated current ΔI [j] to the wiring BL [j]. That is, it can be said that the circuit 630 has a function of holding the current ΔI [j].

Further, when the current I [j] is smaller than the current IREF, the circuit 640 has a function of generating a current corresponding to the absolute value of the current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. .. Further, the circuit 640 has a function of drawing the generated current ΔI [j] from the wiring BL [j]. That is, it can be said that the circuit 640 has a function of holding the current ΔI [j].

Next, an example of the operation of the semiconductor device 600 shown in FIG. 18 will be described.

First, the potential corresponding to the first analog potential is stored in the memory cell MC [i, j]. Specifically, the potential VPR-Vx [i, j] obtained by subtracting the first analog potential Vx [i, j] from the first reference potential VPR is the memory cell MC [i] via the wiring WD [j]. , J]. In the memory cell MC [i, j], the potential VPR-Vx [i, j] is held. Further, in the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR-Vx [i, j] is generated. For example, the first reference potential VPR is set to a potential higher than the ground potential. Specifically, it is desirable that the potential is higher than the ground potential and equal to or lower than the high-level potential VDD supplied to the current source circuit 650.

Further, the first reference potential VPR is stored in the memory cell MCR [i]. Specifically, the potential VPR is input to the memory cell MCR [i] via the wiring WDREF. The potential VPR is held in the memory cell MCR [i]. Further, in the memory cell MCR [i], the current IREF [i] corresponding to the potential VPR is generated.

Further, the potential corresponding to the first analog potential is stored in the memory cell MC [i + 1, j]. Specifically, the potential VPR-Vx [i + 1, j] obtained by subtracting the first analog potential Vx [i + 1, j] from the first reference potential VPR is the memory cell MC [i + 1] via the wiring WD [j]. , J]. In the memory cell MC [i + 1, j], the potential VPR-Vx [i + 1, j] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR-Vx [i + 1, j] is generated.

Further, the first reference potential VPR is stored in the memory cell MCR [i + 1]. Specifically, the potential VPR is input to the memory cell MCR [i + 1] via the wiring WDREF. The potential VPR is held in the memory cell MCR [i + 1]. Further, in the memory cell MCR [i + 1], a current IREF [i + 1] corresponding to the potential VPR is generated.

In the above operation, the wiring RW [i] and the wiring RW [i + 1] are set to the reference potential. For example, as the reference potential, a ground potential, a low level potential VSS lower than the reference potential, or the like can be used. Alternatively, if a potential between the potential VSS and the potential VDD is used as the reference potential, the potential of the wiring RW can be made higher than the reference potential even if the second analog potential Vw is positive or negative, so that signal generation can be facilitated. This is preferable because it enables product calculation for positive and negative analog data.

By the above operation, a current including the currents generated in the memory cells MC connected to the wiring BL [j] flows through the wiring BL [j]. Specifically, in FIG. 18, the current I [i, j] generated by the memory cell MC [i, j] and the current I [i + 1, j] generated by the memory cell MC [i + 1, j] are combined. The current I [j] flows. Further, by the above operation, a current including the currents generated in the memory cells MCR connected to the wiring BLREF will flow through the wiring BLREF. Specifically, in FIG. 18, a current IREF that is a combination of the current IREF [i] generated by the memory cell MCR [i] and the current IREF [i + 1] generated by the memory cell MCR [i + 1] flows.

Next, by inputting the current I [j] obtained by inputting the first analog potential and the first reference potential while keeping the potentials of the wiring RW [i] and the wiring RW [i + 1] as the reference potentials. The offset current OFFset [j] obtained from the difference from the obtained current IREF is held in the circuit 630 or the circuit 640.

Specifically, when the current I [j] is larger than the current IREF, the circuit 630 supplies the current Office [j] to the wiring BL [j]. That is, the current ICM [j] flowing through the circuit 630 corresponds to the current Office [j]. Then, the value of the current ICM [j] is held in the circuit 630. Further, when the current I [j] is smaller than the current IREF, the circuit 640 draws the current Office [j] from the wiring BL [j]. That is, the current ICP [j] flowing through the circuit 640 corresponds to the current Office [j]. Then, the value of the current ICP [j] is held in the circuit 640.

Then, depending on the second analog potential or the second analog potential so as to add to the potential corresponding to the first analog potential or the first analog potential already held in the memory cell MC [i, j]. The potential is stored in the memory cell MC [i, j]. Specifically, by setting the potential of the wiring RW [i] to a potential higher than the reference potential by Vw [i], the second analog potential Vw [i] becomes a memory via the wiring RW [i]. It is input to the cell MC [i, j]. In the memory cell MC [i, j], the potential VPR-Vx [i, j] + Vw [i] is held. Further, in the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR-Vx [i, j] + Vw [i] is generated.

Further, according to the second analog potential or the second analog potential so as to be added to the potential corresponding to the first analog potential or the first analog potential already held in the memory cell MC [i + 1, j]. The potential is stored in the memory cell MC [i + 1, j]. Specifically, by setting the potential of the wiring RW [i + 1] to a potential higher than the reference potential by Vw [i + 1], the second analog potential Vw [i + 1] becomes a memory via the wiring RW [i + 1]. It is input to the cell MC [i + 1, j]. In the memory cell MC [i + 1, j], the potential VPR-Vx [i + 1, j] + Vw [i + 1] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR-Vx [i + 1, j] + Vw [i + 1] is generated.

When the transistor Tr11 operating in the saturation region is used as an element for converting the potential into a current, the potential of the wiring RW [i] is Vw [i] and the potential of the wiring RW [i + 1] is Vw [i + 1]. Assuming that, since the drain current of the transistor Tr11 of the memory cell MC [i, j] corresponds to the current I [i, j], the second analog current is expressed by the following equation 1. Note that k is a coefficient and Vth is the threshold voltage of the transistor Tr11.

I [i, j] = k (Vw [i] -Vth + VPR-Vx [i, j]) ² (Equation 1)

Further, since the drain current of the transistor Tr11 of the memory cell MCR [i] corresponds to the current IREF [i], the second reference current is represented by the following equation 2.

IREF [i] = k (Vw [i] -Vth + VPR) ² (Equation 2)

Then, the current I [j] corresponding to the sum of the current I [i, j] flowing in the memory cell MC [i, j] and the current I [i + 1, j] flowing in the memory cell MC [i + 1, j] is I [j] = Σ _i I [i, j], and the current corresponding to the sum of the current IREF [i] flowing in the memory cell MCR [i] and the current IREF [i + 1] flowing in the memory cell MCR [i + 1]. The IREF is IREF = Σ _i IREF [i], and the current ΔI [j] corresponding to the difference is expressed by the following equation 3.

ΔI [j] = IREF-I [j] = Σ _i IREF [i] -Σ _i I [i, j] (Equation 3)

From Equation 1, Equation 2, and Equation 3, the current ΔI [j] is derived as in Equation 4 below.

ΔI [j]
= Σ _i {k (Vw [i] -Vth + VPR) ² -k (Vw [i] -Vth + VPR-Vx [i, j]) ² }
= 2kΣ _i (Vw [i], Vx [i, j])-2kΣ _i (Vth-VPR), Vx [i, j] -kΣ _i Vx [i, j] ² (Equation 4)

In Equation 4, the term represented by 2kΣ _i (Vw [i] · Vx [i, j]) is the product of the first analog potential Vx [i, j] and the second analog potential Vw [i]. It corresponds to the sum of the product of the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

Further, Office [j] is when all the potentials of the wiring RW [i] are set as reference potentials, that is, when the second analog potential Vw [i] is set to 0 and the second analog potential Vw [i + 1] is set to 0. Given the current ΔI [j] of, the following equation 5 is derived from the equation 4.

Office [j] = -2kΣ _i (Vth-VPR) · Vx [i, j] -kΣ _i Vx [i, j] ² (Equation 5)

Therefore, from Equations 3 to 5, the 2kΣ _i (Vw [i] · Vx [i, j]) corresponding to the sum of products of the first analog data and the second analog data is shown in Equation 6 below. It turns out that it will be done.

2kΣ _i (Vw [i] · Vx [i, j]) = IREF-I [j] -Offset [j] (Equation 6)

If the sum of the currents flowing in the memory cell MC is the current I [j], the sum of the currents flowing in the memory cell MCR is the current IREF, and the current flowing in the circuit 630 or the circuit 640 is the current office [j], the wiring RW [i]. ] Is Vw [i], and the potential of the wiring RW [i + 1] is Vw [i + 1]. It is represented by. From Equation 6, the current Iout [j] is 2kΣ _i (Vw [i] · Vx [i, j]), the first analog potential Vx [i, j] and the second analog potential Vw [i]. It can be seen that it corresponds to the sum of the product of the first analog potential Vx [i + 1, j] and the product of the second analog potential Vw [i + 1].

It is desirable to operate the transistor Tr11 in the saturation region, but even if the operating region of the transistor Tr11 is different from the ideal saturation region, the first analog potential Vx [i, j] and the second analog potential A current corresponding to the product of the product of Vw [i] and the product of the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1] can be obtained without any problem with an accuracy within a desired range. If this is possible, the transistor Tr11 can be regarded as operating in the saturation region.

According to one aspect of the present invention, the arithmetic processing of analog data can be executed without being converted into digital data, so that the circuit scale of the semiconductor device can be kept small. Further, according to one aspect of the present invention, the calculation process of analog data can be executed without being converted into digital data, so that the time required for the calculation process of analog data can be suppressed. Further, according to one aspect of the present invention, it is possible to reduce the power consumption of the semiconductor device while suppressing the time required for the arithmetic processing of analog data.

<Example of memory circuit configuration>
Next, an example of a specific configuration of the storage circuit 610 (MEM) and the reference storage circuit 620 (RMEM) will be described with reference to FIG.

In FIG. 19, the storage circuit 610 (MEM) has a plurality of memory cells MC in y rows and x columns (x and y are natural numbers), and the reference storage circuit 620 (RMEM) has a plurality of memory cells in y rows and 1 column. The case of having an MCR is illustrated.

The storage circuit 610 is connected to the wiring RW, the wiring WW, the wiring WD, the wiring VR, and the wiring BL. In FIG. 19, the wiring RW [1] to the wiring RW [y] are connected to the memory cell MC of each row, and the wiring WW [1] to the wiring WW [y] are connected to the memory cell MC of each row, respectively, and the wiring WD. Illustrate the case where the wiring WD [x] to the wiring WD [x] is connected to the memory cell MC of each row, and the wiring BL [1] to the wiring BL [x] are connected to the memory cell MC of each row. There is. Further, FIG. 19 illustrates a case where the wiring VR [1] to the wiring VR [x] are connected to the memory cells MC in each column. The wiring VR [1] to the wiring VR [x] may be connected to each other.

The reference storage circuit 620 is connected to the wiring RW, the wiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. In FIG. 19, wiring RW [1] to wiring RW [y] are connected to the memory cell MCR of each row, wiring WW [1] to wiring WW [y] are connected to the memory cell MCR of each row, respectively, and wiring WDREF. Is connected to each row of memory cells MCR, the wiring BLREF is connected to each row of memory cells MCR, and the wiring VRREF is connected to each row of memory cells MCR. The wiring VRREF may be connected to the wiring VR [1] to the wiring VR [x].

Next, among the plurality of memory cell MCs shown in FIG. 19, any two-row, two-column memory cell MC, and among the plurality of memory cell MCRs shown in FIG. 19, any two-row, one-column memory cell MCR. The specific circuit configuration and connection relationship with the above are shown in FIG. 20 as an example.

Specifically, in FIG. 20, the memory cell MC [i, j] in the i-row j-th column, the memory cell MC [i + 1, j] in the i + 1-row j-th column, and the memory cell MC [i + 1, j] in the i-row j + 1-th column. , J + 1] and the memory cells MC [i + 1, j + 1] in the i + 1 row, j + 1 column. Specifically, FIG. 20 illustrates the memory cell MCR [i] in the i-th row and the memory cell MCR [i + 1] in the i + 1 row. It should be noted that i and i + 1 are arbitrary numbers from 1 to y, respectively, and j and j + 1 are arbitrary numbers from 1 to x, respectively.

The memory cell MC [i, j] in the i-th row, the memory cell MC [i, j + 1], and the memory cell MCR [i] are connected to the wiring RW [i] and the wiring WW [i]. Further, the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] in the i + 1 row are connected to the wiring RW [i + 1] and the wiring WW [i + 1]. There is.

The memory cell MC [i, j] in the j-th column and the memory cell MC [i + 1, j] are connected to the wiring WD [j], the wiring VR [j], and the wiring BL [j]. Further, the memory cell MC [i, j + 1] in the j + 1st column and the memory cell MC [i + 1, j + 1] are connected to the wiring WD [j + 1], the wiring VR [j + 1], and the wiring BL [j + 1]. .. Further, the memory cell MCR [i] on the i-th row and the memory cell MCR [i + 1] on the i + 1 row are connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

Each memory cell MC and each memory cell MCR has a transistor Tr11, a transistor Tr12, and a capacitive element C11. The transistor Tr12 has a function of controlling the input of the first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr11 has a function of generating an analog current according to the potential input to the gate. The capacitive element C11 sets the potential corresponding to the first analog potential or the first analog potential held in the memory cell MC or the memory cell MCR to the potential corresponding to the second analog potential or the second analog potential. It has a function to add.

Specifically, in the memory cell MC shown in FIG. 20, in the transistor Tr12, the gate is connected to the wiring WW, one of the source or drain is connected to the wiring WD, and the other of the source or drain is connected to the gate of the transistor Tr11. ing. Further, in the transistor Tr11, one of the source and the drain is connected to the wiring VR, and the other of the source and the drain is connected to the wiring BL. In the capacitive element C11, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr11.

Further, in the memory cell MCR shown in FIG. 20, the gate of the transistor Tr12 is connected to the wiring WW, one of the source or the drain is connected to the wiring WDREF, and the other of the source or the drain is connected to the gate of the transistor Tr11. .. Further, in the transistor Tr11, one of the source and the drain is connected to the wiring VRREF, and the other of the source and the drain is connected to the wiring BLREF. In the capacitive element C11, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr11.

Assuming that the gate of the transistor Tr11 is the node N in the memory cell MC, in the memory cell MC, the first analog potential or the potential corresponding to the first analog potential is input to the node N via the transistor Tr12, and then the transistor Tr12 is input. When it is turned off, the node N becomes a floating state, and the potential corresponding to the first analog potential or the first analog potential is held in the node N. Further, in the memory cell MC, when the node N is in a floating state, a second analog potential input to the first electrode of the capacitive element C11 or a potential corresponding to the second analog potential is given to the node N. By the above operation, the node N has a potential obtained by adding a potential corresponding to the second analog potential or the second analog potential to the potential corresponding to the first analog potential or the first analog potential. Become.

Since the potential of the first electrode of the capacitive element C11 is given to the node N via the capacitive element C11, the amount of change in the potential of the first electrode is actually reflected in the amount of change in the potential of the node N as it is. Not done. Specifically, the coupling coefficient uniquely determined from the capacitance value of the capacitance element C11, the capacitance value of the gate capacitance of the transistor Tr11, and the capacitance value of the parasitic capacitance is multiplied by the amount of change in the potential of the first electrode. , The amount of change in the potential of the node N can be calculated accurately. Hereinafter, for the sake of clarity, the description will be made assuming that the amount of change in the potential of the first electrode is substantially reflected in the amount of change in the potential of the node N.

The drain current of the transistor Tr11 is determined according to the potential of the node N. Therefore, when the potential of the node N is held by turning off the transistor Tr12, the value of the drain current of the transistor Tr11 is also held. The drain current reflects the first analog potential and the second analog potential.

Further, when the gate of the transistor Tr11 is the node NREF in the memory cell MCR, in the memory cell MCR, the first reference potential or the potential corresponding to the first reference potential is input to the node NREF via the transistor Tr12, and then the transistor. When Tr12 is turned off, the node NREF is suspended, and the node NREF holds the first reference potential or the potential corresponding to the first reference potential. Further, in the memory cell MCR, when the node NREF is in a floating state, a second analog potential input to the first electrode of the capacitive element C11 or a potential corresponding to the second analog potential is given to the node NREF. By the above operation, the node NREF has a potential obtained by adding a potential corresponding to the second analog potential or the second analog potential to the potential corresponding to the first reference potential or the first reference potential. Become.

The drain current of the transistor Tr11 is determined according to the potential of the node NREF. Therefore, when the potential of the node NREF is maintained by turning off the transistor Tr12, the value of the drain current of the transistor Tr11 is also maintained. The drain current reflects the first reference potential and the second analog potential.

Assuming that the drain current flowing through the transistor Tr11 of the memory cell MC [i, j] is the current I [i, j] and the drain current flowing through the transistor Tr11 of the memory cell MC [i + 1, j] is the current I [i + 1, j]. , The sum of the currents supplied from the wiring BL [j] to the memory cells MC [i, j] and the memory cells MC [i + 1, j] is the current I [j]. Further, the drain current flowing through the transistor Tr11 of the memory cell MC [i, j + 1] is the current I [i, j + 1], and the drain current flowing through the transistor Tr11 of the memory cell MC [i + 1, j + 1] is the current I [i + 1, j + 1]. Then, the sum of the currents supplied from the wiring BL [j + 1] to the memory cells MC [i, j + 1] and the memory cells MC [i + 1, j + 1] is the current I [j + 1]. Further, assuming that the drain current flowing through the transistor Tr11 of the memory cell MCR [i] is the current IREF [i] and the drain current flowing through the transistor Tr11 of the memory cell MCR [i + 1] is the current IREF [i + 1], the memory cell is connected to the wiring BLREF. The sum of the currents supplied to the MCR [i] and the memory cell MCR [i + 1] is the current IREF.

<Circuit 630 / Circuit 640 / Current source circuit configuration example>
Next, an example of a specific configuration of the circuit 630, the circuit 640, and the current source circuit 650 (CREF) will be described with reference to FIG. 21.

FIG. 21 shows an example of the configuration of the circuit 630, the circuit 640, and the current source circuit 650 corresponding to the memory cell MC and the memory cell MCR shown in FIG. Specifically, the circuit 630 shown in FIG. 21 has a circuit 630 [j] corresponding to the memory cell MC in the j-th column and a circuit 630 [j + 1] corresponding to the memory cell MC in the j + 1-th column. Further, the circuit 640 shown in FIG. 21 has a circuit 640 [j] corresponding to the memory cell MC in the jth column and a circuit 640 [j + 1] corresponding to the memory cell MC in the j + 1th column.

The circuit 630 [j] and the circuit 640 [j] are connected to the wiring BL [j]. Further, the circuit 630 [j + 1] and the circuit 640 [j + 1] are connected to the wiring BL [j + 1].

The current source circuit 650 is connected to the wiring BL [j], the wiring BL [j + 1], and the wiring BLREF. The current source circuit 650 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL [j] and the wiring BL [j + 1]. Has.

Specifically, the circuit 630 [j] and the circuit 630 [j + 1] have transistors Tr24 to Tr26 and a capacitive element C22, respectively. When setting the offset current, in the circuit 630 [j], the transistor Tr24 has a current ICM [j] corresponding to the difference between the current I [j] and the current IREF when the current I [j] is larger than the current IREF. j] has a function of generating. Further, in the circuit 630 [j + 1], the transistor Tr24 has a function of generating a current ICM [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is larger than the current IREF. Have. The current ICM [j] and the current ICM [j + 1] are supplied from the circuit 630 [j] and the circuit 630 [j + 1] to the wiring BL [j] and the wiring BL [j + 1].

Then, in the circuit 630 [j] and the circuit 630 [j + 1], the transistor Tr24 is connected to the wiring BL to which one of the source and the drain is connected to the corresponding wiring BL and the other of the source and the drain is supplied with a predetermined potential. It is connected. In the transistor Tr25, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr24. In the transistor Tr26, one of the source and the drain is connected to the gate of the transistor Tr24, and the other of the source and the drain is connected to the wiring to which a predetermined potential is supplied. In the capacitive element C22, the first electrode is connected to the gate of the transistor Tr24, and the second electrode is connected to the wiring to which a predetermined potential is supplied.

The gate of the transistor Tr25 is connected to the wiring OSM, and the gate of the transistor Tr26 is connected to the wiring ORM.

Note that FIG. 21 illustrates a case where the transistor Tr24 is a p-channel type and the transistors Tr25 and Tr26 are an n-channel type.

Further, the circuit 640 [j] and the circuit 640 [j + 1] have transistors Tr21 to Tr23 and a capacitive element C21, respectively. When setting the offset current, in the circuit 640 [j], the transistor Tr21 has a current ICP [j] corresponding to the difference between the current I [j] and the current IREF when the current I [j] is smaller than the current IREF. j] has a function of generating. Further, in the circuit 640 [j + 1], the transistor Tr21 has a function of generating a current ICP [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is smaller than the current IREF. Have. The current ICP [j] and the current ICP [j + 1] are drawn from the wiring BL [j] and the wiring BL [j + 1] into the circuit 640 [j] and the circuit 640 [j + 1].

The current ICM [j] and the current ICP [j] correspond to the office set [j]. Further, the current ICM [j + 1] and the current ICP [j + 1] correspond to the Offset [j + 1].

Then, in the circuit 640 [j] and the circuit 640 [j + 1], the transistor Tr21 is connected to a wiring in which one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is supplied with a predetermined potential. It is connected. In the transistor Tr22, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr21. In the transistor Tr23, one of the source and the drain is connected to the gate of the transistor Tr21, and the other of the source and the drain is connected to the wiring to which a predetermined potential is supplied. In the capacitive element C21, the first electrode is connected to the gate of the transistor Tr21, and the second electrode is connected to the wiring to which a predetermined potential is supplied.

The gate of the transistor Tr22 is connected to the wiring OSP, and the gate of the transistor Tr23 is connected to the wiring ORP.

Note that FIG. 21 illustrates a case where the transistors Tr21 to Tr23 are of the n-channel type.

Further, the current source circuit 650 has a transistor Tr 27 corresponding to the wiring BL and a transistor Tr 28 corresponding to the wiring BLREF. Specifically, the current source circuit 650 shown in FIG. 21 has a transistor Tr27 [j] corresponding to the wiring BL [j] and a transistor Tr27 [j + 1] corresponding to the wiring BL [j + 1] as the transistor Tr27. Is illustrated.

The gate of the transistor Tr27 is connected to the gate of the transistor Tr28. Further, in the transistor Tr27, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is connected to the wiring to which a predetermined potential is supplied. In the transistor Tr28, one of the source and the drain is connected to the wiring BLREF, and the other of the source and the drain is connected to the wiring to which a predetermined potential is supplied.

The transistor Tr27 and the transistor Tr28 have the same polarity. FIG. 21 illustrates a case where both the transistor Tr27 and the transistor Tr28 have a p-channel type.

The drain current of the transistor Tr28 corresponds to the current IREF. Since the transistor Tr27 and the transistor Tr28 have a function as a current mirror circuit, the drain current of the transistor Tr27 is substantially the same as the drain current of the transistor Tr28 or a value corresponding to the drain current of the transistor Tr28.

<Operation example of semiconductor device>
Next, an example of a specific operation of the semiconductor device 600 according to one aspect of the present invention will be described with reference to FIGS. 20, 21 and 22.

FIG. 22 corresponds to an example of a timing chart showing the operations of the memory cell MC and the memory cell MCR shown in FIG. 20 and the circuit 630, the circuit 640, and the current source circuit 650 shown in FIG. 21. In FIG. 22, at time T01 to time T04, the operation of storing the first analog data in the memory cell MC and the memory cell MCR is performed. At time T05 to time T10, an operation of setting an offset current Office is performed in the circuit 630 and the circuit 640. At time T11 to time T16, an operation of acquiring data corresponding to the product-sum value of the first analog data and the second analog data is performed.

It is assumed that low-level potential VSS is supplied to the wiring VR [j] and the wiring VR [j + 1]. Further, it is assumed that all the wiring having a predetermined potential connected to the circuit 630 is supplied with a high level potential VDD. Further, it is assumed that all the wiring having a predetermined potential connected to the circuit 640 is supplied with the low level potential VSS. Further, it is assumed that all the wirings having a predetermined potential connected to the current source circuit 650 are supplied with a high level potential VDD.

Further, it is assumed that the transistors Tr11, Tr21, Tr24, Tr27 [j], Tr27 [j + 1], and Tr28 operate in the saturation region.

First, at time T01 to time T02, a high level potential is given to the wiring WW [i], and a low level potential is given to the wiring WW [i + 1]. By the above operation, the transistor Tr12 is turned on in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] shown in FIG. Further, the transistor Tr12 is maintained in the off state in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1].

Further, at time T01 to time T02, the wiring WD [j] and the wiring WD [j + 1] shown in FIG. 20 are given potentials obtained by subtracting the first analog potential from the first reference potential VPR. Specifically, the wiring WD [j] is given the potential VPR-Vx [i, j], and the wiring WD [j + 1] is given the potential VPR-Vx [i, j + 1]. Further, the wiring WDREF is given a first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD, for example, the potential (whether + VSS) / 2 as a reference potential. Given.

Therefore, the potential VPR-Vx [i, j] is given to the node N [i, j] of the memory cell MC [i, j] shown in FIG. 20 via the transistor Tr12, and the memory cell MC [i, j + 1] The potential VPR-Vx [i, j + 1] is given to the node N [i, j + 1] of the memory cell MCR [i] via the transistor Tr12, and the potential VPR is given to the node NREF [i] of the memory cell MCR [i] via the transistor Tr12. Given.

When the time T02 ends, the potential given to the wiring WW [i] shown in FIG. 20 changes from a high level to a low level, and the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR In [i], the transistor Tr12 is turned off. By the above operation, the potential VPR-Vx [i, j] is held in the node N [i, j], the potential VPR-Vx [i, j + 1] is held in the node N [i, j + 1], and the node NREF is held. The potential VPR is held in [i].

Then, at time T03 to time T04, the potential of the wiring WW [i] shown in FIG. 20 is maintained at a low level, and the potential of the wiring WW [i + 1] is given a high level. By the above operation, the transistor Tr12 is turned on in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] shown in FIG. Further, the transistor Tr12 is maintained in the off state in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i].

Further, at time T03 to time T04, the wiring WD [j] and the wiring WD [j + 1] shown in FIG. 20 are given potentials obtained by subtracting the first analog potential from the first reference potential VPR. Specifically, the wiring WD [j] is given the potential VPR-Vx [i + 1, j], and the wiring WD [j + 1] is given the potential VPR-Vx [i + 1, j + 1]. Further, the wiring WDREF is given a first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD, for example, a potential (whether + VSS) / 2 as a reference potential. Given.

Therefore, the potential VPR-Vx [i + 1, j] is given to the node N [i + 1, j] of the memory cell MC [i + 1, j] shown in FIG. 20 via the transistor Tr12, and the memory cell MC [i + 1, j + 1] The potential VPR-Vx [i + 1, j + 1] is given to the node N [i + 1, j + 1] of the memory cell MCR [i + 1] via the transistor Tr12, and the potential VPR is given to the node NREF [i + 1] of the memory cell MCR [i + 1] via the transistor Tr12. Given.

When the time T04 ends, the potential given to the wiring WW [i + 1] shown in FIG. 20 changes from a high level to a low level, and the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR At [i + 1], the transistor Tr12 is turned off. By the above operation, the potential VPR-Vx [i + 1, j] is held in the node N [i + 1, j], the potential VPR-Vx [i + 1, j + 1] is held in the node N [i + 1, j + 1], and the node NREF is held. The potential VPR is held in [i + 1].

Then, at time T05 to time T06, a high level potential is applied to the wiring ORP and the wiring ORM shown in FIG. In the circuit 630 [j] and the circuit 630 [j + 1] shown in FIG. 21, the transistor Tr26 is turned on by applying a high level potential to the wiring ORM, and the gate of the transistor Tr24 is reset by applying the potential VDD. Will be done. Further, in the circuit 640 [j] and the circuit 640 [j + 1] shown in FIG. 21, the transistor Tr23 is turned on by applying a high level potential to the wiring ORP, and the gate of the transistor Tr21 is given a potential VSS. It is reset by.

At the end of time T06, the potential applied to the wiring ORP and wiring ORM shown in FIG. 21 changes from high level to low level, the transistor Tr26 is turned off in the circuit 630 [j] and the circuit 630 [j + 1], and the circuit 640 The transistor Tr23 is turned off in [j] and the circuit 640 [j + 1]. By the above operation, the potential VDD is held in the gate of the transistor Tr24 in the circuit 630 [j] and the circuit 630 [j + 1], and the potential VSS is held in the gate of the transistor Tr21 in the circuit 640 [j] and the circuit 640 [j + 1]. ..

Then, at time T07 to time T08, a high level potential is applied to the wiring OSP shown in FIG. Further, the wiring RW [i] and the wiring RW [i + 1] shown in FIG. 20 are given a potential between the potential VSS and the potential VDD, for example, the potential (whether + VSS) / 2 as a reference potential. By applying a high level potential to the wiring OSP, the transistor Tr22 is turned on in the circuit 640 [j] and the circuit 640 [j + 1].

When the I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the transistor Tr28 of the memory cell MC [i, j] shown in FIG. 20 is pulled in. It means that the sum of the current that can be generated and the current that can be drawn by the transistor Tr28 of the memory cell MC [i + 1, j] is smaller than the drain current of the transistor Tr27 [j]. Therefore, when the current ΔI [j] is positive, when the transistor Tr22 is turned on in the circuit 640 [j], a part of the drain current of the transistor Tr27 [j] flows into the gate of the transistor Tr21, and the potential of the gate rises. Begin to. Then, when the drain current of the transistor Tr21 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr21 converges to a predetermined value. The potential of the gate of the transistor Tr21 at this time corresponds to a potential at which the drain current of the transistor Tr21 becomes a current ΔI [j], that is, an office set [j] (= ICP [j]). That is, it can be said that the transistor Tr21 of the circuit 640 [j] is set to a current source through which the current ICP [j] can flow.

Similarly, when the I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, when the transistor Tr22 is turned on in the circuit 640 [j + 1], A part of the drain current of the transistor Tr27 [j + 1] flows into the gate of the transistor Tr21, and the potential of the gate starts to rise. Then, when the drain current of the transistor Tr21 becomes substantially equal to the current ΔI [j + 1], the potential of the gate of the transistor Tr21 converges to a predetermined value. The potential of the gate of the transistor Tr21 at this time corresponds to a potential at which the drain current of the transistor Tr21 becomes a current ΔI [j + 1], that is, an office set [j + 1] (= ICP [j + 1]). That is, it can be said that the transistor Tr21 of the circuit 640 [j + 1] is set to a current source through which the current ICP [j + 1] can flow.

When the time T08 ends, the potential given to the wiring OSP shown in FIG. 21 changes from high level to low level, and the transistor Tr22 is turned off in the circuit 640 [j] and the circuit 640 [j + 1]. By the above operation, the potential of the gate of the transistor Tr21 is maintained. Therefore, the circuit 640 [j] maintains the state set to the current source capable of passing the current ICP [j], and the circuit 640 [j + 1] maintains the state set to the current source capable of flowing the current ICP [j + 1]. do.

Then, at time T09 to time T10, a high level potential is applied to the wiring OSM shown in FIG. Further, the wiring RW [i] and the wiring RW [i + 1] shown in FIG. 20 are given a potential between the potential VSS and the potential VDD, for example, the potential (whether + VSS) / 2 as a reference potential. By applying a high level potential to the wiring OSM, the transistor Tr25 is turned on in the circuit 630 [j] and the circuit 630 [j + 1].

When the I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is negative, the transistor Tr28 of the memory cell MC [i, j] shown in FIG. 20 is pulled in. It means that the sum of the current that can be generated and the current that can be drawn by the transistor Tr28 of the memory cell MC [i + 1, j] is larger than the drain current of the transistor Tr27 [j]. Therefore, when the current ΔI [j] is negative, when the transistor Tr25 is turned on in the circuit 630 [j], a current flows from the gate of the transistor Tr24 to the wiring BL [j], and the potential of the gate starts to decrease. Then, when the drain current of the transistor Tr24 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to a potential at which the drain current of the transistor Tr24 becomes a current ΔI [j], that is, an office set [j] (= ICM [j]). That is, it can be said that the transistor Tr24 of the circuit 630 [j] is set to a current source through which the current ICM [j] can flow.

Similarly, when the I [j + 1] flowing through the wiring BL [j + 1] is larger than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is negative, when the transistor Tr25 is turned on in the circuit 630 [j + 1], A current flows from the gate of the transistor Tr24 to the wiring BL [j + 1], and the potential of the gate begins to drop. Then, when the drain current of the transistor Tr24 becomes substantially equal to the absolute value of the current ΔI [j + 1], the potential of the gate of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to a potential at which the drain current of the transistor Tr24 becomes equal to the current ΔI [j + 1], that is, the absolute value of the officet [j + 1] (= ICM [j + 1]). That is, it can be said that the transistor Tr24 of the circuit 630 [j + 1] is set to a current source through which the current ICM [j + 1] can flow.

At the end of time T10, the potential given to the wiring OSM shown in FIG. 21 changes from high level to low level, and the transistor Tr25 is turned off in the circuit 630 [j] and the circuit 630 [j + 1]. By the above operation, the potential of the gate of the transistor Tr24 is maintained. Therefore, the circuit 630 [j] maintains the state set to the current source capable of passing the current ICM [j], and the circuit 630 [j + 1] maintains the state set to the current source capable of flowing the current ICM [j + 1]. do.

In the circuit 640 [j] and the circuit 640 [j + 1], the transistor Tr21 has a function of drawing a current. Therefore, when the current I [j] flowing in the wiring BL [j] is larger than the current IREF flowing in the wiring BLREF and ΔI [j] is negative at time T07 to time T08, or the current I flowing in the wiring BL [j + 1] When [j + 1] is larger than the current flowing through the wiring BLREF and ΔI [j + 1] is negative, the current from the circuit 640 [j] or the circuit 640 [j + 1] to the wiring BL [j] or the wiring BL [j + 1] without excess or deficiency. May be difficult to supply. In this case, in order to balance the current flowing through the wiring BL [j] or the wiring BL [j + 1] with the current flowing through the wiring BLREF, the transistor Tr11 of the memory cell MC and the circuit 640 [j] or the circuit 640 [j + 1] are used. ], And the transistor Tr27 [j] or Tr27 [j + 1] may both be difficult to operate in the saturation region.

Even when ΔI [j] is negative at time T07 to time T08, the transistor at time T05 to time T06 is used to ensure operation in the saturation region of the transistor Tr11, Tr21, Tr27 [j] or Tr27 [j + 1]. Instead of resetting the gate of the Tr24 to the potential VDD, the potential of the gate of the transistor Tr24 may be set to a height sufficient to obtain a predetermined drain current. With the above configuration, since the current is supplied from the transistor Tr24 in addition to the drain current of the transistor Tr27 [j] or Tr27 [j + 1], the current that cannot be drawn in the transistor Tr11 can be drawn to some extent in the transistor Tr21. , The operation in the saturation region of the transistors Tr11, Tr21, Tr27 [j] or Tr27 [j + 1] can be ensured.

When I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF at time T09 to time T10, that is, when ΔI [j] is positive, the circuit 640 at time T07 to time T08. Since [j] is already set as a current source through which the current ICP [j] can flow, the potential of the gate of the transistor Tr24 in the circuit 630 [j] remains substantially the potential VDD. Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j + 1] is positive, the circuit 640 [j + 1] is the current ICP at time T07 to time T08. Since it has already been set as a current source through which [j + 1] can flow, the potential of the gate of the transistor Tr24 in the circuit 630 [j + 1] remains substantially the potential VDD.

Next, at time T11 to time T12, the wiring RW [i] shown in FIG. 20 is given a second analog potential Vw [i]. Further, the wiring RW [i + 1] is still given a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, as a reference potential. Specifically, the potential of the wiring RW [i] is higher by the potential difference Vw [i] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2. For the sake of clarity, it is assumed that the potential of the wiring RW [i] is the potential Vw [i].

Assuming that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, the memory shown in FIG. 20 The potential of the node N in the cell MC [i, j] is VPR-Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR-Vx [i, j + 1] + Vw. It becomes [i]. Then, from the above equation 6, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i, j] is the current obtained by subtracting the Offset [j] from the current ΔI [j]. That is, it can be seen that it is reflected in the current Iout [j] flowing out from the wiring BL [j]. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] is the current obtained by subtracting the office [j + 1] from the current ΔI [j + 1], that is, the wiring BL [ It can be seen that it is reflected in the current Iout [j + 1] flowing out from j + 1].

When the time T12 ends, the wiring RW [i] is again given a potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (whether + VSS) / 2.

Next, at time T13 to time T14, the wiring RW [i + 1] shown in FIG. 20 is given a second analog potential Vw [i + 1]. Further, the wiring RW [i] is still given a potential between the potential VSS and the potential VDD, for example, the potential (whether + VSS) / 2, as a reference potential. Specifically, the potential of the wiring RW [i + 1] is higher by the potential difference Vw [i + 1] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2, but the following For the sake of clarity, it is assumed that the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

Assuming that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, the memory shown in FIG. 20 The potential of the node N in the cell MC [i + 1, j] is VPR-Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR-Vx [i + 1, j + 1] + Vw. It becomes [i + 1]. Then, from the above equation 6, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i + 1, j] is the current obtained by subtracting the Offset [j] from the current ΔI [j]. That is, it can be seen that it is reflected in Iout [j]. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i + 1, j + 1] is the current obtained by subtracting the office [j + 1] from the current ΔI [j + 1], that is, Iout [j + 1]. ] It can be seen that it is reflected.

When the time T12 ends, the wiring RW [i + 1] is again given a potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (whether + VSS) / 2.

Next, at time T15 to time T16, the wiring RW [i] shown in FIG. 20 is given a second analog potential Vw [i], and the wiring RW [i + 1] is given a second analog potential Vw [i + 1]. .. Specifically, the potential of the wiring RW [i] is higher by the potential difference Vw [i] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2, and the wiring RW [i] The potential of i + 1] is higher by the potential difference Vw [i + 1] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2, but in order to make the explanation below easy to understand. It is assumed that the potential of the wiring RW [i] is the potential Vw [i] and the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

Assuming that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, the memory shown in FIG. 20 The potential of the node N in the cell MC [i, j] is VPR-Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR-Vx [i, j + 1] + Vw. It becomes [i]. Further, assuming that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, FIG. 20 shows. The potential of the node N in the memory cell MC [i + 1, j] shown is VPR-Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR-Vx [i + 1, j + 1]. ] + Vw [i + 1].

Then, from the above equation 6, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i, j] and the memory cells MC [i + 1, j] is the current ΔI [j]. ] And Ioffset [j] is subtracted, that is, it is reflected in the current Iout [j]. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is from the current ΔI [j + 1] to the office [j + 1]. It can be seen that it is reflected in the current obtained by subtracting, that is, the current Iout [j + 1].

When the time T16 ends, the wiring RW [i] and the wiring RW [i + 1] are again given a potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (whether + VSS) / 2.

With the above configuration, the product-sum operation can be performed on a small circuit scale. Further, with the above configuration, the product-sum operation can be performed at high speed. Further, with the above configuration, the product-sum calculation can be performed with low power consumption.

As the transistor Tr12, Tr22, Tr23, Tr25, or Tr26, it is desirable to use a transistor having an extremely low off current. By using a transistor having an extremely low off current for the transistor Tr12, the potential of the node N can be maintained for a long period of time. Further, by using a transistor having an extremely low off current for the transistors Tr22 and Tr23, the potential of the gate of the transistor Tr21 can be maintained for a long time. Further, by using a transistor having an extremely low off current for the transistors Tr25 and Tr26, the potential of the gate of the transistor Tr24 can be maintained for a long time.

An OS transistor may be used as a transistor having an extremely low off current. The leak current of the OS transistor standardized by the channel width can be 10 × ^10-21 A / μm (10 Zepto A / μm) or less when the source-drain voltage is 10 V and the room temperature (about 25 ° C.) is normal. Is.

By using the semiconductor device described above, the product-sum operation in the neural network 207 can be performed.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 3)
In the present embodiment, a photoelectric conversion element, a display element, and a transistor that can be used in the image pickup display device of one aspect of the present invention will be described with reference to the drawings.

FIG. 23A is a diagram illustrating a cross section of a pixel included in the image pickup display device 110 shown in FIG. 4A. The layer 111 has a photodiode as a photoelectric conversion element 161. The layer 112 has transistors and the like constituting the pixel circuit 162. The layer 113 has a light emitting element as the display element 163.

The photodiode included in the layer 111 is a pn-type photodiode or a pin-type photodiode having silicon as a photoelectric conversion layer, and has layers 301, 302, and 303.

For example, the layer 301 can be an n-type region, the layer 302 can be a p ^- type region, and the layer 303 can be a p ⁺ type region. The layer 302 may be an i-type region. Further, the layer 302 is provided with a region 304 for connecting the power supply line and the layer 301. For example, the region 304 can be a p ⁺ type region.

The pn-type or pin-type photodiode can be typically formed by using single crystal silicon. Further, the pin junction type photodiode may be formed by using a thin film such as amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

Here, FIG. 23A shows a configuration example in which the layer 111 and the layer 112 are bonded together to obtain an electrical connection.

An insulating layer 362 and a conductive layer 353 and a conductive layer 354 are provided on the first surface of the layer 111 so as to have a region embedded in the insulating layer 362. The conductive layer 353 is electrically connected to the layer 303. The conductive layer 354 is electrically connected to the region 304. Further, the surfaces of the insulating layer 362, the conductive layer 353, and the conductive layer 354 are flattened so as to coincide with each other.

An insulating layer 361 and a conductive layer 351 and a conductive layer 352 are provided on the first surface of the layer 112 so as to have a region embedded in the insulating layer 361. The conductive layer 351 is electrically connected to the power supply line. The conductive layer 352 is electrically connected to the source or drain of the transistor 162a. Further, the surfaces of the insulating layer 361, the conductive layer 351 and the conductive layer 352 are flattened so as to coincide with each other.

Here, it is preferable that the conductive layer 351 and the conductive layer 353 are metal elements having the same main component. It is preferable that the conductive layer 352 and the conductive layer 354 are metal elements having the same main component. Further, it is preferable that the insulating layer 361 and the insulating layer 362 are composed of the same components.

For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 351, 352, 353, and 354. Cu, Al, W, or Au is preferably used because of the ease of joining. Further, silicon oxide, silicon nitriding, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used for the insulating layers 361 and 362.

That is, it is preferable to use the same metal material shown above for each of the combination of the conductive layer 351 and the conductive layer 353 and the combination of the conductive layer 352 and the conductive layer 354. Further, it is preferable to use the same insulating material shown above for each of the insulating layer 361 and the insulating layer 362. With this configuration, the bonding step can be performed with the boundary between the layers 111 and 112 as the joining position. By the bonding step, it is possible to obtain electrical connections between the combination of the conductive layer 351 and the conductive layer 353 and the combination of the conductive layer 352 and the conductive layer 354. Further, it is possible to obtain a connection having mechanical strength of the insulating layer 361 and the insulating layer 362.

For bonding between metal layers, a surface-activated bonding method can be used in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering treatment or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. .. Alternatively, a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonds occur at the atomic level, so excellent bonding can be obtained not only electrically but also mechanically.

In addition, for bonding between insulating layers, after obtaining high flatness by polishing or the like, the surfaces treated with hydrophilicity such as oxygen plasma are brought into contact with each other for temporary bonding, and then main bonding is performed by dehydration by heat treatment. A joining method or the like can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.

When the layer 111 and the layer 112 are bonded together, an insulating layer and a metal layer coexist on the respective bonding surfaces. Therefore, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer. Further, the surface of the metal layer may be made of a refractory metal such as Au and subjected to hydrophilic treatment. A joining method other than the above-mentioned method may be used.

A transistor or the like may be formed on the first surface of the same silicon substrate, and a photodiode may be formed on the surface opposite to the first surface.

The layer 112 has a Si transistor provided on the silicon substrate 370. In FIG. 23A, the Si transistor shows a planar type configuration having an active region on the silicon substrate 370, but as shown in FIGS. 25A and 25B, a fin type semiconductor is formed on the silicon substrate 370. It may be configured to have a layer. Alternatively, as shown in FIG. 25 (C), it may be a transistor having a semiconductor layer 371 of a silicon thin film. The semiconductor layer 371 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 372 on the silicon substrate 370.

The layer 113 has a light emitting element as the display element 163. As the light emitting element, an element capable of self-luminous light can be used, and an element whose brightness is controlled by a current or a voltage is included in the category. For example, LEDs, organic EL elements, inorganic EL elements and the like can be used.

The light emitting element includes a top emission type, a bottom emission type, and a dual emission type. Here, the top emission type is used in order to extract light in the direction opposite to that of the layer 112 of the layer 113. A conductive film that transmits visible light is used for the electrode 333 on the side that extracts light. Further, it is preferable to use a conductive film that reflects visible light for the electrode 331 on the side that does not take out light.

An EL layer 332 is provided between the electrode 331 and the electrode 333. The EL layer 332 has at least a light emitting layer. The EL layer 332, as a layer other than the light emitting layer, has a highly hole-injecting substance, a highly hole-transporting substance, a hole blocking material, a highly electron-transporting substance, a highly electron-injecting substance, or a bipolar substance. It may further have a layer containing the substance (substance having high electron transport property and hole transport property) and the like.

Either a low molecular weight compound or a high molecular weight compound can be used for the EL layer 332, and an inorganic compound may be contained. The layers constituting the EL layer 332 can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like, respectively.

When a voltage higher than the threshold voltage of the light emitting element is applied between the cathode and the anode, holes are injected into the EL layer 332 from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer 332, and the luminescent substance contained in the EL layer 332 emits light.

When a white light emitting element is applied as the light emitting element, it is preferable that the EL layer 332 contains two or more kinds of light emitting substances. For example, white light emission can be obtained by selecting a light emitting substance so that the light emission of each of two or more light emitting substances has a complementary color relationship. For example, a luminescent substance that emits light such as R (red), G (green), B (blue), Y (yellow), O (orange), or a spectral component of two or more colors of R, G, and B, respectively. It is preferable that two or more of the luminescent substances exhibiting luminescence containing the above-mentioned substances are contained. Further, it is preferable to apply a light emitting element having two or more peaks in the spectrum of light emitted from the light emitting element within the wavelength range of the visible light region (for example, 350 nm to 750 nm). Further, the emission spectrum of the material having a peak in the yellow wavelength region is preferably a material having a spectral component also in the green and red wavelength regions.

The EL layer 332 is preferably configured such that a light emitting layer containing a light emitting material that emits one color and a light emitting layer containing a light emitting material that emits another color are laminated. For example, the plurality of light emitting layers in the EL layer 332 may be laminated so as to be in contact with each other, or may be laminated via a region that does not contain any of the light emitting materials. For example, a region is provided between the fluorescent light emitting layer and the phosphorescent light emitting layer, which contains the same material as the fluorescent light emitting layer or the phosphorescent light emitting layer (for example, a host material or an assist material) and does not contain any light emitting material. May be good. This facilitates the fabrication of the light emitting element and reduces the drive voltage.

Further, the light emitting element may be a single element having one EL layer, or may be a tandem element in which a plurality of EL layers are laminated via a charge generation layer.

The conductive film that transmits visible light can be formed by using, for example, indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide added with gallium, or the like. Also, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, alloys containing these metal materials, or nitrides of these metal materials (eg,). Titanium nitride) or the like can also be used by forming it thin enough to have translucency. Further, the laminated film of the above material can be used as a conductive film. For example, it is preferable to use a laminated film of an alloy of silver and magnesium and an indium tin oxide because the conductivity can be enhanced. Further, graphene or the like may be used.

As the conductive film that reflects visible light, for example, a metal material such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy containing these metal materials shall be used. Can be done. Further, lanthanum, neodymium, germanium or the like may be added to the above metal materials or alloys. Further, an alloy containing titanium, nickel, or neodymium and aluminum (aluminum alloy) may be used. Further, an alloy containing copper, palladium, magnesium and silver may be used. Alloys containing silver and copper are preferred because of their high heat resistance. Further, by laminating the metal film or the metal oxide film in contact with the aluminum film or the aluminum alloy film, oxidation can be suppressed. Examples of the material of such a metal film and a metal oxide film include titanium and titanium oxide. Further, the conductive film that transmits the visible light and the film made of a metal material may be laminated. For example, a laminated film of silver and indium tin oxide, a laminated film of an alloy of silver and magnesium and indium tin oxide, and the like can be used.

The electrodes may be formed by using a vapor deposition method or a sputtering method, respectively. In addition, it can be formed by using a ejection method such as an inkjet method, a printing method such as a screen printing method, or a plating method.

The above-mentioned light emitting layer and the layer containing a substance having a high hole injecting property, a substance having a high hole transporting property, a substance having a high electron transporting property, a substance having a high electron injecting property, a bipolar substance, and the like are included. Each may have an inorganic compound such as a quantum dot or a polymer compound (oligoform, dendrimer, polymer, etc.). For example, by using quantum dots in the light emitting layer, it can be made to function as a light emitting material.

As the quantum dot material, a colloidal quantum dot material, an alloy type quantum dot material, a core / shell type quantum dot material, a core type quantum dot material, or the like can be used. Further, a material containing an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, a quantum dot material containing elements such as cadmium, selenium, zinc, sulfur, phosphorus, indium, tellurium, lead, gallium, arsenic and aluminum may be used.

A substrate 382 that transmits visible light as a protective layer is formed on the light emitting element via the adhesive layer 381. As the substrate 382, for example, a glass substrate, a resin film, or the like can be used.

As the adhesive layer 381, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable type, a reaction curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Examples of these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin and the like. In particular, a material having low moisture permeability such as an epoxy resin is preferable. Further, a two-component mixed type resin may be used. Further, an adhesive sheet or the like may be used.

Further, the resin may contain a desiccant. For example, a substance that adsorbs water by chemisorption, such as an oxide of an alkaline earth metal (calcium oxide, barium oxide, etc.), can be used. Alternatively, a substance that adsorbs water by physical adsorption, such as zeolite or silica gel, may be used. It is preferable that a desiccant is contained because impurities such as moisture can be suppressed from entering the device and the reliability of the display panel is improved.

Further, by mixing the resin with a filler having a high refractive index or a light scattering member, the light extraction efficiency can be improved. For example, titanium oxide, barium oxide, zeolite, zirconium and the like can be used.

When a white light emitting element is applied, R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta) and the like are colored on the light emitting element. By providing the layer, a color image can be obtained. Examples of the material that can be used for the colored layer include a metal material, a resin material, a resin material containing a pigment or a dye, and the like.

FIG. 23 (B) is a diagram illustrating a cross section of a pixel included in the image pickup display device 120 shown in FIG. 4 (B). The layer 115 has a photodiode as a photoelectric conversion element 161. The layer 112 has transistors and the like constituting the pixel circuit 162. The layer 113 has a light emitting element as the display element 163. The image pickup display device 120 has a different photodiode configuration from the image pickup display device 110. For the configuration of the layer 112 and the layer 113, the description of the image pickup display device 110 can be referred to.

The photodiode shown in the layer 115 is a pn-type photodiode having a selenium-based material as a photoelectric conversion layer, and has layers 391, 392, 393, 394.

The layer 391 corresponds to a common electrode, and it is preferable to use a conductive layer having high translucency with respect to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene and the like can be used. It should be noted that the layer 391 may be omitted.

Layers 392 and 393 are photoelectric conversion units. It is preferable to use a selenium-based material which is a p-type semiconductor as the layer 393 and gallium oxide which is an n-type semiconductor as the layer 392.

A photoelectric conversion element using a selenium-based material has a characteristic of high external quantum efficiency with respect to visible light. In the photoelectric conversion element, by utilizing the avalanche multiplication effect, it is possible to obtain a highly sensitive sensor in which the amplification of electrons with respect to the amount of incident light is large. Further, since the selenium-based material has a high light absorption coefficient, it has a production advantage that the photoelectric conversion layer can be formed of a thin film. The thin film of the selenium-based material can be formed by a vacuum vapor deposition method, a sputtering method, or the like.

Examples of the selenium-based material include crystalline selenium such as single-crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, and selenium compounds (CIS), or copper, indium, gallium, and selenium compounds (CIGS). Can be used.

The n-type semiconductor is preferably made of a material having a wide bandgap and translucency with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used. In addition, these materials also have a function as a hole injection blocking layer, and can reduce the dark current.

The layer 394 corresponds to a pixel electrode, and it is preferable to use a metal layer having low resistance or the like. For example, aluminum, titanium, tungsten, tantalum, silver or a laminate thereof can be used.

The layer 115 can be formed on the layer 112. The layer 394 is electrically connected to the source or drain of the transistor 162a via the conductive layer 351 provided on the layer 112. The layer 391 is electrically connected to the power supply line via the conductive layer 352 provided on the conductive layer 395 and the layer 112.

FIG. 24A is a diagram illustrating a cross section of a pixel included in the image pickup display device 130 shown in FIG. 5A. The layer 111 has a photodiode as a photoelectric conversion element 161. The layer 112 and the layer 114 have transistors and the like constituting the pixel circuit 167. The layer 113 has a light emitting element as the display element 163. The image pickup display device 130 is different from the image pickup display device 110 in that it has a layer 114. For the configurations of the layers 111, 112 and 113, the description of the image pickup display device 110 can be referred to.

Layer 114 has an OS transistor. Although the OS transistor shows a self-aligned configuration in FIG. 24 (A), it may be a non-self-aligned top gate type transistor as shown in FIG. 25 (D).

Although the transistors 167a and 167b both show a configuration having a back gate 365, either of them may have a back gate. As shown in FIG. 25E, the back gate 365 may be electrically connected to the front gate of the transistor provided so as to face each other. Alternatively, the back gate 365 may be configured to be able to supply a fixed potential different from that of the front gate.

As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, and for example, CAC-OS, which will be described later, can be used.

The semiconductor layer is represented by an In—M—Zn based oxide containing, for example, indium, zinc and M (metals such as aluminum, titanium, gallium, germanium, ittrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It can be a membrane.

When the oxide semiconductor constituting the semiconductor layer is an In—M—Zn-based oxide, the atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn oxide is In ≧ M, Zn. It is preferable to satisfy ≧ M. The atomic number ratios of the metal elements of such a sputtering target are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 1. 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 1. 7, In: M: Zn = 5: 1: 8 and the like are preferable. The atomic number ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor having a low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, and more preferably 1 × 10 ¹¹ / cm. Oxide semiconductors having a carrier density of ³ or less, more preferably less than 1 × 10 ¹⁰ / cm ³ and a carrier density of 1 × 10 ^-9 / cm ³ or more can be used. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. As a result, the impurity concentration is low and the defect level density is low, so that it can be said that the oxide semiconductor has stable characteristics.

Not limited to these, a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the semiconductor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic number ratio between the metal element and oxygen, the interatomic distance, the density, etc. of the semiconductor layer are appropriate. ..

If silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen deficiency increases and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, alkali metals and alkaline earth metals may generate carriers when combined with oxide semiconductors, which may increase the off-current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

Further, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure is, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor or C-Axis Aligned and AB-plane Amorphous Crystal, Polycrystal) having crystals oriented on the c-axis. Includes microcrystalline or amorphous structures. In the non-single crystal structure, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and has no crystal component. Alternatively, the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal portion.

Even if the semiconductor layer is a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystal structure region, a CAAC-OS region, and a single crystal structure region. good. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.

Hereinafter, the configuration of the CAC (Cloud-Aligned Complex) -OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

The CAC-OS is, for example, a composition of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The state of being mixed in is also called a mosaic shape or a patch shape.

The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.

For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO in CAC-OS) is an indium oxide (hereinafter, InO). _X1 (X1 is a real number larger than 0), or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers larger than 0)) and gallium. With an oxide (hereinafter, GaO _X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers larger than 0)). _{In _ _ _} be.

That is, the CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are mixed. In the present specification, for example, the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region 2.

In addition, IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (-1≤x0≤1 and m0 is an arbitrary number). Crystalline compounds can be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.

On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

The CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between the region containing GaO _X3 as the main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component.

Instead of gallium, choose from aluminum, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. When one or more of these species are contained, CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component. The regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated. When the CAC-OS is formed by the sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good. Further, the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..

CAC-OS is characterized by the fact that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction, it can be seen that the orientation of the measurement region in the ab plane direction and the c-axis direction is not observed.

Further, CAC-OS has a ring-shaped high-brightness region and a plurality of ring regions in an electron beam diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam). Bright spots are observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, GaO _X3 is the main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component have a structure in which they are unevenly distributed and mixed.

CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.

Here, the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component is a region having higher conductivity than the region in which GaO _X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component. Therefore, a high field effect mobility (μ) can be realized by distributing the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component in the oxide semiconductor in a cloud shape.

On the other hand, the region in which GaO _X3 or the like is the main component is a region having higher insulating properties than the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component. That is, since the region containing GaO _X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _X3 and the like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner, so that the insulation is high. _On current (Ion) and high field effect mobility (μ) can be achieved.

Further, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

An insulating layer 385 having a function of preventing the diffusion of hydrogen is provided between the region where the OS transistor is formed and the region where the Si transistor is formed. Hydrogen in the insulating layer provided near the active region of the transistors 165a and 165b terminates the dangling bond of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer which is the active layer of the transistors 167a and 167b is one of the factors for generating carriers in the oxide semiconductor layer.

The insulating layer 385 can improve the reliability of the transistors 165a and 165b by confining hydrogen in one of the layers. Further, the reliability of the transistors 167a and 167b can be improved by suppressing the diffusion of hydrogen from one layer to the other layer.

As the insulating layer 385, for example, aluminum oxide, aluminum nitride, gallium oxide, gallium nitride, yttrium oxide, yttrium nitride, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.

FIG. 24B is a diagram illustrating a cross section of a pixel included in the image pickup display device 140 shown in FIG. 5B. The layer 115 has a photodiode as a photoelectric conversion element 161. The layer 112 and the layer 114 have transistors and the like constituting the pixel circuit 167. The layer 113 has a light emitting element as the display element 163. The image pickup display device 140 is different from the image pickup display device 120 in that it has a layer 114. For the configuration of the layers 112, 113, 114, 115, the description of the image pickup display devices 110 to 130 can be referred to.

FIG. 26A is a cross-sectional view showing an example in which a color filter or the like is added on the image pickup unit 101 of the image pickup display device according to one aspect of the present invention. The cross-sectional view shows a part of a region having a pixel circuit for three pixels. An insulating layer 400 is formed on the layer 111 or 115 on which the photoelectric conversion element 161 is formed. As the insulating layer 400, a silicon oxide film or the like having high translucency with respect to visible light can be used. Further, a silicon nitride film may be laminated as a passivation film. Further, as the antireflection film, a dielectric film such as hafnium oxide may be laminated.

A light-shielding layer 410 may be formed on the insulating layer 400. The light-shielding layer 410 has a function of preventing color mixing of light passing through the upper color filter. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 410. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.

An organic resin layer 420 can be provided as a flattening film on the insulating layer 400 and the light-shielding layer 410. Further, a color filter 430 (color filter 430a, color filter 430b, color filter 430c) is formed for each pixel. For example, assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter 430a, the color filter 430b, and the color filter 430c. Therefore, a color image can be obtained.

When a color filter is provided on the photoelectric conversion element 161, it is preferable to provide a color filter of the same color on the display element 163. When the color filters on the photoelectric conversion element 161 have a Bayer arrangement, the color filters on the display element 163 also have a Bayer arrangement, and both have the same arrangement.

An insulating layer 460 or the like having transparency to visible light can be provided on the color filter 430.

Further, as shown in FIG. 26B, an optical conversion layer 450 may be used instead of the color filter 430. With such a configuration, it is possible to obtain an image pickup device that can obtain images in various wavelength regions.

For example, an infrared image pickup device can be obtained by using a filter that blocks light having a wavelength equal to or lower than that of visible light in the optical conversion layer 450. Further, if the optical conversion layer 450 is provided with a filter that blocks light having a wavelength of near infrared rays or less, a far infrared ray imaging device can be obtained. Further, if the optical conversion layer 450 is provided with a filter that blocks light having a wavelength equal to or higher than that of visible light, it can be used as an ultraviolet imaging device.

Further, if a scintillator is used for the optical conversion layer 450, it can be used as an image pickup device for obtaining an image in which the intensity of radiation is visualized, which is used in an X-ray image pickup device or the like. When radiation such as X-rays transmitted through a subject is incident on a scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Then, the image data is acquired by detecting the light with the photoelectric conversion element 161. Further, an image pickup device having the above configuration may be used for a radiation detector or the like.

The scintillator contains a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible light and ultraviolet light. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO and the like. Those dispersed in resin or ceramics can be used.

In the photoelectric conversion element 161 using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a scintillator can be omitted.

Further, as shown in FIG. 26C, a microlens array 440 may be provided on the color filter 430a, the color filter 430b, and the color filter 430c. The light passing through the individual lenses of the microlens array 440 passes through the color filter directly below and irradiates the photoelectric conversion element 161. Further, the microlens array 440 may be provided on the optical conversion layer 450 shown in FIG. 26 (B).

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 4)
FIG. 27 shows a specific example of an electronic device that can use the image pickup display device according to one aspect of the present invention.

FIG. 27A is a smart glass, which has an image pickup display device 902, an objective lens 903, and an eyepiece lens 904 according to an aspect of the present invention inside the main body 901. It is fixed to the head using a belt 905, and information can be viewed on the AR display in addition to the outside image. It can also be used as a head-mounted display that blocks outside images and allows you to view images input from the outside.

FIG. 27B shows binoculars, which have an image pickup display device 912, an objective lens 913, and an eyepiece lens 914 according to an aspect of the present invention inside the lens barrel 911. It is equipped with an objective lens 913 with a high magnification, and information can be viewed on the AR display even for a distant subject. Further, a monocular or a telescope can have the same configuration.

FIG. 27C is a night-vision scope, which has an image pickup display device 922, an objective lens 923, and an eyepiece lens 924 according to an aspect of the present invention inside the lens barrel 921. It has basically the same configuration as the above binoculars, but also includes an infrared irradiation device 925. By irradiating the subject with infrared rays, it is possible to perform highly visible imaging and display even in the dark night.

This embodiment can be appropriately combined with the description of other embodiments.

10 Photoelectric conversion element 11 Display element 12 Display element C11 Capacitive element C21 Capacitive element C22 Capacitive element Tr11 Transistor Tr12 Transistor Tr21 Transistor Tr22 Transistor Tr23 Transistor Tr24 Transistor Tr25 Transistor Tr26 Transistor Tr27 Transistor Tr28 Transistor 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Transistor 58 Transistor 59 Transistor 60 Capacitive element 61 Transistor 62 Transistor 63 Transistor 64 Capacitive element 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 80 Wiring 81 Wiring 82 Wiring 83 Wiring 84 Wiring 85 Wiring 86 Wiring 87 Wiring 100 Imaging display device 101 Imaging unit 102 Display unit 102a Circuit unit 103 Lens 104 Lens 105 Subject 106 Viewer 110 Imaging display device 111 Layer 112 Layer 113 Layer 114 Layer 115 Layer 120 Imaging display device 130 Imaging display device 140 Imaging display Device 150 Region 151 Region 152 Region 152a Circuit 152b Circuit 152c Circuit 152d Circuit 152e Circuit 152f Circuit 152g Circuit 152h Circuit 153 Region 154 Region 155 Region 155a Circuit 155b Circuit 161 Photoelectric conversion element 162 Pixel circuit 162a Transistor 162b Transistor 163 Transistor 166 Connection part 167 Pixel circuit 167a Transistor 167b Transistor 171 Pixel circuit 172 Pixel circuit 173 Pixel circuit 174 Pixel circuit 175 Pixel circuit 176 Pixel circuit 177 Pixel circuit 178 Pixel circuit 179 Pixel circuit 180 Pixel circuit 200 Data processing section 201 Processing unit 203 Position sensor 204 Input / output unit 205 Storage unit 206 Server 207 Neural network 208 Storage medium 301 Layer 302 Layer 303 Layer 304 Region 331 Electrode 332 EL layer 333 Electrode 351 Conductive layer 352 Conductive layer 353 Conductive layer 354 Conductive layer 361 Insulation layer 362 Insulation layer 365 Backgate 370 Silicon substrate 371 Semiconductor layer 372 Insulation layer 381 Adhesion layer 382 Substrate 385 Insulation layer 3 91 Layer 392 Layer 393 Layer 394 Layer 395 Conductive layer 400 Insulation layer 410 Light-shielding layer 420 Organic resin layer 430 Color filter 430a Color filter 430b Color filter 430c Color filter 440 Microlens array 450 Optical conversion layer 460 Insulation layer 501 Input layer 502 Intermediate layer 503 Output layer 505 Server 600 Semiconductor device 610 Storage circuit 620 Reference storage circuit 630 Circuit 640 Circuit 650 Current source circuit 901 Main unit 902 Image pickup display device 903 Objective lens 904 Eyepiece lens 905 Belt 911 Lens tube 912 Image pickup display device 913 Objective lens 914 Eyepiece Lens 921 Lens barrel 922 Image pickup display device 923 Objective lens 924 Eyepiece lens 925 Infrared irradiation device

Claims (7)

It has an image pickup unit on the first surface.
The display unit is provided on the second surface opposite to the first surface.
Has a data processing unit
The image pickup unit has a photoelectric conversion element that receives light radiated to the first surface.
The display unit has a light emitting element that emits light in a direction opposite to that of the first surface.
The photoelectric conversion element is electrically connected to the gate of the transistor and is connected to the gate of the transistor.
The light emitting element is electrically connected to either the source or the drain of the transistor .
The data processing unit is an image pickup display device having a neural network for estimating the type of subject . In claim 1 ,
The data processing unit is an image pickup display device provided between the photoelectric conversion element and the light emitting element. It has a first layer, a second layer, a third layer, and a fourth layer .
The second layer is provided between the first layer and the third layer.
The first layer has a light emitting element and has a light emitting element.
The second layer has a first transistor and a second transistor.
The third layer has a photoelectric conversion element and has a photoelectric conversion element.
The fourth layer is provided between the second layer and the third layer.
The fourth layer has a third transistor and
The light emitting element is electrically connected to the first transistor and is connected to the first transistor.
The photoelectric conversion element is electrically connected to the second transistor and is connected to the second transistor.
The first transistor and the second transistor are electrically connected to each other .
The third transistor and the second transistor are electrically connected to each other.
The first and second transistors have a metal oxide in the channel forming region, and the first and second transistors have a metal oxide in the channel forming region.
The third transistor is an image pickup display device having silicon in the channel forming region . In claim 3 ,
The metal oxide is an image pickup display device having In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf). In claim 3 or 4 ,
The photoelectric conversion element is an image pickup display device having selenium or a compound containing selenium. An image pickup display device including a first transistor, a second transistor, a third transistor, a fourth transistor, a photoelectric conversion element, and a light emitting element.
One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor.
One of the source and drain of the second transistor is electrically connected to one electrode of the photoelectric conversion element.
The gate of the third transistor is electrically connected to the other of the source or drain of the second transistor.
One electrode of the light emitting element is electrically connected to one of the source or drain of the third transistor .
One of the source or drain of the fourth transistor is electrically connected to the other of the source or drain of the second transistor.
An image pickup display device in which the other of the source or drain of the fourth transistor is electrically connected to the gate of the third transistor . An electronic device comprising the image pickup display device according to any one of claims 1 to 6 and a lens.

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