JP7095781B2 - Semi-insulating gallium arsenide crystal substrate - Google Patents

Semi-insulating gallium arsenide crystal substrate Download PDF

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JP7095781B2
JP7095781B2 JP2021098885A JP2021098885A JP7095781B2 JP 7095781 B2 JP7095781 B2 JP 7095781B2 JP 2021098885 A JP2021098885 A JP 2021098885A JP 2021098885 A JP2021098885 A JP 2021098885A JP 7095781 B2 JP7095781 B2 JP 7095781B2
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JP2021155330A (en
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真弥 河本
誠 木山
幸雄 石川
克司 橋尾
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Sumitomo Electric Industries Ltd
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Description

本発明は、半絶縁性ヒ化ガリウム結晶基板に関する。 The present invention relates to a semi-insulating gallium arsenide crystal substrate.

半絶縁性ヒ化ガリウム結晶基板などの半絶縁性化合物半導体基板では、半導体デバイスの性能向上に直結する構造の微細化および複雑化に資するため、主面のミクロ領域における平坦性(以下、ミクロ平坦性ともいう)を向上させることが求められている。基板の主面のミクロ平坦性は、研磨条件だけでなく基板の物性の影響を受ける。具体的には、基板主面のミクロ平坦性を向上させるには、基板の主面内の比抵抗のミクロ領域における分布(以下、ミクロ分布ともいう)が均一であることが重要である。 Semi-insulating compound semiconductor substrates such as gallium arsenide crystal substrates have flatness in the micro region of the main surface (hereinafter referred to as micro-flatness) in order to contribute to the miniaturization and complexity of structures that directly improve the performance of semiconductor devices. It is required to improve (also called sex). The micro-flatness of the main surface of the substrate is affected not only by the polishing conditions but also by the physical properties of the substrate. Specifically, in order to improve the micro-flatness of the main surface of the substrate, it is important that the distribution of the specific resistance in the main surface of the substrate in the micro region (hereinafter, also referred to as micro distribution) is uniform.

比抵抗の主面のミクロ領域における分布(ミクロ分布)が均一であり主面のミクロ平坦性が高い半絶縁性ヒ化ガリウム基板を得る観点から、T. Kawase et al., "Properties of 6-inch Semi-insulating GaAs Substrates Manufactured by Vertical Boat Method", GaAs ManTech1999, April, 1999, pp19-22(非特許文献1)は、比抵抗および基板の中心から100μmピッチで外周方向に80mm長のミクロ領域における変動係数(当該ミクロ領域における標準偏差を平均値で除したものをいう。)が0.073である半絶縁性ヒ化ガリウム基板を開示する。 From the viewpoint of obtaining a semi-insulating gallium arsenide substrate having a uniform distribution (micro distribution) of the resistivity in the micro region of the main surface and high micro flatness of the main surface, T. Kawase et al., "Properties of 6- inch Semi-insulating GaAs Substrates Manufactured by Vertical Boat Method ", GaAs ManTech 1999, April, 1999, pp19-22 (Non-Patent Document 1) describes resistivity and in a micro region 80 mm long in the outer peripheral direction at a pitch of 100 μm from the center of the substrate. A semi-insulating gallium arsenide substrate having a variation coefficient (meaning the standard deviation in the micro region divided by an average value) is 0.073 is disclosed.

T. Kawase et al., "Properties of 6-inch Semi-insulating GaAs Substrates Manufactured by Vertical Boat Method", GaAs ManTech1999, April, 1999, pp19-22T. Kawase et al., "Properties of 6-inch Semi-insulating GaAs Substrates Manufactured by Vertical Boat Method", GaAs ManTech 1999, April, 1999, pp19-22

本開示の一態様にかかる半絶縁性ヒ化ガリウム結晶基板は、面方位が(100)の直径2Rmmの主面において、前記主面の中心から[010]方向に、0mm、0.5Rmm、および(R-17)mmの距離の点を中心とする3つの測定領域のそれぞれについて、比抵抗の平均値が5×107Ω・cm以上であり、比抵抗の標準偏差を比抵抗の平均値で除して得られる変動係数が0.50以下である。 The semi-insulating gallium arsenide crystal substrate according to one aspect of the present disclosure has a main surface having a plane orientation of (100) and a diameter of 2 Rmm, and has 0 mm, 0.5 Rmm, and 0 mm, 0.5 Rmm, and the like in the [010] direction from the center of the main surface. The average value of resistivity is 5 × 10 7 Ω · cm or more for each of the three measurement regions centered on the point with a distance of (R-17) mm, and the standard deviation of resistivity is the mean value of resistivity. The coefficient of variation obtained by dividing by is 0.50 or less.

図1は、本態様にかかる半絶縁性ヒ化ガリウム結晶基板の一例を示す概略平面図である。FIG. 1 is a schematic plan view showing an example of a semi-insulating gallium arsenide crystal substrate according to this embodiment. 図2は、本態様にかかる半絶縁性ヒ化ガリウム結晶基板の比抵抗を測定する方法の一例を示す概略断面図である。FIG. 2 is a schematic cross-sectional view showing an example of a method for measuring the specific resistance of the semi-insulating gallium arsenide crystal substrate according to this embodiment. 図3は、本態様にかかる半絶縁性ヒ化ガリウム結晶基板の製造に用いられる装置の一例を示す概略図である。FIG. 3 is a schematic view showing an example of an apparatus used for manufacturing a semi-insulating gallium arsenide crystal substrate according to this embodiment. 図4は、本態様にかかる半絶縁性ヒ化ガリウム結晶基板の製造に用いられる装置の別の例を示す概略図である。FIG. 4 is a schematic view showing another example of the apparatus used for manufacturing the semi-insulating gallium arsenide crystal substrate according to this embodiment. 図5は、本態様にかかる半絶縁性ヒ化ガリウム結晶基板の製造に用いられる装置のさらに別の例を示す概略図である。FIG. 5 is a schematic view showing still another example of the apparatus used for manufacturing the semi-insulating gallium arsenide crystal substrate according to this embodiment.

[本開示が解決しようとする課題]
しかしながら、T. Kawase et al., "Properties of 6-inch Semi-insulating GaAs Substrates Manufactured by Vertical Boat Method", GaAs ManTech1999, April, 1999, pp19-22(非特許文献1)に開示の半絶縁性ヒ化ガリウム基板の比抵抗は、その最大値は非特許文献1に記載されていないが、非特許文献1に記載されているグラフから読み取ると、5×107Ω・cm未満である。比抵抗が5×107Ω・cm以上に大きい半絶縁性ヒ化ガリウム結晶基板においては、比抵抗のミクロ分布のばらつきが基板の中心部と外周部とで大きくなり、比抵抗のミクロ分布を均一にすることが困難であり、主面のミクロ平坦性が低くなるという問題点がある。
[Problems to be solved by this disclosure]
However, the semi-insulating gallium disclosed in T. Kawase et al., "Properties of 6-inch Semi-insulating GaAs Substrates Manufactured by Vertical Boat Method", GaAs ManTech 1999, April, 1999, pp19-22 (Non-Patent Document 1). Although the maximum value of the specific resistance of the gallium arsenide substrate is not described in Non-Patent Document 1, it is less than 5 × 10 7 Ω · cm when read from the graph described in Non-Patent Document 1. In a semi-insulating gallium arsenide crystal substrate having a specific resistance of 5 × 10 7 Ω · cm or more, the variation in the micro distribution of the specific resistance becomes large between the central part and the outer peripheral part of the substrate, and the micro distribution of the specific resistance becomes large. There is a problem that it is difficult to make it uniform and the micro flatness of the main surface becomes low.

本開示は、上記問題点を解決して、比抵抗が高くとも、主面のミクロ平坦性が高い半絶縁性ヒ化ガリウム結晶基板を提供することを目的とする。 It is an object of the present disclosure to solve the above-mentioned problems and to provide a semi-insulating gallium arsenide crystal substrate having high micro-flatness of the main surface even if the specific resistance is high.

[本開示の効果]
本開示によれば、比抵抗が高くとも、主面のミクロ平坦性が高い半絶縁性ヒ化ガリウム結晶基板を提供できる。
[Effect of this disclosure]
According to the present disclosure, it is possible to provide a semi-insulating gallium arsenide crystal substrate having high micro-flatness of the main surface even if the specific resistance is high.

[本発明の実施形態の説明]
最初に本発明の実施態様を列記して説明する。
[Explanation of Embodiment of the present invention]
First, embodiments of the present invention will be listed and described.

[1]本発明の一実施形態にかかる半絶縁性ヒ化ガリウム結晶基板は、面方位が(100)の直径2Rmmの主面において、上記主面の中心から[010]方向に、0mm、0.5Rmm、および(R-17)mmの距離の点を中心とする3つの測定領域のそれぞれについて、比抵抗の平均値が5×107Ω・cm以上であり、比抵抗の標準偏差を比抵抗の平均値で除して得られる変動係数が0.50以下である。本実施形態の半絶縁性ヒ化ガリウム結晶基板は、面方位が(100)である主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い。 [1] The semi-insulating gallium arsenide crystal substrate according to the embodiment of the present invention has a surface orientation of (100) and is 0 mm, 0 in the [010] direction from the center of the main surface on a main surface having a diameter of 2 Rmm. The mean value of resistivity is 5 × 10 7 Ω · cm or more for each of the three measurement regions centered on points with distances of .5 R mm and (R-17) mm, and the standard deviation of resistivity is compared. The coefficient of variation obtained by dividing by the average value of resistance is 0.50 or less. In the semi-insulating gallium arsenide crystal substrate of the present embodiment, the micro distribution of the specific resistance on the main surface having the plane orientation (100) is uniform, and the micro flatness of the main surface is high.

[2]上記半絶縁性ヒ化ガリウム結晶基板において、上記主面の直径2Rmmを150mm以上とすることができる。かかる半絶縁性ヒ化ガリウム結晶基板は、面方位が(100)である主面の直径が150mm以上の大口径であっても、主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い。 [2] In the semi-insulating gallium arsenide crystal substrate, the diameter of the main surface of the main surface can be set to 150 mm or more. In such a semi-insulating gallium arsenide crystal substrate, even if the surface orientation is (100) and the diameter of the main surface is a large diameter of 150 mm or more, the micro distribution of the specific resistance on the main surface is uniform, and the surface of the main surface has a uniform micro-distribution. High micro flatness.

[3]上記半絶縁性ヒ化ガリウム結晶基板において、比抵抗の上記変動係数を0.10以下とすることができる。かかる半絶縁性ヒ化ガリウム結晶基板は、面方位が(100)である主面における比抵抗のミクロ分布が極めて均一であり、主面のミクロ平坦性が極めて高い。 [3] In the semi-insulating gallium arsenide crystal substrate, the coefficient of variation of specific resistance can be set to 0.10 or less. In such a semi-insulating gallium arsenide crystal substrate, the micro distribution of specific resistance on the main surface having a plane orientation of (100) is extremely uniform, and the micro flatness of the main surface is extremely high.

[本発明の実施形態の詳細]
以下、本発明の実施形態についてさらに詳細に説明するが、これらに限定されるものではない。以下においては、図面を参照しながら説明するが、本明細書および図面において同一または対応する要素に同一の符号を付すものとし、それらについて同じ説明は繰り返さない。また、本明細書および図面中の(hkl)は面方位を示し、[hkl]は方位を示す。ここで、h、kおよびlは同じまたは異なる整数でありミラー指数と呼ばれる。ミラー指数の前に表される「-」は、本来数字の頭上に表されるものであり、そのミラー指数の後に「バー」と読まれる。たとえば、[0-10]は、「ゼロ・イチ・バー・ゼロ」と読まれる。
[Details of Embodiments of the present invention]
Hereinafter, embodiments of the present invention will be described in more detail, but the present invention is not limited thereto. In the following, although the description will be made with reference to the drawings, the same or corresponding elements shall be designated by the same reference numerals in the present specification and the drawings, and the same description thereof will not be repeated. Further, (hkl) in the present specification and drawings indicates a plane direction, and [hkl] indicates an orientation. Here, h, k and l are the same or different integers and are called the Miller index. The "-" that appears before the Miller index is originally represented above the number, and is read as "bar" after the Miller index. For example, [0-10] is read as "zero, one, bar, zero."

本明細書において「A~B」という形式の表記は、範囲の上限下限(すなわちA以上B以下)を意味し、Aにおいて単位の記載がなく、Bにおいてのみ単位が記載されている場合、Aの単位とBの単位とは同じである。さらに、本明細書において、化合物などを化学式で表す場合、原子比を特に限定しないときは従来公知のあらゆる原子比を含むものとし、必ずしも化学量論的範囲のもののみに限定されるべきではない。 In the present specification, the notation in the form of "A to B" means the upper and lower limits of the range (that is, A or more and B or less), and when there is no description of the unit in A and the unit is described only in B, A. The unit of and the unit of B are the same. Further, in the present specification, when a compound or the like is represented by a chemical formula, it shall include all conventionally known atomic ratios when the atomic ratio is not particularly limited, and should not necessarily be limited to those in the stoichiometric range.

≪半絶縁性ヒ化ガリウム結晶基板≫
図1を参照して、本実施形態にかかる半絶縁性GaAs結晶基板11(半絶縁性ヒ化ガリウム結晶基板)は、面方位が(100)の直径2Rmmの主面において、上記主面の中心から[010]方向に、0mm、0.5Rmm、および(R-17)mmを中心とする3つの測定領域のそれぞれについて、比抵抗の平均値が5×107Ω・cm以上であり、比抵抗の標準偏差を比抵抗の平均値で除して得られる変動係数が0.50以下である。本実施形態の半絶縁性GaAs結晶基板11は、面方位が(100)である主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い。
≪Semi-insulating gallium arsenide crystal substrate≫
With reference to FIG. 1, the semi-insulating GaAs crystal substrate 11 (semi-insulating gallium arsenide crystal substrate) according to the present embodiment is the center of the main surface having a plane orientation of (100) and a diameter of 2 Rmm. In the direction from [010], the average value of resistivity is 5 × 10 7 Ω · cm or more for each of the three measurement regions centered on 0 mm, 0.5 Rmm, and (R-17) mm, and the ratio. The variation coefficient obtained by dividing the standard deviation of resistance by the average value of specific resistance is 0.50 or less. In the semi-insulating GaAs crystal substrate 11 of the present embodiment, the micro distribution of the specific resistance on the main surface having the plane orientation (100) is uniform, and the micro flatness of the main surface is high.

本実施形態の半絶縁性GaAs結晶基板11は、その比抵抗の平均が5×107Ω・cm以上であり、好ましくは7.5×107Ω・cm以上であり、より好ましくは1.0×108Ω・cm以上である。 The semi-insulating GaAs crystal substrate 11 of the present embodiment has an average specific resistance of 5 × 10 7 Ω · cm or more, preferably 7.5 × 10 7 Ω · cm or more, and more preferably 1. It is 0 × 10 8 Ω · cm or more.

<主面>
図1に示すように、本実施形態の半絶縁性GaAs結晶基板11は、主面の面方位が(100)である。すなわち、半絶縁性GaAs結晶基板11は、半絶縁性GaAs結晶体から、その(100)面を主面として切り出すことにより得られる。
<Main side>
As shown in FIG. 1, the semi-insulating GaAs crystal substrate 11 of the present embodiment has a main surface orientation of (100). That is, the semi-insulating GaAs crystal substrate 11 is obtained by cutting out the semi-insulating GaAs crystal body with its (100) plane as the main plane.

半絶縁性GaAs結晶基板11の主面の直径2Rmmは、特に制限はないが、大きいほど好ましく、150mm以上が好ましい。かかる半絶縁性GaAs結晶基板は、面方位が(100)である主面の直径が150mm以上の大口径であっても、主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い。 The diameter of the main surface of the semi-insulating GaAs crystal substrate 11 is not particularly limited, but is preferably larger, preferably 150 mm or more. In such a semi-insulating GaAs crystal substrate, even if the diameter of the main surface having a plane orientation of (100) is a large diameter of 150 mm or more, the micro distribution of specific resistance on the main surface is uniform and the main surface is micro flat. High sex.

<比抵抗の平均値および変動係数>
図1に示すように、本実施形態の半絶縁性GaAs結晶基板11は、主面の中心から[010]方向に、0mm、0.5Rmm、および(R-17)mmを中心とする3つの測定領域のそれぞれについて、比抵抗の平均値が5×107Ω・cm以上であり、比抵抗の標準偏差を比抵抗の平均値で除して得られる変動係数が0.50以下である。本実施形態の半絶縁性GaAs結晶基板11は、比抵抗の上記変動係数が0.50以下であることから、主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い。
<Mean and coefficient of variation of specific resistance>
As shown in FIG. 1, the semi-insulating GaAs crystal substrate 11 of the present embodiment has three centers centered on 0 mm, 0.5 Rmm, and (R-17) mm in the [010] direction from the center of the main surface. For each of the measurement regions, the average value of the specific resistance is 5 × 10 7 Ω · cm or more, and the coefficient of variation obtained by dividing the standard deviation of the specific resistance by the average value of the specific resistance is 0.50 or less. Since the semi-insulating GaAs crystal substrate 11 of the present embodiment has the above-mentioned coefficient of variation of specific resistance of 0.50 or less, the micro distribution of specific resistance on the main surface is uniform and the micro flatness of the main surface is high. ..

主面の中心とは、図1に示すように、半絶縁性GaAs結晶基板11の主面を円であると仮定した場合に、その円の中心をさす。主面の中心から[010]方向は、主面の中心から[0-10]方向にノッチ部11nが形成されている基板においては、ノッチ部11nから主面の中心を見る方向に相当する。 As shown in FIG. 1, the center of the main surface refers to the center of the circle, assuming that the main surface of the semi-insulating GaAs crystal substrate 11 is a circle. The [010] direction from the center of the main surface corresponds to the direction in which the center of the main surface is viewed from the notch portion 11n in the substrate in which the notch portion 11n is formed in the [0-10] direction from the center of the main surface.

主面の直径が2Rmmの半絶縁性GaAs結晶基板において、比抵抗のミクロ分布を測定するための3つの測定領域は、図1に示すように、主面の中心から[010]方向にr0=0mm(すなわち主面の中心点)を中心とする中心部測定領域F0、主面の中心から[010]方向にr1=0.5Rmm(すなわち主面の中心と主面の外周との中間点)を中心とする中間部測定領域F1、および主面の中心から[010]方向にr2=(R-17)mm(すなわち主面の外周から内側に17mmの距離にある点)を中心とする外周部測定領域F2である。 In a semi-insulating GaAs crystal substrate having a main surface diameter of 2 Rmm, the three measurement regions for measuring the micro distribution of specific resistance are r 0 in the [010] direction from the center of the main surface, as shown in FIG. = 0 mm (that is, the center point of the main surface) in the center measurement area F0, r 1 = 0.5 Rmm (that is, between the center of the main surface and the outer periphery of the main surface) in the [010] direction from the center of the main surface. Centered at the middle measurement region F1 centered on the point) and r 2 = (R-17) mm (that is, a point 17 mm inward from the outer circumference of the main surface) in the [010] direction from the center of the main surface. It is the outer peripheral portion measurement area F2.

比抵抗の測定は、中心部測定領域F0、中間部測定領域F1および外周部測定領域F2のそれぞれの領域において、それぞれの領域の中心から[010]方向に-5mmから+5mmの距離の範囲に亘って100μm(0.1mm)ピッチの101点で行う。上記101点における比抵抗の測定値から比抵抗の平均値および比抵抗の標準偏差を算出する。得られた比抵抗の標準偏差を得られた比抵抗の平均値で除することにより比抵抗の変動係数を算出する。 The specific resistance is measured over a distance of -5 mm to +5 mm in the [010] direction from the center of each region in each of the central measurement region F0, the intermediate measurement region F1 and the outer peripheral measurement region F2. At 101 points with a pitch of 100 μm (0.1 mm). The average value of the specific resistance and the standard deviation of the specific resistance are calculated from the measured values of the specific resistance at the above 101 points. The coefficient of variation of the specific resistance is calculated by dividing the standard deviation of the obtained specific resistance by the average value of the obtained specific resistance.

比抵抗の測定は、図2に示すような3端子ガード法により行う。すなわち、半絶縁性GaAs結晶基板11の比抵抗を測定する主面(以下、表側主面ともいう)上に直径70μmの円が上記の3つの測定領域のそれぞれの中心から[010]方向に-5mmから+5mmの距離の範囲に亘って100μm(0.1mm)ピッチで101個配置するパターンをフォトリソグラフィにより作製する。その後、半絶縁性GaAs結晶基板11の表側主面およびその反対側の主面(以下、裏側主面ともいう)に、厚さ300nmのAu層、厚さ40nmのNi層および厚さ80nmのAuGe層を順次蒸着して、リフトオフした後、475℃で6分間熱処理して合金化することにより測定用電極E1,E2を形成する。測定用電極E1,E2について図2に示すように配線して、電圧印加範囲0V~10V、電圧印加ステップ1Vの条件で、裏側主面から電圧を印加し、パターン化された測定用電極E1内の電流を測定する。かかる測定を[010]方向に10mmの長さに亘って100μmピッチでパターン化された測定用電極E1毎に行う。比抵抗の測定値は、電流-電圧曲線の傾きから算出した抵抗値を半絶縁性GaAs結晶基板11の試料厚さdで除した後、パターン化された測定用電極E1の面積Sを乗じることにより導出する。 The specific resistance is measured by the 3-terminal guard method as shown in FIG. That is, a circle having a diameter of 70 μm is formed on the main surface (hereinafter, also referred to as the front main surface) for measuring the specific resistance of the semi-insulating GaAs crystal substrate 11 in the [010] direction from the center of each of the above three measurement regions. A pattern in which 101 pieces are arranged at a pitch of 100 μm (0.1 mm) over a distance range of 5 mm to +5 mm is produced by photolithography. Then, on the front main surface of the semi-insulating GaAs crystal substrate 11 and the main surface on the opposite side thereof (hereinafter, also referred to as the back main surface), an Au layer having a thickness of 300 nm, a Ni layer having a thickness of 40 nm, and AuGe having a thickness of 80 nm. The layers are sequentially vapor-deposited, lifted off, and then heat-treated at 475 ° C. for 6 minutes to alloy them to form measurement electrodes E1 and E2. The measurement electrodes E1 and E2 are wired as shown in FIG. 2, and a voltage is applied from the back side main surface under the conditions of a voltage application range of 0V to 10V and a voltage application step of 1V, and the inside of the patterned measurement electrodes E1. Measure the current of. Such measurement is performed for each measurement electrode E1 patterned at a pitch of 100 μm over a length of 10 mm in the [010] direction. The measured value of resistivity is obtained by dividing the resistance value calculated from the slope of the current-voltage curve by the sample thickness d of the semi-insulating GaAs crystal substrate 11 and then multiplying by the area S of the patterned measurement electrode E1. Derived by.

比抵抗の平均値は、デバイス作製時のリーク電流を低減する観点から、5×107Ω・cm以上が好ましい。また、比抵抗の平均値は、半絶縁性発現の機構から、1×109Ω・cm以下である場合が多い。 The average value of the specific resistance is preferably 5 × 10 7 Ω · cm or more from the viewpoint of reducing the leakage current at the time of manufacturing the device. In addition, the average value of resistivity is often 1 × 10 9 Ω · cm or less due to the mechanism of semi-insulating property development.

本実施形態の半絶縁性GaAs結晶基板11において、上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれについて、比抵抗の変動係数は0.10以下が好ましい。かかる半絶縁性GaAs結晶基板は、比抵抗の変動係数が0.10以下であることから、主面における比抵抗のミクロ分布が極めて均一であり、主面のミクロ平坦性が極めて高い。 In the semi-insulating GaAs crystal substrate 11 of the present embodiment, the coefficient of variation of the specific resistance is 0.10 for each of the above three measurement regions (central measurement region F0, intermediate measurement region F1 and outer peripheral measurement region F2). The following is preferable. Since the coefficient of variation of the specific resistance of such a semi-insulating GaAs crystal substrate is 0.10 or less, the micro distribution of the specific resistance on the main surface is extremely uniform, and the micro flatness of the main surface is extremely high.

<転位密度>
本実施形態の半絶縁性GaAs結晶基板11において、主面における比抵抗のミクロ分布を均一にする観点から、上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれについて、転位密度は、9.5×103cm-2以下が好ましく、5.5×103cm-2以下がより好ましい。
<Dislocation density>
In the semi-insulating GaAs crystal substrate 11 of the present embodiment, from the viewpoint of making the micro distribution of the specific resistance on the main surface uniform, the above three measurement regions (central measurement region F0, intermediate measurement region F1 and outer peripheral measurement region) For each of F2), the dislocation density is preferably 9.5 × 10 3 cm −2 or less, and more preferably 5.5 × 10 3 cm −2 or less.

転位密度の測定は、半絶縁性GaAs結晶基板11を450℃の溶融KOH(水酸化カリウム)中で20分間エッチングしたときに形成されるエッチピットの密度の測定により行う。上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれの中心を顕微鏡により拡大し、それらの1mm角視野内のエッチピットの数を計測することによりエッチピット密度を算出する。 The dislocation density is measured by measuring the density of the etch pits formed when the semi-insulating GaAs crystal substrate 11 is etched in molten KOH (potassium hydroxide) at 450 ° C. for 20 minutes. By magnifying the center of each of the above three measurement areas (central measurement area F0, intermediate measurement area F1 and outer peripheral measurement area F2) with a microscope and measuring the number of etch pits in the 1 mm square field of view. Calculate the etch pit density.

≪半絶縁性ヒ化ガリウム結晶基板の製造方法≫
半絶縁性GaAs結晶基板の比抵抗のミクロ分布を均一化するためには、比抵抗のミクロ分布に影響を与える転位密度の分布を均一化することが重要である。半絶縁性GaAs結晶基板は、通常、[100]方向に結晶成長させた大口径の半絶縁性GaAs結晶体を(100)面およびそれに平行な面で切り出すことにより製造する。[100]方向に結晶成長させた大口径の半絶縁性GaAs結晶体においては、面方位が(100)の断面における転位密度は、その断面の中心および外周において高くなり、中心と外周との中間において低くなるという不均一な分布を有する。したがって、このような転位密度の不均一な分布を均一化する必要がある(方策I)。また、GaAs結晶の結晶学的性質から、半絶縁性GaAs結晶体の転位密度は<100>方向([010]方向ならびにこの方向に結晶学的に等価な[00-1]方向、[0-10]方向および[001]方向の4方向の総称)で高くなりやすい。そのため、<100>方向における転位密度を低くする必要がある(方策II)。さらに、上記転位密度の不均一な分布を均一化する(方策I)とともに、<100>方向における転位密度を低くする(方策II)ことが好ましい(方策III)。
≪Manufacturing method of semi-insulating gallium arsenide crystal substrate≫
In order to make the micro distribution of the specific resistance of the semi-insulating GaAs crystal substrate uniform, it is important to make the distribution of the dislocation density that affects the micro distribution of the specific resistance uniform. The semi-insulating GaAs crystal substrate is usually produced by cutting out a large-diameter semi-insulating GaAs crystal body crystal-grown in the [100] direction on the (100) plane and a plane parallel to it. In a large-diameter semi-insulating GaAs crystal grown in the [100] direction, the dislocation density in the cross section having the plane orientation (100) is high at the center and the outer periphery of the cross section, and is intermediate between the center and the outer periphery. It has a non-uniform distribution that it becomes low in. Therefore, it is necessary to make such a non-uniform distribution of dislocation density uniform (Measures I). Further, due to the crystallographic properties of the GaAs crystal, the dislocation density of the semi-insulating GaAs crystal is in the <100> direction ([010] direction and the crystallographically equivalent [00-1] direction in this direction, [0-]. It tends to be higher in the four directions of [10] direction and [001] direction). Therefore, it is necessary to reduce the dislocation density in the <100> direction (Measures II). Further, it is preferable to make the non-uniform distribution of the dislocation density uniform (Measures I) and lower the dislocation density in the <100> direction (Measures II) (Measures III).

<方策I>
図3に、半絶縁性GaAs結晶体の製造に用いられる装置の第1例を示す。図3(A)は装置の概略上面図であり、図3(B)は装置の概略側断面図である。上記の転位密度の不均一な分布は、半絶縁性GaAs結晶体10の結晶成長の際に、半絶縁性GaAs結晶体10とGaAs原料融液4との固液界面からの下方の放熱が減少することに由来するものと考えられる。すなわち、固液界面からの下方への放熱は、固液界面が上昇することにより、GaAs原料融液4からステージ(坩堝を支持するために坩堝下方に位置する台をいう、図示せず)への直接的な放熱から、GaAs原料融液4から半絶縁性GaAs結晶体10を介在したステージへの間接的な放熱に変化するため、減少する。しかし、従来の半絶縁性GaAs結晶体の製造方法においては、図3に示すような断熱材3が配置されていないため、結晶成長用坩堝2の側面側に配置されたヒータ(図示せず。)からの加熱は、固液界面が上昇しても変化しない。このため、従来の半絶縁性GaAs結晶体の製造方法においては、固液界面の上昇に伴って下方への放熱が小さくなるため、側面からの入熱が一定のままでは、固液界面の液相側からの入熱と、固相側からの放熱の熱収支が変わってしまい、固液界面相対位置や形状の変化による熱応力が発生して転位密度の分布を不均一にする。第1例は、方策Iとして、上記の熱収支の変化を抑制することにより転位密度の分布を均一化するために、結晶成長用坩堝2とヒータとの間に、具体的には結晶成長用坩堝2の側面外周の周りに、テーパ付の断熱材3を配置する。
<Measures I>
FIG. 3 shows a first example of an apparatus used for producing a semi-insulating GaAs crystal. FIG. 3A is a schematic top view of the device, and FIG. 3B is a schematic side sectional view of the device. The non-uniform distribution of the transition density described above reduces the lower heat dissipation from the solid-liquid interface between the semi-insulating GaAs crystal 10 and the GaAs raw material melt 4 during crystal growth of the semi-insulating GaAs crystal 10. It is thought that it is derived from doing. That is, the downward heat radiation from the solid-liquid interface is caused by the rise of the solid-liquid interface from the GaAs raw material melt 4 to the stage (a platform located below the pit to support the pit, not shown). The direct heat dissipation from the GaAs raw material melt 4 changes to the indirect heat dissipation from the semi-insulating GaAs crystal 10 to the stage, which is reduced. However, in the conventional method for producing a semi-insulating GaAs crystal, the heat insulating material 3 as shown in FIG. 3 is not arranged, so that the heater arranged on the side surface side of the crystal growth crucible 2 (not shown). ) Does not change even if the solid-liquid interface rises. For this reason, in the conventional method for producing a semi-insulating GaAs crystal, the downward heat dissipation decreases as the solid-liquid interface rises, so if the heat input from the side surface remains constant, the liquid at the solid-liquid interface The heat balance between the heat input from the phase side and the heat dissipation from the solid phase side changes, and thermal stress is generated due to changes in the relative position and shape of the solid-liquid interface, making the distribution of the dislocation density non-uniform. The first example is, as a measure I, in order to make the dislocation density distribution uniform by suppressing the above-mentioned change in the heat balance, between the crystal growth crucible 2 and the heater, specifically for crystal growth. A tapered heat insulating material 3 is arranged around the outer periphery of the side surface of the crucible 2.

第1例における断熱材3は、筒状形状を有し、GaAs種結晶SC側(以下、シード側ともいう。)に対応する部分に比べて半絶縁性GaAs結晶体の結晶成長面側(以下、テール側ともいう。)に対応する部分の断熱性が高くなるようにテーパが設けられている。断熱材3の材質は、特に制限はなく、たとえば、カーボン、窒化ホウ素(BN)、窒化ケイ素(Si34)、ムライト(3Al23・2SiO2~2Al23・SiO2)およびアルミナ(Al23)などが挙げられる。これにより、半絶縁性GaAs結晶体10の結晶成長の際、固液界面が上昇するにつれて、結晶成長用坩堝2の側面側からの入熱が減少することにより熱収支の変化が抑制されるため、熱応力の発生が抑制されて、転位密度の分布が均一になる。 The heat insulating material 3 in the first example has a tubular shape and has a crystal growth surface side (hereinafter, also referred to as) of a semi-insulating GaAs crystal as compared with a portion corresponding to the GaAs seed crystal SC side (hereinafter, also referred to as seed side). , Also referred to as the tail side), a taper is provided so as to increase the heat insulating property of the portion corresponding to). The material of the heat insulating material 3 is not particularly limited, and is, for example, carbon, boron nitride (BN), silicon nitride (Si 3 N 4 ), mullite (3Al 2 O 3・ 2SiO 2 to 2Al 2 O 3・ SiO 2 ) and Alumina (Al 2 O 3 ) and the like can be mentioned. As a result, during crystal growth of the semi-insulating GaAs crystal body 10, as the solid-liquid interface rises, the heat input from the side surface side of the crystal growth pit 2 decreases, so that the change in heat balance is suppressed. , The generation of thermal stress is suppressed and the distribution of dislocation density becomes uniform.

<方策II>
図4に、半絶縁性GaAs結晶体の製造に用いられる装置の第2例を示す。図4(A)は装置の概略上面図であり、図4(B)は装置の概略側断面図である。半絶縁性GaAs結晶体10中の転位は熱応力により発生するものと考えられることから、半絶縁性GaAs結晶体10の<100>方向における転位密度を低くするために、半絶縁性GaAs結晶体10の<100>方向の温度差を小さくする必要がある。このため、第2例は、方策IIとして、結晶成長用坩堝2とヒータとの間に、具体的には結晶成長用坩堝2の側面外周の周りに、半絶縁性GaAs結晶体10の<100>方向([010]方向を含む結晶学的に等価な4方向、具体的には、[010]方向、[00-1]方向、[0-10]方向および[001]方向を意味する。以下同じ。)に断熱性が高い部分を有する断熱材3を配置する。
<Measures II>
FIG. 4 shows a second example of an apparatus used for manufacturing a semi-insulating GaAs crystal. FIG. 4A is a schematic top view of the device, and FIG. 4B is a schematic side sectional view of the device. Since dislocations in the semi-insulating GaAs crystal 10 are considered to be generated by thermal stress, the semi-insulating GaAs crystal is in order to reduce the dislocation density in the <100> direction of the semi-insulating GaAs crystal 10. It is necessary to reduce the temperature difference in the <100> direction of 10. Therefore, in the second example, as a measure II, between the crystal growth crucible 2 and the heater, specifically, around the outer periphery of the side surface of the crystal growth crucible 2, the semi-insulating GaAs crystal 10 <100. > Direction (4 crystallographically equivalent directions including [010] direction, specifically, [010] direction, [00-1] direction, [0-10] direction and [001] direction. The same applies hereinafter), the heat insulating material 3 having a portion having a high heat insulating property is arranged.

第2例における断熱材3は、第1材料3aと、第1材料3aよりも断熱性の高い(すなわち、熱伝導率の低い)材質からなる第2材料3bと、を周方向に45°ずつ交互に並べることより形成されている円筒形状を有する。断熱材3は、結晶成長用坩堝2において[100]方向に結晶成長する半絶縁性GaAs結晶体10の<110>方向([01-1]方向を含む結晶学的に等価な4方向、具体的には、[01-1]方向、[0-1-1]方向、[0-11]方向および[011]方向を意味する。以下同じ。)に第1材料3aが位置し、<100>方向に第2材料3bが位置するように配置される。断熱材3の第1材料3aおよび第2材料3bは、第2材料3bが第1材料3aに比べて断熱性の高い(熱伝導率の低い)材質で形成されていれば特に制限はなく、たとえば、第1材料3aの材質としてカーボンを挙げられ、第2材料3bの材質として窒化ホウ素(BN)、窒化ケイ素(Si34)、ムライト(3Al23・2SiO2~2Al23・SiO2)およびアルミナ(Al23)などが挙げられる。これにより、半絶縁性GaAs結晶体10の結晶成長の際、半絶縁性GaAs結晶体10の<110>方向の温度分布が均一化されるため、熱応力の発生が抑制されて、転位密度の分布が均一になる。 The heat insulating material 3 in the second example has a first material 3a and a second material 3b made of a material having higher heat insulating properties (that is, lower thermal conductivity) than the first material 3a by 45 ° in the circumferential direction. It has a cylindrical shape formed by arranging them alternately. The heat insulating material 3 is a crystallographically equivalent four directions including the <110> direction ([01-1] direction) of the semi-insulating GaAs crystal body 10 in which the crystal grows in the [100] direction in the crystal growth pit 2. The first material 3a is located in the [01-1] direction, the [0-1-1] direction, the [0-11] direction, and the [011] direction. The same shall apply hereinafter), and <100. The second material 3b is arranged so as to be located in the> direction. The first material 3a and the second material 3b of the heat insulating material 3 are not particularly limited as long as the second material 3b is made of a material having higher heat insulating properties (lower thermal conductivity) than the first material 3a. For example, carbon is mentioned as the material of the first material 3a, and boron nitride (BN), silicon nitride (Si 3 N 4 ), and mulite (3Al 2 O 3.2SiO 2 to 2Al 2 O 3 ) are used as the material of the second material 3b. -SiO 2 ) and alumina (Al 2 O 3 ) and the like. As a result, when the semi-insulating GaAs crystal 10 grows, the temperature distribution of the semi-insulating GaAs crystal 10 in the <110> direction is made uniform, so that the generation of thermal stress is suppressed and the dislocation density is reduced. The distribution becomes uniform.

<方策III>
図5に、半絶縁性GaAs結晶体の製造に用いられる装置の第3例を示す。図5(A)は装置の概略上面図であり、図5(B)は装置の概略側断面図である。第3例は、上記方策Iおよび方策IIを組み合わせた方策IIIとして、結晶成長用坩堝2とヒータとの間に、具体的には結晶成長用坩堝2の側面外周の周りに、半絶縁性GaAs結晶体10の<100>方向に断熱性が高い部分を有するテーパ付の断熱材3を配置する。
<Measures III>
FIG. 5 shows a third example of an apparatus used for producing a semi-insulating GaAs crystal. 5 (A) is a schematic top view of the device, and FIG. 5 (B) is a schematic side sectional view of the device. A third example is a semi-insulating GaAs between the crystal growth crucible 2 and the heater, specifically around the outer periphery of the side surface of the crystal growth crucible 2, as a measure III in which the above measures I and II are combined. A tapered heat insulating material 3 having a portion having a high heat insulating property is arranged in the <100> direction of the crystal body 10.

第3例における断熱材3は、上記方策Iのため、筒状形状を有し、GaAs種結晶SC側(以下、シード側ともいう。)に対応する部分に比べて半絶縁性GaAs結晶体の結晶成長面側(以下、テール側ともいう。)に対応する部分の断熱性が高くなるようにテーパが設けられているとともに、上記方策IIのため、第1材料3aと、第1材料3aよりも断熱性の高い(すなわち、熱伝導率の低い)材質からなる第2材料3bと、を周方向に45°ずつ交互に並べることより形成されており、結晶成長用坩堝2において[100]方向に結晶成長する半絶縁性GaAs結晶体10の<110>方向に第1材料3aが位置し、<100>方向に第2材料3bが位置するように配置される。断熱材3の第1材料3aおよび第2材料3bは、第2材料3bが第1材料3aに比べて断熱性の高い(熱伝導率の低い)材質で形成されていれば特に制限はなく、たとえば、第1材料3aの材質としてカーボンを挙げられ、第2材料3bの材質として窒化ホウ素(BN)、窒化ケイ素(Si34)、ムライト(3Al23・2SiO2~2Al23・SiO2)およびアルミナ(Al23)などが挙げられる。 Due to the above measure I, the heat insulating material 3 in the third example has a tubular shape and is a semi-insulating GaAs crystal as compared with the portion corresponding to the GaAs seed crystal SC side (hereinafter, also referred to as the seed side). A taper is provided so that the heat insulating property of the portion corresponding to the crystal growth surface side (hereinafter, also referred to as the tail side) is high, and due to the above-mentioned measure II, the first material 3a and the first material 3a The second material 3b, which is made of a material having high heat insulating properties (that is, having low thermal conductivity), is formed by alternately arranging the second material 3b in the circumferential direction by 45 ° each, and is formed in the [100] direction in the crystal growth pit 2. The first material 3a is located in the <110> direction of the semi-insulating GaAs crystal body 10 in which the crystal grows, and the second material 3b is located in the <100> direction. The first material 3a and the second material 3b of the heat insulating material 3 are not particularly limited as long as the second material 3b is made of a material having higher heat insulating properties (lower thermal conductivity) than the first material 3a. For example, carbon is mentioned as the material of the first material 3a, and boron nitride (BN), silicon nitride (Si 3 N 4 ), and mulite (3Al 2 O 3.2SiO 2 to 2Al 2 O 3 ) are used as the material of the second material 3b. -SiO 2 ) and alumina (Al 2 O 3 ) and the like.

第3例においては、上記方策Iに対応する構成により、半絶縁性GaAs結晶体10の結晶成長の際、固液界面が上昇するにつれて、結晶成長用坩堝2の側面側からの吸熱が減少することにより熱収支の変化が抑制されるため、熱応力の発生が抑制されるとともに、上記方策IIに対応する構成により、半絶縁性GaAs結晶体10の結晶成長の際、半絶縁性GaAs結晶体10の<110>方向の温度分布が均一化されるため、熱応力の発生が抑制される。このため、転位密度の分布がさらに均一になる。 In the third example, according to the configuration corresponding to the above measure I, the heat absorption from the side surface side of the crystal growth chamber 2 decreases as the solid-liquid interface rises during crystal growth of the semi-insulating GaAs crystal body 10. As a result, changes in the heat balance are suppressed, so that the generation of thermal stress is suppressed, and with the configuration corresponding to the above-mentioned measure II, the semi-insulating GaAs crystal is formed during crystal growth of the semi-insulating GaAs crystal 10. Since the temperature distribution in the <110> direction of 10 is made uniform, the generation of thermal stress is suppressed. Therefore, the distribution of dislocation density becomes more uniform.

上記第1例~第3例の製造方法により得られた半絶縁性GaAs結晶体10から、その(100)面を主面として切り出すことにより、上述の半絶縁性GaAs結晶基板11を製造することができる。 The semi-insulating GaAs crystal substrate 11 described above is manufactured by cutting out the semi-insulating GaAs crystal body 10 obtained by the manufacturing methods of the first to third examples with the (100) plane as the main surface. Can be done.

≪実施例I≫
<半絶縁性GaAs結晶基板の製造>
実施例Iにおいては、図3に示す装置を用いて、直径150mmの大口径のカーボンをドープした半絶縁性GaAs結晶体10を垂直ボート法により成長させた。断熱材3は、筒状形状を有し、GaAs種結晶SC側(以下、シード側ともいう。)に対応する部分に比べて半絶縁性GaAs結晶体の結晶成長面側(以下、テール側ともいう。)に対応する部分の断熱性が高くなるように、具体的にはシード側に比べてテール側の断熱材3の厚さが大きくなるように、テーパを設けた。断熱材3の材質は窒化ケイ素(Si34)とした。半絶縁性GaAs結晶体10の成長条件は常法とした。これにより実施例Iの半絶縁性GaAs結晶体を製造した。
<< Example I >>
<Manufacturing of semi-insulating GaAs crystal substrate>
In Example I, a semi-insulating GaAs crystal 10 doped with a large diameter carbon of 150 mm in diameter was grown by a vertical boat method using the apparatus shown in FIG. The heat insulating material 3 has a tubular shape, and has a semi-insulating GaAs crystal on the crystal growth surface side (hereinafter, also referred to as the tail side) as compared with the portion corresponding to the GaAs seed crystal SC side (hereinafter, also referred to as the seed side). A taper is provided so that the heat insulating property of the portion corresponding to) is increased, specifically, the thickness of the heat insulating material 3 on the tail side is larger than that on the seed side. The material of the heat insulating material 3 was silicon nitride (Si 3 N 4 ). The growth condition of the semi-insulating GaAs crystal 10 was a conventional method. As a result, the semi-insulating GaAs crystal body of Example I was produced.

上記のように製造された半絶縁性GaAs結晶体から(100)面を主面として切り出すことにより、厚さ600μmの複数の半絶縁性GaAs結晶基板を製造した。製造された複数の半絶縁性GaAs結晶基板のうち、半絶縁性GaAs結晶体10の最もGaAs種結晶SC側(以下、最シード側ともいう。)に対応する部分から得られた半絶縁性GaAs結晶基板を実施例I-1の半絶縁性GaAs結晶基板とし、半絶縁性GaAs結晶体10の最も結晶成長面側(以下、最テール側ともいう。)に対応する部分から得られた半絶縁性GaAs結晶基板を実施例I-2の半絶縁性GaAs結晶基板とした。 By cutting out the (100) plane as the main surface from the semi-insulating GaAs crystal body manufactured as described above, a plurality of semi-insulating GaAs crystal substrates having a thickness of 600 μm were manufactured. Among the plurality of manufactured semi-insulating GaAs crystal substrates, the semi-insulating GaAs obtained from the portion of the semi-insulating GaAs crystal body 10 corresponding to the most GaAs seed crystal SC side (hereinafter, also referred to as the most seed side). The crystal substrate was used as the semi-insulating GaAs crystal substrate of Example I-1, and the semi-insulating obtained from the portion corresponding to the most crystal growth surface side (hereinafter, also referred to as the tail side) of the semi-insulating GaAs crystal body 10. The sex GaAs crystal substrate was used as the semi-insulating GaAs crystal substrate of Example I-2.

<比抵抗の平均値および変動係数ならびに転位密度の評価>
上記のように製造された実施例I-1(最シード側)および実施例I-2(最テール側)の半絶縁性GaAs結晶基板の主面の上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれにおける比抵抗のミクロ分布の指標となる平均値および変動係数ならびに転位密度を上述の方法により測定し、上記3つの測定領域のそれぞれにおける比抵抗の平均値および変動係数ならびに転位密度の評価を行った。結果を表1にまとめた。
<Evaluation of mean value and coefficient of variation of specific resistance and dislocation density>
The above three measurement regions (center measurement region F0) on the main surface of the semi-insulating GaAs crystal substrate of Example I-1 (most seed side) and Example I-2 (tailmost side) manufactured as described above. , The average value and the coefficient of variation and the coefficient of variation, which are indicators of the micro distribution of specific resistance in each of the intermediate measurement region F1 and the outer peripheral measurement region F2), are measured by the above method, and the ratio in each of the above three measurement regions is measured. The mean resistance, coefficient of variation and dislocation density were evaluated. The results are summarized in Table 1.

<表面平坦度の評価>
上記のようにして製造された実施例I-1(最シード側)および実施例I-2(最テール側)の半絶縁性GaAs結晶基板の主面の上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれにおける表面平坦度を測定して評価した。その測定方法は、以下のとおりとした。すなわち、実施例I-1および実施例I-2の半絶縁性GaAs結晶基板の主面をミラー加工した。上記中心部測定領域F0、中間部測定領域F1および外周部測定領域F2のそれぞれの中心を中心とする20mm角の範囲について、各20mm角領域における平坦度測定器(コーニング・トロペル社ウルトラソート6220)を用いて、LTV(Local Thickness Variation)測定を行なった。結果を表1にまとめた。
<Evaluation of surface flatness>
The above three measurement regions (central measurement regions) on the main surface of the semi-insulating GaAs crystal substrate of Example I-1 (most seed side) and Example I-2 (tailmost side) manufactured as described above. The surface flatness in each of F0, the intermediate portion measurement region F1 and the outer peripheral portion measurement region F2) was measured and evaluated. The measurement method was as follows. That is, the main surfaces of the semi-insulating GaAs crystal substrates of Examples I-1 and I-2 were mirrored. A flatness measuring instrument in each 20 mm square region (Ultrasort 6220, Corning Tropel Co., Ltd.) in a 20 mm square range centered on the center of each of the center measurement region F0, the middle measurement region F1 and the outer peripheral measurement region F2. LTV (Local Thickness Variation) measurement was performed using. The results are summarized in Table 1.

≪実施例II≫
<半絶縁性GaAs結晶基板の製造>
実施例IIにおいては、図4に示す装置を用いて、直径150mmの大口径のカーボンをドープした半絶縁性GaAs結晶体10を垂直ブリッジマン法により成長させた。断熱材3は、第1材料3aと、第1材料3aよりも断熱性の高い(すなわち、熱伝導率の低い)材質からなる第2材料3bと、を周方向に45°ずつ交互に並べることより形成されている円筒形状を有し、第1材料3aの材質をカーボンとし、第2材料3bの材質を窒化ケイ素(Si34)とした。また、断熱材3は、結晶成長用坩堝2において[100]方向に結晶成長する半絶縁性GaAs結晶体10の<110>方向に第1材料3aの中心軸が位置し、<100>方向に第2材料3bの中心軸が位置するように配置した。これにより実施例IIの半絶縁性GaAs結晶体を製造した。
<< Example II >>
<Manufacturing of semi-insulating GaAs crystal substrate>
In Example II, a semi-insulating GaAs crystal 10 doped with a large diameter carbon of 150 mm in diameter was grown by the vertical Bridgeman method using the apparatus shown in FIG. In the heat insulating material 3, the first material 3a and the second material 3b made of a material having higher heat insulating property (that is, lower thermal conductivity) than the first material 3a are alternately arranged by 45 ° in the circumferential direction. It has a cylindrical shape formed by, and the material of the first material 3a is carbon, and the material of the second material 3b is silicon nitride (Si 3 N 4 ). Further, in the heat insulating material 3, the central axis of the first material 3a is located in the <110> direction of the semi-insulating GaAs crystal body 10 in which the crystal grows in the [100] direction in the crystal growth chamber 2, and the central axis of the first material 3a is located in the <100> direction. It was arranged so that the central axis of the second material 3b was located. As a result, the semi-insulating GaAs crystal body of Example II was produced.

上記のように製造された実施例IIの半絶縁性GaAs結晶体から実施例Iと同様に切り出すことにより、厚さ600μmの複数の半絶縁性GaAs結晶基板を製造した。製造された複数の半絶縁性GaAs結晶基板のうち、半絶縁性GaAs結晶体10の最シード側に対応する部分から得られた半絶縁性GaAs結晶基板を実施例II-1の半絶縁性GaAs結晶基板とし、半絶縁性GaAs結晶体10の最テール側に対応する部分から得られた半絶縁性GaAs結晶基板を実施例II-2の半絶縁性GaAs結晶基板とした。 By cutting out the semi-insulating GaAs crystal body of Example II produced as described above in the same manner as in Example I, a plurality of semi-insulating GaAs crystal substrates having a thickness of 600 μm were produced. Among the plurality of manufactured semi-insulating GaAs crystal substrates, the semi-insulating GaAs crystal substrate obtained from the portion corresponding to the most seed side of the semi-insulating GaAs crystal body 10 is the semi-insulating GaAs of Example II-1. As the crystal substrate, the semi-insulating GaAs crystal substrate obtained from the portion corresponding to the tail end side of the semi-insulating GaAs crystal body 10 was used as the semi-insulating GaAs crystal substrate of Example II-2.

<比抵抗の平均値および変動係数、転位密度、ならびに表面平坦度の評価>
上記のように製造された実施例II-1(最シード側)および実施例II-2(最テール側)の半絶縁性GaAs結晶基板の主面の上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれにおける比抵抗の平均値および変動係数、転位密度、ならびに表面平坦度を実施例Iと同様にして評価した。結果を表1にまとめた。
<Evaluation of mean and coefficient of variation of specific resistance, dislocation density, and surface flatness>
The above three measurement regions (center measurement region F0) on the main surface of the semi-insulating GaAs crystal substrate of Example II-1 (most seed side) and Example II-2 (tailmost side) manufactured as described above. , The mean value and coefficient of variation of the specific resistance in each of the intermediate portion measurement region F1 and the outer peripheral portion measurement region F2), the shift density, and the surface flatness were evaluated in the same manner as in Example I. The results are summarized in Table 1.

≪実施例III≫
<半絶縁性GaAs結晶基板の製造>
実施例IIIにおいては、図5に示す装置を用いて、直径150mmの大口径のカーボンをドープした半絶縁性GaAs結晶体10を垂直ブリッジマン法により成長させた。断熱材3は、筒状形状を有し、GaAs種結晶SC側(以下、シード側ともいう。)に対応する部分に比べて半絶縁性GaAs結晶体の結晶成長面側(以下、テール側ともいう。)に対応する部分の断熱性が高くなるように、具体的にはシード側に比べてテール側の断熱材3の厚さが大きくなるように、テーパを設けた。また、断熱材3は、第1材料3aと、第1材料3aよりも断熱性の高い(すなわち、熱伝導率の低い)材質からなる第2材料3bと、を周方向に45°ずつ交互に並べることより形成されており、第1材料3aの材質をカーボンとし、第2材料3bの材質を窒化ケイ素(Si34)とした。また、断熱材3は、結晶成長用坩堝2において[100]方向に結晶成長する半絶縁性GaAs結晶体10の<110>方向に第1材料3aの中心軸が位置し、<100>方向に第2材料3bの中心軸が位置するように配置した。これにより実施例IIIの半絶縁性GaAs結晶体を製造した。
<< Example III >>
<Manufacturing of semi-insulating GaAs crystal substrate>
In Example III, a large-diameter carbon-doped semi-insulating GaAs crystal 10 having a diameter of 150 mm was grown by the vertical Bridgeman method using the apparatus shown in FIG. The heat insulating material 3 has a tubular shape, and has a semi-insulating GaAs crystal on the crystal growth surface side (hereinafter, also referred to as the tail side) as compared with the portion corresponding to the GaAs seed crystal SC side (hereinafter, also referred to as the seed side). A taper is provided so that the heat insulating property of the portion corresponding to) is increased, specifically, the thickness of the heat insulating material 3 on the tail side is larger than that on the seed side. Further, in the heat insulating material 3, the first material 3a and the second material 3b made of a material having higher heat insulating property (that is, lower thermal conductivity) than the first material 3a are alternately arranged by 45 ° in the circumferential direction. It is formed by arranging them side by side, and the material of the first material 3a is carbon, and the material of the second material 3b is silicon nitride (Si 3 N 4 ). Further, in the heat insulating material 3, the central axis of the first material 3a is located in the <110> direction of the semi-insulating GaAs crystal body 10 in which the crystal grows in the [100] direction in the crystal growth chamber 2, and the central axis of the first material 3a is located in the <100> direction. It was arranged so that the central axis of the second material 3b was located. As a result, the semi-insulating GaAs crystal of Example III was produced.

上記のように製造された実施例IIIの半絶縁性GaAs結晶体から実施例Iと同様に切り出すことにより、厚さ600μmの複数の半絶縁性GaAs結晶基板を製造した。製造された複数の半絶縁性GaAs結晶基板のうち、半絶縁性GaAs結晶体10の最シード側に対応する部分から得られた半絶縁性GaAs結晶基板を実施例III-1の半絶縁性GaAs結晶基板とし、半絶縁性GaAs結晶体10の最テール側に対応する部分から得られた半絶縁性GaAs結晶基板を実施例III-2の半絶縁性GaAs結晶基板とした。 By cutting out the semi-insulating GaAs crystal body of Example III manufactured as described above in the same manner as in Example I, a plurality of semi-insulating GaAs crystal substrates having a thickness of 600 μm were manufactured. Among the plurality of manufactured semi-insulating GaAs crystal substrates, the semi-insulating GaAs crystal substrate obtained from the portion corresponding to the most seed side of the semi-insulating GaAs crystal body 10 is the semi-insulating GaAs of Example III-1. As the crystal substrate, the semi-insulating GaAs crystal substrate obtained from the portion corresponding to the tail end side of the semi-insulating GaAs crystal body 10 was used as the semi-insulating GaAs crystal substrate of Example III-2.

<比抵抗の平均値および変動係数、転位密度、ならびに表面平坦度の評価>
上記のように製造された実施例III-1(最シード側)および実施例III-2(最テール側)の半絶縁性GaAs結晶基板の主面の上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれにおける比抵抗の平均値および変動係数、転位密度、ならびに表面平坦度を実施例Iと同様にして評価した。結果を表1にまとめた。
<Evaluation of mean and coefficient of variation of specific resistance, dislocation density, and surface flatness>
The above three measurement regions (center measurement region F0) on the main surface of the semi-insulating GaAs crystal substrate of Example III-1 (most seed side) and Example III-2 (tailmost side) manufactured as described above. , The mean value and coefficient of variation of the specific resistance in each of the intermediate portion measurement region F1 and the outer peripheral portion measurement region F2), the shift density, and the surface flatness were evaluated in the same manner as in Example I. The results are summarized in Table 1.

≪比較例I≫
断熱材を用いなかったこと以外は、実施例Iと同様にして比較例Iの半絶縁性GaAs結晶体を製造した。製造された比較例Iの半絶縁性GaAs結晶体から実施例Iと同様に切り出すことにより、厚さ600μmの複数の半絶縁性GaAs結晶基板を製造した。製造された複数の半絶縁性GaAs結晶基板のうち、半絶縁性GaAs結晶体10の最シード側に対応する部分から得られた半絶縁性GaAs結晶基板を比較例I-1の半絶縁性GaAs結晶基板とし、半絶縁性GaAs結晶体10の最テール側に対応する部分から得られた半絶縁性GaAs結晶基板を比較例I-2の半絶縁性GaAs結晶基板とした。製造された比較例I-1(最シード側)および比較例I-2(最テール側)の半絶縁性GaAs結晶基板の主面の上記3つの測定領域(中心部測定領域F0、中間部測定領域F1および外周部測定領域F2)のそれぞれにおける比抵抗の平均値および変動係数、転位密度、ならびに表面平坦度を実施例Iと同様にして評価した。結果を表1にまとめた。
<< Comparative Example I >>
A semi-insulating GaAs crystal of Comparative Example I was produced in the same manner as in Example I except that no heat insulating material was used. By cutting out the semi-insulating GaAs crystal body of Comparative Example I produced in the same manner as in Example I, a plurality of semi-insulating GaAs crystal substrates having a thickness of 600 μm were produced. Among the plurality of manufactured semi-insulating GaAs crystal substrates, the semi-insulating GaAs crystal substrate obtained from the portion corresponding to the most seed side of the semi-insulating GaAs crystal body 10 is the semi-insulating GaAs of Comparative Example I-1. As the crystal substrate, the semi-insulating GaAs crystal substrate obtained from the portion corresponding to the tail end side of the semi-insulating GaAs crystal body 10 was used as the semi-insulating GaAs crystal substrate of Comparative Example I-2. The above three measurement regions (center measurement region F0, intermediate portion measurement) of the main surface of the semi-insulating GaAs crystal substrate of Comparative Example I-1 (most seed side) and Comparative Example I-2 (tailmost side) manufactured. The mean value and coefficient of variation of the specific resistance in each of the region F1 and the outer peripheral measurement region F2), the dislocation density, and the surface flatness were evaluated in the same manner as in Example I. The results are summarized in Table 1.

Figure 0007095781000001
Figure 0007095781000001

表1を参照して、比較例I-1および比較例I-2の半絶縁性GaAs結晶基板においては、主面の中心部測定領域、中間部測定領域および外周部測定領域のいずれにおいても比抵抗の平均値は5.0×107Ω・cm以上であったが、主面の中心部測定領域および外周部測定領域において、比抵抗の変動係数が0.50を超えており、転位密度が1.0×104cm-2以上であり、表面平坦度も1.0μm以上と大きかった。 With reference to Table 1, in the semi-insulating GaAs crystal substrates of Comparative Example I-1 and Comparative Example I-2, the ratio was obtained in any of the central measurement region, the intermediate measurement region, and the outer peripheral measurement region of the main surface. The average value of the resistance was 5.0 × 10 7 Ω · cm or more, but the coefficient of variation of the specific resistance exceeded 0.50 in the central measurement region and the outer peripheral measurement region of the main surface, and the dislocation density. Was 1.0 × 10 4 cm −2 or more, and the surface flatness was as large as 1.0 μm or more.

上記の比較例I-1および比較例I-2の半絶縁性GaAs結晶基板に対して、上記方策Iを行って製造した実施例I-1および実施例I-2の半絶縁性GaAs結晶基板においては、主面の中心部測定領域、中間部測定領域および外周部測定領域のいずれにおいても、比抵抗の平均値は5.0×107Ω・cm以上であり、比抵抗の変動係数が0.50以下である0.39以下であり、転位密度が9.5×103cm-2以下である8.6×103cm-2以下であり、表面平坦度も0.8μm以下と小さかった。すなわち、上記方策Iを行った実施例I-1および実施例I-2においては、主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い半絶縁性GaAs結晶基板が得られた。 The semi-insulating GaAs crystal substrate of Example I-1 and Example I-2 manufactured by performing the above-mentioned measure I with respect to the semi-insulating GaAs crystal substrate of Comparative Example I-1 and Comparative Example I-2. In, the average value of the specific resistance is 5.0 × 10 7 Ω · cm or more in any of the central measurement area, the middle measurement area, and the outer peripheral measurement area of the main surface, and the variation coefficient of the specific resistance is It is 0.50 or less, 0.39 or less, the transfer density is 9.5 × 10 3 cm -2 or less, 8.6 × 10 3 cm -2 or less, and the surface flatness is 0.8 μm or less. It was small. That is, in Example I-1 and Example I-2 in which the above measure I was carried out, a semi-insulating GaAs crystal substrate having a uniform microdistribution of specific resistance on the main surface and high micro flatness on the main surface was obtained. Obtained.

ここで、実施例I-1の半絶縁性GaAs結晶基板は実施例Iの半絶縁性GaAs結晶体の最シード側から切り出されたものであるため、実施例I-1の半絶縁性GaAs結晶基板の主面は、実施例Iの半絶縁性GaAs結晶体の最シード側の断面に相当した。また、実施例I-2の半絶縁性GaAs結晶基板は実施例Iの半絶縁性GaAs結晶体の最テール側から切り出されたものであるため、実施例I-2の半絶縁性GaAs結晶基板の主面は、実施例Iの半絶縁性GaAs結晶体の最テール側の断面に相当した。したがって、実施例I-1および実施例I-2の主面についての結果は、実施例Iの半絶縁性GaAs結晶体の最シード側および最テール側の断面についての結果に相当した。すなわち、上記方策Iを行った実施例Iにおいては、断面における比抵抗のミクロ分布が均一であり、断面のミクロ平坦性が高い半絶縁性GaAs結晶体が得られた。 Here, since the semi-insulating GaAs crystal substrate of Example I-1 is cut out from the most seed side of the semi-insulating GaAs crystal of Example I, the semi-insulating GaAs crystal of Example I-1 The main surface of the substrate corresponds to the cross section of the semi-insulating GaAs crystal of Example I on the most seed side. Further, since the semi-insulating GaAs crystal substrate of Example I-2 is cut out from the tail end side of the semi-insulating GaAs crystal body of Example I, the semi-insulating GaAs crystal substrate of Example I-2 The main surface of the semi-insulating GaAs crystal of Example I corresponded to the cross section on the tail end side of the semi-insulating GaAs crystal. Therefore, the results for the main surfaces of Examples I-1 and I-2 corresponded to the results for the most seeded and tailed cross sections of the semi-insulating GaAs crystal of Example I. That is, in Example I in which the above measure I was carried out, a semi-insulating GaAs crystal body having a uniform micro-distribution of resistivity in the cross section and high micro flatness in the cross section was obtained.

上記の比較例I-1および比較例I-2の半絶縁性GaAs結晶基板に対して、上記方策IIを行って製造した実施例II-1および実施例II-2の半絶縁性GaAs結晶基板においては、主面の中心部測定領域、中間部測定領域および外周部測定領域のいずれにおいても、比抵抗の平均値は5.0×107Ω・cm以上であり、比抵抗の変動係数が0.50以下である0.42以下であり、転位密度が9.5×103cm-2以下である9.0×103cm-2以下であり、表面平坦度も0.8μm以下と小さかった。すなわち、上記方策IIを行った実施例II-1および実施例II-2においては、主面における比抵抗のミクロ分布が均一であり、主面のミクロ平坦性が高い半絶縁性GaAs結晶基板が得られた。 The semi-insulating GaAs crystal substrates of Example II-1 and Example II-2 manufactured by performing the above-mentioned measure II with respect to the semi-insulating GaAs crystal substrates of Comparative Example I-1 and Comparative Example I-2. In, the average value of the specific resistance is 5.0 × 10 7 Ω · cm or more in any of the central part measurement area, the middle part measurement area, and the outer peripheral part measurement area of the main surface, and the variation coefficient of the specific resistance is It is 0.42 or less, which is 0.50 or less, the dislocation density is 9.5 × 10 3 cm -2 or less, 9.0 × 10 3 cm -2 or less, and the surface flatness is 0.8 μm or less. It was small. That is, in Example II-1 and Example II-2 in which the above measure II was performed, a semi-insulating GaAs crystal substrate having a uniform microdistribution of specific resistance on the main surface and high micro flatness on the main surface was obtained. Obtained.

ここで、実施例II-1の半絶縁性GaAs結晶基板は実施例IIの半絶縁性GaAs結晶体の最シード側から切り出されたものであるため、実施例II-1の半絶縁性GaAs結晶基板の主面は、実施例IIの半絶縁性GaAs結晶体の最シード側の断面に相当した。また、実施例II-2の半絶縁性GaAs結晶基板は実施例IIの半絶縁性GaAs結晶体の最テール側から切り出されたものであるため、実施例II-2の半絶縁性GaAs結晶基板の主面は、実施例IIの半絶縁性GaAs結晶体の最テール側の断面に相当した。したがって、実施例II-1および実施例II-2の主面についての結果は、実施例IIの半絶縁性GaAs結晶体の最シード側および最テール側の断面についての結果に相当した。すなわち、上記方策IIを行った実施例IIにおいては、断面における比抵抗のミクロ分布が均一であり、断面のミクロ平坦性が高い半絶縁性GaAs結晶体が得られた。 Here, since the semi-insulating GaAs crystal substrate of Example II-1 is cut out from the most seed side of the semi-insulating GaAs crystal of Example II, the semi-insulating GaAs crystal of Example II-1 The main surface of the substrate corresponded to the cross section on the most seed side of the semi-insulating GaAs crystal of Example II. Further, since the semi-insulating GaAs crystal substrate of Example II-2 is cut out from the tail end side of the semi-insulating GaAs crystal body of Example II, the semi-insulating GaAs crystal substrate of Example II-2 The main surface of the semi-insulating GaAs crystal of Example II corresponded to the cross section on the tail end side of the semi-insulating GaAs crystal. Therefore, the results for the main surfaces of Examples II-1 and II-2 corresponded to the results for the most seeded and tailed cross sections of the semi-insulating GaAs crystals of Example II. That is, in Example II in which the above-mentioned measure II was carried out, a semi-insulating GaAs crystal body having a uniform micro-distribution of resistivity in the cross section and high micro flatness in the cross section was obtained.

上記の比較例I-1および比較例I-2の半絶縁性GaAs結晶基板に対して、上記方策IIIを行って製造した実施例III-1および実施例III-2の半絶縁性GaAs結晶基板においては、主面の中心部測定領域、中間部測定領域および外周部測定領域のいずれにおいても、比抵抗の平均値は5.0×107Ω・cm以上であり、比抵抗の変動係数が0.10以下であり、転位密度が5.5×103cm-2以下であり、表面平坦度も0.5μm以下と極めて小さかった。すなわち、上記方策IIIを行った実施例III-1および実施例III-2においては、主面における比抵抗のミクロ分布が極めて均一であり、主面のミクロ平坦性が極めて高い半絶縁性GaAs結晶基板が得られた。 The semi-insulating GaAs crystal substrate of Example III-1 and Example III-2 manufactured by performing the above-mentioned measure III with respect to the semi-insulating GaAs crystal substrate of Comparative Example I-1 and Comparative Example I-2. In, the average value of the specific resistance is 5.0 × 10 7 Ω · cm or more in any of the central measurement area, the middle measurement area, and the outer peripheral measurement area of the main surface, and the coefficient of variation of the specific resistance is It was 0.10 or less, the dislocation density was 5.5 × 10 3 cm -2 or less, and the surface flatness was 0.5 μm or less, which was extremely small. That is, in Examples III-1 and III-2 in which the above-mentioned measure III was carried out, the micro-distribution of the specific resistance on the main surface was extremely uniform, and the micro-flatness of the main surface was extremely high. The substrate was obtained.

ここで、実施例III-1の半絶縁性GaAs結晶基板は実施例IIIの半絶縁性GaAs結晶体の最シード側から切り出されたものであるため、実施例III-1の半絶縁性GaAs結晶基板の主面は、実施例IIIの半絶縁性GaAs結晶体の最シード側の断面に相当した。また、実施例III-2の半絶縁性GaAs結晶基板は実施例IIIの半絶縁性GaAs結晶体の最テール側から切り出されたものであるため、実施例III-2の半絶縁性GaAs結晶基板の主面は、実施例IIIの半絶縁性GaAs結晶体の最テール側の断面に相当した。したがって、実施例III-1および実施例III-2の主面についての結果は、実施例IIIの半絶縁性GaAs結晶体の最シード側および最テール側の断面についての結果に相当した。すなわち、上記方策IIIを行った実施例IIIにおいては、断面における比抵抗のミクロ分布が極めて均一であり、断面のミクロ平坦性が極めて高い半絶縁性GaAs結晶体が得られた。 Here, since the semi-insulating GaAs crystal substrate of Example III-1 is cut out from the most seed side of the semi-insulating GaAs crystal body of Example III, the semi-insulating GaAs crystal of Example III-1 The main surface of the substrate corresponded to the most seeded cross section of the semi-insulating GaAs crystal of Example III. Further, since the semi-insulating GaAs crystal substrate of Example III-2 is cut out from the tail end side of the semi-insulating GaAs crystal body of Example III, the semi-insulating GaAs crystal substrate of Example III-2 The main surface of the semi-insulating GaAs crystal of Example III corresponded to the cross section on the tail end side of the semi-insulating GaAs crystal. Therefore, the results for the main surfaces of Examples III-1 and III-2 corresponded to the results for the most seeded and tailed cross sections of the semi-insulating GaAs crystals of Example III. That is, in Example III in which the above-mentioned measure III was carried out, a semi-insulating GaAs crystal body in which the micro-distribution of resistivity in the cross section was extremely uniform and the micro flatness in the cross section was extremely high was obtained.

今回開示された実施の形態および実施例はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した実施の形態および実施例ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 The embodiments and examples disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the embodiments and examples described above, and is intended to include the meaning equivalent to the scope of claims and all modifications within the scope.

2 結晶成長用坩堝、3 断熱材、3a 第1材料、3b 第2材料、4 GaAs原料融液、10 半絶縁性GaAs結晶体、11 半絶縁性GaAs結晶基板、11n ノッチ部、E1,E2 測定用電極、F0 中心部測定領域、F1 中間部測定領域、F2 外周部測定領域、SC GaAs種結晶。 2 Crystal growth substrate, 3 Insulation material, 3a 1st material, 3b 2nd material, 4 GaAs raw material melt, 10 Semi-insulating GaAs crystal, 11 Semi-insulating GaAs crystal substrate, 11n notch, E1, E2 measurement Electrode, F0 center measurement area, F1 middle measurement area, F2 outer circumference measurement area, SC GaAs seed crystal.

Claims (3)

面方位が(100)の直径2Rmmの主面において、
前記主面の中心から[010]方向に、0mm、0.5Rmm、および(R-17)mmの距離の点を中心とする3つの測定領域のそれぞれについて、
前記測定領域の中心から[010]方向に-5mmから+5mmの距離の範囲に亘って100μmピッチの101点で比抵抗の測定を行い、前記101点における前記比抵抗の測定値から算出される前記比抵抗の平均値が5×107Ω・cm以上であり、
450℃の溶融水酸化カリウム中で20分間エッチングしたときに形成されるエッチピットの各前記測定領域の中心の1mm角内の密度として算出される転位密度が9.5×103cm-2以下である、半絶縁性ヒ化ガリウム結晶基板。
On a main surface with a diameter of 2 Rmm and a surface orientation of (100),
For each of the three measurement regions centered on points at distances of 0 mm, 0.5 Rmm, and (R-17) mm in the [010] direction from the center of the main surface.
The resistivity is measured at 101 points with a pitch of 100 μm over a distance of -5 mm to +5 mm in the [010] direction from the center of the measurement region, and the resistivity is calculated from the measured values of the resistivity at the 101 points. The average value of resistivity is 5 × 10 7 Ω · cm or more,
The dislocation density calculated as the density within 1 mm square of the center of each measurement region of the etch pit formed when etching in molten potassium hydroxide at 450 ° C. for 20 minutes is 9.5 × 10 3 cm -2 or less. A semi-insulating gallium arsenide crystal substrate.
前記主面の直径2Rmmが150mm以上である、請求項1に記載の半絶縁性ヒ化ガリウム結晶基板。 The semi-insulating gallium arsenide crystal substrate according to claim 1, wherein the main surface has a diameter of 2 Rmm of 150 mm or more. 前記転位密度が5.5×103cm-2以下である、請求項1または請求項2に記載の半絶縁性ヒ化ガリウム結晶基板。 The semi-insulating gallium arsenide crystal substrate according to claim 1 or 2, wherein the dislocation density is 5.5 × 10 3 cm −2 or less.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000103699A (en) 1998-09-28 2000-04-11 Sumitomo Electric Ind Ltd Gallium arsenide single crystal substrate and epitaxial wafer produced by using the same
JP2002540051A (en) 1999-03-19 2002-11-26 フライベルガー・コンパウンド・マテリアルズ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング Equipment for manufacturing single crystals
JP2004026584A (en) 2002-06-26 2004-01-29 Sumitomo Electric Ind Ltd METHOD OF MANUFACTURING GaAs SINGLE CRYSTAL AND GaAs SINGLE CRYSTAL

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JPS56100410A (en) * 1980-01-14 1981-08-12 Sumitomo Electric Ind Ltd Gallium arsenide crystal of low defect density and semi-insulation
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JPH08188499A (en) * 1995-01-10 1996-07-23 Japan Energy Corp Production of gallium-arsenic single crystal
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000103699A (en) 1998-09-28 2000-04-11 Sumitomo Electric Ind Ltd Gallium arsenide single crystal substrate and epitaxial wafer produced by using the same
JP2002540051A (en) 1999-03-19 2002-11-26 フライベルガー・コンパウンド・マテリアルズ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング Equipment for manufacturing single crystals
JP2004026584A (en) 2002-06-26 2004-01-29 Sumitomo Electric Ind Ltd METHOD OF MANUFACTURING GaAs SINGLE CRYSTAL AND GaAs SINGLE CRYSTAL

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GaAs Mantech,1999,p.19-22

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