JP7091929B2 - Relay system - Google Patents

Description

The present invention relates to a relay system.

In Patent Document 1, a high-speed device is connected to a switch having a buffer via a high-speed interface that enables high-speed data transfer, and the switch has a plurality of low speeds via a plurality of low-speed interfaces that enable low-speed data transfer. The configuration to be connected to the device is disclosed.
Patent Document 2 discloses that the route for the first CPU to access the HDD is automatically switched depending on whether the second CPU is in the operating state or the non-operating state.

Japanese Patent No. 5057833 Japanese Unexamined Patent Publication No. 2005-135269

There is a technique for controlling the operation of a device by using a first processing means and a second processing means, each of which executes processing. The first processing means and the second processing means are started by reading the start program from the storage means, respectively.
Here, the second processing means may be provided so that the activation program of the storage means can be acquired via the first processing means. In this case, the second processing is performed until the first processing means is activated. The means could not read the start program, and the second processing means had to wait for the start until the first processing means was started.

An object of the present invention is to activate each of the first processing means and the second processing means without waiting for the activation of the other processing means.

The invention according to claim 1 is a first processing means that starts by reading a first start program and executes a process, and a second process that starts by reading a second start program and executes a process. To the processing means, the storage means for storing the first activation program and the second activation program, and the first processing means and the second processing means for the data stored in the storage means. A first communication path that connects the relay means for relaying delivery, the first processing means, and the relay means, and constitutes a passage through which a data read request from the first processing means passes, and the first communication path. It has a second communication path that connects the second processing means and the relay means and constitutes a passage through which a data read request from the second processing means passes, and the storage means is stored. The data is transmitted to the relay means via the first communication path and the high-speed communication path in which the speed at which the data passes is faster than that of the second communication path, and the relay means communicates with the first communication. Upon receiving a data read request via either the path or the second communication path, the requested data is read from the storage means via the high-speed communication path, and the communication path through which the read request passes. It is a relay system characterized by transmitting the data via the above.
According to the second aspect of the present invention, the first processing means and the relay means are connected to each other, and the speed at which data passes is faster than that of the first communication path and the second communication path. It further has a third communication path that becomes available after the activation of the first processing means, and the second processing means is attached to the storage means via the first processing means and the third communication path. The relay system according to claim 1, wherein the stored data is acquired.
According to the third aspect of the present invention, the storage means has a first storage area for storing the first start program, a second storage area for storing the second start program, and the third communication. It has a third storage area for storing the data specified in the data read request received by the relay means via the channel, and the data read request received by the relay means via the third communication path. The relay system according to claim 2, wherein the storage destination of the data designated in the above-mentioned is the same as the storage destination in the third storage area.
According to a fourth aspect of the present invention, the storage means is activated by a first storage area for storing the first activation program, a second storage area for storing the second activation program, and the relay means. The relay means has a third storage area for storing the data specified by the read request received from the first processing means and / or the second processing means after activation, and the relay means is one of the above. The relay according to claim 1, wherein data can be read from each of the first storage area, the second storage area, and the third storage area via a high-speed communication path. It is a system.
The third aspect of claim 5, wherein the first processing means and the relay means are connected to each other, and the transfer speed when data passes through the first communication path and the second communication path is faster. Further, when the relay means receives a request to read data via the third communication path, the data stored in the third storage area is transferred to the third storage area via the high-speed communication path. The fourth aspect of claim 4, wherein the data is read out and transmitted via the third communication path, and the third communication path and the high-speed communication path are configured by a communication path of the same standard. It is a relay system.
The invention according to claim 6 is characterized in that the relay means acquires the data related to the read request from the storage area of the storage means corresponding to the communication path through which the data read request has passed. The relay system described.
According to the invention of claim 7, the storage means has a first storage area for storing the first start program and a second storage area for storing the second start program, and the relay means. When the communication path through which the data read request passes is the first communication path, the data related to the read request is acquired from the first storage area, and the communication path through which the data read request passes is said. The relay system according to claim 6, wherein in the case of the second communication path, the data related to the read request is acquired from the second storage area.
According to the eighth aspect of the present invention, the relay means has a storage destination of data specified by a data read request received via either the first communication path or the second communication path. A management unit is provided to manage the storage destination information associated with the storage destination of the data stored in the storage means, and when the relay means receives the read request, it is designated by the read request. The relay system according to claim 1, wherein the storage destination reads out data corresponding to the storage destination of the storage means associated with the storage destination information.

According to the first aspect of the present invention, each of the first processing means and the second processing means can be activated without waiting for the activation of the other processing means.
According to the second aspect of the present invention, when data passes through a second communication path without connecting a communication path having a higher speed for passing data than the second communication path to the second processing means. The second processing means can acquire the data via the high-speed communication path.
According to the third aspect of the present invention, the relay means reads the data to the storage means without replacing the storage destination of the data specified by the read request received via the third communication path with another storage destination. You can make a request.
According to the invention of claim 4, as a communication path used for transmitting data stored in the first storage area, the second storage area, and the third storage area of the storage means to the relay means. There is no need to provide a communication path other than the high-speed communication path.
According to the invention of claim 5, the relay means reads out to the storage means without replacing the storage destination of the data specified by the read request received via the third communication path with another storage destination. You can make a request.
According to the sixth aspect of the present invention, the communication path through which the data read request passes and the data acquired from the storage means can be set in association with the type of the processing means that made the read request.
According to the invention of claim 7, the relay means can acquire the start program for starting the processing means for which the read request is made according to the communication path through which the data read request has passed.
According to the invention of claim 8, even if the communication path connecting the processing means and the relay means and the communication path connecting the relay means and the storage means are different standards, the processing means makes a read request. Data can be read from the storage means.

It is a figure which shows an example of the structure of an image formation system. It is a block diagram which shows an example of the internal structure of a control part. It is a figure which showed an example of the internal structure of an HDD module. It is a flowchart which showed the flow of the activation process of an image forming apparatus. It is a flowchart which showed the flow of the data read processing by the 1st CPU after the communication protocol of the 1st high-speed bus was established. It is a figure which showed the modification of the internal structure of the HDD module. It is a figure which showed the structure of the control part which connected the option board.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Structure of image formation system>
FIG. 1 is a diagram showing an example of the configuration of an image forming system according to the present embodiment.
The image forming system of this embodiment includes an image forming apparatus 1, a terminal apparatus 3, a facsimile apparatus 4, and a server apparatus 5. The image forming apparatus 1 and the terminal apparatus 3, the image forming apparatus 1 and the facsimile apparatus 4, and the image forming apparatus 1 and the server apparatus 5 are connected via the network 2.
The image forming apparatus 1 includes a scanning function, a printing function, a copying function, and a facsimile function.

The network 2 is an information communication network responsible for communication between the image forming apparatus 1 and the terminal apparatus 3, the image forming apparatus 1 and the facsimile apparatus 4, and the image forming apparatus 1 and the server apparatus 5. The type of the network 2 is not particularly limited as long as it can transmit and receive data, and may be, for example, the Internet, a LAN (Local Area Network), a WAN (Wide Area Network), or the like. The communication line used for data communication may be wired or wireless. The network 2 that connects the image forming apparatus 1 and the terminal apparatus 3, the network 2 that connects the image forming apparatus 1 and the facsimile apparatus 4, and the network 2 that connects the image forming apparatus 1 and the server apparatus 5 are common. It may be the network 2 of the above, or it may be a different network. Although not particularly shown, the network 2 may be provided with a relay device such as a gateway or a hub for connecting a network or a communication line.

The terminal device 3 is a computer device operated by the user when printing a document. The terminal device 3 gives an instruction such as printing to the image forming device 1 via the network 2. The terminal device 3 is realized by, for example, a computer, a tablet-type information terminal, or another information processing device.
The facsimile machine 4 transmits and receives a facsimile to and from the image forming apparatus 1 via the network 2.
The server device 5 is a server that transmits / receives data to / from the image forming device 1 via the network 2. The server device 5 is realized by, for example, a computer. The server device 5 may be configured by a single computer or may be realized by distributed processing by a plurality of computers.

Further, the image forming apparatus 1 receives an image reading unit 10 for reading an image formed on a recording medium such as paper, an image forming unit 20 for forming an image on the recording medium, and an instruction from the user to the user. It is provided with a user interface (UI) 30 for displaying a message. Further, the image forming apparatus 1 operates the transmission / reception unit 40 for transmitting / receiving data between the terminal device 3, the facsimile apparatus 4 and the server apparatus 5 via the network 2, and the operation of the image forming unit 20, the UI 30 and the transmission / reception unit 40. A control unit 50 for controlling the above is provided.

In the image forming apparatus 1, the scanning function is realized by the image reading unit 10, the printing function is realized by the image forming unit 20, the copying function is realized by the image reading unit 10 and the image forming unit 20, and the image reading unit 10 and the image are realized. The facsimile function is realized by the forming unit 20 and the transmitting / receiving unit 40.

<Internal structure of control unit 50>
FIG. 2 is a block diagram showing an example of the internal structure of the control unit 50.
The control unit 50 includes a first CPU 51A, a second CPU 51B, a first DRAM 53, a second DRAM 54, an HDD (Hard Disk Drive) module 55, and an interface (IF) switch 56. Further, the control unit 50 includes a first low-speed bus 57 connecting the first CPU 51A and the IF switch 56, a first high-speed bus 58 connecting the first CPU 51A and the IF switch 56, and a second CPU 51B and the IF switch 56. A second low-speed bus 59 connecting the above, a second high-speed bus 60 connecting the IF switch 56 and the HDD module 55, and a third high-speed bus 52 connecting the first CPU 51A and the second CPU 51B are provided. ing.

As the first low-speed bus 57 and the second low-speed bus 59 of the present embodiment, a bus according to the communication standard of SPI (Serial Peripheral Interface) is used.
Further, as the first high-speed bus 58, the second high-speed bus 60, and the third high-speed bus 52 of the present embodiment, a bus according to the communication standard of SATA (Serial AT Attachment) is used.

The data transfer speed in the first high-speed bus 58 is faster than the transfer speed in the first low-speed bus 57 and the second low-speed bus 59.
Further, the data transfer speed in the second high-speed bus 60 as an example of the high-speed communication path is faster than the transfer speed in the first low-speed bus 57 and the second low-speed bus 59.
Further, the data transfer speed in the third high-speed bus 52 is faster than the transfer speed in the first low-speed bus 57 and the second low-speed bus 59.

The first CPU 51A as an example of the first processing means controls the operation of the entire image forming apparatus 1. The first CPU 51A executes processing while exchanging data with the first DRAM 53.
The second CPU 51B as an example of the second processing means processes the image data input from the image reading unit 10 and the image data output to the image forming unit 20. The second CPU 51B executes processing while exchanging data with the second DRAM 54. In the following, when the first CPU 51A and the second CPU 51B are not distinguished, they are simply referred to as the CPU 51.
Both the first DRAM 53 and the second DRAM 54 are volatile memories.

The HDD module 55 as an example of the storage means stores the first boot program. The first CPU 51A is started by reading the first boot program. Specifically, the first CPU 51A is started by expanding the first boot program read from the HDD module 55 to the first DRAM 53. Here, the first boot program is regarded as the first boot program.
Further, the HDD module 55 stores the second boot program. The second CPU 51B is started by reading the second boot program. Specifically, the second CPU 51B is started by expanding the second boot program read from the HDD module 55 to the second DRAM 54. Here, the second boot program is regarded as the second boot program.
Further, the HDD module 55 is a non-volatile memory.

The IF switch 56 as an example of the relay means relays the transfer of the data stored in the HDD module 55 to the first CPU 51A and the second CPU 51B. Specifically, when the IF switch 56 receives a read request for data stored in the HDD module 55 from the first CPU 51A or the second CPU 51B, the IF switch 56 reads the requested data from the HDD module 55 and transmits the requested data to the requesting CPU 51. do.

Further, the IF switch 56 is provided with an address translation table 561 as an example of the management unit. The address translation table 561 is a table in which the address information on the first low-speed bus 57 and the address information on the second low-speed bus 59 are associated with the address information on the second high-speed bus 60.

Specifically, in the address translation table 561, the first boot stored in the HDD module 55 is included in the address information included in the read request of the first boot program received by the IF switch 56 via the first low-speed bus 57. The address information corresponding to the program is associated. Further, the address information included in the read request of the second boot program received by the IF switch 56 via the second low-speed bus 59 is associated with the address information corresponding to the second boot program stored in the HDD module 55. Has been done. The information shown in the address conversion table 561, that is, the address information and the HDD module specified in the data read request received via either the first low-speed bus 57 or the second low-speed bus 59. The information associated with the address information corresponding to the data stored in 55 is captured as the storage destination information.

When the IF switch 56 receives a read request of the first boot program or a read request of the second boot program, the IF switch 56 refers to the address translation table 561. Then, a read request is made to the HDD module 55 by replacing it with the address information associated with the address conversion table 561.

In the present embodiment, as described above, the first high-speed bus 58 and the second high-speed bus 60 are configured by a communication path of the same standard.
Therefore, the address information included in the data read request received by the IF switch 56 via the first high-speed bus 58 matches the address information corresponding to the data stored in the HDD module 55. Therefore, when the IF switch 56 receives a data read request via the first high-speed bus 58, the IF switch 56 makes a read request to the HDD module 55 without referring to the address translation table 561. In other words, when the IF switch 56 receives a data read request via the first high-speed bus 58, the IF switch 56 makes a read request to the HDD module 55 without performing address translation.

Further, in the present embodiment, the first CPU 51A, the second CPU 51B, the first DRAM 53, the second DRAM 54, the HDD module 55, the IF switch 56, the first low-speed bus 57, the first high-speed bus 58, the second low-speed bus 59, and the second. The high-speed bus 60 and the third high-speed bus 52 are regarded as a relay system that relays the transfer of data stored in the HDD module 55 to the CPU 51.

<Internal configuration of HDD module 55>
Next, the internal configuration of the HDD module 55 will be described.
FIG. 3 is a diagram showing an example of the internal configuration of the HDD module 55.
The HDD module 55 has an HDD 551 and an internal controller 552.

The HDD 551 is provided with a first boot program storage area A1, a second boot program storage area A2, a program storage area A3, and a work area A4.
The first boot program storage area A1 as an example of the first storage area is an area in which the first boot program is stored.
The second boot program storage area A2 as an example of the second storage area is an area in which the second boot program is stored.
The program storage area A3 is an area in which a program file executed by the first CPU 51A and the second CPU 51B is stored after the start processing of the image forming apparatus 1 is completed.
The work area A4 as an example of the third storage area is an area in which data or the like generated by processing by the first CPU 51A or the second CPU 51B or execution of a program is temporarily stored.

The internal controller 552 transfers data to and from the IF switch 56, and controls reading and writing of data to and from the HDD 551.
When the internal controller 552 receives a data read request from the IF switch 56, the internal controller 552 takes out the requested data from the data storage area corresponding to the address information included in the read request from the storage area of the HDD 551, and takes out the requested data from the IF switch 56. Send to.

<Starting process of image forming apparatus 1>
Next, the activation process of the image forming apparatus 1 will be described.
FIG. 4 is a flowchart showing the flow of the activation process of the image forming apparatus 1. The activation process of the image forming apparatus 1 is executed, for example, when a reset instruction is input to the CPU 51 when the power of the image forming apparatus 1 is turned on via the UI 30 (see FIG. 1).

When the CPU 51 receives the reset instruction, the CPU 51 executes the reset (S101). Specifically, the first CPU 51A clears the stored contents of the first DRAM 53. Further, the second CPU 51B clears the stored contents of the second DRAM 54.

In the present embodiment, once the stored contents of the first DRAM 53 are cleared, data cannot be transmitted / received via the first high-speed bus 58 until the communication protocol of the first high-speed bus 58 is established. On the other hand, even if the stored contents of the first DRAM 53 and the stored contents of the second DRAM 54 are cleared, the communication protocols of the first low-speed bus 57 and the second low-speed bus 59 are established, and the communication protocol is established via the first low-speed bus 57. Data can be transmitted / received and data can be transmitted / received via the second low-speed bus 59. That is, the first low-speed bus 57 is a bus used when the first CPU 51A is started. The second low-speed bus 59 is a bus used when the second CPU 51B is started.
In the present embodiment, the first low-speed bus 57 is regarded as the first communication path. Further, the second low-speed bus 59 is regarded as a second communication path. Further, the first high-speed bus 58 is regarded as a third communication path.

Subsequently, the IF switch 56 receives a data read request from the CPU 51 (S102). Specifically, the IF switch 56 receives a boot program read request from the CPU 51.

The IF switch 56 requests the HDD module 55 to read the boot program (S103). Specifically, the IF switch 56 replaces the address information included in the read request received from the CPU 51 with the address information associated with the address information in the address translation table 561, and the second high-speed bus 60 A read request is made to the HDD module 55 via the above.

Subsequently, the IF switch 56 acquires the boot program stored in the HDD 551 from the internal controller 552 of the HDD module 55 (S104). Specifically, when the internal controller 552 receives a read request from the IF switch 56, it refers to the address information included in the read request, and corresponds to the referenced address information among the boot programs stored in the HDD 551. Get the boot program. Then, the acquired boot program is transmitted to the IF switch 56 via the second high-speed bus 60.

Subsequently, the IF switch 56 transmits the boot program to the CPU 51 (S105). Specifically, the IF switch 56 transmits the acquired boot program to the CPU 51 that has received the read request. When the IF switch 56 receives a boot program read request via the first low-speed bus 57, the IF switch 56 acquires the first boot program and sends the first boot program to the first CPU 51A via the first low-speed bus 57. Send. When the boot program read request is received via the second low-speed bus 59, the second boot program is acquired and the second boot program is transmitted to the second CPU 51B via the second low-speed bus 59.

Subsequently, the CPU 51 reads the boot program and starts it (S106). When the first CPU 51A acquires the first boot program in step 105, the first CPU 51A is started by expanding the first boot program to the first DRAM 53. Further, when the second CPU 51B acquires the second boot program in step 105, the second CPU 51B is started by expanding the second boot program to the second DRAM 54.
Further, the first CPU 51A acquires a program necessary for establishing the communication protocol of the first high-speed bus 58 from the HDD 551, and expands this program to the first DRAM 53 to establish the communication protocol of the first high-speed bus 58. ..

As described above, in the present embodiment, when the IF switch 56 receives a data read request via either the first low-speed bus 57 or the second low-speed bus 59, the requested data is transferred to the HDD module 55. Is read via the second high-speed bus 60, and the data read from the HDD module 55 is transmitted via the bus of the first low-speed bus 57 and the second low-speed bus 59 to which the read request has passed.

Here, the second CPU 51B may acquire the second boot program from the HDD module 55 via the first CPU 51A and start the program. In this case, the second CPU 51B cannot read the second boot program until the first CPU 51A starts, and the start of the second CPU 51B is waited until the first CPU 51A reads and starts the first boot program.
On the other hand, when each of the first CPU 51A and the second CPU 51B has a configuration in which the boot program can be read regardless of the startup of the other CPU 51 as in the present embodiment, each of the first CPU 51A and the second CPU 51B is used as the other CPU. It can be started without waiting for the start of.

In particular, in the present embodiment, an IF switch 56 is provided between the first CPU 51A and the second CPU 51B and the HDD module 55, and the IF switch 56 transmits / receives data to / from the HDD module 55 via the second high-speed bus 60. ..

Further, in the present embodiment, the IF switch 56 has the address of the data specified in the data read request received by the IF switch 56 via either the first low-speed bus 57 or the second low-speed bus 59. An address conversion table 561 that manages the storage destination information in which the information and the address information corresponding to the data stored in the HDD module 55 are associated with each other is provided. Then, when the IF switch 56 receives the read request, the IF switch 56 reads out the data corresponding to the address information of the HDD module 55 to which the address information specified in the read request is associated with the address conversion table 561.

In this case, even if the communication path connecting the CPU 51 and the IF switch 56 and the communication path connecting the IF switch 56 and the HDD module 55 are different standards, the data requested by the CPU 51 to be read is the HDD module 55. Read from.

<Data reading process after starting the image forming apparatus 1>
Next, the data read processing by the first CPU 51A after the communication protocol of the first high-speed bus 58 is established will be described.
FIG. 5 is a flowchart showing a flow of data reading processing by the first CPU 51A after the communication protocol of the first high-speed bus 58 is established.
First, the first CPU 51A requests the IF switch 56 to read data (S201). Specifically, the first CPU 51A makes a data read request to the IF switch 56 via the first high-speed bus 58.

Next, the IF switch 56 requests the HDD module 55 to read data via the second high-speed bus 60 (S202). When the bus through which the data read request has passed is the first high-speed bus 58, the IF switch 56 refers to the HDD module 55 via the second high-speed bus 60 without referring to the address translation table 561. Make a data read request.

Subsequently, the IF switch 56 acquires the data related to the read request from the HDD module 55, and transmits the acquired data to the first CPU 51A (S203). Specifically, the internal controller 552 of the HDD module 55 acquires the data corresponding to the address information included in the read request among the data stored in the HDD 551, and the acquired data is used as the second high-speed bus 60. It is transmitted to the IF switch 56 via. Then, the IF switch 56 transmits the acquired data to the first CPU 51A via the first high-speed bus 58.

When the second CPU 51B makes a data read request via the first CPU 51A, the second CPU 51B first makes a data read request to the first CPU 51A via the third high-speed bus 52. Subsequently, after the processes of steps 201 to 203 shown in FIG. 5 are performed, the first CPU 51A transmits the acquired data to the second CPU 51B via the third high-speed bus 52.

As described above, in the present embodiment, after the first CPU 51A is started, the first high-speed bus 58 is used for the data read request by the first CPU 51A. Further, after the first CPU 51A and the second CPU 51B are started, the first high-speed bus 58 is used for the data read request by the second CPU 51B.

As described above, in the present embodiment, the IF switch 56 is an HDD module corresponding to the bus of the first low-speed bus 57, the first high-speed bus 58, and the second low-speed bus 59 to which the data read request has passed. The data related to the read request is acquired from the storage area of 55.
Specifically, the IF switch 56 acquires the first boot program from the first boot program storage area A1 of the HDD 551 when the bus through which the data read request has passed is the first low-speed bus 57. Further, when the bus through which the data read request has passed is the second low-speed bus 59, the second boot program is acquired from the second boot program storage area A2 of the HDD 551. Further, when the bus through which the data read request has passed is the first high-speed bus 58, the data related to the read request is acquired from the work area A4 of the HDD 551.

Further, in the present embodiment, the HDD module 55 is designated by the read request received from the first CPU 51A and / or the second CPU 51B after the first boot program storage area A1, the second boot program storage area A2, and the IF switch 56 are started. It has a work area A4 for storing the data to be generated. Then, the IF switch 56 reads data from each of the first boot program storage area A1, the second boot program storage area A2, and the work area A4 via the second high-speed bus 60.

In this case, the second high-speed bus used to transmit the data stored in the first boot program storage area A1, the second boot program storage area A2, and the work area A4 of the HDD module 55 to the IF switch 56. There is no need to provide a bus other than the bus 60.

<Modification example>
Subsequently, a modified example of the internal configuration of the HDD module 55 will be described.
FIG. 6 is a diagram showing a modified example of the internal configuration of the HDD module 55.
As shown in FIG. 6, the HDD 551 is provided with a first boot program storage area A1, a second boot program storage area A2, a program storage area A3, and a work area A4. Further, the HDD 551 is provided with an additional boot program storage area A5.

The additional boot program storage area A5 is an area in which the additional boot program is stored. Here, the additional boot program is a boot program to be read by the CPU provided in the option board when the option board to which the CPU is added is provided in the control unit 50.

FIG. 7 is a diagram showing the configuration of the control unit 50 to which the option board is connected.
As shown in FIG. 7, an option board 61 is connected to the control unit 50. Specifically, the option board 61 and the IF switch 56 are connected by a third low-speed bus 62. Further, the second CPU 51B and the option board 61 are connected by the fourth high-speed bus 63.
The option board 61 is provided with an additional CPU 64 and an additional DRAM 65.

As the third low-speed bus 62, a bus according to the communication standard of SPI is used. Further, as the fourth high-speed bus 63, a bus according to the communication standard of SATA is used.
Further, in the address translation table 561, the address information corresponding to the additional boot program stored in the HDD 551 is associated with the address information included in the read request of the additional boot program performed via the third low-speed bus 62. Has been done.

When the additional CPU 64 is started in the start processing of the image forming apparatus 1, the additional CPU 64 requests the IF switch 56 to read the additional boot program via the third low-speed bus 62.

The IF switch 56 refers to the address translation table 561 when the bus to which the read request of the additional boot program has passed is the third low-speed bus 62. Then, the address information included in the read request is replaced with the address information associated with the address information in the address translation table 561, and additional boot is performed for the HDD module 55 via the second high-speed bus 60. Make a read request for the program.
Upon receiving the read request of the additional boot program, the internal controller 552 of the HDD module 55 reads the additional boot program stored in the additional boot program storage area of the HDD 551 as data corresponding to the address information included in the read request. Then, the additional boot program is transmitted to the IF switch 56 via the second high-speed bus 60.
The IF switch 56 transmits the acquired additional boot program to the additional CPU 64 via the third low-speed bus 62.
The additional CPU 64 is started by expanding the acquired additional boot program to the additional DRAM 65.

Further, the additional CPU 64 reads a program for establishing the communication protocol of the fourth high-speed bus 63 from the HDD 551 and deploys it to the additional DRAM 65, whereby the communication protocol of the fourth high-speed bus 63 is established.
After the third communication protocol is established, the additional CPU 64 acquires the data stored in the work area A4 of the HDD 551 via the fourth high-speed bus 63, the second CPU 51B, and the first CPU 51A.

In this way, the additional boot program may be stored in the HDD 551 in advance.
In this case, the additional CPU 64 can be started without waiting for the first CPU 51A and the second CPU 51B to start. Further, it is not necessary to store the additional boot program in the option board 61.

In this embodiment, the second CPU 51B and the option board 61 are connected, but the present invention is not limited to this.
For example, the first CPU 51A and the option board 61 may be connected to each other.

Further, in the present embodiment, as the first high-speed bus 58, the second high-speed bus 60, the third high-speed bus 52, and the fourth high-speed bus 63, a bus according to the SATA communication standard is used. Not limited to.
For example, as the first high-speed bus 58, the second high-speed bus 60, the third high-speed bus 52, and the fourth high-speed bus 63, a bus according to a PCIe (PCI express) communication standard may be used.

Further, in the present embodiment, the configurations (first CPU 51A, second CPU 51B, first DRAM 53, second DRAM 54, HDD module 55, IF switch 56, first low-speed bus 57, first high-speed bus) necessary for realizing the relay system are realized. 58, the second low-speed bus 59, the second high-speed bus 60, and the third high-speed bus 52) are provided in the image forming apparatus 1, but the image forming apparatus 1 is provided with the relay system. Not limited to.

Further, the present disclosure is not limited to the above-described embodiment, and can be carried out in various forms without departing from the gist of the present disclosure.

1 ... Image forming apparatus, 50 ... Control unit, 51A ... First CPU, 51B ... Second CPU, 55 ... HDD module, 56 ... IF switch, 57 ... First low-speed bus, 58 ... First high-speed bus, 59 ... First 2 low speed bus, 60 ... 2nd high speed bus

Claims (8)

The first processing means that starts by loading the first startup program and executes the processing,
A second processing means that starts by loading a second startup program and executes processing,
A storage means for storing the first boot program and the second boot program, and
A relay means for relaying the transfer of data stored in the storage means to the first processing means and the second processing means, and
A first communication path that connects the first processing means and the relay means and constitutes a passage through which a data read request from the first processing means passes.
A second communication path that connects the second processing means and the relay means and constitutes a passage through which a data read request from the second processing means passes.
Have,
The storage means transmits the stored data to the relay means via a high-speed communication path in which the speed at which data passes is faster than that of the first communication path and the second communication path.
When the relay means receives a request for reading data via either the first communication path or the second communication path, the requested data is transmitted from the storage means via the high-speed communication path. A relay system characterized by reading and transmitting the data via a communication path through which the read request has passed. The first processing means and the relay means are connected to each other, and the speed at which data passes is faster than that of the first communication path and the second communication path, and the data can be used after the first processing means is activated. Further has a third communication path to
The relay system according to claim 1, wherein the second processing means acquires data stored in the storage means via the first processing means and the third communication path. The storage means is received by the relay means via a first storage area for storing the first start program, a second storage area for storing the second start program, and the third communication path. It has a third storage area for storing the data specified in the data read request.
2. The second aspect of the present invention, wherein the storage destination of the data specified by the data read request received by the relay means via the third communication path matches the storage destination in the third storage area. Relay system. The storage means includes a first storage area for storing the first start program, a second storage area for storing the second start program, and the first processing means and the first processing means after the relay means is started. / Or has a third storage area for storing the data specified by the read request received from the second processing means after startup.
The relay means is characterized in that data can be read from each of the first storage area, the second storage area, and the third storage area via one high-speed communication path. The relay system according to claim 1. It further has a third communication path that connects the first processing means and the relay means and has a faster transfer rate when data passes through the first communication path and the second communication path.
When the relay means receives a request to read data via the third communication path, the relay means reads the data stored in the third storage area via the high-speed communication path, and reads the data stored in the third communication path through the high-speed communication path. Send the data via
The relay system according to claim 4, wherein the third communication path and the high-speed communication path are configured by a communication path of the same standard. The relay system according to claim 1, wherein the relay means acquires data related to the read request from a storage area of the storage means according to a communication path through which the data read request has passed. The storage means has a first storage area for storing the first start-up program and a second storage area for storing the second start-up program.
When the communication path through which the data read request has passed is the first communication path, the relay means acquires the data related to the read request from the first storage area, and the communication through which the data read request passes. The relay system according to claim 6, wherein when the path is the second communication path, data related to the read request is acquired from the second storage area. In the relay means, the data storage destination designated by the data read request received via either the first communication path or the second communication path and the data stored in the storage means are stored. A management unit is provided to manage the storage destination information associated with the storage destination of
The relay means is characterized in that when it receives the read request, the storage destination specified in the read request reads out the data corresponding to the storage destination of the storage means associated with the storage destination information. The relay system according to claim 1.

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