JP7088050B2 - Power converter for resonant load - Google Patents

Description

The present invention relates to soft switching of a switching element in a load resonance power conversion device that supplies a rectangular wave voltage to a resonance load such as an induction heating circuit.

FIG. 9 shows a circuit configuration of a load resonant power converter (AC / DC converter) connected to a resonant load. In FIG. 9, the AC / DC converter 10 includes a single-phase inverter whose input side is connected to a DC voltage source 11 and whose output side is connected to a resonance load 12 such as an induction heating circuit. By controlling ON and OFF of each switching element of this single-phase inverter, a rectangular wave voltage is output to the resonance load 12 at the resonance frequency.

When the resonance load 12 is an induction heating circuit, the AC / DC conversion device 10 is configured as an induction heating load resonance AC / DC conversion device (induction heating resonance type inverter).

In this load resonance AC / DC converter for inductive heating, the alternating current generated by turning on / off each switching element of the single-phase inverter is passed through the LC resonance circuit by the coil and the capacitor, and the alternating magnetic field generated by the alternating current is heated. It is a method in which an eddy current is applied to a body (electric conductor) to cause an eddy current, and the Joule heat generated by the current causes heating from the inside.

It has been conventionally known that an induction heating circuit as a resonance load connected to the output side of a load resonance power converter (for example, the AC / DC converter 10 in FIG. 9) has a property that the current penetration depth decreases as the frequency increases. There is.

In the electric sewing pipe joining (joining the seams by electric resistance welding to form a pipe), since it is performed by surface quenching, it is possible to output a high frequency voltage to the load resonance AC / DC converter used for induction heating. Required.

On the other hand, since the switching element of the load resonance AC / DC converter used for induction heating has an upper limit of the drive frequency, there is a problem that it cannot cope with a voltage frequency higher than the drive frequency of the switching element.

In order to solve this problem, the inventor of the present application proposes a time-division operation method described in Patent Document 1. Further, conventionally, as a high output high frequency resonant load inverter, the one described in Patent Document 2 has been proposed.

Japanese Patent No. 6079861 Japanese Patent No. 4761696

However, according to the time-division operation method of Patent Document 1, the switching of the upper and lower arms is performed as shown in FIG. 10, which shows the relationship between the ON / OFF timing of each switching element and the load current due to the variation of the switching element of the load resonance AC / DC converter. A dead time must be set when switching. Soft cutoff cannot be realized near the current zero cross, and a cutoff current is generated.

Along with this, there is a problem that the element is overheated due to the occurrence of switching loss and the element is overvoltage due to the breaking surge. In relation to this problem, it is also a problem that the switching loss has a characteristic close to the proportional relationship with the input voltage, so it is difficult to increase the high voltage, and the switching loss increases in proportion to the output frequency, so that the limitation due to overheating is caused by the frequency. ..

The present invention solves the above-mentioned problems, and an object thereof is to generate a k-th harmonic switching pattern in a time-divided operation in which the number of switching elements of a single-phase inverter is M and the number of parallels is N, and the current is zero crossed. It is an object of the present invention to provide a power conversion device for a resonance load that can realize a soft cutoff in the vicinity.

The power conversion device for a resonant load according to claim 1 for solving the above problems is
It is a power conversion device for resonance load equipped with a single-phase inverter that outputs a square wave voltage at the resonance frequency by connecting the DC input side to the DC voltage source and the output side to the resonance load.
N series of m (m is an integer of 2 or more) switching elements connected to the upper and lower arms of one phase and the upper and lower arms of the other phase, respectively (n is 2). The above integers) A switch group circuit configured by connecting each series in parallel with a main circuit conductor,
It is provided with a control unit that controls switching of each switching element of the switch group circuit of the single-phase inverter by time division in 1 / (m × n).
In the switch group circuit of the upper arm of one phase of the single-phase inverter, a first series body in which m switching elements of U11 to U1 m are connected in series and ... m switching elements of Un1 to Unm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of one phase of the single-phase inverter, a first series body in which m switching elements of X11 to X1 m are connected in series and ... m switching elements of Xn1 to Xnm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the upper arm of the other phase of the single-phase inverter, a first series body in which m switching elements of V11 to V1 m are connected in series and ... m switching elements of Vn1 to Vnm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of the other phase of the single-phase inverter, a first series body in which m switching elements of Y11 to Y1 m are connected in series and m switching elements of Yn1 to Ynm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
The control unit
A clock that outputs k (k is an odd harmonic order of 3 or more) every half cycle, triggered by a half cycle of the output current frequency of the single-phase inverter.
2 × number of series M × number of parallels N × k clock (M and N are integers of 2 or more) is set as one cycle, and 2 × number of parallels N × (number of series M-1) × k + 1 clock period ON signal is output. , {2 x number of series M x number of parallels N x k}-{2 x number of parallels N x (number of series M-1) x k + 1} Switching element U11 that outputs a clock period OFF signal, gate command signal U11_gate for Y11 / Y11_gate and
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) 1_gate / V (n-1) 1_gate for the switching elements X (n-1) 1 and V (n-1) 1, and the ON period of the gate command signal is And the gate command signals Un1_gate / Yn1_gate for the switching elements Un1 and Yn1 having the same ON period and OFF period as the OFF period,
The gate command signals Xn1_gate / Vn1_gate for the switching elements Xn1 and Vn1 which are delayed by k clocks from the gate command signal Un1_gate / Yn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal Xn1_gate / Vn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X (n-1) 2, V (n-1) 2 is delayed by k clocks from the gate command signal X (n-1) 2_gate / V (n-1) 2_gate, and the ON period of the gate command signal is And the gate command signal Un2_gate / Yn2_gate for the switching elements Un2 and Yn2 having the same ON period and OFF period as the OFF period,
The gate command signals Xn2_gate / Vn2_gate for the switching elements Xn2 and Vn2, which are delayed by k clocks from the gate command signal Un2_gate / Yn2_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X1 (m-1) and V1 (m-1) is delayed by k clocks from the gate command signal X1 (m-1) _gate / V1 (m-1) _gate, and the gate command signal is turned on and off. A gate command signal U1m_gate / Y1m_gate for switching elements U1m and Y1m having the same ON period and OFF period as the period,
The gate command signals X1m_gate / V1m_gate for the switching elements X1m and V1m, which are delayed by k clocks from the gate command signal U1m_gate / Y1m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U2m_gate / Y2m_gate for switching elements U2m and Y2m, which are delayed by k clocks from the gate command signal X1m_gate / V1m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X2m_gate / V2m_gate for switching elements X2m and V2m, which are delayed by k clocks from the gate command signal U2m_gate / Y2m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) m_gate / V (n-1) m_gate for the switching elements X (n-1) m and V (n-1) m, and the ON period of the gate command signal is And the gate command signal Unm_gate / Ynm_gate for switching elements Unm, Ynm having the same ON period and OFF period as the OFF period,
The gate command signals Xnm_gate / Vnm_gate for switching elements Xnm and Vnm, which are delayed by k clocks from the gate command signal Unm_gate / Ynm_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
Equipped with a gate command creation unit to create
It is characterized in that each switching element is ON / OFF controlled by each of the created gate command signals.

The power conversion device for a resonant load according to claim 2 is claimed in claim 1.
The gate command creation unit
A harmonic command calculation unit that calculates the harmonic command k by sample-holding a variable harmonic command with the rising clock of the gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11.
A carrier upper limit calculation unit that obtains the number of clocks in one cycle of each gate command signal and the carrier upper limit value by calculating 2 × the number of series M × the number of parallels N × k.
The number of clocks in the ON signal period in one cycle (2 × (M-1) × N × k + 1) is subtracted from the number of clocks in one cycle of each gate command signal obtained by the carrier upper limit calculation unit, and 1 The number of clocks in the OFF signal period during the cycle (2 × M × N × k)-{(2 × (M-1) × N × k + 1)} is obtained, and the clocks in the ON signal period in one cycle are used as described above. A PWM command generator that generates a PWM (Pulse Width Modulation) command signal by subtracting the number of clocks during the OFF signal period in one cycle.
A cycle calculation unit that calculates the cycle T of the output current from the zero cross timing of the output current of the single-phase inverter.
The carrier slope obtained by dividing the cycle T calculated by the cycle calculation unit by 2, the carrier upper limit value obtained by the carrier upper limit calculation unit, and the carrier obtained by multiplying the carrier upper limit value by -1. A triangle wave generator that generates a triangle wave signal based on the lower limit,
A delay unit of 2 × N × M-1 that sequentially delays the triangle wave signal generated by the triangle wave generation unit by (T × K) / 2 clocks, and
The PWM command signal generated by the PWM command generation unit is compared with the triangle wave signal generated by the triangle wave generation unit and the triangle wave signal delayed by the 2 × N × M-1 delay units, respectively. A 2 × N × M comparator that outputs a gate ON signal when the triangle wave signal is smaller than the PWM command signal and a gate OFF signal when the triangle wave signal is larger than the PWM command signal.
It is characterized by being equipped with.

The power conversion device for a resonant load according to claim 3 is claimed in claim 2.
The number M in series and the number N in parallel of the switching elements constituting the switch group circuit of each arm of the single-phase inverter are 2.
In the switch group circuit of the upper arm of one phase of the single-phase inverter, a first series body in which two switching elements U11 and U12 are connected in series and two switching elements U21 and U22 are connected in series. It has a second series body and a third series body in which two switching elements U31 and U32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
In the switch group circuit of the lower arm of one phase of the single-phase inverter, a first series body in which two switching elements X11 and X12 are connected in series and two switching elements X21 and X22 are connected in series. It has a second series body and a third series body in which two switching elements of X31 and X32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
In the switch group circuit of the upper arm of the other phase of the single-phase inverter, a first series body in which two switching elements of V11 and V12 are connected in series and two switching elements of V21 and V22 are connected in series. It has a second series body and a third series body in which two switching elements of V31 and V32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
In the switch group circuit of the lower arm of the other phase of the single-phase inverter, a first series body in which two switching elements Y11 and Y12 are connected in series and two switching elements Y21 and Y22 are connected in series. It has a second series body and a third series body in which two switching elements of Y31 and Y32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
The 2 × N × M-1 delay part is composed of 11 delay parts.
The 2 × N × M comparators are composed of 12 comparators.
The gate command creation unit
A clock that outputs k (k is an odd harmonic order of 3 or more) every half cycle, triggered by a half cycle of the output current frequency of the single-phase inverter.
2 x 2 (= series number M) x 3 (= parallel number N) x k clock is set as one cycle, and 2 x 3 (= parallel number N) x 1 (= series number M-1) x k + 1 clock period ON Output a signal, {2 x 2 (= series number M) x 3 (= parallel number N) x k}-{2 x 3 (= parallel number N) x 1 (= series number M-1) x k + 1} The gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11 that output the clock period OFF signal,
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U31_gate / Y31_gate for the switching elements U31 and Y31, which are delayed by k clocks from the gate command signal X21_gate / V21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X31_gate / V31_gate for the switching elements X31 and V31, which are delayed by k clocks from the gate command signal U31_gate / Y31_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal X31_gate / V31_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U32_gate / Y32_gate for the switching elements U32 and Y32, which are delayed by k clocks from the gate command signal X22_gate / V22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X32_gate / V32_gate for the switching elements X32 and V32, which are delayed by k clocks from the gate command signal U32_gate / Y32_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
It is characterized by creating.

The power conversion device for a resonant load according to claim 4 is claimed in claim 2.
The series number M of the switching elements constituting the switch group circuit of each arm of the single-phase inverter is 2.
In the switch group circuit of the upper arm of one phase of the single-phase inverter, a first series body in which two switching elements U11 and U12 are connected in series and ... Two switching elements Un1 and Un2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of one phase of the single-phase inverter, a first series body in which two switching elements X11 and 12 are connected in series and ... Two switching elements Xn1 and Xn2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the upper arm of the other phase of the single-phase inverter, a first series body in which two switching elements of V11 and V12 are connected in series and ... Two switching elements of Vn1 and Vn2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of the other phase of the single-phase inverter, a first series body in which two switching elements Y11 and Y12 are connected in series and ... Two switching elements Yn1 and Yn2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
The gate command creation unit
A clock that outputs k (k is an odd harmonic order of 3 or more) every half cycle, triggered by a half cycle of the output current frequency of the single-phase inverter.
2 x 2 (= series number M) x parallel number N x k clock (N is an integer of 2 or more) is set as one cycle, and 2 x parallel number N x 1 (= series number M-1) x k + 1 clock period ON Outputs a signal and outputs a {2 × 2 (= series number M) × parallel number N × k}-{2 × parallel number N × 1 (= series number M-1) × k + 1} clock period OFF signal. Gate command signals U11_gate / Y11_gate for switching elements U11 and Y11,
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) 1_gate / V (n-1) 1_gate for the switching elements X (n-1) 1 and V (n-1) 1, and the ON period of the gate command signal is And the gate command signals Un1_gate / Yn1_gate for the switching elements Un1 and Yn1 having the same ON period and OFF period as the OFF period,
The gate command signals Xn1_gate / Vn1_gate for the switching elements Xn1 and Vn1 which are delayed by k clocks from the gate command signal Un1_gate / Yn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal Xn1_gate / Vn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X (n-1) 2, V (n-1) 2 is delayed by k clocks from the gate command signal X (n-1) 2_gate / V (n-1) 2_gate, and the ON period of the gate command signal is And the gate command signal Un2_gate / Yn2_gate for the switching elements Un2 and Yn2 having the same ON period and OFF period as the OFF period,
The gate command signals Xn2_gate / Vn2_gate for the switching elements Xn2 and Vn2, which are delayed by k clocks from the gate command signal Un2_gate / Yn2_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
It is characterized by creating.

The power conversion device for a resonant load according to claim 5 is claimed in claim 2.
The feature is that the harmonic command calculation unit is removed and a harmonic command setting unit for setting a fixed harmonic command k is provided.

(1) According to the inventions of claims 1 to 5 , by inputting an odd value to k, k in the time-divided operation in which the number of series of switching elements of the single-phase inverter is M and the number of parallels is N. The next harmonic switching pattern can be generated.

By controlling by this k-th harmonic switching pattern, soft cutoff in the vicinity of the current zero cross is realized, and current cutoff does not occur. Therefore, even if the output voltage is increased, the loss does not increase, and the output is not restricted depending on the output frequency. Moreover, since the dead time can be long, variations in the characteristics of the switching element can be widely tolerated.
(2) According to the inventions of claims 2 to 4, since the harmonic command calculation unit is provided, if the series number M of the switching elements in the single-phase inverter is 2, the harmonic command k is continuously provided. Can be changed, and the device output impedance can be auto-matched. For example, as the harmonic order k increases, the ON period of the switching element in one cycle decreases and the output power decreases, so that the impedance of the resonant load circuit can be adjusted equivalently.
(3) According to the fifth aspect of the present invention, when the number of series M of switching elements in a single-phase inverter is 2 or more and the number of parallels N is 2 or more, the harmonics set by the harmonic command setting unit are used. A control model corresponding to the command k can be generated.

The block diagram of the single-phase inverter according to Example 1 of this invention. The block diagram of the control block according to Example 1 of this invention. The block diagram of the single-phase inverter according to Example 2 of this invention. The block diagram of the control block according to Example 2 of this invention. The block diagram of the single-phase inverter according to Example 3 of this invention. The block diagram of the control block according to Example 3 of this invention. FIG. 3 is a signal waveform diagram showing an example of a gate command signal generation pattern according to the third embodiment of the present invention. An explanatory diagram showing ON / OFF timing and output current waveform of each switching element according to the present invention. The block diagram of the power conversion apparatus for resonance load to which this invention is applied. An explanatory diagram showing the relationship between the dead time and the breaking current of the AC / DC converter connected to the resonant load.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

FIG. 1 shows the configuration of the single-phase inverter unit according to the first embodiment, and shows, for example, a single-phase inverter applied to the AC / DC converter 10 (resonant load power converter) of FIG.

The DC input section of the single-phase inverter shown in FIG. 1 is connected to the DC link voltage input section Vdc, and each arm is connected to M series and N parallel (M = 2 or more integers, N = 2 or more integers; 2 series in the example of FIG. 1). Switch group circuits 100U, 100V, 100X, 100Y equipped with switching elements (for example, IGBTs) of 3 parallel) are connected, respectively, and the common connection points of the switch group circuits 100U and 100X and the common connection points of the switch group circuits 100V and 100Y are connected. In the meantime, the output voltage Vout of the rectangular wave is configured to be output.

In the switch group circuit 100U of the upper arm of one phase of a single-phase inverter, a first series body in which two switching elements U11 and U12 are connected in series and two switching elements U21 and U22 are connected in series. It has a second series body and a third series body in which two switching elements U31 and U32 are connected in series, and three series bodies from the first series body to the third series body. Are connected in parallel and each series is connected by a main circuit conductor.

In the switch group circuit 100X of the lower arm of one phase of the single-phase inverter, a first series body in which two switching elements X11 and X12 are connected in series and two switching elements X21 and X22 are connected in series. It has a second series body and a third series body in which two switching elements of X31 and X32 are connected in series, and three series from the first series body to the third series body. The bodies are connected in parallel and the series are connected by a main circuit conductor.

In the switch group circuit 100V of the upper arm of the other phase of the single-phase inverter, a first series body in which two switching elements V11 and V12 are connected in series and two switching elements V21 and V22 are connected in series. It has a second series body and a third series body in which two switching elements of V31 and V32 are connected in series, and three series from the first series body to the third series body. The bodies are connected in parallel and the series are connected by a main circuit conductor.

In the switch group circuit 100Y of the lower arm of the other phase of the single-phase inverter, a first series body in which two switching elements Y11 and Y12 are connected in series and two switching elements Y21 and Y22 are connected in series. It has a second series body and a third series body in which two switching elements of Y31 and Y32 are connected in series, and three series from the first series body to the third series body. The bodies are connected in parallel and the series are connected by a main circuit conductor.

Each of the above-mentioned series bodies is composed of, for example, a module having a 2in1 structure, and the two switching elements of each series body are connected to each other inside the module.

As described above, according to the single-phase inverter of FIG. 1, since the switching elements of the switch group circuit are connected in series and parallel, the DC link voltage input unit Vdc and the DC input side terminals of the switching elements of the upper and lower arms are connected. The number of main circuit conductors connected between the rectangular wave voltage output unit Vout and the output side terminals of the switching elements of the upper and lower arms can be made smaller than the number of switching elements (M × N). Since the switching elements are connected in series and parallel, the space for arranging the main circuit conductor is not expanded in proportion to the number of switching elements (M × N), and the impedance is based on the variation in the path length of the main circuit conductor. Variation can be reduced.

The control unit that controls the single-phase inverter of FIG. 1 has a control block shown in FIG. 2 that performs k-th harmonic switching by time-division operation. When the number of series M = 2 and the number of parallels N = 3 shown in FIG. 1, the control block of FIG. 2 is triggered by a half cycle of the output current frequency of the single-phase inverter, and k (k is) every half cycle. Using a clock that outputs an odd harmonic order of 3 or more, 2 * N * M * k = 12k clock is used for one cycle, and the ON signal is 2 * N * (M-1) * k + 1 = 7k clock, OFF signal. Is (2 * N * M * k)-{2 * N * (M-1 * k) +1} = 5k clock, and a gate command signal for each switching element is generated.

In FIG. 2, 111 calculates the harmonic command k by sample-holding the input harmonic command with the rising clock of the gate command signal for the switching elements U11 and Y11 output from the comparator _121-1 described later. It is a harmonic command calculation unit.

Reference numeral 112 denotes a carrier upper limit calculation unit for obtaining the number of clocks in one cycle of each gate command signal and the carrier upper limit value by calculating 2 × series number M × parallel number N × harmonic order k.

Reference numeral 113 denotes an ON signal clock number calculation unit that calculates (2 × (M-1) × N × k + 1) to obtain the number of clocks in the ON signal period in one cycle.

In 114, the number of clocks in one cycle obtained by the carrier upper limit calculation unit 112 is subtracted from the number of clocks in one cycle obtained by the ON signal clock number calculation unit 113, and the number of clocks in one cycle is subtracted. It is a subtractor that outputs the number of clocks (2 × M × N × k) − {(2 × (M-1) × N × k + 1)} in the OFF signal period.

The 115 is the output of the subtractor 114 (the number of OFF signal clocks (2 × M × N × k) − (2) from the output (2 × (M-1) × N × k + 1) of the ON signal clock number calculation unit 113. It is a subtractor that outputs a PWM command signal by subtracting × (M-1) × N × k + 1)).

The PWM command generation unit of the present invention is configured by the ON signal clock number calculation unit 113, subtractors 114, and 115.

Reference numeral 116 denotes a cycle calculation unit that calculates the cycle T of the output current from the zero cross timing of the output current of the single-phase inverter of FIG.

117 is a divider that calculates the carrier inclination by dividing the period T calculated by the cycle calculation unit 116 by 2, and 118 sets -1 to the carrier upper limit value obtained by the carrier upper limit calculation unit 112. It is a multiplier that multiplies and outputs the lower limit of the carrier.

119 generates a triangular wave that generates a triangular wave signal based on the carrier upper limit value obtained by the carrier upper limit calculation unit 112, the carrier lower limit value that is the output of the multiplier 118, and the carrier inclination that is the output of the divider 117. It is a department.

120 _-1 to 120 _-11 are 2 × N × M-1 pieces (11 pieces in this Example 1) in which the triangular wave signal generated by the triangular wave generation unit 119 is sequentially delayed by (T × K) / 2 clocks. It is a delay part of.

121 _-1 to 121 _-12 are a PWM command signal output from the subtractor 115, a triangular wave signal generated by the triangular wave generation unit 119, and a triangular wave signal delayed by the delay units 120 _-1 to 120 _-11 , respectively. When the triangular wave signal is smaller than the PWM command signal, the gate ON signal is output, and when the triangular wave signal is larger than the PWM command signal, the gate OFF signal is output 2 × N × M (this implementation). 12 in Example 1).

In the above configuration, using a clock that is triggered by a half cycle of the output current frequency of the single-phase inverter and outputs k (k is an odd harmonic order of 3 or more) every half cycle, the comparators 121 _{-1 to} 121- In ₁₂ , the triangular wave signal output from the triangular wave generation unit 119 is delayed by sequentially (T × k) / 2 clocks in the delay units 120 _-1 to 120 _-11 , and the PWM command output from the subtractor 115. Since the signals are compared with each other, the gate command signals output from the comparators 121 _-1 to 121 _-12 are sequentially delayed by k clocks.

That is, the gate command signals output from the comparators 121 _-1 to 121 _-12 are as follows.

First, from the comparator _121-1 , 2 × 2 (= series number M) × 3 (= parallel number N) × k clock is set as one cycle, and 2 × 3 (= parallel number N) × 1 (= series number M). -1) × k + 1 Clock period ON signal is output, {2 × 2 (= series number M) × 3 (= parallel number N) × k} － {2 × 3 (= parallel number N) × 1 (= Number of series M-1) × k + 1} The gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11 that output the clock period OFF signal are output.

In FIG. 2, the gate command signal U11_gate / Y11_gate is simply described as “U11 / Y11”, and other gate command signals are also described in the same manner.

From the comparator 121-2, the gate command for the switching elements X11 and V11, which is delayed by k clock from the gate command signal _{U11_gate} / Y11_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal X11_gate / V11_gate is output.

From the comparator 121-3, the gate command for the switching elements U21 and Y21, which is delayed by k clock from the gate command signal _{X11_gate} / V11_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal U21_gate / Y21_gate is output.

From the comparator 121 _-4 , the gate command for the switching elements X21 and V21, which is delayed by k clock from the gate command signal U21_gate / Y21_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal X21_gate / V21_gate is output.

From the comparator 121 _-5 , the gate command for the switching elements U31 and Y31, which is delayed by k clock from the gate command signal X21_gate / V21_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal U31_gate / Y31_gate is output.

From the comparator 121 _-6 , the gate command for the switching elements X31 and V31, which is delayed by k clock from the gate command signal U31_gate / Y31_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal X31_gate / V31_gate is output.

From the comparator 121 _-7 , the gate command for the switching elements U12 and Y12, which is delayed by k clock from the gate command signal X31_gate / V31_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal U12_gate / Y12_gate is output.

From the comparator 121 _-8 , the gate command for the switching elements X12 and V12, which is delayed by k clock from the gate command signal U12_gate / Y12_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal X12_gate / V12_gate is output.

From the comparator 121 _-9 , the gate command for the switching elements U22 and Y22, which is delayed by k clock from the gate command signal X12_gate / V12_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal U22_gate / Y22_gate is output.

From the comparator 121 _-10 , the gate command for the switching elements X22 and V22, which is delayed by k clocks from the gate command signal U22_gate / Y22_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal X22_gate / V22_gate is output.

From the comparator _121-11 , the gate command for the switching elements U32 and Y32, which is delayed by k clock from the gate command signal X22_gate / V22_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal U32_gate / Y32_gate is output.

From the comparator _121-12 , the gate command for the switching elements X32 and V32, which is delayed by k clock from the gate command signal U32_gate / Y32_gate and has the same ON period and OFF period as the ON period and OFF period of the gate command signal. The signal X32_gate / V32_gate is output.

When the series number M of the switch group circuit of each arm in the single-phase inverter of FIG. 1 is 2 and the parallel number N is 3, each switching element has each gate command signal U11_gate / Y11_gate ... X32_gate of FIG. By / V32_gate, ON / OFF control is performed by repeating the pattern within one cycle (2 * M * N * k clock).

As described above, according to the control block of FIG. 2, by inputting an odd value to k, the kth order in the time division operation in which the series number M of the switching element of the single-phase inverter is 2 and the parallel number N is 3. Harmonic switching patterns can be generated.

By controlling by this k-th harmonic switching pattern, soft cutoff in the vicinity of the current zero cross is realized, and current cutoff does not occur.

That is, in FIG. 8 showing the relationship between the ON / OFF timing of each of the positive-phase and negative-phase switching elements of the single-phase inverter of FIG. 1 and the load current, it is assumed that the positive-phase output section is 1 and the front and rear thereof are 1a and 1b. Reference numeral 1b is a diode conduction section of the negative phase output element, and even if the positive phase output element is turned off, the current is not cut off. Assuming that the negative phase output section in FIG. 8 is 2 and the front and back thereof are 2a and 2b, the positive phase output element may be turned off and the negative phase output element may be turned on between 1b and 2a, so that the dead time should be long. It is possible to widely tolerate variations in the characteristics of the element.

Since the current cutoff does not occur, the loss does not increase even if the output voltage is increased, and the output restriction depending on the output frequency does not occur.

Further, since the harmonic calculation unit 111 is provided, the harmonic command k can be continuously changed, and the device output impedance can be automatically matched. For example, as the harmonic order k increases, the ON period of the switching element in one cycle decreases and the output power decreases, so that the impedance of the resonant load circuit can be adjusted equivalently.

FIG. 3 shows the configuration of the single-phase inverter unit according to the second embodiment, and shows, for example, the single-phase inverter applied to the AC / DC converter 10 (resonant load power converter) of FIG.

The DC input section of the single-phase inverter shown in FIG. 3 is connected to the DC link voltage input section Vdc, and each arm is a switch group circuit 200U equipped with a switching element (for example, an IGBT) having a series number M of 2 and a parallel number N of 2 or more. , 200V, 200X, 200Y are connected respectively, and a rectangular wave output voltage Vout is output between the common connection point of the switch group circuits 200U and 200X and the common connection point of the switch group circuits 200V and 200Y. Has been done.

In the switch group circuit 200U of the upper arm of one phase of a single-phase inverter, a first series body in which two switching elements U11 and U12 are connected in series and two switching elements U21 and U22 are connected in series. It has a second series body and an nth series body in which two switching elements of Un1 and Un2 are connected in series, and n pieces from the first series body to the nth series body. It is configured by connecting series bodies in parallel and connecting each series body with a main circuit conductor.

In the switch group circuit 200X of the lower arm of one phase of the single-phase inverter, a first series body in which two switching elements X11 and X12 are connected in series and two switching elements X21 and X22 are connected in series. It has a second series body connected and an nth series body in which two switching elements Xn1 and Xn2 are connected in series, and n pieces from the first series body to the nth series body. The series are connected in parallel and the series are connected by a main circuit conductor.

In the switch group circuit 200V of the upper arm of the other phase of the single-phase inverter, a first series body in which two switching elements V11 and V12 are connected in series and two switching elements V21 and V22 are connected in series. It has a second series body connected and an nth series body in which two switching elements of Vn1 and Vn2 are connected in series, and n pieces from the first series body to the nth series body. Series bodies are connected in parallel, and each series body is connected by a main circuit conductor.

In the switch group circuit 200Y of the lower arm of the other phase of the single-phase inverter, a first series body in which two switching elements Y11 and Y12 are connected in series and two switching elements Y21 and Y22 are connected in series. It has a second series body connected and an nth series body in which two switching elements of Yn1 and Yn2 are connected in series, and n pieces from the first series body to the nth series body. The series are connected in parallel and the series are connected by a main circuit conductor.

Each of the above-mentioned series bodies is composed of a series body of two switching elements in one module, and the two switching elements of the series body are connected to each other inside the module.

As described above, according to the single-phase inverter of FIG. 3, since the switching elements of the switch group circuit are connected in series and parallel, the DC link voltage input unit Vdc and the DC input side terminals of the switching elements of the upper and lower arms are connected. The number of main circuit conductors connected between the rectangular wave voltage output unit Vout and the output side terminals of the switching elements of the upper and lower arms can be made smaller than the number of switching elements (M × N). Since the switching elements are connected in series and parallel, the space for arranging the main circuit conductor is not expanded in proportion to the number of switching elements (M × N), and the impedance is based on the variation in the path length of the main circuit conductor. Variation can be reduced.

The control unit that controls the single-phase inverter of FIG. 3 has a control block shown in FIG. 4 that performs k-th harmonic switching by time-division operation. When the number of series M = 2 and the number of parallels N = 2 or more shown in FIG. 3, the control block of FIG. 4 is triggered by a half cycle of the output current frequency of the single-phase inverter, and is k (k) per half cycle. Uses a clock that outputs an odd harmonic order of 3 or more), sets 1 cycle with a 2 * N * M * k = 4Nk clock, and sets the ON signal to 2 * N * (M-1) * k + 1 = 2Nk + 1 clock, OFF. A gate command signal for each switching element is generated with the signal as (2 * N * M * k)-{2 * N * (M-1) * k) +1} = 2Nk-1 clock.

In FIG. 4, the same parts as those in FIG. 2 are indicated by the same reference numerals. The difference from FIG. 2 in FIG. 4 is that the number of delay units 120 installed for sequentially delaying the triangle wave signal generated by the triangle wave generation unit 119 by (T × k) / 2 clocks is 4N-1, and the comparator 121 has. The number of installations is 4N, and the other parts are configured in the same way as in FIG. The gate command signals output from the comparators 121 ... In FIG. 4 are as follows.

That is, the gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11 that output the period ON signal of the 2Nk + 1 clock and the period OFF signal of the 2Nk-1 clock with the 4Nk clock as one cycle (note that the gate in FIG. 4). The command signal U11_gate / Y11_gate is simply written as "U11 / Y11", and other gate command signals are also written in the same manner),
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
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For switching elements Un1 and Yn1 that are delayed by k clocks from the gate command signal X (n-1) 1_gate / V (n-1) 1_gate and have the same ON and OFF periods as the ON and OFF periods of the command signal. Gate command signals Un1_gate / Yn1_gate and
The gate command signals Xn1_gate / Vn1_gate for the switching elements Xn1 and Vn1 which are delayed by k clocks from the gate command signal Un1_gate / Yn1_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal.
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal Xn1_gate / Vn1_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal,
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For switching elements Un2 and Yn2 that are delayed by k clocks from the gate command signal X (n-1) 2_gate / V (n-1) 2_gate and have the same ON and OFF periods as the ON and OFF periods of the command signal. Gate command signals Un2_gate / Yn2_gate and
Outputs gate command signals Xn2_gate / Vn2_gate for switching elements Xn2 and Vn2, which are delayed by k clocks from the gate command signal Un2_gate / Yn2_gate and have the same ON period and OFF period as the ON period and OFF period of the command signal. do.

When the number of series M of the switch group circuit of each arm in the single-phase inverter of FIG. 3 is 2 and the number of parallels is N, each switching element of each gate command signal U11_gate / Y11_gate ... Xn2_gate / By Vn2_gate, ON / OFF control is performed by repeating the pattern within one cycle (2 * M * N * k clock).

As described above, according to the control block of FIG. 4, by inputting an odd value to k, the time division operation is set so that the number of series of switching elements of the single-phase inverter is M = 2 and the number of parallels is N (= 2 or more). It is possible to generate the k-th harmonic switching pattern in.

By controlling by this k-th harmonic switching pattern, soft cutoff in the vicinity of the current zero cross is realized as in the case of the first embodiment, and no current cutoff occurs.

Further, assuming that the number of switching elements in series is M, the number of parallel elements is N (2 or more), and the harmonic command is k, the relational expression of the PWM command is the following equation (1).

PWM command = 2 (M-1), Nk + 1- {2MNK- (2 (M-1), NK + 1)} = 2 (M-1), Nk + 2 (M-1), Nk-2MNK + 2 = 4 (M-1) ) Nk-2MNk + 2 ... (1)
If M in the above equation (1) is 2, the PWM command value is always 2, and a control model capable of continuously switching the harmonic command (k) can be generated.

Therefore, as in the case of the first embodiment, the harmonic command k can be continuously changed, and the device output impedance can be automatically matched. For example, as the harmonic order k increases, the ON period of the switching element in one cycle decreases and the output power decreases, so that the impedance of the resonant load circuit can be adjusted equivalently.

FIG. 5 shows the configuration of the single-phase inverter unit according to the third embodiment, and shows, for example, the single-phase inverter applied to the AC / DC converter 10 (resonant load power converter) of FIG.

The DC input section of the single-phase inverter of FIG. 5 is connected to the DC link voltage input section Vdc, and each arm is a switch group circuit 300U equipped with a switching element (for example, an IGBT) having a series number M of 2 and a parallel number N of 2 or more. , 300V, 300X, 300Y are connected respectively, and a rectangular wave output voltage Vout is output between the common connection point of the switch group circuits 300U and 300X and the common connection point of the switch group circuits 300V and 300Y. Has been done.

The switch group circuit 300U of the upper arm of one phase of the single-phase inverter has m switching of U21, U22 ... U2m and a first series body in which m switching elements of U11, U12 ... U1m are connected in series. It has a second series body in which elements are connected in series, and an nth series body in which m switching elements of Un1, Un2 ... Unm are connected in series, and the first series body to the nth series. It is configured by connecting n series of bodies up to the body in parallel and connecting each series with a main circuit conductor.

The switch group circuit 300X of the lower arm of one phase of the single-phase inverter has a first series body in which m switching elements of X11, X12 ... X1m are connected in series, and m pieces of X21, X22 ... X2m. It has a second series body in which switching elements are connected in series, and an nth series body in which m switching elements of Xn1, Xn2 ... Xnm are connected in series, and the first series body to the nth series body. It is configured by connecting n series bodies up to the series bodies in parallel and connecting each series body with a main circuit conductor.

The switch group circuit 300V of the upper arm of the other phase of the single-phase inverter has a first series body in which m switching elements of V11, V12 ... V1m are connected in series, and m of V21, V22 ... V2m. It has a second series body in which switching elements are connected in series, and an nth series body in which m switching elements of Vn1, Vn2 ... Vnm are connected in series, and the first series body to the nth series body. It is configured by connecting n series bodies up to the series bodies in parallel and connecting each series body with a main circuit conductor.

The switch group circuit 300Y of the lower arm of the other phase of the single-phase inverter includes a first series body in which m switching elements of Y11, Y12 ... Y1m are connected in series, and m of Y21, Y22 ... Y2m. It has a second series body in which switching elements are connected in series, and an nth series body in which m switching elements of Yn1, Yn2 ... Ynm are connected in series, and the first series body to the nth series body. It is configured by connecting n series bodies up to the series bodies in parallel and connecting each series body with a main circuit conductor.

In each of the above-mentioned series bodies, a series body of m switching elements is composed of one module, and the m switching elements of the series body are connected to each other inside the module.

As described above, according to the single-phase inverter of FIG. 5, since the switching elements of the switch group circuit are connected in series and parallel, the DC link voltage input unit Vdc and the DC input side terminals of the switching elements of the upper and lower arms are connected. The number of main circuit conductors connected between the rectangular wave voltage output unit Vout and the output side terminals of the switching elements of the upper and lower arms can be made smaller than the number of switching elements (M × N). Since the switching elements are connected in series and parallel, the space for arranging the main circuit conductor is not expanded in proportion to the number of switching elements (M × N), and the impedance is based on the variation in the path length of the main circuit conductor. Variation can be reduced.

The control unit that controls the single-phase inverter of FIG. 5 has a control block shown in FIG. 6 that performs k-th harmonic switching by time-division operation. When the number of series M = 3 or more and the number of parallels N = 2 or more shown in FIG. 5, the control block of FIG. 6 is triggered by half a cycle of the output current frequency of the single-phase inverter, and k pieces (k) per half cycle. k is a clock that outputs an odd harmonic order of 3 or more), 2 * M * N * k clocks are used for one cycle, ON signals are 2 * (M-1) * N * k + 1 clocks, and OFF signals are used. (2 * M * N * k)-{2 * (M-1) * N * k + 1} clocks are used to generate a gate command signal for each switching element.

In FIG. 6, the same parts as those in FIG. 4 are indicated by the same reference numerals. The difference from FIG. 4 in FIG. 6 is that the number of delay units 120 installed for sequentially delaying the triangle wave signal generated by the triangle wave generation unit 119 by (T × k) / 2 clocks is 2 × N × M-1. The number of comparators 121 installed is 2 × N × M, the harmonic command calculation unit 111 is removed, and a setting unit (not shown) for setting a fixed harmonic command k is provided instead. Yes, the other parts are configured in the same way as in FIG.

FIG. 7 shows an example of the signal generation pattern generated by the control block of FIG. FIG. 7 assumes the case of 3 series (M = 3), 6 parallel (N = 6), and 3rd harmonic switching (k = 3), and 1 cycle is 2 * M * N * k = 108 clocks. , ON signal is 2 * (M-1) * N * k + 1 = 73 clock, OFF signal is (2 * M * N * k)-{2 * (M-1) * N * k + 1} = 35 clock signal The generation pattern is shown.

The gate command signals output from the comparators 121 ... In FIG. 6 are as follows.

That is, the 2 * M * N * k clock is set as one cycle, and the ON signal for the period of 2 * (M-1) * N * k + 1 clock is output, and (2 * M * N * k)-{2 * (M). -1) * N * k + 1} The gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11 that output the clock period OFF signal (note that in FIGS. 6 and 7, the gate command signals U11_gate / Y11_gate are simply "U11 / Y11". , And other gate command signals are also described in the same way),
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) 1_gate / V (n-1) 1_gate for the switching elements X (n-1) 1 and V (n-1) 1, and the ON period of the gate command signal is And the gate command signals Un1_gate / Yn1_gate for the switching elements Un1 and Yn1 having the same ON period and OFF period as the OFF period,
The gate command signals Xn1_gate / Vn1_gate for the switching elements Xn1 and Vn1 which are delayed by k clocks from the gate command signal Un1_gate / Yn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal Xn1_gate / Vn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X (n-1) 2, V (n-1) 2 is delayed by k clocks from the gate command signal X (n-1) 2_gate / V (n-1) 2_gate, and the ON period of the gate command signal is And the gate command signal Un2_gate / Yn2_gate for the switching elements Un2 and Yn2 having the same ON period and OFF period as the OFF period,
The gate command signals Xn2_gate / Vn2_gate for the switching elements Xn2 and Vn2, which are delayed by k clocks from the gate command signal Un2_gate / Yn2_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X1 (m-1) and V1 (m-1) is delayed by k clocks from the gate command signal X1 (m-1) _gate / V1 (m-1) _gate, and the gate command signal is turned on and off. A gate command signal U1m_gate / Y1m_gate for switching elements U1m and Y1m having the same ON period and OFF period as the period,
The gate command signals X1m_gate / V1m_gate for the switching elements X1m and V1m, which are delayed by k clocks from the gate command signal U1m_gate / Y1m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U2m_gate / Y2m_gate for switching elements U2m and Y2m, which are delayed by k clocks from the gate command signal X1m_gate / V1m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X2m_gate / V2m_gate for switching elements X2m and V2m, which are delayed by k clocks from the gate command signal U2m_gate / Y2m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) m_gate / V (n-1) m_gate for the switching elements X (n-1) m and V (n-1) m, and the ON period of the gate command signal is And the gate command signal Unm_gate / Ynm_gate for switching elements Unm, Ynm having the same ON period and OFF period as the OFF period,
The gate command signals Xnm_gate / Vnm_gate for switching elements Xnm and Vnm, which are delayed by k clocks from the gate command signal Unm_gate / Ynm_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal, respectively. Output.

In the single-phase inverter of FIG. 5, when the series number M of the switch group circuit of each arm is 3, the parallel number N is 6, and the harmonic order k is 3, each switching element is each gate of FIG. The command signal U11_gate / Y11_gate ... Xnm_gate / Vnm_gate controls ON / OFF by repeating the pattern in one cycle (2 * M * N * k clock).

As described above, according to the control block of FIG. 6, by inputting an odd value to k, the k-th harmonic in the time-divided operation in which the number of series of switching elements of the single-phase inverter is M and the number of parallels is N is Switching patterns can be generated.

By controlling by this k-th harmonic switching pattern, soft cutoff in the vicinity of the current zero cross is realized as in the case of the first and second embodiments, and the current cutoff does not occur.

Further, from the PWM command relational expression (1) described in the second embodiment, the harmonic command cannot be switched unless M is 2, but according to the third embodiment, the number of series M of the switching elements of the single-phase inverter is M. When is 3 or more and the number of parallels N is 2 or more, a control model corresponding to the fixed harmonic command k can be generated.

10 ... AC / DC converter 11 ... DC voltage source 12 ... Resonant load 100U, 100V, 100X, 100Y, 200U, 200V, 200X, 200Y, 300U, 300V, 300X, 300Y ... Switch group circuit 111 ... Harmonic command calculation unit 112 ... Carrier upper limit calculation unit 113 ... ON signal Clock number calculation unit 114, 115 ... Subtractor 116 ... Periodic calculation unit 117 ... Divider 118 ... Multiplier 119 ... Triangular wave generator 120, 120 _-1 to 120 _-11 ... Delay unit 121, 121 _-1 to 121 _-12 ... Comparer U11 to U1m, U21 to U2m, ... Un1 to Unm, V11 to V1m, V21 to V2m, ... Vn1 to Vnm, X11 to X1m, X21 to X2m, ... Xn1 to Xnm, Y11 ~ Y1m, Y21 ~ Y2m, ... Yn1 ~ Ynm ... Switching element

Claims (5)

It is a power conversion device for resonance load equipped with a single-phase inverter that outputs a square wave voltage at the resonance frequency by connecting the DC input side to the DC voltage source and the output side to the resonance load.
N series of m (m is an integer of 2 or more) switching elements connected to the upper and lower arms of one phase and the upper and lower arms of the other phase, respectively (n is 2). The above integers) A switch group circuit configured by connecting each series in parallel with a main circuit conductor,
It is provided with a control unit that controls switching of each switching element of the switch group circuit of the single-phase inverter by time division in 1 / (m × n).
In the switch group circuit of the upper arm of one phase of the single-phase inverter, a first series body in which m switching elements of U11 to U1 m are connected in series and ... m switching elements of Un1 to Unm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of one phase of the single-phase inverter, a first series body in which m switching elements of X11 to X1 m are connected in series and ... m switching elements of Xn1 to Xnm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the upper arm of the other phase of the single-phase inverter, a first series body in which m switching elements of V11 to V1 m are connected in series and ... m switching elements of Vn1 to Vnm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of the other phase of the single-phase inverter, a first series body in which m switching elements of Y11 to Y1 m are connected in series and m switching elements of Yn1 to Ynm are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
The control unit
A clock that outputs k (k is an odd harmonic order of 3 or more) every half cycle, triggered by a half cycle of the output current frequency of the single-phase inverter.
2 × number of series M × number of parallels N × k clock (M and N are integers of 2 or more) is set as one cycle, and 2 × number of parallels N × (number of series M-1) × k + 1 clock period ON signal is output. , {2 x number of series M x number of parallels N x k}-{2 x number of parallels N x (number of series M-1) x k + 1} Switching element U11 that outputs a clock period OFF signal, gate command signal U11_gate for Y11 / Y11_gate and
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) 1_gate / V (n-1) 1_gate for the switching elements X (n-1) 1 and V (n-1) 1, and the ON period of the gate command signal is And the gate command signals Un1_gate / Yn1_gate for the switching elements Un1 and Yn1 having the same ON period and OFF period as the OFF period,
The gate command signals Xn1_gate / Vn1_gate for the switching elements Xn1 and Vn1 which are delayed by k clocks from the gate command signal Un1_gate / Yn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal Xn1_gate / Vn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X (n-1) 2, V (n-1) 2 is delayed by k clocks from the gate command signal X (n-1) 2_gate / V (n-1) 2_gate, and the ON period of the gate command signal is And the gate command signal Un2_gate / Yn2_gate for the switching elements Un2 and Yn2 having the same ON period and OFF period as the OFF period,
The gate command signals Xn2_gate / Vn2_gate for the switching elements Xn2 and Vn2, which are delayed by k clocks from the gate command signal Un2_gate / Yn2_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X1 (m-1) and V1 (m-1) is delayed by k clocks from the gate command signal X1 (m-1) _gate / V1 (m-1) _gate, and the gate command signal is turned on and off. A gate command signal U1m_gate / Y1m_gate for switching elements U1m and Y1m having the same ON period and OFF period as the period,
The gate command signals X1m_gate / V1m_gate for the switching elements X1m and V1m, which are delayed by k clocks from the gate command signal U1m_gate / Y1m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U2m_gate / Y2m_gate for switching elements U2m and Y2m, which are delayed by k clocks from the gate command signal X1m_gate / V1m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X2m_gate / V2m_gate for switching elements X2m and V2m, which are delayed by k clocks from the gate command signal U2m_gate / Y2m_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) m_gate / V (n-1) m_gate for the switching elements X (n-1) m and V (n-1) m, and the ON period of the gate command signal is And the gate command signal Unm_gate / Ynm_gate for switching elements Unm, Ynm having the same ON period and OFF period as the OFF period,
The gate command signals Xnm_gate / Vnm_gate for switching elements Xnm and Vnm, which are delayed by k clocks from the gate command signal Unm_gate / Ynm_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
Equipped with a gate command creation unit to create
A power conversion device for a resonance load that controls ON / OFF of each switching element by each gate command signal created. The gate command creation unit
A harmonic command calculation unit that calculates the harmonic command k by sample-holding a variable harmonic command with the rising clock of the gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11.
A carrier upper limit calculation unit that obtains the number of clocks in one cycle of each gate command signal and the carrier upper limit value by calculating 2 × the number of series M × the number of parallels N × k.
The number of clocks in the ON signal period in one cycle (2 × (M-1) × N × k + 1) is subtracted from the number of clocks in one cycle of each gate command signal obtained by the carrier upper limit calculation unit, and 1 The number of clocks in the OFF signal period during the cycle (2 × M × N × k)-{(2 × (M-1) × N × k + 1)} is obtained, and the clocks in the ON signal period in one cycle are used as described above. A PWM command generator that generates a PWM (Pulse Width Modulation) command signal by subtracting the number of clocks during the OFF signal period in one cycle.
A cycle calculation unit that calculates the cycle T of the output current from the zero cross timing of the output current of the single-phase inverter.
The carrier slope obtained by dividing the cycle T calculated by the cycle calculation unit by 2, the carrier upper limit value obtained by the carrier upper limit calculation unit, and the carrier obtained by multiplying the carrier upper limit value by -1. A triangle wave generator that generates a triangle wave signal based on the lower limit,
A delay unit of 2 × N × M-1 that sequentially delays the triangle wave signal generated by the triangle wave generation unit by (T × K) / 2 clocks, and
The PWM command signal generated by the PWM command generation unit is compared with the triangle wave signal generated by the triangle wave generation unit and the triangle wave signal delayed by the 2 × N × M-1 delay units, respectively. A 2 × N × M comparator that outputs a gate ON signal when the triangle wave signal is smaller than the PWM command signal and a gate OFF signal when the triangle wave signal is larger than the PWM command signal.
The power conversion device for a resonant load according to claim 1, further comprising. The number M in series and the number N in parallel of the switching elements constituting the switch group circuit of each arm of the single-phase inverter are 2.
In the switch group circuit of the upper arm of one phase of the single-phase inverter, a first series body in which two switching elements U11 and U12 are connected in series and two switching elements U21 and U22 are connected in series. It has a second series body and a third series body in which two switching elements U31 and U32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
In the switch group circuit of the lower arm of one phase of the single-phase inverter, a first series body in which two switching elements X11 and X12 are connected in series and two switching elements X21 and X22 are connected in series. It has a second series body and a third series body in which two switching elements of X31 and X32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
In the switch group circuit of the upper arm of the other phase of the single-phase inverter, a first series body in which two switching elements of V11 and V12 are connected in series and two switching elements of V21 and V22 are connected in series. It has a second series body and a third series body in which two switching elements of V31 and V32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
In the switch group circuit of the lower arm of the other phase of the single-phase inverter, a first series body in which two switching elements Y11 and Y12 are connected in series and two switching elements Y21 and Y22 are connected in series. It has a second series body and a third series body in which two switching elements of Y31 and Y32 are connected in series, and three series bodies from the first series body to the third series body. Are configured in parallel and each series is connected by a main circuit conductor.
The 2 × N × M-1 delay part is composed of 11 delay parts.
The 2 × N × M comparators are composed of 12 comparators.
The gate command creation unit
A clock that outputs k (k is an odd harmonic order of 3 or more) every half cycle, triggered by a half cycle of the output current frequency of the single-phase inverter.
2 x 2 (= series number M) x 3 (= parallel number N) x k clock is set as one cycle, and 2 x 3 (= parallel number N) x 1 (= series number M-1) x k + 1 clock period ON Output a signal, {2 x 2 (= series number M) x 3 (= parallel number N) x k}-{2 x 3 (= parallel number N) x 1 (= series number M-1) x k + 1} The gate command signals U11_gate / Y11_gate for the switching elements U11 and Y11 that output the clock period OFF signal,
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U31_gate / Y31_gate for the switching elements U31 and Y31, which are delayed by k clocks from the gate command signal X21_gate / V21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X31_gate / V31_gate for the switching elements X31 and V31, which are delayed by k clocks from the gate command signal U31_gate / Y31_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal X31_gate / V31_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U32_gate / Y32_gate for the switching elements U32 and Y32, which are delayed by k clocks from the gate command signal X22_gate / V22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X32_gate / V32_gate for the switching elements X32 and V32, which are delayed by k clocks from the gate command signal U32_gate / Y32_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
2. The power conversion device for a resonant load according to claim 2. The series number M of the switching elements constituting the switch group circuit of each arm of the single-phase inverter is 2.
In the switch group circuit of the upper arm of one phase of the single-phase inverter, a first series body in which two switching elements U11 and U12 are connected in series and ... Two switching elements Un1 and Un2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of one phase of the single-phase inverter, a first series body in which two switching elements X11 and 12 are connected in series and ... Two switching elements Xn1 and Xn2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the upper arm of the other phase of the single-phase inverter, a first series body in which two switching elements of V11 and V12 are connected in series and ... Two switching elements of Vn1 and Vn2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
In the switch group circuit of the lower arm of the other phase of the single-phase inverter, a first series body in which two switching elements Y11 and Y12 are connected in series and ... Two switching elements Yn1 and Yn2 are connected in series. It has a connected nth series body, and n series bodies from the first series body to the nth series body are connected in parallel, and each series body is connected by a main circuit conductor. Configured,
The gate command creation unit
A clock that outputs k (k is an odd harmonic order of 3 or more) every half cycle, triggered by a half cycle of the output current frequency of the single-phase inverter.
2 x 2 (= series number M) x parallel number N x k clock (N is an integer of 2 or more) is set as one cycle, and 2 x parallel number N x 1 (= series number M-1) x k + 1 clock period ON Outputs a signal and outputs a {2 × 2 (= series number M) × parallel number N × k}-{2 × parallel number N × 1 (= series number M-1) × k + 1} clock period OFF signal. Gate command signals U11_gate / Y11_gate for switching elements U11 and Y11,
The gate command signals X11_gate / V11_gate for the switching elements X11 and V11, which are delayed by k clocks from the gate command signal U11_gate / Y11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U21_gate / Y21_gate for the switching elements U21 and Y21, which are delayed by k clocks from the gate command signal X11_gate / V11_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X21_gate / V21_gate for the switching elements X21 and V21, which are delayed by k clocks from the gate command signals U21_gate / Y21_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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A k clock delay is delayed from the gate command signal X (n-1) 1_gate / V (n-1) 1_gate for the switching elements X (n-1) 1 and V (n-1) 1, and the ON period of the gate command signal is And the gate command signals Un1_gate / Yn1_gate for the switching elements Un1 and Yn1 having the same ON period and OFF period as the OFF period,
The gate command signals Xn1_gate / Vn1_gate for the switching elements Xn1 and Vn1 which are delayed by k clocks from the gate command signal Un1_gate / Yn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals U12_gate / Y12_gate for the switching elements U12 and Y12, which are delayed by k clocks from the gate command signal Xn1_gate / Vn1_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal.
The gate command signals X12_gate / V12_gate for the switching elements X12 and V12, which are delayed by k clocks from the gate command signal U12_gate / Y12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals U22_gate / Y22_gate for the switching elements U22 and Y22, which are delayed by k clocks from the gate command signal X12_gate / V12_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
The gate command signals X22_gate / V22_gate for the switching elements X22 and V22, which are delayed by k clocks from the gate command signal U22_gate / Y22_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
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The gate command signal for the switching elements X (n-1) 2, V (n-1) 2 is delayed by k clocks from the gate command signal X (n-1) 2_gate / V (n-1) 2_gate, and the ON period of the gate command signal is And the gate command signal Un2_gate / Yn2_gate for the switching elements Un2 and Yn2 having the same ON period and OFF period as the OFF period,
The gate command signals Xn2_gate / Vn2_gate for the switching elements Xn2 and Vn2, which are delayed by k clocks from the gate command signal Un2_gate / Yn2_gate and have the same ON period and OFF period as the ON period and OFF period of the gate command signal,
2. The power conversion device for a resonant load according to claim 2. The power conversion device for a resonance load according to claim 2, wherein the harmonic command calculation unit is removed and a harmonic command setting unit for setting a fixed harmonic command k is provided.

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