JP7087013B2 - Memory system and non-volatile memory control method - Google Patents

Description

Embodiments of the present invention relate to a memory system and a method of controlling a non-volatile memory.

A memory system including a non-volatile memory such as a NAND flash memory and a memory controller, and a method for controlling the non-volatile memory are provided.

Special Table 2012-513702 Publication No. Japanese Unexamined Patent Publication No. 2013-122804 US Pat. No. 8,884,453 Japanese Patent Publication No. 2011-527067 Special Table 2010-533929 Gazette

An object to be solved by the present invention is to provide a memory system with improved performance and a method for controlling a non-volatile memory.

In order to achieve the above-mentioned problems, the controller controls a non-volatile memory having a word line and a plurality of memory cells connected to the word line and having a plurality of blocks which are data erasing units. A second search is requested from the sex memory, and in the second search, the non-volatile memory reads data from a plurality of memory cells a plurality of times using each of the second plurality of read voltages, and the second plurality of reads. The number of seventh values contained in each of the second plurality of data read from the plurality of memory cells using the voltage is calculated, and two adjacent read voltages out of the second plurality of read voltages are used. The difference in the number of the seventh values included in each of the two read data is calculated for each of the second plurality of data. When the minimum value of the calculated differences is equal to or less than the eighth value, the read voltage at which the difference is minimized is determined as the second read voltage, and a response indicating that the second read voltage can be searched is given. Send to the controller. If the minimum value is greater than the eighth value, a response indicating that the second read voltage could not be searched is sent to the controller. The controller performs the first search in response to receiving a response from the non-volatile memory indicating that the second read voltage could not be searched. In the first search, the controller reads data from the plurality of memory cells a plurality of times using each of the first plurality of read voltages, and reads data from the plurality of memory cells using the first plurality of read voltages. The number of the sixth value included in each of the plurality of data of the above is calculated, and the sixth value included in each of the two data read using the two adjacent read voltages out of the first plurality of read voltages. The difference in the number of values is calculated for each of the first plurality of data. Of the differences calculated for each, the read voltage at which the difference is the smallest is determined as the first read voltage. The controller calculates a first difference, which is the difference between the first read voltage and the second reference voltage, and when the first difference is equal to or greater than a predetermined first value, a block containing a plurality of memory cells. Save the data saved in to another block.

The block diagram which shows the configuration example of the memory system which concerns on 1st Embodiment. The figure exemplifying the system which incorporated the memory system which concerns on 1st Embodiment. The figure exemplifying the portable computer which incorporated the memory system which concerns on 1st Embodiment. The figure which shows an example of the appearance of the memory system which concerns on 1st Embodiment. The block diagram of the memory chip of the memory system which concerns on 1st Embodiment. The circuit diagram of the memory cell array of the memory system which concerns on 1st Embodiment. Sectional drawing of the memory cell array of the memory system which concerns on 1st Embodiment. The figure which shows the relationship between the data held in the non-volatile memory of the memory system which concerns on 1st Embodiment, and the threshold voltage of a cell transistor. The figure which shows the shift of the threshold voltage in the memory cell included in the non-volatile memory of the memory system which concerns on 1st Embodiment. The figure which shows the difference data of the number of memory cells which read data is "1". The figure which shows an example of the content of the 1st parameter information of the memory system which concerns on 1st Embodiment. The figure which shows an example of the content of the 2nd parameter information of the memory system which concerns on 1st Embodiment. The flowchart of the patrol processing of the memory system which concerns on 1st Embodiment. An example of a command sequence transmitted from the memory controller of the memory system according to the first embodiment to the memory chip. The flowchart of the 1st modification of the patrol processing of the memory system which concerns on 1st Embodiment. The flowchart of the 2nd modification of the patrol processing of the memory system which concerns on 1st Embodiment. The flowchart of the data read processing for the read request from the host apparatus 2 of the memory system which concerns on 2nd Embodiment. The flowchart of the patrol processing of the memory system which concerns on 3rd Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of a memory system according to the first embodiment. The memory system 1 is connected to the host device 2 by a communication line and functions as an external storage device of the host device 2. The host device 2 may be, for example, an information processing device such as a personal computer, a mobile phone, an image pickup device, a mobile terminal such as a tablet computer or a smartphone, or a game device. , It may be an in-vehicle terminal such as a car navigation system.

The non-volatile memory 100 is a memory that stores data non-volatilely. The non-volatile memory 100 is, for example, a non-volatile semiconductor memory including memory chips # 1 110-1, ..., And memory chips # N 110-N, which are a plurality of memory chips. N is an arbitrary natural number.

In the following description, when it is necessary to specify one of the plurality of memory chips 110-1, ..., 110-N, the reference numerals 110-1, ..., 110-N are used, but are optional. When referring to a memory chip of, or when one memory chip is not distinguished from another memory chip, reference numeral 110 is used.

Each of the memory chips 110 can operate independently of each other, for example, and one example thereof is a NAND flash memory chip. In NAND flash memory, writing and reading are generally performed in data units called pages, and erasing is performed in data units called blocks.

An example of using a NAND flash memory as the non-volatile memory 100 will be described. However, as the non-volatile memory 100, a NAND flash such as a three-dimensional structure flash memory, ReRAM (Resistance Random Access Memory), and FeRAM (Ferroelectric Random Access Memory) will be described. A storage means other than the memory may be used. Further, although an example in which a semiconductor memory is used as the storage means will be described here, a storage means other than the semiconductor memory may be used.

The memory system 1 may be a memory card in which the memory controller 200 and the non-volatile memory 100 are configured as one package, or may be an SSD (Solid State Drive).

The memory controller 200 controls writing to the non-volatile memory 100 according to a write request from the host device 2. In this embodiment, the request is, for example, an instruction or a command. Further, the read from the non-volatile memory 100 is controlled according to the read request from the host device 2. A memory controller is also called a controller.

The memory controller 200 includes a host interface (host I / F) 210, a control unit 220, a data buffer 230, an encoding unit / decoding unit (Encoder / Decoder) 240, and a memory interface (memory I / F) 250. The host I / F 210, the control unit 220, the data buffer 230, the coding unit / decoding unit 240, and the memory I / F 250 are connected by an internal bus 260.

The host I / F 210 performs processing according to the interface standard with the host device 2, and outputs requests, user data, etc. received from the host device 2 to the internal bus 260. Further, the host I / F 210 transmits the user data read from the non-volatile memory 100, the response from the control unit 220, and the like to the host device 2. In the present embodiment, the data written in the non-volatile memory 100 by the write request from the host device 2 is referred to as user data.

The control unit 220 comprehensively controls each component of the memory system 1. The control unit 220 may be realized by hardware, or may be realized by a processor such as a CPU (Central Processing Unit) executing firmware. In the latter case, for example, when the memory system 1 is powered, the processor reads the firmware (control program) stored in the ROM (not shown) onto the buffer 230 or the RAM (not shown) in the control unit 220. By executing a predetermined process, the process of the control unit 220 is realized. Here, the processor is also referred to as a core or a processor core.

When the control unit 220 receives a request from the host device 2 via the host I / F 210, the control unit 220 performs control according to the command. For example, the control unit 220 instructs the memory I / F 250 to write the user data and the parity to the non-volatile memory 100 in accordance with the request from the host device 2. Further, the control unit 220 instructs the memory I / F 250 to give an instruction to the non-volatile memory 100 according to the request from the host device 2.

Further, when the control unit 220 receives the write request from the host device 2, the control unit 220 stores the user data specified in the write request in the data buffer 230, and stores the user data in the non-volatile memory 100 (memory area). To determine. That is, the control unit 220 determines and manages the writing destination of the user data. The correspondence between the logical address of the user data received from the host device 2 and the physical address indicating the storage area on the non-volatile memory 100 in which the user data is stored is stored as an address conversion table.

When the control unit 220 receives a read request from the host device 2, the control unit 220 converts the logical address specified by the read request into a physical address using the above-mentioned address translation table, and reads from the physical address in the memory I. Instruct / F250.

The data buffer 230 temporarily stores the user data received from the host device 2 by the memory controller 200 until it is stored in the non-volatile memory 100. Further, the data buffer 230 temporarily stores the user data read from the non-volatile memory 100 until it is transmitted to the host device 2. The data buffer 230 is composed of, for example, a general-purpose memory such as a SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). Further, the data buffer 230 may be mounted inside the memory controller 200, or may be mounted outside the memory controller 200 independently of the memory controller 200.

Further, the control unit 220 stores the management information 2201 including the address translation table in the data buffer 230. The control unit 220 stores the management information 2201 of the data buffer 230 in the non-volatile memory 100 at a predetermined timing. The control unit 220 stores the management information 2201 of the non-volatile memory 100 in the data buffer 230 when the memory system 1 is started, and updates the management information 2201 of the data buffer 230 when the management information 2201 is changed.

The coding unit / decoding unit 240 includes a coding circuit 241 and a decoding circuit 242. The coding unit / decoding unit is also referred to as an ECC (Error Correcting Code) circuit. The coding circuit 241 encodes the data held in the data buffer 230 to generate a code word having the data and a redundant portion (parity). The coding circuit 241 encodes the user data of the first data length (error correction coding) to generate a code word of the second data length. In the coding performed by the coding circuit 241, for example, a BCH (Bose-Chaudhuri-Hocquenghem) code, an RS (Reed-Solomon) code, an LDPC (Low Density Parity Check) code, or the like can be used. The error correction code used by the coding circuit 241 is not limited to these. The decoding circuit 242 acquires a codeword which is data read from the non-volatile memory 100 via the memory I / F 250, and decodes the acquired codeword. If the decoding circuit 242 fails in error correction during decoding, the decoding circuit 242 notifies the control unit 220 of the error correction failure.

The memory I / F 250 controls the non-volatile memory 110. The memory I / F 250 writes the codeword output from the coding circuit 241 to the non-volatile memory 110 under the control of the control unit 220 and the like. Further, the memory I / F 250 reads data from the non-volatile memory 110 under the control of the control unit 220 and the like, and transfers the data to the decoding circuit 242 via the buffer 230. Further, the memory I / F 250 erases the data stored in the non-volatile memory 110 under the control of the control unit 220 and the like.

The memory I / F 250 is connected to each memory chip 110 via a bus. The bus is a NAND bus based on the example where each memory chip 110 is a NAND flash memory, and the following description and figure are based on the example of the NAND bus. The NAND bus transmits the signals Cen, CLE, ALE, WEen, REN, WPn, RY / BYn, DQ, DQS, and DQSn. As used herein, the trailing n in the name of the signal indicates the inversion logic of the trailing n signal, meaning that it is asserted when the signal is low level.

The asserted signal CEn enables the memory chip 110. The asserted signal CLE notifies the memory chip 110 that the signal DQ flowing to the memory chip 110 in parallel with the asserted signal CLE is a command. The asserted signal ALE notifies the memory chip 110 that the signal DQ flowing to the memory chip 110 in parallel with the asserted signal ALE is an address. The asserted signal WEen indicates that the signal DQ flowing to the memory chip 110 in parallel with the asserted signal WEen is taken into the memory chip 110. The asserted signal REN indicates that the signal DQ is output to the memory chip 110. The asserted signal WPn instructs the memory chip 110 to prohibit data writing and erasing. The signal RY / BYn indicates whether the memory chip 110 is in the ready state or the busy state, and indicates the busy state by the low level. The memory chip 110 accepts an instruction from the memory controller 200 in the ready state and does not accept an instruction from the memory controller 200 in the busy state.

The signal DQ (DQ0 to DQ7) has a width of, for example, 8 bits and is an entity of data, such as a command (CMD), data written to the memory chip 110 or data read from the memory chip 110 (DAT), and an address signal. (ADD), status data (STA), etc. are included. The read data from the memory chip 110 may be simply referred to as read data. The signals DQS and DQSn from the memory controller 200 to the memory chip 110 indicate to the memory chip 110 when to output the signal DQ. On the other hand, the signals DQS and DQSn from the memory chip 110 to the memory controller 200 notify the memory controller 200 of the timing to output the signal DQ.

The memory system 1 is a sensor for measuring the temperature of the memory controller 200, and may include a temperature sensor 300 arranged in the vicinity of the memory controller 200. In this case, the memory controller 200 includes a temperature sensor I / F270 having a function of a communication interface between the memory controller 200 and the temperature sensor 300, and the control unit 220 uses the temperature information measured by the temperature sensor 300 as the temperature. It may be acquired via the sensor I / F270.

2 and 3 show an example of a system 3 in which a memory system 1 and a host device 2 are incorporated. The system 3 is an example of an electronic device.

As shown in FIG. 2, the memory system 1 is incorporated as a storage device in a system 3 such as a server. The system 3 includes a memory system 1 and a host device 2 to which the memory system 1 is mounted. The host device 2 has, for example, a plurality of connectors 4 that are open upward. The connector 4 is, for example, a slot. In the example shown in FIG. 2, the memory system 1 includes a substrate 400, and the non-volatile memory 100 and the memory controller 200 are mounted on the substrate 400. The plurality of memory systems 1 are attached to the connectors 4 of the host device 2 respectively, and are supported side by side in a posture of standing upright in a substantially vertical direction. According to such a configuration, a plurality of memory systems 1 can be compactly mounted, and the host device 2 can be miniaturized.

Further, the memory system 1 may be used as a storage device for electronic devices such as notebook-type portable computers, tablet terminals, and other detachable notebook PCs (personal computers). As shown in FIG. 3, the memory system 1 is mounted on, for example, a portable computer corresponding to the host device 2. Here, the entire portable computer including the memory system 1 becomes the system 3.

The portable computer includes a main body 301 and a display unit 302. The display unit 302 includes a display housing 303 and a display device 304 housed in the display housing 303.

The main body 301 includes a housing 305, a keyboard 306, and a touch pad 307 which is a pointing device. The housing 305 includes a main circuit board, an ODD (Optical Disk Device) unit, a card slot 308, and the like.

The card slot 308 is provided on the side surface of the housing 305. The user can insert the additional device 309 into the card slot 308 from outside the housing 305.

The memory system 1 may be used as a replacement for an HDD (Hard disk drive) in a state of being mounted inside a portable computer, or may be used as an additional device 309.

FIG. 4 is a perspective view showing an example of the appearance of the memory system according to the first embodiment. In this example, the memory system 1 includes a substrate 400. The board 400 includes memory chips 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, and a connection portion 211 included in the host I / F 210. A memory controller 200, a DRAM as a buffer 230, and a temperature sensor 300 may be mounted, but are not limited thereto.

The host I / F 210 has a connection unit 211 (terminal unit), and in the memory system 1 shown in FIG. 4, the connection unit 211 is mounted independently of the memory controller 200 in addition to the memory controller 200. The connection portion 211 has, for example, a plurality of connection terminals (metal terminals). The connection portion 211 is, for example, inserted into the connector 4 of the host device 2 and electrically connected to the connector 4. The host I / F 210 exchanges signals with the host device 2 via the connection unit 211.

Further, in the memory system 1 shown in FIG. 4, the memory chip 110 faces the other memory chip 110, the memory controller 200, the DRAM as the buffer 230, or the temperature sensor 300 with the side surfaces facing each other through a gap of an arbitrary length. The temperature sensor 300 is arranged at a position surrounded by a memory controller 200, a NAND memory 110-1, ..., 110-8, and a DRAM as a buffer 230. The arrangement of 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, the host interface 210, the memory controller 200, the DRAM as the buffer 230, and the temperature sensor 300 is an example. And is not limited to this.

Next, the configuration of the memory chip 110 will be described. FIG. 5 is a block diagram of the memory chip 110 according to the present embodiment. As described above, the memory chip 110 is, for example, a NAND flash memory chip, and in this embodiment, it is a three-dimensional stacked NAND flash memory in which memory cells are three-dimensionally stacked on a semiconductor substrate.

As shown in FIG. 5, the memory chip 110 includes a memory cell array 111, an input / output circuit 112, an input / output control circuit 113, a sequencer (control circuit) 114, a voltage generation circuit 115, a driver 116, a sense amplifier 117, and a column decoder 118. , Data latch 119, row decoder 120, and the like.

The memory cell array 111 includes a plurality of blocks (BLK0, BLK1, ...). A block is, for example, a data erasing unit, and the data in each block is erased all at once. Data may be erased in units smaller than one block (eg, half a block).

Each block is a set of a plurality of string units SU (SU0, SU1, ...). Each string unit SU is a set of a plurality of NAND strings 131. The NAND string 131 includes a plurality of memory cell transistors MT. The memory cell array 111 is further provided with wiring such as a word line WL, a bit line BL, a cell source line CELSRC, and a selection gate line SGDL and SGSL.

The input / output circuit 112 receives the signal DQ or transmits the signal DQ. The input / output circuit 112 also transmits the data strobe signals DQS and DQSn.

The input / output control circuit 113 receives various control signals from the memory controller 200, and controls the input / output circuit 12 based on the control signals. Control signals include signals Cen, CLE, ALE, Wen, REN, WPn, and data strobe signals DQS and DQSn.

The sequencer 114 receives commands and address signals from the input / output circuit 112, and controls the voltage generation circuit 115, the driver 116, the sense amplifier 117, and the column decoder 118 based on the commands and address signals. The sequencer 114 includes a counter 114a and a register 114b.

The voltage generation circuit 115 receives predetermined numerical data from the outside of the memory chip 110, and generates various potentials (voltages) from the received numerical data. The predetermined numerical data is, for example, a digital value (DAC value). The generated potential is supplied to elements such as the driver 116 and the sense amplifier 117. The potential generated by the voltage generation circuit 115 includes, for example, the potential applied to the word line WL, the selective gate lines SGDL and SGSL, and the source line CELSRC. By applying various potentials, voltages are applied to various elements. The driver 116 receives the potential generated by the voltage generation circuit 115 and supplies a selected one of the received potentials to the row decoder 120 under the control of the sequencer 114.

The row decoder 120 receives various potentials from the driver 116, receives an address signal from the input / output circuit 112, selects one block based on the received address signal, and applies the potential from the driver 116 to the selected block. Forward.

The sense amplifier 117 senses the state of the memory cell transistor MT, generates read data based on the sensed state, and transfers the write data to the memory cell transistor MT.

The data latch 119 holds the write data from the input / output circuit 112 and supplies the write data to the sense amplifier. Further, the data latch 119 receives the read data from the sense amplifier 117, and supplies the read data to the input / output circuit 112 under the control of the column decoder 118. The column decoder 118 controls the data latch 119 based on the address signal.

Next, the configuration of the block included in the memory cell array 111 will be described with reference to FIG. FIG. 6 is a circuit diagram of the block.

As shown, the block contains, for example, four string units SU (SU0-SU3). Further, each string unit SU includes a plurality of NAND strings 131.

Each of the NAND strings 131 includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. The memory cell transistor MT includes a laminated gate including a control gate and a charge storage layer, and holds data non-volatilely. The number of memory cell transistors MT is not limited to eight, and may be 16, 32, 64, 128, or the like, and the number is not limited. The memory cell transistor MT is arranged so that its current path is connected in series between the selection transistors ST1 and ST2. The current path of the memory cell transistor MT7 on one end side of this series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected to one end of the current path of the selection transistor ST2. ing.

The gates of the selection transistors ST1 of the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same select gate line SGS among the plurality of string units. Further, the control gates of the memory cell transistors MT0 to MT7 in the same block 0 are commonly connected to the word lines WL0 to WL7, respectively.

That is, the word lines WL0 to WL7 and the select gate line SGS are commonly connected between a plurality of string units SU0 to SU3 in the same block, whereas the select gate line SGD is a string even in the same block. It is independent for each unit SU0 to SU3.

Further, among the NAND strings 131 arranged in a matrix in the memory cell array 111, the other end of the current path of the selection transistor ST1 of the NAND string 131 in the same row is one of the bit lines BL (BL0 to BL (L). -1) and (L-1) are commonly connected to 1 or more natural numbers). That is, the bit line BL commonly connects the NAND string 131 between the plurality of blocks. Further, the other end of the current path of the selection transistor ST2 is commonly connected to the source line SL. The source line SL commonly connects the NAND string 131 between, for example, a plurality of blocks.

As described above, the data of the memory cell transistor MT in the same block is erased all at once. On the other hand, reading and writing of data are collectively performed for a plurality of memory cell transistors MT commonly connected to any word line WL in any string unit SU of any block. In the case of the memory cell transistor MT in which the memory cell transistor MT stores two values (1 bit), the unit performed collectively corresponds to one page.

FIG. 7 is a cross-sectional view of a part of the memory cell array 111 according to the present embodiment. As shown, a plurality of NAND strings 131 are formed on the p-type well region 20. That is, on the well region 20, a plurality of wiring layers 27 functioning as select gate line SGS, a plurality of wiring layers 23 functioning as word line WL, and a plurality of wiring layers 25 functioning as select gate line SGD are formed. ing.

Then, a memory hole 26 that penetrates the wiring layers 25, 23, and 27 and reaches the well region 20 is formed. A block insulating film 28, a charge storage layer 29 (insulating film), and a gate insulating film 30 are sequentially formed on the side surface of the memory hole 26, and a conductive film 31 further embeds the inside of the memory hole 26. The conductive film 31 functions as a current path of the NAND string 131, and is a region in which a channel is formed during the operation of the memory cell transistor MT and the selection transistors ST1 and ST2.

The wiring layer 27 is provided with, for example, four layers, and functions as a gate electrode of the select gate wire SGS and the selection transistor ST2. The wiring layer 27 and the gate insulating film 30 of the lowermost layer are provided up to the vicinity of the n + type impurity diffusion region 33 formed in the surface of the p-type well region 20.

The wiring layer 23 is provided, for example, eight layers, and is provided above the wiring layer 27. The wiring layer 23 functions as a control gate electrode for the corresponding word line WL and the memory cell transistor MT, respectively.

The wiring layer 25 is provided, for example, four layers, and is provided above the wiring layer 23. The wiring layer 25 functions as a select gate wire SGD and a gate electrode of the selection transistor ST1.

With the above configuration, in each NAND string 131, the selection transistor ST2, the plurality of memory cell transistors MT, and the selection transistor ST1 are sequentially stacked on the well region 20.

In the example of FIG. 7, the selection transistors ST1 and ST2 include a charge storage layer 29 like the memory cell transistor MT. However, the selection transistors ST1 and ST2 do not substantially function as memory cells for holding data, but function as switches. At this time, the threshold value at which the selection transistors ST1 and ST2 are turned on / off may be controlled by injecting a charge into the charge storage layer 29.

A wiring layer 32 that functions as a bit line BL is formed at the upper end of the conductive film 31. The bit line BL is connected to the sense amplifier 117.

Further, an n + type impurity diffusion layer 33 and a p + type impurity diffusion layer 34 are formed on the surface of the well region 20. A contact plug 35 is formed on the diffusion layer 33, and a wiring layer 36 that functions as a source line SL is formed on the contact plug 35. The source line SL is connected to a source line driver (not shown). Further, a contact plug 37 is formed on the diffusion layer 34, and a wiring layer 38 that functions as a well wiring CPWELL is formed on the contact plug 37. The well wiring CPWELL is connected to a well driver (not shown). The wiring layers 36 and 38 are formed in a layer above the select gate line SGD and below the wiring layer 32, but this structure is an example and is not limited thereto.

A plurality of the above configurations are arranged in the depth direction of the paper surface shown in FIG. 7, and the string unit SU is formed by a set of a plurality of NAND strings 131 arranged in the depth direction. Further, the wiring layers 27 that are included in the same string unit SU and function as a plurality of select gate line SGS are connected to each other in common. That is, the gate insulating film 30 is also formed on the well region 20 between the adjacent NAND strings 131, and the semiconductor layer 27 and the gate insulating film 28 adjacent to the diffusion layer 33 are formed up to the vicinity of the diffusion layer 33.

Therefore, when the selection transistor ST2 is turned on, the channel electrically connects the memory cell transistor MT0 and the diffusion layer 33. Further, by applying a voltage to the well wiring CPWELL, a potential can be applied to the conductive film 31.

The configuration of the memory cell array 111 may be another configuration. That is, the configuration of the memory cell array 111 is described in, for example, US Patent Application No. 12 / 407, 403 filed on March 19, 2009, entitled "Three-dimensional laminated non-volatile semiconductor memory". In addition, US Patent Application No. 12 / 406,524, which was filed on March 18, 2009, "Three-dimensional laminated non-volatile semiconductor memory", and "Non-volatile semiconductor storage device and its manufacturing method", March 25, 2010. It is described in US Patent Application No. 12 / 679,991 "Semiconductor Memory and its Manufacturing Method" filed in US Patent Application No. 12 / 532,030 filed on March 23, 2009. These patent applications are incorporated herein by reference in their entirety.

Next, the memory cell transistor MT will be described with reference to FIG. The memory chip 110 can hold one bit or more of data in one memory cell transistor MT. As an example, FIG. 8 shows the distribution of the threshold voltage of the memory cell transistor MT holding 3 bits of data per memory cell transistor as a result of data writing. The threshold voltage of each memory cell transistor MT has a value corresponding to the held 3-bit data. For storage of 3 bits per memory cell transistor MT, each memory cell transistor MT may have any of eight threshold voltages. The eight threshold voltages are, for example, "111" data, "110" data, "100" data, "000" data, "010" data, "011" data, "001" data, and "101" data, respectively. It is in a holding state. The combination of the eight threshold voltages and the 3-bit data is not limited to the example of FIG.

A set of data of bits at the same position in the memory cell transistor MT of one cell unit CU constitutes a page. The set of data of the most significant bit of the memory cell transistor MT of one cell unit CU constitutes the upper page. The set of data of the middle bits of the memory cell transistor MT of one memory cell unit CU constitutes a middle page. The set of data of the least significant bits of the memory cell transistor MT of one cell unit CU constitutes a lower page.

Even a plurality of memory cell transistors MTs holding the same 3-bit data may have different threshold voltages due to variations in the characteristics of the memory cell transistors MT and the like. Therefore, the threshold voltages of the plurality of transistors MT holding the same data form one distribution. The distribution is referred to as Er, A, B, C, D, E, F, and G levels. The threshold voltage in the A level is higher than the threshold voltage in the Er level. Similarly, the threshold voltages in the B, C, D, E, F, and G levels are higher than the threshold voltages in the A, B, C, D, E, and F levels, respectively. The Er level is the distribution of the threshold voltage of the memory cell transistor MT in the erased state.

In order to determine the data held by the memory cell transistor MT to be read, the level to which the threshold voltage of the memory cell transistor MT belongs is determined. Readout voltages VA, VB, VC, VD, VE, VF, and VG are used to determine the level. Hereinafter, the voltage of a certain value applied to the memory cell transistor MT to be read for level determination, including the voltages VA, VB, VC, VD, VE, VF, and VG, is referred to as a read voltage VCGR. There is.

Whether or not the threshold voltage of the memory cell transistor MT to be read exceeds a certain read voltage VCGR is used to determine the level to which the threshold voltage of the memory cell transistor MT belongs. The read voltage VA is higher than the highest threshold voltage of the Er level memory cell transistor MT and lower than the lowest threshold voltage of the B level memory cell transistor MT, that is, located between the Er level and the A level. Similarly, the read voltages VB, VC, VD, VE, and VF are between A and B levels, between B and C levels, between C and D levels, and between D and E levels, respectively. , E level and F level, and between F level and G level. The memory cell transistor MT having a threshold voltage equal to or higher than the read voltage VCGR keeps off even if the read voltage VCGR is received at the control gate electrode. On the other hand, the memory cell transistor MT having a threshold voltage lower than the read voltage VR is turned on when the read voltage VCGR is received at the control gate electrode. The voltage VREAD is applied to the word line WL of the memory cell transistor MT of the cell unit CU to be non-read, and is higher than the threshold voltage of the memory cell transistor MT at any level.

Readout voltages VA, VB, VC, VF, VE, VF, and VG are preset, and more specifically, numerical data corresponding to readout voltages VA, VB, VC, VF, VE, VF, and VG. (DAC value) is set in advance. The preset numerical data is, for example, 25DAC, 90DAC, 140DAC, 220DAC, 300DAC, 370DAC, 420DAC. These numerical data are stored in, for example, the data area of the memory cell array 111. This numerical data is read from the memory cell array 111 when the memory chip 110 is powered on, and is transferred to, for example, the register 114b. The memory controller 200 may acquire and retain these numerical data via the memory I / F 250.

The shift of the threshold voltage of the memory cell transistor MT will be described with reference to FIG. The memory cell transistor MT is affected by, for example, a program disturb after writing and a read disturb after reading. Under this influence, the threshold voltage of the memory cell transistor MT may shift to the negative side, for example, as shown in FIG.

At this time, with the preset read voltage, data cannot be read accurately from the memory cell transistor MT, and the bit error rate may increase. Here, the bit error rate indicates the ratio of error bits contained in the read data.

Therefore, the memory controller 200 may execute shift read or Vth tracking in order to specify the optimum read voltage for the page where the bit error rate has increased.

The shift read is a read operation for searching for the optimum read voltage of the memory cell transistor MT, and is a read operation performed by using a voltage value shifted from a preset read voltage.

In the shift read, the read voltage is changed by a fixed amount, and data is read from the non-volatile memory 100 using each read voltage. The control unit 220 provides a search area centered on a preset read voltage corresponding to each threshold voltage distribution, and executes a read operation for the non-volatile memory 110 for each read voltage. Then, in this search region, the optimum read voltage is determined based on the read voltage having the smallest number of error bits.

Vth tracking is also a read operation for the non-volatile memory 110 for searching for the optimum read voltage of the memory cell transistor MT. The Vth tracking executed by the memory controller 200 is also referred to as a first Vth tracking.

In the first Vth tracking, the control unit 220 divides the read voltage range into predetermined numbers, for example, and obtains the Vth distribution based on the data read using each read voltage.

For example, the control unit 220 first reads data by applying a certain read voltage to a predetermined word line, and counts the number of “1” contained in the read data.

For example, the control unit 220 then reads data by applying a read voltage shifted by a predetermined voltage width to the predetermined word line, counts the number of “1” contained in the read data, and counts the number of “1”. The difference from the number of "1" counted when the read voltage before shifting the voltage width is used is obtained.

For example, the control unit 220 then repeats the above operation a predetermined number of times to obtain a Vth distribution as shown in FIG. 10 when the read voltage is plotted on the horizontal axis and the difference is plotted on the vertical axis. The control unit 220 may perform a predetermined smoothing process after plotting to obtain a Vth distribution as shown in FIG.

Then, for example, the control unit 220 obtains a valley of the Vth distribution as shown in FIG. 10, that is, a read voltage that minimizes the difference between the numbers of "1" counted by the adjacent read voltages in the Vth distribution. Is determined as the optimum read voltage of the memory cell transistor MT. The memory cell transistor MT is also simply referred to as a memory cell.

Next, the management information 2201 will be described with reference to FIGS. 11 and 12. The management information 2201 may further include, but is not limited to, first parameter information 2202 and second parameter information 2203.

FIG. 11 is a diagram showing an example of the contents of the first parameter information 2202. As shown in the figure, the first parameter information 2202 is a table in which various operation parameters are associated with a page number which is an example of page identification information. The operating parameter is, for example, a read voltage used when reading data from the page, but is not limited to this. When the operating parameter is the read voltage, a preset read voltage value is set as the initial value, but the control unit 220 uses, for example, an optimum read voltage determined by shift read or Vth tracking. The operating parameters may be updated. Further, the control unit 220 may store the preset read voltage value in the first parameter information 2202 separately from the read voltage.

FIG. 12 is a diagram showing an example of the contents of the second parameter information 2203. As shown in the figure, the second parameter information 2203 includes, for example, a write generation number, temperature information such as the temperature of the memory controller 220 acquired from the temperature sensor 300 at the time of writing, and writing to the page number, which is an example of page identification information. Includes part or all of the number of reads, erases, writes, etc. since the process was performed.

Both the first parameter information 2202 and the second parameter information 2203 may be tables classified for each memory chip 110 and for each block.

The write generation number is information related to the order in which the data is written. When the memory system 1 starts writing data to a block, the memory system 1 writes the data to the pages of the block until all the pages of the block have been written. For example, the memory system 1 may assign write generation numbers "1" to "m" (m is a natural number of 2 or more) in the writing order of the pages of a certain block, and the writing generation is common to each page of the block. The number "m" may be assigned.

Then, for example, when writing data to another block, the memory system 1 may assign write generation numbers "m + 1" to "2m" in the writing order of the pages of the other block, or each page of the block may be given a write generation number "m + 1" to "2m". The writing generation number "2m" may be assigned in common.

As described above, the value of the writing generation number tends to become smaller as the elapsed time from the writing is increased. Since the frequency of writing is not uniform, the difference in write generation number is not directly proportional to the difference in elapsed time, but at least pages with a small write generation number are compared to pages with a large write generation number. It can be said that the elapsed time from writing is long. In addition, instead of the writing generation number, the elapsed time from the writing may be retained.

Next, the access process for the data stored in the non-volatile memory 100 of the memory system according to the first embodiment will be described.

In the memory system according to the first embodiment, when the memory system 1 receives a read request, a write request, a data erase request, a data deletion request such as a trim command, or the like from the host device 2, the memory controller 200 is in the background. However, the memory controller 200 accesses the non-volatile memory 100 when performing garbage collection, refreshing, wear leveling, patrol processing, and the like.

Garbage collection is also known as compaction. Since the non-volatile memory 100 has a different data erasing unit and data read / write unit, as the rewriting of the non-volatile memory progresses, the blocks are fragmented by invalid data, and the number of such fragmented blocks increases. , Fewer blocks can be used. Garbage collection is a process for increasing the available blocks, for example, collecting valid data from multiple active blocks containing valid and invalid data, rewriting it into another block, and securing free blocks. Means processing.

The active block indicates a block in which valid data is recorded. A free block indicates a block in which valid data is not recorded. Free blocks can be reused as erased blocks after being erased. In the present embodiment, the free block includes both the pre-erased block in which valid data is not recorded and the erased block. The valid data is the data associated with the logical address, and the invalid data is the data not associated with the logical address. The erased block becomes an active block when data is written.

Refreshing is the process of rewriting the data in one block to another block. When the memory controller 200 detects deterioration of data in a certain block such as an increase in the number of correction bits in error correction processing, the memory controller 200 executes a refresh to rewrite the data in the block to another block.

Wear leveling rewrites a block of the non-volatile memory 100 by, for example, exchanging data stored in a block having a large number of rewrites or erasures with data stored in a block having a small number of rewrites or erasures. It is a process to level the number of times.

The patrol process is an operation for checking and confirming whether the data recorded in the non-volatile memory 100 is lost due to deterioration of the medium, and the memory system 100 voluntarily performs without receiving an instruction from the host device 1. To do.

In the patrol process, for example, in order to detect a block in which an error has increased, the data stored in the non-volatile memory 100 is read out in predetermined units, and the read data is read out based on the error correction result in the decoding circuit 242. It is a process to check. In this embodiment, the predetermined unit is one cell unit CU, but other units may be used as the patrol read unit.

In this check process, for example, the number of error bits of the read data is compared with the threshold value, and the data whose number of error bits exceeds the threshold value is targeted for refreshment. For example, when the number of error bits of the data read from a certain cell unit CU exceeds the threshold value, the control unit 220 refreshes the data in the block including the cell unit CU. That is, the control unit 220 re-stores the data stored in the block including the cell unit CU in which the number of error bits exceeds the threshold value in another block. The control unit 220 invalidates the data stored in the original block, that is, makes the original block a free block.

The control unit 220 periodically executes a patrol process on the active block in the non-volatile memory 100. The control unit 220 executes patrol processing for all active blocks within the time of the cycle time Ta. When the control unit 220 completes the patrol processing for all active blocks within a certain cycle time Ta time, the control unit 220 can continuously perform the patrol processing and complete the patrol processing for all active blocks within the next cycle time Ta time. To do so.

The cycle time Ta is counted in terms of time when the memory system 1 is on, and is set in any time unit such as 10 hours or 100 hours. When the memory system 1 receives a command such as a read request or a write request from the host device 1 while the patrol process is being executed, the memory controller 200 executes the process for the command received from the host device 1 in preference to the patrol process. do.

FIG. 13 is a flowchart of the patrol process of the memory system according to the first embodiment. In the flowchart of FIG. 13, the description will be made from the stage when the memory controller 200 decides to patrol the predetermined cell unit CU of the non-volatile memory 100.

In the present embodiment, the memory chip 110 including the cell unit CU to be patrolled will be described as the memory chip 110-1.

The control unit 220 requests the memory chip 110-1 for Vth tracking for the cell unit CU to be patrolled via the memory I / F 250 (step 1301).

The control unit 220 patrols the memory chip 110-1 via the memory I / F 250 in order to request the memory chip 110-1 to search for the optimum value of the read voltage for the cell unit CU to be patrol. Sends a command requesting the execution of Vth tracking of the cell unit CU of.

The memory chip 110-1 transmits a Vth tracking result (VD) via the memory I / F 250 as a response to a command requesting execution of Vth tracking transmitted from the control unit 220 via the memory I / F 250. The control unit 220 acquires the Vth tracking result (VD) transmitted from the memory chip 110-1 via the memory I / F 250.

In this way, the control unit 220 requests the memory chip 110 to execute Vth tracking of the predetermined cell unit CU, and the memory chip 110 executes Vth tracking of the predetermined cell unit CU to the memory controller 200. On the other hand, outputting the Vth tracking result and acquiring the Vth tracking result output from the memory chip 110 in response to the Vth tracking execution request by the control unit 220 is also referred to as a second Vth tracking.

FIG. 14 is a command showing a signal transmitted from the memory controller 200 to the memory chip 110 via the memory I / F 250 in order to request the memory chip 110 to execute Vth tracking of the cell unit CU to be patrol. An example of the sequence is shown. FIG. 14 also shows a signal flowing from the memory chip 110 to the memory controller 200 in response to a request for Vth tracking, and a signal RY / BYn. FIG. 14 shows only the signal transmitted as the signal DQ and the RY / BYn signal indicating the ready / busy state of the memory chip 110-1, and the other signals Cen, CLE, ALE, Wen, REN, WPn, The illustration of DQS and DQSn is omitted.

As shown in FIG. 14, the control unit 220 transmits the command XXh via the memory I / F 250. During the transmission of command XXh, the signal CLE (not shown) is asserted. The command XXh is, for example, a command for instructing a request for Vth tracking.

The control unit 220 transmits an address signal over 5 cycles following the command XXh via the memory I / F 250. The address signal specifies an area to be read out of the storage area of the non-volatile memory 100. During the transmission of the address signal, the signal ALE (not shown) is asserted. The address signal includes, for example, the column address signals CA (AD1 and AD2) in the first and second cycles. The column address signal CA includes a column address, and the column address specifies the column to be read from the specified page. The address signal includes, for example, a low address signal RA (AD3 to AD5) in the third to fifth cycles. The row address signal RA specifies a row address, i.e., a selection page. The word line WL connected to the cell unit CU containing the cell transistor MT that provides the storage space for the selection page is referred to as the selection word line WL.

After transmitting the row address signals RA (AD3 to AD5), the control unit 220 transmits a signal (DA1) that specifies the minimum voltage value when the memory chip 110 executes Vth tracking via the memory I / F 250. .. The minimum voltage value at which Vth tracking is started is specified by, for example, a DAC value.

The control unit of the memory controller 200 changes when the memory chip 110 executes Vth tracking via the memory I / F 250 after transmitting a signal (DA1) that specifies the minimum voltage value when Vth tracking is executed. A signal (DA2) that specifies the read voltage to be generated is transmitted. The read voltage to be changed is specified by, for example, a DAC value.

When the memory chip 110 receives a signal (DA2) that specifies a read voltage to be changed when executing Vth tracking, the memory chip 110 executes Vth tracking. The memory chip 110 notifies the memory controller 200 of the busy state during the execution of Vth tracking.

The memory chip 110 receives from the memory controller 200 from the memory controller 200 with respect to the cell unit CU specified by the column address signals CA (AD1 and AD2) and the low address signals RA (AD3 to AD5) received from the memory controller 200 via the memory I / F250. Vth tracking is performed using the signal (DA1) that specifies the minimum received voltage value and the signal (DA2) that specifies the read voltage to be changed.

As a first step, the memory chip 110 reads data by applying a read voltage corresponding to the minimum voltage value to the selected word line WL of the cell unit CU to be Vth tracked, and is included in the read data. Count the number of 1 ”.

After the first step, the memory chip 110 applies a read voltage corresponding to the read voltage to be changed with respect to the voltage corresponding to the minimum voltage value to the selected word line WL as the second step. By doing so, the data is read, the number of "1" contained in the read data is counted, and the difference from the number of "1" counted in the first step is obtained.

After the second step, the memory chip 110 adds a read voltage corresponding to the read voltage to be changed with respect to the voltage used in the second step to the selected word line WL as a third step. By applying the data, the data is read out, the number of "1" s included in the read data is counted, and the difference from the number of "1" s counted in the second step is obtained.

After that, when the memory chip 110 repeats the process as in the third step a predetermined number of times to plot the read voltage on the horizontal axis and plot the difference on the vertical axis, the same graph as in FIG. 10 can be obtained. .. It should be noted that a predetermined smoothing process may be performed after plotting to form a graph.

The memory chip 110 calculates the read voltage at which the difference between the numbers of "1" is the minimum value as the optimum read voltage, and uses the calculated optimum read voltage as the Vth tracking result (VD). Further, the memory chip 110 could not calculate the optimum read voltage when the bottom (concave portion) of the graph could not be found or the bottom of a plurality of graphs could be found when graphing. The indicated information may be used as a Vth tracking result (VD).

Further, when the minimum value of the difference between the number of "1" is larger than the predetermined number, the memory chip 110 may use the information indicating that the optimum read voltage could not be calculated as the Vth tracking result (VD). good.

The memory controller 200 repeatedly asserts a signal REN (not shown), outputs a Vth tracking result (VD) from the memory chip 110, and acquires the output Vth tracking result (VD) via the memory I / F 250.

The command described with reference to FIG. 14 is output to only one memory chip 110. That is, for example, the memory controller 200 issues a Vth tracking request command to each of the memory chips 110-1, ..., And the memory chips 110-N via the memory I / F 250, so that the memory controller 200 can be used. Vth tracking for a predetermined cell unit CU can be requested for each of the memory chips 110-1, ..., And the memory chips 110-N.

The control unit 220 has succeeded in Vth tracking of the memory chip 110-1 based on the Vth tracking result (VD) acquired from the memory chip 110-1 via the memory I / F 250, that is, the second Vth tracking has succeeded. It is determined whether or not it has been done (step 1302).

The control unit 220 states that, for example, if the Vth tracking result acquired from the memory chip 110-1 is not information indicating that the optimum read voltage could not be calculated, the memory chip 110-1 succeeded in Vth tracking. judge.

When the control unit 220 determines that the memory chip 110-1 has succeeded in Vth tracking (step 1302: Yes), the control unit 220 acquires the optimum read voltage, which is the Vth tracking result, from the memory chip 110-1 and obtains the acquired read voltage. And the difference from the predetermined read voltage are obtained (step 1303).

The information of the optimum read voltage, which is the Vth tracking result transmitted by the memory chip 110-1 via the memory I / F 250, may be a voltage value in V units, or may be predetermined numerical data such as a DAC value. May be good.

The control unit 220 determines whether the difference between the acquired read voltage and the predetermined read voltage is less than a predetermined first value (step 1304), and if it is equal to or more than a predetermined first value (step 1304: No). , Refresh the block containing the cell unit CU to be patrolled (step 1305).

When the control unit 220 does not determine that the memory chip 110-1 has succeeded in Vth tracking (step 1302: No), the control unit 220 optimally performs the first Vth tracking described above or the shift read described above for the cell unit CU. Obtain a good read voltage (step 1306).

The control unit 220 calculates the difference between the optimum read voltage acquired by the first Vth tracking or shift read and the predetermined read voltage (step 1307), and determines whether the difference is less than a predetermined second value. (Step 1308). If the difference is greater than or equal to a predetermined second value (step 1308: No), the block containing the patrol target cell unit CU is refreshed (step 1309). The predetermined second value may be the same as or different from the predetermined first value.

The control unit 220 uses the read voltage acquired by the first Vth tracking or shift read in step 1306 for the read voltage information held by the memory controller 200 or the operation parameter information of the first parameter information 2202. You may update it.

FIG. 15 is a flowchart of a first modification of the patrol processing of the memory system according to the first embodiment. Also in the flowchart of FIG. 15, the description will be made from the stage where the memory controller 200 decides to patrol the predetermined cell unit CU of the non-volatile memory 100, similarly to FIG. Further, in FIG. 15, the same parts as those in FIG. 13 are indicated by the same reference numerals.

The control unit 220 determines whether the difference between the read voltage acquired by the second Vth tracking and the predetermined read voltage is less than a predetermined first value (step 1304), and if it is equal to or more than a predetermined first value. (Step 1304: No), the read voltage acquired by the second Vth tracking is used to read the data of the cell unit CU via the memory I / F250. (Step 1501).

The memory controller 200 decodes the read data (step 1502). The control unit 220 instructs the decoding circuit 242 to decode the read data of the cell unit CU, and the decoding circuit 242 decodes the data instructed by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, if the error correction is successful at the time of decoding, the decoded data is notified, and if the error correction fails at the time of decoding, the error correction failure is notified to the control unit 220.

The control unit 220 determines whether the number of error bits detected in decoding the data of the cell unit CU read by the decoding circuit 242 is less than the predetermined number of first bits (step 1503), and determines whether the number of error bits is less than the predetermined number of first bits (step 1503). If the number is greater than or equal to the number (step 1503: No), the block containing the cell unit CU to be patrolled is refreshed (step 1504).

FIG. 16 is a flowchart of a second modification of the patrol processing of the memory system according to the first embodiment. Also in the flowchart of FIG. 16, the description will be made from the stage where the memory controller 200 decides to patrol the predetermined cell unit CU of the non-volatile memory 100, similarly to FIG. Further, in FIG. 16, the same parts as those of FIGS. 13 and 15 are indicated by the same reference numerals.

The control unit 220 uses the read voltage held by the memory controller 200 when it is determined that the memory chip 110-1 does not succeed in Vth tracking (step 1302: No), and the cell unit CU is used via the memory I / F 250. Data is read (step 1601), and the read data is decoded (step 1602). The control unit 220 instructs the decoding circuit 242 to decode the read data of the cell unit CU, and the decoding circuit 242 decodes the data instructed by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, if the error correction is successful at the time of decoding, the decoded data is notified, and if the error correction fails at the time of decoding, the error correction failure is notified to the control unit 220.

The control unit 220 determines whether the number of error bits detected in decoding the data of the cell unit CU read by the decoding circuit 242 is less than the predetermined number of second bits (step 1603), and determines whether the number of error bits is less than the predetermined number of second bits (step 1603). In the case of a number or more (step 1603: No), the optimum read voltage is acquired for the cell unit CU by the first Vth tracking or shift read (step 1306). The control unit 220 calculates the difference between the acquired read voltage and the read voltage held by the memory controller 200 (step 1307), and determines whether the difference is less than a predetermined second value (step 1308). When the difference is equal to or greater than a predetermined second value (step 1308: No), the control unit 220 refreshes the block including the cell unit CU to be patroled (step 1309).

According to the first embodiment described above, the memory controller 200 determines whether to refresh based on the difference between the read voltage acquired by the second Vth tracking and the predetermined read voltage during the patrol process. ..

Therefore, in the memory system according to the first embodiment, the memory controller 200 uses the result of the second Vth tracking executed by the memory chip 110 without performing the first Vth tracking or shift reading. Since the patrol process can be performed, the processing load of the memory controller 200 can be reduced.

Further, in the memory system according to the first embodiment, since it is determined whether to refresh without executing the error correction processing, the processing load of the memory controller 200 at the time of the patrol processing can be reduced. By reducing the processing load of the memory controller 200, the performance of the memory system 1 is improved. In the memory system according to the first embodiment, the processing load of the memory controller 200 during the patrol processing is reduced, so that the time required for the patrol processing can be shortened, the power consumption of the memory controller 200 can also be reduced, and the time is shorter. Patrol processing can be executed in a short time and with low power consumption.

Further, according to the first embodiment, when the memory controller 200 cannot acquire the optimum read voltage by the second Vth tracking, the read voltage acquired by the memory controller 200 by the first Vth tracking or the shift read. Determines whether to refresh based on the difference between the voltage and the predetermined read voltage. Also in this case, since the memory controller 200 determines whether to refresh without executing the error correction processing, the processing load of the memory controller 200 during the patrol processing can be reduced, and the processing load of the memory controller 200 can be reduced in a shorter time and with lower power consumption. Patrol processing can be executed.

(Second embodiment)
FIG. 17 is a flowchart of data read processing from the non-volatile memory 100 in response to a read request from the host device 2 of the memory system according to the second embodiment. In FIG. 17, the same parts as those in FIG. 13 are indicated by the same reference numerals. In the description of the present embodiment, duplicate description will be omitted for the same configuration and operation as those of the first embodiment. Further, the appearance, configuration, and the like of the memory system 1 in the present embodiment are the same as those in FIGS. 1 to 12.

The flowchart of FIG. 17 shows a process of receiving a read request from the host device 2, reading the requested data from the non-volatile memory 100, and transmitting the read result to the host device 2.

In the read request from the host device 2, the amount of data that the host device 2 wants to read from the memory system 1 and the address information indicating the data read position are specified. The memory system 1 may determine whether or not the read request can be received, and may receive the read request from the host device 2 when the read request can be received. In the flowchart of FIG. 17, this process is omitted, and it is assumed that the read request can be received, and the description will be made from the stage where the memory controller 200 of the memory system 1 receives the read request from the host device 2 via the host I / F 210.

When the memory controller 200 receives a read instruction from the host device 300, the flow of FIG. 17 starts. When the memory controller 200 receives a read request from the host device 2 via the host I / F 210 (step 1701), the control unit 220 uses the address conversion table to specify the storage location of the data subject to the read request. Then, the logical address, which is the address specified in the read request, is converted into a physical address, and which physical address of which memory chip 110 should be accessed in order to process the read request from the host device 2 is solved (). Step 1702).

In the present embodiment, the memory chip 110 of the access destination to the logical address specified by the read request from the host device 2 will be described as the memory chip 110-1.

The control unit 220 instructs the memory I / F 250 to read the data from the memory chip 110-1, and reads the data from the memory chip 110-1 via the memory I / F 250 (step 1703).

The read here is a normal read, and the memory controller 200 reads data from the memory chip 110-1 via the memory I / F 250 using the operation parameter of the first parameter information 2202. When the memory chip 110-1 receives a read instruction in the input / output circuit 112, the sequencer 114 controls the voltage generation circuit 115, the driver 116, the sense amplifier 117, the column decoder 118, and the row decoder 120 to give a read instruction. Data is read from the page specified in the above, and the read data is output to the memory I / F 250 by the input / output circuit 112. The memory controller 200 receives the data read via the memory I / F 250.

Next, the memory controller 200 decodes the data read from the memory chip 110-1 (step 1704). The control unit 220 instructs the decoding circuit 242 to decode the data read from the memory chip 110-1, and the decoding circuit 242 decodes the data instructed by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, if the error correction is successful at the time of decoding, the decoded data is notified, and if the error correction fails at the time of decoding, the error correction failure is notified to the control unit 220.

After that, if the error correction is successful (step 1705: Yes), the control unit 220 transmits the user data, which is the decoded data, to the host device 2 via the host I / F 210 (step 1706).

If the error correction is not successful (step 1705: No), the control unit 220 executes the second Vth tracking. That is, when the error correction is not successful (step 1705: No), the control unit 220 acquires the Vth tracking result (VD) for the cell unit CU to be patrol from the memory chip 110-1 via the memory I / F250. (Step 1707). The process in step 1707 is the same as the request for Vth tracking to the memory chip 110-1 and the acquisition of the Vth tracking result (VD) from the memory chip 110-1 for the request (step 1301) in the first embodiment. ..

The control unit 220 determines whether the memory chip 110-1 succeeds in Vth tracking based on the Vth tracking result (VD) acquired from the memory chip 110-1 via the memory I / F 250, that is, the second Vth tracking is performed. It is determined whether it was successful (step 1708). The process in step 1707 is the same as the process for determining whether the memory chip 110-1 succeeded in Vth tracking, that is, whether the second Vth tracking was successful (step 1302) in the first embodiment. ..

When the control unit 220 determines that the memory chip 110-1 has succeeded in Vth tracking (step 1708: Yes), the control unit 220 acquires a read voltage from the Vth tracking result output from the memory chip 110-1, and obtains the read voltage. Is used to read data from the memory chip 110-1 (step 1709).

Next, the memory controller 200 decodes the data read from the memory chip 110-1 in step 1709 (step 1710). The control unit 220 instructs the decoding circuit 242 to decode the data read from the memory chip 110-1 in step 1709, and the decoding circuit 242 decodes the data instructed by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, if the error correction is successful at the time of decoding, the decoded data is notified, and if the error correction fails at the time of decoding, the error correction failure is notified to the control unit 220.

After that, if the error correction is successful (step 1711: Yes), the control unit 220 transmits the user data, which is the decoded data, to the host device 2 via the host I / F 210 (step 1706).

If the error correction is not successful (step 1711: No), the control unit 220 executes the first Vth tracking (step 1712).

The control unit 220 uses the read voltage obtained in the first Vth tracking to instruct the memory I / F 250 to read data from the memory chip 110-1, and the memory chip 110-1 via the memory I / F 250. Read data from (step 1713).

Next, the memory controller 200 decodes the data read from the memory chip 110-1 (step 1714). The control unit 220 instructs the decoding circuit 242 to decode the data read from the memory chip 110-1, and the decoding circuit 242 decodes the data instructed by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, if the error correction is successful at the time of decoding, the decoded data is notified, and if the error correction fails at the time of decoding, the error correction failure is notified to the control unit 220.

After that, the control unit 220 reads the user data, which is the decoded data, when the error correction is successful, and reads the error when the decoding circuit 242 notifies the error correction failure, via the host I / F 210. (Step 1706).

In the memory system according to the present embodiment, the control unit 220 executes the first Vth tracking in the processes of steps 1712 and 1713, and uses the read voltage obtained in the first Vth tracking to use the memory chip. Although the data is read from 110-1, the shift read may be used instead to read the data from the memory chip 110-1.

According to the second embodiment described above, the memory controller 200 first performs a normal read, and if the error correction of the data obtained by the normal read is not successful, the memory controller 200 executes the second Vth tracking. Data is read from the memory chip 110 using the read voltage acquired by the second Vth tracking.

Therefore, in the second embodiment, when the memory controller 200 does not succeed in correcting the error of the data obtained by the normal read, the memory controller 200 does not perform the first Vth tracking or shift read. Data can be read using the result of Vth tracking executed by the memory chip 110, the processing load of the memory controller 200 can be reduced, and as a result, the performance of the memory system 1 is improved. By reducing the processing load of the memory controller 200 in the read process, the power consumption of the memory controller 200 can also be reduced, and the read process can be executed with lower power consumption. That is, according to the second embodiment, high-precision readout can be realized with less processing, and low power consumption can be achieved.

(Third embodiment)
FIG. 18 is a flowchart of the patrol process of the memory system according to the third embodiment. In FIG. 18, the same parts as those in FIG. 13 are indicated by the same reference numerals. In the description of the present embodiment, duplicate description will be omitted for the same configuration and operation as those of the first embodiment. Further, the appearance, configuration, and the like of the memory system 1 in the present embodiment are the same as those in FIGS. 1 to 12.

In the flowchart of FIG. 18, the description will be made from the stage when the memory controller 200 decides to patrol the predetermined cell unit CU of the non-volatile memory 100, as in the flowchart of FIG.

In the present embodiment, the memory chip 110 including the cell unit CU to be patrolled will be described as the memory chip 110-1.

The difference between the memory system according to the third embodiment and the memory system according to the first embodiment is that when the memory controller 200 consumes more than a predetermined degree of consumption of the cell unit CU of the access destination, the second embodiment is used. The purpose is to specify the read voltage by the first Vth tracking or shift read without executing the second Vth tracking.

The control unit 220 calculates the degree of wear for the cell unit CU to be patrol from the memory chip 110-1 (step 1801), and determines whether the calculated degree of wear is smaller than the predetermined degree of wear (step 1802).

When the control unit 220 calculates the degree of wear, the degree of wear may be the number of reads, the number of writes, the write generation number, the number of erases including the access destination cell unit CU, and the like. , These may be calculated by a calculation formula combining these.

By referring to the second parameter information 2203, the control unit 220 can acquire the read count, the write count, the write generation number, the erase count including the access destination cell unit CU, and the like. can.

The control unit 220 may, for example, have an access-destination cell unit CU read less than a predetermined read count, an access-destination cell unit CU write a write count less than a predetermined read count, or an access-destination cell unit. When the write generation number of the CU is smaller than the predetermined number, or when the number of erasures including the cell unit CU of the access destination is smaller than the predetermined number of erasures, it is determined that the calculated consumption degree is smaller than the predetermined consumption degree. However, the determination method is not limited to this. The control unit 220 may determine the degree of wear by calculating the degree of wear by an arithmetic expression and comparing the calculated degree of wear with a predetermined degree of wear.

Further, the control unit 220 determines the degree of wear of the access destination cell unit CU by using data other than the number of reads, the number of writes, and the number of erases including the access destination cell unit CU. You may. The control unit 220 calculates, for example, the consumption degree of the cell unit CU of the access destination by the total number of erasures of all the blocks included in the memory chip 110-1 which is the access destination, and the calculated consumption degree and a predetermined value. The determination in step 1802 may be performed by comparing with the degree of wear.

When the control unit 220 determines that the calculated degree of wear is smaller than the predetermined degree of wear (step 1802: Yes), the control unit 220 stores the Vth tracking result (VD) from the memory chip 110-1 to the cell unit CU to be patroled in the memory I. It is acquired via / F250 (step 1301), and thereafter, the same processing as that of the memory system according to the first embodiment is executed.

When the control unit 220 determines that the calculated degree of wear is equal to or higher than the predetermined degree of wear (step 1802: No), the control unit 220 optimally performs the first Vth tracking or shift read on the cell unit CU to be patrolled. The read voltage is acquired (step 1306), the difference between the read voltage acquired by the first Vth tracking or shift read and the predetermined read voltage is calculated (step 1307), and the difference is a predetermined second value. It is determined whether it is less than (step 1308), and if the difference is equal to or greater than a predetermined second value (step 1308: No), the block containing the cell unit CU to be patrol is refreshed (step 1309).

In the memory controller 200 of the memory system in the present embodiment, when it is determined that the calculated consumption degree is equal to or higher than the predetermined consumption degree (step 1802: No), or when the memory chip 110-1 succeeds in Vth tracking. When the determination is not made (step 1302: No), the difference between the read voltage acquired by the first Vth tracking or shift read and the predetermined read voltage is compared with the predetermined second value, but the comparison target. The predetermined second value is may be a different value in each case.

According to the third embodiment described above, in the memory system 1, similarly to the first embodiment, the memory controller 200 performs the first Vth tracking and shift read during the patrol process. Data can be read out using the result of the second Vth tracking, and the processing load of the memory controller 200 can be reduced.

Further, as in the first embodiment, since it is determined whether to refresh without executing the error correction processing, the processing load of the memory controller 200 at the time of the patrol processing can be reduced. As a result of reducing the processing load of the memory controller 200 during the patrol processing, the performance of the memory system 1 is improved.

Further, as in the first embodiment, by reducing the processing load of the memory controller 200 during the patrol processing, the time required for the patrol processing can be shortened, and the power consumption of the memory controller 200 can also be reduced, which is shorter. Patrol processing can be executed in a short time and with low power consumption.

Further, according to the third embodiment, when the memory chip 110 is exhausted to some extent, the second Vth tracking is not executed. If the memory chip 110 is exhausted to some extent, the second Vth tracking may fail, that is, the memory chip 110 is likely to fail in Vth tracking, so that the memory chip 110 is exhausted to some extent. If it is advanced, the memory controller 200 can execute the patrol process more efficiently by skipping the second Vth tracking.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope of the invention described in the claims and the equivalent scope thereof, as are included in the scope and gist of the invention.

1 ... Memory system 2 ... Host device 3 ... System 4 ... Connector 100 ... Non-volatile memory 110 ... Memory chip 200 ... Memory controller 210 ... Host I / F
220 ... Control unit 230 ... Data buffer 240 ... Encoding unit / Decoding unit 250 ... Memory I / F
260 ... Internal bus 400 ... Board

Claims (24)

It is a control method by a controller of a non-volatile memory having a word line and a plurality of memory cells connected to the word line and having a plurality of blocks which are data erasing units.
The controller requests the non-volatile memory to perform a second search, and in the second search, the non-volatile memory is used.
Data is read multiple times from the plurality of memory cells using each of the second plurality of read voltages.
Using the second plurality of read voltages, the number of seventh values included in each of the second plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the seventh values included in each of the two data read using the two adjacent read voltages out of the second plurality of read voltages is obtained for each of the second plurality of data. Calculate and
When the minimum value of the differences calculated above is equal to or less than the eighth value, the read voltage at which the difference is minimized is determined to be the second read voltage, and the second read voltage can be searched. The indicated response is sent to the controller and
When the minimum value is larger than the eighth value, a response indicating that the second read voltage could not be searched is transmitted to the controller.
The controller performs the first search in response to receiving the response from the non-volatile memory indicating that the second read voltage could not be searched.
In the first search, the controller
Data is read multiple times from the plurality of memory cells using each of the first plurality of read voltages.
Using the first plurality of read voltages, the number of sixth values included in each of the first plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the sixth values included in each of the two data read using the two adjacent read voltages out of the first plurality of read voltages is set for each of the first plurality of data. Calculate and
Of the differences calculated above, the read voltage at which the difference is the smallest is determined as the first read voltage.
The first difference, which is the difference between the first read voltage and the second reference voltage, is calculated.
When the first difference is equal to or greater than a predetermined first value, the data stored in the block containing the plurality of memory cells is stored in another block.
Control method. When the response received from the non-volatile memory to the second search request is information indicating that the second read voltage could be searched, the controller could search for the second read voltage. Based on the information indicating that, it is determined whether to save the data stored in the block containing the plurality of memory cells in another block.
The control method according to claim 1. The controller makes the determination for the plurality of memory cells included in each of the plurality of blocks within a predetermined time.
The control method according to claim 2. When the response corresponding to the second search is information indicating that the second read voltage could be searched.
The controller calculates a second difference, which is a difference between the second read voltage and the third reference voltage included in the response corresponding to the second search.
When the second difference is equal to or greater than a predetermined second value, the data stored in the block containing the plurality of memory cells is stored in another block.
The control method according to claim 2 or 3. When the response corresponding to the second search is information indicating that the second read voltage could not be searched.
The controller reads data from the plurality of memory cells using a fourth reference voltage.
When the number of error bits is equal to or greater than the first threshold value when the read data is decoded, the first search is executed.
The control method according to claim 1. The controller calculates the degree of consumption of the plurality of memory cells, and when the calculated degree of consumption is equal to or higher than a predetermined degree of consumption, the first search is performed without requesting the non-volatile memory for the second search. To execute,
The control method according to claim 1. When the calculated degree of wear is less than the predetermined degree of wear
The controller requests the non-volatile memory for the second search.
When the response corresponding to the second search is information indicating that the second read voltage could be searched.
The third difference, which is the difference between the searched second read voltage and the fifth reference voltage, is calculated.
When the third difference is equal to or greater than a predetermined third value, the data stored in the block containing the plurality of memory cells is stored in another block.
The control method according to claim 6. When a read command is received from the host device
The controller reads the data corresponding to the read instruction from the non-volatile memory, decodes the first data which is the read data, and decodes the first data.
If the decoding of the first data is successful, the decoded first data is transmitted to the host device, and the decrypted first data is transmitted to the host device.
If the decryption of the first data fails,
The controller requests the non-volatile memory for the second search.
When the response from the non-volatile memory is information indicating that the second read voltage could be searched for,
The controller reads the data corresponding to the read instruction from the non-volatile memory using the second read voltage included in the information indicating that the second read voltage could be searched.
Decoding the second data, which is the data read using the second read voltage,
If the decoding of the second data is successful, the decoded second data is transmitted to the host device.
The control method according to claim 1. When the response corresponding to the second search is information indicating that the second read voltage could not be searched.
The controller performs the first search and
The sixth reference voltage used when reading the data corresponding to the read instruction from the host device from the non-volatile memory is updated with the first read voltage searched by the first search.
The control method according to claim 8. When the response corresponding to the second search is information indicating that the second read voltage could not be searched.
The controller performs the first search and
Using the first read voltage searched by the first search, the data corresponding to the read instruction is read from the non-volatile memory.
Decoding the third data, which is the data read using the first read voltage,
If the decoding of the third data is successful, the decoded third data is transmitted to the host device.
The control method according to claim 9. A non-volatile memory having a word line and a plurality of memory cells connected to the word line, each having a plurality of blocks as a data erasing unit, and a non-volatile memory.
A controller that can control the non-volatile memory and
Equipped with
The controller transmits a second search command for causing the non-volatile memory to search the second read voltage for the plurality of memory cells to the non-volatile memory.
In response to the second search command, the non-volatile memory
Data is read multiple times from the plurality of memory cells using each of the second plurality of read voltages.
Using the second plurality of read voltages, the number of seventh values included in each of the second plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the seventh values included in each of the two data read using the two adjacent read voltages out of the second plurality of read voltages is obtained for each of the second plurality of data. Calculate and
When the minimum value of the calculated differences is larger than the eighth value, a response indicating that the second read voltage could not be searched is transmitted to the controller.
When the minimum value is equal to or less than the eighth value, the read voltage at which the difference is minimized is determined as the second read voltage, and the controller responds indicating that the second read voltage can be searched. Send to
The controller calculates a second difference, which is a difference between the second read voltage and the third reference voltage included in the response corresponding to the second search command.
When the second difference is equal to or greater than the predetermined second value,
Data is read from the plurality of memory cells using the second read voltage,
Of the data, the data stored in the block containing the plurality of memory cells is placed in another block based on the comparison between the fourth value, which is the number of erroneous bits, and the predetermined fifth value. Determine if you want to save,
Memory system. When the second difference is greater than or equal to the second value, the controller reads from the plurality of memory cells using the second read voltage included in the response corresponding to the second search command. When the fourth value, which is the number of erroneous bits, is equal to or greater than the fifth value, the data stored in the block including the plurality of memory cells is stored in the other block. ,
The memory system according to claim 11. The second search command specifies a first voltage and a second voltage.
The non-volatile memory starts the search for the second read voltage from the first voltage.
The second read voltage is searched for by changing the read voltage by at least the second voltage.
The memory system according to claim 11 or 12. The memory system according to claim 13, wherein the controller makes the determination within a predetermined time with respect to the plurality of memory cells included in each of the plurality of blocks. When the response corresponding to the second search command is information indicating that the second read voltage could not be searched.
The controller executes a first search to search for a first read voltage by reading data from the plurality of memory cells using a plurality of read voltages obtained by changing from the first reference voltage. The first difference, which is the difference between the first read voltage and the second reference voltage, is calculated.
When the first difference is equal to or greater than a predetermined first value, the data stored in the block containing the plurality of memory cells is stored in another block.
13. The memory system according to claim 13. The controller
In the first search, data is read a plurality of times from the plurality of memory cells using each of the first plurality of read voltages.
Using the first plurality of read voltages, the number of sixth values included in each of the first plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the sixth values included in each of the two data read using the two adjacent read voltages out of the first plurality of read voltages is set for each of the first plurality of data. Calculate and
Of the differences calculated above, the read voltage at which the difference is the smallest is determined as the first read voltage.
The memory system according to claim 15. When the response corresponding to the second search command is information indicating that the second read voltage could not be searched.
The controller reads data from the plurality of memory cells using a fourth reference voltage.
When the read data cannot be decoded, the first read voltage is searched for by reading data from the plurality of memory cells using a plurality of read voltages obtained by changing from the first reference voltage. Perform a search for 1,
The memory system according to claim 11. The controller calculates the degree of consumption of the plurality of memory cells, and the controller calculates the degree of consumption of the plurality of memory cells.
When the calculated degree of wear is less than the predetermined degree of wear, the second search command is transmitted to the non-volatile memory.
When the calculated consumption degree is equal to or higher than the predetermined consumption degree, a plurality of read voltages obtained by changing from the first reference voltage without transmitting the second search command to the non-volatile memory are used. The first search for searching the first read voltage by reading data from the plurality of memory cells is executed.
The memory system according to claim 11. The memory system according to claim 18, wherein the controller holds management information of a block including the plurality of memory cells, and calculates the degree of consumption of the plurality of memory cells from the management information. 19. The memory system of claim 19, wherein the management information includes the number of times a block containing the plurality of memory cells is erased. A non-volatile memory having a word line and a plurality of memory cells connected to the word line, each having a plurality of blocks as a data erasing unit, and a non-volatile memory.
A controller that can control the non-volatile memory and
Equipped with
The controller calculates the degree of consumption of the plurality of memory cells, and the controller calculates the degree of consumption of the plurality of memory cells.
If the calculated degree of wear is less than the specified degree of wear
A second search command for causing the non-volatile memory to search for a second read voltage for the plurality of memory cells is transmitted to the non-volatile memory.
In response to the second search command, the non-volatile memory
Data is read multiple times from the plurality of memory cells using each of the second plurality of read voltages.
Using the second plurality of read voltages, the number of seventh values included in each of the second plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the seventh values included in each of the two data read using the two adjacent read voltages out of the second plurality of read voltages is obtained for each of the second plurality of data. Calculate and
Of the differences calculated above, the read voltage at which the difference is the smallest is determined as the second read voltage, and a response indicating that the second read voltage has been searched is transmitted to the controller.
The controller calculates a second difference, which is a difference between the second read voltage and the third reference voltage included in the response corresponding to the second search command.
When the second difference is greater than or equal to the second value, the data stored in the block containing the plurality of memory cells is stored in another block.
When the calculated consumption degree is equal to or higher than the predetermined consumption degree, a plurality of read voltages obtained by changing from the first reference voltage without transmitting the second search command to the non-volatile memory are used. The first search for searching the first read voltage by reading data from the plurality of memory cells is executed.
In the first search, the controller
Data is read multiple times from the plurality of memory cells using each of the first plurality of read voltages.
Using the first plurality of read voltages, the number of sixth values included in each of the first plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the sixth values included in each of the two data read using the two adjacent read voltages out of the first plurality of read voltages is set for each of the first plurality of data. Calculate and
Of the differences calculated above, the read voltage at which the difference is the smallest is determined as the first read voltage.
Memory system. The memory system can be connected to the host device and
When the controller receives a read request from the host device, the controller reads the data corresponding to the read request from the non-volatile memory.
Decoding the first data, which is the read data,
If the decoding of the first data is successful, the decoded first data is transmitted to the host device, and the decrypted first data is transmitted to the host device.
If the decryption of the first data fails,
The second search command is transmitted to the non-volatile memory, and the second search command is transmitted to the non-volatile memory.
When the response received from the non-volatile memory to the second search command is information indicating that the second read voltage could be searched.
Using the second read voltage included in the response corresponding to the second search command, the data corresponding to the read request is read from the non-volatile memory.
Decoding the second data, which is the data read using the second read voltage,
If the decoding of the second data is successful, the decoded second data is transmitted to the host device.
The memory system according to claim 11. The controller performs the first search in response to receiving the response from the non-volatile memory indicating that the second read voltage could not be searched.
In the first search, the controller reads data from the plurality of memory cells a plurality of times using the first plurality of read voltages obtained by changing from the first reference voltage.
Using the first plurality of read voltages, the number of sixth values included in each of the first plurality of data read from the plurality of memory cells is calculated.
The difference in the number of the sixth values included in each of the two data read using the two adjacent read voltages out of the first plurality of read voltages is set for each of the first plurality of data. Calculate and
Of the differences calculated above, the read voltage at which the difference is the smallest is determined as the first read voltage.
Decoding the third data, which is the data read using the first read voltage,
If the decoding of the third data is successful, the decoded third data is transmitted to the host device.
The memory system according to claim 22. The controller holds a read voltage for reading data corresponding to the read request from the non-volatile memory.
The held read voltage is updated with the first read voltage.
The memory system according to claim 23.

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