JP2018055759A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system with reduced occurrence frequency of read-out error.SOLUTION: A memory system according to an embodiment includes a nonvolatile memory having a plurality of memory chips and a controller controlling the nonvolatile memory. The controller accesses a first memory chip when a temperature of the controller is higher than a first temperature or when a temperature of the first memory chip of the plurality of memory chips is higher than a second temperature.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a memory system.

There is provided a memory system including a nonvolatile memory such as a NAND flash memory and a memory controller.

JP 2012-194897 A US Patent Application Publication No. 2012/0287711 JP 2012-212486 A

The problem to be solved by the present invention is to provide a memory system in which the frequency of occurrence of read errors is reduced.

In order to achieve the above object, a memory system according to an embodiment includes a nonvolatile memory having a plurality of memory chips, and a controller that controls the nonvolatile memory. The controller accesses the first memory chip when the temperature of the controller is higher than the first temperature or when the temperature of the first memory chip among the plurality of memory chips is higher than the second temperature. .

1 is a block diagram showing a configuration example of a memory system according to a first embodiment. 1 is a diagram illustrating a system in which a memory system according to a first embodiment is incorporated. 1 is a diagram illustrating a portable computer in which a memory system according to a first embodiment is incorporated. 1 is a diagram showing an example of the appearance of a memory system according to a first embodiment. 1 is a block diagram of a memory chip of a memory system according to a first embodiment. 1 is a circuit diagram of a memory cell array in a memory system according to a first embodiment. 1 is a cross-sectional view of a memory cell array of a memory system according to a first embodiment. 5 is a flowchart of processing for a read request in the memory system according to the first embodiment. 6 is an example of a command sequence transmitted from the memory controller of the memory system according to the first embodiment to the memory chip. 5 is a flowchart of processing for a write request in the memory system according to the first embodiment. 9 is a flowchart of a modification example of processing for a write request in the memory system according to the first embodiment. 4 is a flowchart of an erasing process of a predetermined block in the nonvolatile memory of the memory system according to the first embodiment. 9 is a flowchart of processing for a read request in the memory system according to the second embodiment. 10 is a flowchart of processing for a write request in the memory system according to the third embodiment. 14 is a flowchart of erasing processing of a predetermined block in a nonvolatile memory of a memory system according to a fourth embodiment. 10 is a flowchart of processing of a memory controller of a memory system according to a fifth embodiment. 20 is a flowchart of processing for a read request in the memory system according to the sixth embodiment. 20 is a flowchart of processing for a write request in the memory system according to the sixth embodiment. 14 is a flowchart of erasing processing of a predetermined block in a nonvolatile memory of a memory system according to a sixth embodiment. 18 is a flowchart of processing for a read request in the memory system according to the seventh embodiment. 18 is a flowchart of processing for a write request in the memory system according to the seventh embodiment. 15 is a flowchart of a modified example of processing for a write request in the memory system according to the seventh embodiment. 15 is a flowchart of erasing processing of a predetermined block in a nonvolatile memory of a memory system according to a seventh embodiment.

  Embodiments for carrying out the invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of the memory system according to the first embodiment. The memory system 1 is connected to the host device 2 via a communication line and functions as an external storage device of the host device 2. The host device 2 may be, for example, an information processing device such as a personal computer, a mobile phone, an imaging device, a mobile terminal such as a tablet computer or a smartphone, or a game device. An in-vehicle terminal such as a car navigation system may be used.

The nonvolatile memory 100 is a memory that stores data in a nonvolatile manner. Non-volatile memory 1
00 is, for example, memory chip # 1 110-1, which is a plurality of memory chips.
A non-volatile semiconductor memory including a memory chip #N 110-N. N is an arbitrary natural number.

In the following description, reference numerals 110-1,..., 110-N are used when one of the plurality of memory chips 110-1,. When referring to a memory chip or when not distinguishing a memory chip from other memory chips,
Reference numeral 110 is used.

Each of the memory chips 110 can operate, for example, independently of each other, and an example thereof is a NAND flash memory chip. In a NAND flash memory, writing and reading are generally performed in data units called pages, and erasing is performed in data units called blocks.

Although an example in which a NAND flash memory is used as the nonvolatile memory 100 will be described, a three-dimensional flash memory, a ReRAM (Resistance) is used as the nonvolatile memory 100.
Random Access Memory), FeRAM (Ferroelectric Random Access Memory), etc.
Storage means other than the AND flash memory may be used. Although an example in which a semiconductor memory is used as the storage unit will be described here, a storage unit other than the semiconductor memory may be used.

The memory system 1 may be a memory card in which the memory controller 200 and the nonvolatile memory 100 are configured as one package, or an SSD (Solid State Drive).
It may be.

The memory controller 200 controls writing to the nonvolatile memory 100 in accordance with a write request from the host device 2. In the present embodiment, the request is, for example, an instruction or a command. Further, reading from the nonvolatile memory 100 is controlled in accordance with a reading request from the host device 2. The memory controller is also called a controller.

The memory controller 200 includes a host interface (host I / F) 210, a control unit 220, a data buffer 230, an encoding / decoding unit (Encoder / Decoder) 240, a memory interface (memory I / F) 250, and a temperature sensor interface ( Temperature sensor I / F) 260. Host I / F 210, control unit 220, data buffer 230
The encoder / decoder 240, the memory I / F 250, and the temperature sensor I / F 260 are connected by an internal bus 270.

The host I / F 210 performs processing according to the interface standard with the host device 2, and outputs a request, user data, and the like received from the host device 2 to the internal bus 270.
The host I / F 210 transmits user data read from the nonvolatile memory 100, a response from the control unit 220, and the like to the host device 2. In the present embodiment, data written to the nonvolatile memory 100 in response to a write request from the host device 2 is referred to as user data.

The control unit 220 comprehensively controls each component of the memory system 1. The control unit 220 may be realized by hardware, or may be realized by a processor such as a CPU (Central Processing Unit) executing firmware. In the latter case, for example, when the memory system 1 is supplied with power, the processor reads the firmware (control program) stored in the ROM (not shown) onto the buffer 230 or the RAM (not shown) in the control unit 220. By executing the predetermined process, the process of the control unit 220 is realized. Here, the processor is also referred to as a core or a processor core.

When receiving a request from the host device 2 via the host I / F 210, the control unit 220 performs control according to the command. For example, the control unit 220 writes user data and parity to the nonvolatile memory 100 according to a request from the host device 2.
Specify 0. Further, the control unit 220 instructs the memory I / F 250 to issue a command for the nonvolatile memory 100 in accordance with a request from the host device 2.

Further, when receiving a write request from the host device 2, the control unit 220 determines a storage area (memory area) on the nonvolatile memory 100 for user data stored in the data buffer 230. That is, the control unit 220 manages the writing destination of user data.
The correspondence between the logical address of the user data received from the host device 2 and the physical address indicating the storage area on the nonvolatile memory 100 in which the user data is stored is stored as an address conversion table.

In addition, when receiving a read request from the host device 2, the control unit 220 converts the logical address specified by the read request into a physical address using the above-described address conversion table, and reads the physical address from the memory I. / F250 is instructed.

The data buffer 230 temporarily stores user data received by the memory controller 200 from the host device 2 until it is stored in the nonvolatile memory 100. The data buffer 230 temporarily stores user data read from the nonvolatile memory 100 until it is transmitted to the host device 2. The data buffer 230 is, for example, an SRAM (Static Rand
om Access Memory) and DRAM (Dynamic Random Access Memory). The data buffer 230 may be mounted inside the memory controller 200 or may be mounted outside the memory controller 200 independently of the memory controller 200.

The encoding unit / decoding unit 240 includes an encoding circuit 241 and a decoding circuit 242. The encoding unit / decoding unit is also referred to as an ECC (Error Correcting Code) circuit. The encoding circuit 241
The data held in the data buffer 230 is encoded to generate a code word having data and a redundant part (parity). The encoding circuit 241 encodes (error correction encodes) user data having a first data length to generate a code word having a second data length. In the encoding performed by the encoding circuit 241, for example, a BCH (Bose-Chaudhuri-Hocquenghem) code, RS (Reed-Solomon)
) Code, LDPC (Low Density Parity Check) code, or the like. Note that the error correction code used by the encoding circuit 241 is not limited to these. The decoding circuit 242 acquires a code word that is data read from the nonvolatile memory 100 via the memory I / F 250 and decodes the acquired code word. If the error correction fails during decoding, the decoding circuit 242 notifies the controller 220 of the error correction failure.

The memory I / F 250 controls the nonvolatile memory 110. The memory I / F 250 stores the code word output from the encoding circuit 241 according to the control of the control unit 220 and the like in the nonvolatile memory 1.
Write to 10. Further, the memory I / F 250 reads data from the nonvolatile memory 110 under the control of the control unit 220 and the like, and transfers the data to the decoding circuit 242 via the buffer 230.
Further, the memory I / F 250 erases data stored in the nonvolatile memory 110 under the control of the control unit 220 or the like.

The memory I / F 250 and each memory chip 110 are connected by a bus according to the NAND interface. Signals transmitted / received on this bus are, for example, a chip enable signal / CE, an address latch enable signal ALE, and a command latch enable signal C
LE, write enable signal / WE, read enable signal / RE, and input / output signal I /
O and the like. The signal / CE is a signal for enabling the memory chip 110. The signal ALE is a signal that notifies the memory chip 110 that the input signal is an address. The signal CLE is a signal that notifies the memory chip 110 that the input signal is a command. The signal / WE is a signal for causing the memory chip 110 to capture an input signal.
The signal / RE is a signal for causing the memory I / F 250 to take an output signal. The input / output signal I / O is a signal such as a net command, an address, and data.

The temperature sensor 300 is a sensor for measuring the temperature of the memory controller 200 and is disposed in the vicinity of the memory controller 200. In the following description, “the temperature of the memory controller 200” is a temperature measured at a position where the temperature sensor 300 is mounted, and includes temperature information measured by the temperature sensor 300. The temperature sensor I / F 260 has a function of a communication interface between the memory controller 200 and the temperature sensor 300, and the control unit 220 transmits temperature information measured by the temperature sensor 300 via the temperature sensor I / F 260. get.

The temperature sensor 300 may spontaneously output the temperature information to the control unit 220 via the temperature sensor I / F 260, or the temperature sensor I / F 260 acquired from the temperature sensor 300 in response to a request from the control unit 220. The measurement information may be transmitted to the control unit 220. In the latter case, a command for acquiring temperature information is transmitted from the control unit 220 to the temperature sensor I / F 260.
The temperature sensor I / F 260 transmits the temperature information acquired from the temperature sensor 300 to the control unit 220 as a response to the command.

The memory system 1 may be equipped with a plurality of temperature sensors 300. Multiple temperature sensors 30
Each temperature sensor I / F 260 may be provided for each of 0, and the control unit 220 may acquire temperature information via each temperature sensor I / F 260, or 1 for a plurality of temperature sensors 300. One temperature sensor I / F 260 is provided, and the controller 220 controls the temperature sensor I / F 260.
The temperature information measured by each of the plurality of temperature sensors 300 may be acquired via the. Control unit 22
0 determines the temperature of the memory controller 200 based on the temperature information measured by the plurality of temperature sensors 300 acquired via the temperature sensor I / F 260. As a method of determining the temperature of the memory controller 200, for example, when using the average value of each temperature information measured by the plurality of temperature sensors 300, when using the median value of each temperature information,
In some cases, temperature information measured by a specific temperature sensor 300 among a plurality of temperature sensors 300 is used.

Note that the temperature sensor 300 may be mounted in the memory controller 200. Further, the temperature sensor 300 is mounted in the memory controller 200, and the temperature sensor 300 and the control unit 2 are mounted.
20 may be connected via the bus 270, and the temperature sensor 300 may transmit temperature information to the control unit 220 in response to a request from the control unit 220. Further, the temperature sensor 300 is connected to the memory controller 2.
A plurality may be mounted in 00. When a plurality of temperature sensors 300 are mounted in the memory controller 200, the control unit 220 determines the temperature of the memory controller 200 based on temperature information obtained from the plurality of temperature sensors 300. As a method of determining the temperature of the memory controller 200, for example, when using the average value of each temperature information obtained from the plurality of temperature sensors 300, when using the median value of each temperature information, In some cases, temperature information obtained from a specific temperature sensor 300 is used.

2 and 3 show an example of the system 3 in which the memory system 1 and the host device 2 are incorporated. The system 3 is an example of an electronic device.

As shown in FIG. 2, the memory system 1 is incorporated as a storage device in a system 3 such as a server. The system 3 includes a memory system 1 and a host device 2 to which the memory system 1 is attached. The host device 2 has, for example, a plurality of connectors 4 opened upward. The connector 4 is, for example, a slot. In the example illustrated in FIG. 2, the memory system 1 includes a substrate 400, and the nonvolatile memory 100 and the memory controller 200 are mounted on the substrate 400. The plurality of memory systems 1 are respectively mounted on the connectors 4 of the host device 2 and supported side by side in a posture that stands up in a substantially vertical direction. According to such a configuration, a plurality of memory systems 1 can be mounted in a compact manner, and the host device 2 can be reduced in size.

The memory system 1 may be used as a storage device of an electronic device such as a notebook portable computer, a tablet terminal, or other detachable notebook PC (personal computer). As shown in FIG. 3, the memory system 1
Is mounted on a portable computer corresponding to the host device 2, for example. here,
The entire portable computer including the memory system 1 is the system 3.

The portable computer includes a main body 301 and a display unit 302. The display unit 302 includes a display housing 303 and the display housing 303.
And a display device 304 housed in the device.

The main body 301 includes a housing 305, a keyboard 306, and a touch pad 307 that is a pointing device. The housing 305 is a main circuit board, ODD (Optical Disk
Device) unit, card slot 308, and the like.

The card slot 308 is provided on the side surface of the housing 305. The user can insert the additional device 309 into the card slot 308 from the outside of the housing 305.

The memory system 1 may be used in a state where it is mounted inside a portable computer as a replacement of an HDD (Hard disk drive), or may be used as an additional device 309.

FIG. 4 is a perspective view showing an example of the appearance of the memory system according to the first embodiment. In this example, the memory system 1 includes a substrate 400. The substrate 400 includes a memory chip 110-
1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 11
0-8, the connection unit 211 included in the host I / F 210, the memory controller 200, the DRAM as the buffer 230, and the temperature sensor 300 may be mounted, but is not limited thereto.

Note that the host I / F 210 includes a connection unit 211 (terminal unit). In the memory system 1 illustrated in FIG. 4, the connection unit 211 is provided outside the memory controller 200.
And mounted independently. The connection unit 211 has, for example, a plurality of connection terminals (metal terminals).
The connection unit 211 is inserted into the connector 4 of the host device 2 and is electrically connected to the connector 4, for example. The host I / F 210 exchanges signals with the host device 2 via the connection unit 211.

In the memory system 1 shown in FIG. 4, the memory chip 110 is another memory chip 1.
10, the memory controller 200, the DRAM as the buffer 230, or the temperature sensor 300 is arranged so that the side faces the gap with an arbitrary length, and the temperature sensor 300 includes the memory controller 200, the NAND memory 110-1,. .., 110-8 are arranged at positions surrounded by the DRAM as the buffer 230, but the NAND memory 110-
1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 11
The arrangement of 0-8, the host interface 210, the memory controller 200, the DRAM as the buffer 230, and the temperature sensor 300 is an example, and is not limited thereto.

Next, the configuration of the memory chip 110 will be described. FIG. 5 is a block diagram of the memory chip 110 according to the present embodiment. As described above, the memory chip 110 is, for example, the NAN.
A D-type flash memory chip, which is a three-dimensional stacked NAND flash memory in which memory cells are three-dimensionally stacked above a semiconductor substrate in this embodiment.

The memory chip 110 includes an I / O (Input / Output) controller 111, a command / signal buffer 112, an address buffer 113, a voltage controller 114, a voltage generator 115, a driver 116, a sense amplifier 117, A decoder 118, a memory cell array 119, a page buffer 120, and a chip temperature sensor 121 are provided.

The memory cell array 119 includes a plurality of blocks BLK (BLK0, BLK1, BLK2) each of which is a set of a plurality of nonvolatile memory cells associated with a word line and a bit line.
, ...). The block BLK serves as a data erasing unit, and data in the same block BLK is erased collectively. Each of the blocks BLK includes a plurality of string units SU (SU0, SU1) that are sets of NAND strings 131 in which memory cells are connected in series.
, SU2, ...). Of course, the number of blocks in the memory cell array 119 and 1
The number of string units in the block BLK is arbitrary.

Based on the input signal, the I / O controller 111 outputs a command from the memory I / F 250 to the command / signal buffer 112 and outputs an address to the address buffer 113. The I / O controller 111 sends data to the page buffer 120 when receiving a write command for the memory chip 110, and receives data from the page buffer 120 when receiving a read command for the memory chip 110.

The command / signal buffer 112 decodes the command output from the I / O controller 111 and outputs an instruction for realizing an operation (for example, read, write, erase, etc.) indicated by the command to the voltage controller 114. The address buffer 113
The address output from the I / O controller 111 is decoded and the address is output to the driver 116.

The voltage controller 114 controls an access operation to the memory cell array 119 in accordance with the command instruction output from the command / signal buffer 112.

The voltage generator 115 generates a program voltage CGPV for realizing, for example, a write operation based on the control signal CGPVDAC from the voltage controller 114. The voltage generator 115 generates a read voltage CGRV for realizing, for example, a read operation based on the control signal CGRVDAC from the voltage controller 114.

The chip temperature sensor 121 measures the temperature of the memory chip 110 and outputs the measured temperature information to the voltage controller 114 as memory chip temperature information. Chip temperature sensor 1
21 may be mounted in the memory chip 110 or may be disposed in the vicinity of the memory chip 110.

The voltage controller 114 outputs the memory chip temperature information output from the chip temperature sensor 121 to the memory controller 200 via the command / signal buffer 112 and the I / O controller 111. The voltage controller 114 may acquire the memory chip temperature information output from the chip temperature sensor 121 and correct the control signal CGPVDAC for generating a program voltage using the acquired memory chip temperature information.

The driver 116 receives the address from the address buffer 113 and the voltage controller 114.
The operation of the sense amplifier 117, the row decoder 118, and the memory cell array 119 is controlled based on the instruction from.

The row decoder 118 decodes the block address and page address and selects any word line of the corresponding block BLK. The row decoder 118 applies an appropriate voltage to the selected word line, the non-selected word line, and the like.

The sense amplifier 117 senses data read from the memory cell to the bit line when reading data. When data is written, the write data is transferred to the memory cell.

Next, the configuration of the block BLK included in the memory cell array 119 will be described with reference to FIG. FIG. 6 is a circuit diagram of the block BLK.

As illustrated, the block BLK includes, for example, four string units SU (SU0 to S0).
U3). Each string unit SU includes a plurality of NAND strings 131.
including.

Each of the NAND strings 131 includes, for example, eight memory cell transistors MT (MT
0 to MT7) and select transistors ST1 and ST2. The memory cell transistor MT includes a stacked gate including a control gate and a charge storage layer, and holds data in a nonvolatile manner. Note that the number of memory cell transistors MT is not limited to eight, but 16 or 32, 6
There may be four, 128, etc., and the number is not limited. The memory cell transistor MT is arranged between the select transistors ST1 and ST2 such that the current path is connected in series. The current path of the memory cell transistor MT7 on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected to one end of the current path of the selection transistor ST2. ing.

The gates of the select transistors ST1 of the string units SU0 to SU3 are commonly connected to select gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the select transistors ST2 are commonly connected to the same select gate line SGS among a plurality of string units. Further, the memory cell transistors MT0 to MT0 in the same block BLK0.
The control gates of T7 are commonly connected to word lines WL0 to WL7, respectively.

That is, the word lines WL0 to WL7 and the select gate line SGS are in the same block BLK.
The plurality of string units SU0 to SU3 are commonly connected, while the select gate line SGD is connected to the string units SU0 to S even in the same block BLK.
Each U3 is independent.

The NAND strings 13 arranged in a matrix in the memory cell array 119
1, the other end of the current path of the selection transistor ST1 of the NAND string 131 in the same row is one of the bit lines BL (BL0 to BL (L-1), (L-1) is a natural number of 1 or more). Commonly connected to That is, the bit line BL is NAND between a plurality of blocks BLK.
The strings 131 are connected in common. The other end of the current path of the selection transistor ST2 is commonly connected to the source line SL. The source line SL is, for example, NA between a plurality of blocks.
The ND strings 131 are connected in common.

As described above, the data of the memory cell transistors MT in the same block BLK are
Erased all at once. On the other hand, data reading and writing are performed collectively for a plurality of memory cell transistors MT connected in common to any word line WL in any string unit SU in any block BLK. . When the memory cell is a single level cell (SLC), the unit that is collectively performed corresponds to one page.

FIG. 7 is a cross-sectional view of a partial region of the memory cell array 119 according to the present embodiment. As illustrated, a plurality of NAND strings 131 are formed on the p-type well region 20.
That is, a plurality of wiring layers 27 functioning as select gate lines SGS, a plurality of wiring layers 23 functioning as word lines WL, and a plurality of wiring layers 25 functioning as select gate lines SGD are formed on the well region 20. ing.

A memory hole 26 that penetrates through these wiring layers 25, 23, and 27 and reaches the well region 20 is formed. On the side surface of the memory hole 26, a block insulating film 28, a charge storage layer 29 (insulating film), and a gate insulating film 30 are sequentially formed.
A conductive film 31 is embedded inside. The conductive film 31 functions as a current path of the NAND string 131 and is a region where a channel is formed when the memory cell transistor MT and the select transistors ST1 and ST2 are operated.

In each NAND string 131, a plurality of (four layers in this example) wiring layers 27 are electrically connected in common and connected to the same select gate line SGS. That is,
The four wiring layers 27 substantially function as the gate electrode of one select transistor ST2. The same applies to the select transistor ST1 (four-layer select gate line SGD).

With the above configuration, in each NAND string 131, the selection transistor ST2, the plurality of memory cell transistors MT, and the selection transistor ST1 are sequentially stacked on the well region 20.

In the example of FIG. 7, the selection transistors ST1 and ST2 are the memory cell transistors M.
Similar to T, a charge storage layer 29 is provided. However, the selection transistors ST1 and ST2 are
It does not function as a memory cell that substantially holds data, but functions as a switch. At this time, the threshold value at which the select transistors ST1 and ST2 are turned on / off may be controlled by injecting charges into the charge storage layer 29.

A wiring layer 32 that functions as the bit line BL is formed on the upper end of the conductive film 31. Bit line BL is connected to sense amplifier 117.

Further, an n + -type impurity diffusion layer 33 and a p + -type impurity diffusion layer 34 are formed in the surface of the well region 20. A contact plug 35 is formed on the diffusion layer 33, and a wiring layer 36 that functions as the source line SL is formed on the contact plug 35. Source line SL
Are connected to a source line driver (not shown). A contact plug 37 is formed on the diffusion layer 34, and a wiring layer 38 that functions as the well wiring CPWELL is formed on the contact plug 37. The well wiring CPWELL is connected to a well driver (not shown). The wiring layers 36 and 38 are formed in an upper layer than the select gate line SGD and in a lower layer than the wiring layer 32, but this structure is an example and the present invention is not limited to this.

A plurality of the above configurations are arranged in the depth direction of the paper surface illustrated in FIG. 7, and a string unit SU is formed by a set of a plurality of NAND strings 131 arranged in the depth direction. Further, the wiring layers 27 functioning as a plurality of select gate lines SGS included in the same string unit SU are connected in common to each other. That is, the gate insulating film 30 is also formed on the well region 20 between the adjacent NAND strings 131, and the semiconductor layer 27 and the gate insulating film 30 adjacent to the diffusion layer 33 are formed up to the vicinity of the diffusion layer 33.

Therefore, when the selection transistor ST2 is turned on, the channel electrically connects the memory cell transistor MT0 and the diffusion layer 33. Also, the well wiring CPWEL
By applying a voltage to L, a potential can be applied to the conductive film 31.

Note that the memory cell array 119 may have other configurations. That is, the configuration of the memory cell array 119 is described in, for example, US patent application Ser. No. 12 / 407,403 filed on Mar. 19, 2009, “Three-dimensional stacked nonvolatile semiconductor memory”. Also, US patent application Ser. No. 12 / 406,524 filed Mar. 18, 2009 entitled “Three-dimensional stacked nonvolatile semiconductor memory”, Mar. 25, 2010 entitled “Nonvolatile semiconductor memory device and manufacturing method thereof” US patent application 12 / 679,991 filed on
No. 12 / 532,030, filed Mar. 23, 2009, entitled “Semiconductor Memory and Manufacturing Method”. These patent applications are hereby incorporated by reference in their entirety.

Next, access processing for data stored in the nonvolatile memory 100 of the memory system according to the first embodiment will be described.

In the memory system according to the first embodiment, when the memory system 1 receives a read request, a write request, a data erase request, a data deletion request such as a trim command from the host device 2, or in the background, the memory controller 200 However, the memory controller 200 accesses the nonvolatile memory 100 when executing garbage collection, refresh, wear leveling, patrol read, or the like.

Garbage collection is also called compaction. In the nonvolatile memory 100, since the data erasure unit and the data read / write unit are different, when the rewriting of the nonvolatile memory 100 proceeds, the blocks are fragmented by invalid data, and the number of such fragmented blocks increases. , Fewer blocks are available. Garbage collection is a process to increase the number of usable blocks. For example, valid data is collected from a plurality of active blocks containing valid data and invalid data, and rewritten to another block to secure a free block. Means processing.

The active block indicates a block in which valid data is recorded. The free block indicates a block in which valid data is not recorded. After erasing, the free block can be reused as an erased block. In this embodiment, the free block includes both a block before erasure in which valid data is not recorded and an erased block. Valid data is data associated with a logical address, and invalid data is data that is not associated with a logical address. When data is written, the erased block becomes an active block.

The refresh is a process of rewriting data in a block to another block when deterioration of data in the block is detected, for example, the number of correction bits in the error correction process is increased.

In wear leveling, for example, data stored in a block with a large number of rewrites or erasures is replaced with data stored in a block with a small number of rewrites or erasures, thereby rewriting the block of the nonvolatile memory 100. This is a process of leveling the number of times.

In the patrol read, in order to detect a block with increased errors, for example, data stored in the nonvolatile memory 100 is read in units of a predetermined unit, and the read data is read based on an error correction result in the decoding circuit 242. It is a process to test. In this test processing, for example, the number of error bits of the read data is compared with a threshold value, and data whose error bit number exceeds the threshold value is targeted for refresh.

In the following description, the processing of the memory system 1 when a read request is received from the host device 2, the processing of the memory system 1 when a data write request is received from the host device 2, and the memory controller 200 The processing of the memory system 1 when it is decided to erase a predetermined block of the non-volatile memory 100, the memory controller 2
An example of access processing for data stored in the nonvolatile memory 100 will be described.

FIG. 8 is a flowchart of data read processing from the nonvolatile memory 100 in response to a read request from the host device 2 of the memory system according to the first embodiment. This flowchart shows processing for receiving a read request from the host device 2, reading the requested data from the nonvolatile memory 100, and transmitting the read result to the host device 2.

In the read request described above, the amount of data that the host apparatus 2 wants to read from the memory system 1 and address information indicating the data read position are specified. The memory system 1 may determine whether or not the read request can be received, and may receive the read request from the host device 2 when the read request can be received. In the flowchart of FIG. 8, this process is omitted, and it will be described from the stage that the memory controller 200 of the memory system 1 receives the read request from the host apparatus 2 via the host I / F 210, assuming that the read request can be received.

When a read request is received from the host device 2 (step 801), the memory controller 2
The 00 control unit 220 converts the logical address, which is the address specified in the read request, into a physical address using the address conversion table in order to specify the storage location of the data that is the target of the read request. It is resolved which physical address of which memory chip 110 should be accessed in order to process a read request from (step 802).

In the present embodiment, description will be made assuming that the memory chip 110 that is the access destination for the logical address specified by the read request from the host device 2 is the memory chip 110-1.

Next, the controller 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 (step 803).

Thereafter, the control unit 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined first temperature (step 804).

When the temperature of the memory controller 200 is not higher than the predetermined first temperature (step 80)
4: No), the control unit 220 of the memory controller 200 determines the memory chip 1 to be accessed.
The memory I / F 250 is instructed to read the memory chip temperature information from the memory 10-1, and the memory I
Memory chip temperature information is acquired from the memory chip 110-1 via / F250 (step 805).

The control unit 220 of the memory controller 200 transmits a command to the memory chip 110-1 via the memory I / F 250 in order to acquire memory chip temperature information from the memory chip 110-1.

FIG. 9 shows a memory I / F for acquiring memory chip temperature information of the memory chip 110.
An example of a command sequence indicating a signal transmitted from the memory controller 200 to the memory chip 110 via 250 is shown. In FIG. 9, only the signal transmitted as the input / output signal I / O and the R / B signal indicating the ready / busy state of the memory chip 110-1 are shown.
The other signals / CE, ALE, CLE, / WE, and / RE are not shown.

As shown in FIG. 9, when the memory controller 200 transmits a memory chip temperature information acquisition command (XXh) as an input / output signal I / O, the memory chip 110 becomes busy, and the R / B signal becomes “L” level. . Then, the memory chip temperature information acquisition operation is started in the memory chip 110. When the memory chip temperature information of the memory chip 110 is output to the memory controller 200 and the memory chip 110 returns to the ready state, the R / B signal becomes “H” level. As a result, the memory chip temperature information is stored in the memory controller 20.
Read to zero.

The operation described with reference to FIG. 9 is performed only on one memory chip 110. That is,
For example, the memory controller 200 issues a memory chip temperature information acquisition command to each of the memory chips 110-1,.
The memory controller 200 includes memory chips 110-1, ..., memory chips 110-N.
Each temperature information can be acquired, and the memory chip 110-1,.
-N Recognizes each temperature.

The control unit 220 of the memory controller 200 specifies the temperature of the memory chip 110-1 from the memory chip temperature information acquired from the memory chip 110-1, and the memory chip 110-
It is determined whether the temperature of 1 is higher than a predetermined second temperature (step 806). The predetermined second temperature may be the same as the predetermined first temperature, or may be a different temperature.

When the temperature of the memory chip 110-1 is not higher than the predetermined second temperature (step 806)
: No), the controller 220 of the memory controller 200 executes the temperature raising process (step 807).

The execution of the temperature raising process is a process executed to raise the temperature of the memory controller 200 and the temperature of the memory chip 110. For example, the control unit 220 of the memory controller 200 may drive a temperature increasing unit such as a heater (not shown),
The control unit 220 of the memory controller 200 may drive the encoding / decoding unit 240. If the temperature of the memory controller 200 and the temperature of the memory chip 110 of the memory system 1 can be raised, the control unit 220 of the memory controller 200 is used.
May execute a process different from the driving of the temperature raising unit and the driving of the encoding unit / decoding unit 240. When the memory system 1 mounts the temperature raising unit, the temperature raising unit can be mounted on the substrate 400. The temperature raising unit is also referred to as a temperature raising circuit, a temperature raising device, and a temperature raising module.

Here, driving the encoding unit / decoding unit 240 means driving the encoding circuit 241 without driving the decoding circuit 242, driving both the encoding circuit 241 and the decoding circuit 242, or This includes driving the decoding circuit 242 without driving the encoding circuit 241.

Driving the encoding circuit 241 means, for example, outputting dummy data to the encoding circuit 241 and discarding (ignoring) the dummy data encoded by the encoding circuit 241.
Here, the dummy data may be any data that is not written as user data to the memory chip 110 and may be any value such as all zeros or all ones.

Driving the decoding circuit 242 means, for example, outputting dummy data to the decoding circuit 242
The decoding result by the decoding circuit 242 is discarded (ignored). Here, the dummy data may be any data that is not written as user data to the memory chip 110, and may be any value such as all zeros or all ones. Here, when the decoding circuit 242 can decode the dummy data, the data after decoding the dummy data cannot be decoded by the decoding circuit 242.
That is, when the decoding circuit 242 fails in error correction, error correction failure becomes a decoding result.

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the temperature of the memory controller 200 is higher than the predetermined first temperature (step 804:
Yes), or when the temperature of the memory chip 110-1 is higher than the predetermined second temperature (step 806: Yes), the control unit 220 of the memory controller 200 causes the memory chip 1 to
Data read from 10-1 is instructed to the memory I / F 250, and data is read from the memory chip 110-1 via the memory I / F 250 (step 808).

Next, the memory controller 200 decodes the data read from the memory chip 110-1 (step 809). The control unit 220 of the memory controller 200 instructs the decoding circuit 242 to decode the data read from the memory chip 110-1, and the decoding circuit 242 decodes the data instructed by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, when error correction is successful during decoding, the decoded data is notified to the control unit 220, and when error correction fails during decoding, the error correction failure is notified to the control unit 220.

Thereafter, the control unit 220 transmits user data, which is decoded data, when error correction is successful, and a read error to the host device 2 via the host I / F 210 when error correction failure is notified (step S120). 810).

In the flowchart shown in FIG. 8, unless the temperature of the memory controller 200 is higher than the predetermined first temperature and the temperature of the memory chip 110-1 is not higher than the predetermined second temperature, the control unit of the memory controller 200. 220 does not read data from the memory chip 110-1, but when the control unit 220 of the memory controller 200 detects a timeout, that is, when a predetermined time elapses, the control unit 220 of the memory controller 200 Data decoded from the memory chip 110-1 may be transmitted to the host device 2. Alternatively, the memory controller 200 may transmit a read error to the host device 2 when a timeout is detected, that is, when a predetermined time has elapsed.

The start timing of the predetermined time when detecting the timeout may be any timing, for example, the timing when the memory system 1 receives a read request from the host device 2,
The timing of starting execution of the temperature raising process may be used.

FIG. 10 is a flowchart of a data write process to the nonvolatile memory 100 in response to a write request from the host device 2 of the memory system according to the first embodiment. This flowchart shows processing for receiving a data write request from the host device 2, writing data designated by the write request to the nonvolatile memory 100, and transmitting the write result to the host device 2. 10, the same parts as those in FIG. 8 are denoted by the same reference numerals.

In the write request described above, user data, user data address information, and the like are specified. The memory system 1 may determine whether or not the write request can be received, and may receive the write request from the host device 2 when the write request can be received. In the flowchart of FIG. 10, this process is omitted, and it is assumed that the write request can be received, and the description starts from the stage when the memory controller 200 of the memory system 1 receives the write request from the host device 2 via the host I / F 210.

When receiving a write request from the host device 2 (step 1001), the control unit 220 of the memory controller 200 determines a physical address corresponding to the logical address specified by the write request, and transfers the determined physical address to the address conversion table. Reflect (Step 1
002). Then, the control unit 220 of the memory controller 200 instructs the encoding circuit 241 to encode the user data to be written designated by the write request, and the encoding circuit 24.
1 encodes user data to be written (step 1003).

In the present embodiment, the memory chip 110 corresponding to the physical address determined with respect to the logical address specified by the write request from the host 2 will be described as the memory chip 110-1.

Next, the control unit 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 (step 803).

Thereafter, the controller 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined third temperature (step 1004). The predetermined third temperature may be the same as the predetermined first temperature or may be a different temperature.

When the temperature of the memory controller 200 is not higher than the predetermined third temperature (step 10)
04: No), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to read the memory chip temperature information in order to acquire the memory chip temperature information of the memory chip 110-1 to be accessed, and the memory I / F Memory chip temperature information is acquired from the memory chip 110-1 via F250 (step 805). The memory chip temperature information acquisition process from the memory chip 110-1 by the control unit 220 of the memory controller 200 is the same as the process when a read request is received from the host device 2.

The control unit 220 of the memory controller 200 identifies the temperature of the memory chip 110-1 based on the memory chip temperature information acquired from the memory chip 110-1, and the memory chip 110
It is determined whether the temperature of −1 is higher than a predetermined fourth temperature (step 1005).

The predetermined fourth temperature may be the same as the predetermined second temperature, or may be a different temperature. The predetermined fourth temperature may be the same as the predetermined third temperature or may be a different temperature.

When the temperature of the memory chip 110-1 is not higher than the predetermined fourth temperature (step 100)
5: No), the control unit 220 of the memory controller 200 executes the temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the encoding unit / decoding unit 240 is driven as the temperature increase process, the memory controller 200 controls the memory controller 1 in the same manner as when the memory system 1 reads data from the nonvolatile memory 100 in response to a read request from the host device 2. The unit 220 may drive both the encoding circuit 241 and the decoding circuit 242 instead of driving only the encoding circuit 241,
The decoding circuit 242 may be driven without driving the encoding circuit 241.

When the temperature of the memory controller 200 is higher than the predetermined third temperature (step 1004)
: Yes) or when the temperature of the memory chip 110-1 is higher than a predetermined fourth temperature (
Step 1005: Yes), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to write the encoded data to the memory chip 110-1, and sends the memory chip 110-1 via the memory I / F 250. Data is written (step 1006).

Next, the memory controller 200 transmits the data write result to the memory chip 110-1 to the host device 2 via the host I / F 210 (step 1007).

In the flowchart shown in FIG. 10, if the temperature of the memory controller 200 is not higher than the predetermined third temperature and the temperature of the memory chip 110-1 is not higher than the predetermined fourth temperature, the control unit of the memory controller 200 220 does not write data to the memory chip 110-1, but when the memory controller 200 detects a timeout, that is, when a predetermined time elapses, the control unit 220 of the memory controller 200 causes the memory chip 110- The encoded data may be written to 1. Alternatively, the memory controller 200 may transmit a write error to the host device 2 when a timeout is detected, that is, when a predetermined time has elapsed.

The start timing of the predetermined time when detecting the timeout may be any timing, for example, the timing when the memory system 1 receives a write request from the host device 2, the timing when the execution of the temperature raising process is started, or the like.

FIG. 11 is a flowchart of a modification of the data writing process to the nonvolatile memory 100 in response to a write request from the host device 2 of the memory system according to the first embodiment. This flowchart shows processing for receiving a data write request from the host device 2, writing user data specified by the write request to the nonvolatile memory 100, and transmitting the write result to the host device 2. 11, the same parts as those in FIGS. 8 and 10 are denoted by the same reference numerals.

In the memory system according to the present modification, when the temperature of the memory chip 110 is not higher than the predetermined fourth temperature (step 1005: No), the control unit 220 of the memory controller 200.
Does not execute the temperature raising process, but instead of the memory chip 110-1.
.., And the temperature of the memory chip 110-N are acquired (step 1101).

And the control part 220 of the memory controller 200 is the memory chip 110-2, ...
It is determined whether there is a memory chip whose temperature is higher than the fourth reference value among the memory chips 110-N (step 1102).

When there is no memory chip whose temperature is higher than the fourth reference value (step 1102: N
o) The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
), Returning to step 803, the temperature of the memory controller 200 is again set to the temperature sensor I /
Obtained via F260 (step 803).

When there is a memory chip whose temperature is higher than the fourth reference value (step 1102: Ye)
s) The control unit 220 of the memory controller 200 changes the physical address corresponding to the logical address specified in the write request, and reflects the changed physical address in the address conversion table (step 1103).

In this modification, the memory chip 110 corresponding to the changed physical address is the memory chip 1.
10-2, that is, among the memory chips 110-2,..., The memory chip 110-N has a memory chip 110 whose temperature is higher than the fourth temperature.
Explanation will be made assuming that −2.

When the controller 220 of the memory controller 200 reflects the changed physical address in the address conversion table (step 1103), the changed physical address is stored in the memory chip 11.
The address conversion table is changed so that the physical address corresponds to 0-2.

The control unit 220 of the memory controller 200 reflects the changed physical address in the address conversion table (step 1103), and then instructs the memory I / F 250 to write the encoded data to the memory chip 110-2. Then, data is written to the memory chip 110-2 via the memory I / F 250 (step 1006).

Next, the memory controller 200 transmits the data write result to the memory chip 110-2 to the host device 2 via the host I / F 210 (step 1007).

On the other hand, when the temperature of the memory controller 200 is higher than the predetermined third temperature (step 1004: Yes), or when the temperature of the memory chip 110-1 is higher than the predetermined fourth temperature (step 1005: Yes). The control unit 220 of the memory controller 200 instructs the memory I / F 250 to write the encoded data to the memory chip 110-1, and writes the data to the memory chip 110-1 via the memory I / F 250 (Step S1). 10
06) The memory controller 200 transmits the data write result to the memory chip 110-1 to the host device 2 via the host I / F 210 (step 1007).

In this modification, the physical address corresponding to the logical address designated by the write request of the host device 2 is determined before acquiring the memory chip temperature information (step 1002).
Instead of determining the physical address corresponding to the logical address specified in the write request before acquiring the memory chip temperature information, acquire the memory chip temperature information and write request based on the acquired memory chip temperature information The physical address corresponding to the logical address specified in (1) may be determined.

That is, in this modification, the memory chips 110-1,.
Memory chip temperature information is obtained, and when the temperature of the memory chip 110-1 is not higher than the predetermined fourth temperature, but the temperature of the memory chip 110-2 is higher than the predetermined fourth temperature, the memory chip 110-2 may be determined as the data write destination memory chip 110, and the physical address corresponding to the memory chip 110-2 may be reflected in the address conversion table.

FIG. 12 is a flowchart of the erasing process of a predetermined block in the nonvolatile memory 100 of the memory system according to the first embodiment. The flowchart in FIG. 12 will be described from the stage when the memory controller 200 has decided to erase a predetermined block of the nonvolatile memory 100. In FIG. 12, the same parts as those in FIG.

In the present embodiment, description will be made assuming that the memory chip 110 including a predetermined block to be erased is the memory chip 110-1.

The control unit 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 (step 803).

Thereafter, the control unit 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined fifth temperature (step 1201). The predetermined fifth temperature may be the same as the predetermined first temperature or the predetermined third temperature, or may be a different temperature.

When the temperature of the memory controller 200 is not higher than the predetermined fifth temperature (step 12)
01: No), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to read the memory chip temperature information in order to obtain the memory chip temperature information of the memory chip 110-1 to be accessed, and the memory I / F Memory chip temperature information is acquired from the memory chip 110-1 via F250 (step 805). The memory chip temperature information acquisition process from the memory chip 110-1 by the control unit 220 of the memory controller 200 is the same as the process when a read request is received from the host device 2.

The control unit 220 of the memory controller 200 identifies the temperature of the memory chip 110-1 based on the memory chip temperature information acquired from the memory chip 110-1, and the memory chip 110
It is determined whether the temperature of −1 is higher than a predetermined sixth temperature (step 1202).

The predetermined sixth temperature may be the same as the predetermined second temperature or the predetermined fourth temperature, or may be a different temperature. The predetermined sixth temperature may be the same as the predetermined fifth temperature or may be a different temperature.

When the temperature of the memory chip 110-1 is not higher than the predetermined sixth temperature (step 120)
2: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the encoding unit / decoding unit 240 is driven as the temperature increase process, the memory controller 200 controls the memory controller 1 in the same manner as when the memory system 1 reads data from the nonvolatile memory 100 in response to a read request from the host device 2. The unit 220 may drive both the encoding circuit 241 and the decoding circuit 242 instead of driving only the encoding circuit 241,
The decoding circuit 242 may be driven without driving the encoding circuit 241.

When the temperature of the memory controller 200 is higher than the predetermined fifth temperature (step 1201)
: Yes) or when the temperature of the memory chip 110-1 is higher than a predetermined sixth temperature (
Step 1202: Yes), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to erase a predetermined block (Step 1203).

Next, the memory controller 200 may reflect the block erase result for the memory chip 110-1 in a management table for managing erase blocks.

In the flowchart shown in FIG. 12, if the temperature of the memory controller 200 is not higher than the predetermined fifth temperature and the temperature of the memory chip 110-1 is not higher than the predetermined sixth temperature, the control unit of the memory controller 200 220 does not erase the block of the memory chip 110-1, but when the memory controller 200 detects a timeout, that is, when a predetermined time has elapsed, the control unit 220 of the memory controller 200 causes the memory chip 110- One predetermined block may be erased. Alternatively, the memory controller 20
When 0 is detected, that is, when a predetermined time elapses, the memory controller 200 may give up erasing a predetermined block of the memory chip 110-1.

The start timing of the predetermined time when detecting the timeout may be any timing, for example, the timing when the memory controller 200 decides to erase the predetermined block of the nonvolatile memory 100, and the execution of the temperature raising process is started. The timing to do so may be sufficient.

As described above, according to the first embodiment, in the memory system 1, when the temperature of the memory controller 200 is not higher than the predetermined temperature and the temperature of the memory chip 110 to be accessed is not higher than the predetermined temperature, the memory The controller 200 is a memory controller 200.
In order to increase the temperature of the memory chip 110 and the temperature of the memory chip 110, a temperature raising process is executed. After executing the temperature raising process, when the temperature of the memory controller 200 becomes higher than a predetermined temperature or when the temperature of the memory chip 110 to be accessed becomes higher than the predetermined temperature, the memory controller 200
Accesses the memory chip 110.

In the memory system according to the present embodiment, when the temperature of the memory controller 200 or the temperature of the memory chip 110 is not higher than a predetermined temperature corresponding to each, the temperature of the memory controller 200 or the temperature of the memory chip 110 corresponds to each. Since the nonvolatile memory 110 is accessed after waiting for a predetermined temperature to be reached, the stress on the memory cells of the nonvolatile memory 110 can be reduced even when the nonvolatile memory 110 is vulnerable to low temperature operation. Data stored in the nonvolatile memory 110, the nonvolatile memory 11
The reliability of data read from 0 can be improved, and the occurrence frequency of read errors from the nonvolatile memory 110 and write errors to the nonvolatile memory 110 can be reduced.

(Second Embodiment)
FIG. 13 is a flowchart of a process of reading data from the nonvolatile memory 100 in response to a read request from the host device 2 of the memory system according to the second embodiment. FIG.
3, the same parts as those in FIG. In the description of this embodiment,
For the same configuration and operation as in the first embodiment, a duplicate description is omitted. The external appearance and configuration of the memory system 1 in the present embodiment are the same as those in FIGS.

In the present embodiment, as in the first embodiment, the memory chip 110 that is the access destination for the logical address specified by the read request from the host device 2 is described as the memory chip 110-1.

The memory system according to the second embodiment is different from the memory system according to the first embodiment in that the control unit 220 of the memory controller 200 converts a logical address, which is an address specified by a read request, into a physical address. Then, after processing for solving which physical address of which memory chip 110 should be accessed to process a read request from the host device 2 (step 802), data is read from the memory chip 110-1 and read. Is successful, that is, if the read data can be decoded, the memory controller 2
It is to transmit the decoded data to the host device 2 without acquiring the temperature of 00 or the temperature of the memory chip 110.

The control unit 220 of the memory controller 200 converts a logical address, which is an address specified by the read request, into a physical address, and accesses which physical address of which memory chip 110 to process the read request from the host device 2. Solving what to do (
Step 802), reading data from the memory chip 110-1 to the memory I / F 250
To read data from the memory chip 110-1 via the memory I / F 250 (step 1301).

Then, the memory controller 200 decodes the data read from the memory chip 110-1 (Step 1302). The control unit 220 of the memory controller 200 instructs the decoding circuit 242 to decode the data read from the memory chip 110-1, and the decoding circuit 242 decodes the data specified by the control unit 220. The decoding circuit 242 outputs the decoding result to the control unit 220. That is, when error correction is successful during decoding, the decoded data is notified to the control unit 220, and when error correction fails during decoding, the error correction failure is notified to the control unit 220.

When the decoding by the decoding circuit 242 is successful (step 1303: Yes), that is, when error correction is successful at the time of decoding, the control unit 220 of the memory controller 200 sends user data that is decoded data via the host I / F 210. To the host device 2 (step 810).

When the decoding by the decoding circuit 242 is not successful (step 1303: No), that is, when the error correction failure is notified from the decoding circuit 242, the control unit 220 of the memory controller 200 changes the temperature of the memory controller 200 to the temperature Obtained via the sensor I / F 260 (step 803), and thereafter, processing similar to that of the memory system according to the first embodiment is executed.

According to the second embodiment described above, in the memory system 1, as in the first embodiment, the reliability of data read from the nonvolatile memory 110 even when the nonvolatile memory 110 is vulnerable to low-temperature operation. Can be improved.

Further, according to the second embodiment, in response to a read request from the host device 2, when reading from the memory chip 110 is successful, the process of acquiring the temperature of the memory controller 200 and the temperature of the memory chip 110 is performed. Since it is not executed, the latency is shorter than when the temperature of the memory controller 200 and the temperature of the memory chip 110 are acquired.

(Third embodiment)
FIG. 14 is a flowchart of a data write process to the nonvolatile memory 100 in response to a data write request from the host device 2 of the memory system according to the third embodiment.
14, the same parts as those in FIG. 10 are denoted by the same reference numerals. In the description of the present embodiment, the description of the same configuration and operation as in the first embodiment will be omitted. The external appearance and configuration of the memory system 1 in the present embodiment are the same as those in FIGS.

In the present embodiment, as in the first embodiment, the memory chip 110 corresponding to the physical address determined for the logical address specified by the write request from the host device 2 is the memory chip 110-1. explain.

The difference between the memory system according to the third embodiment and the memory system according to the first embodiment is that the control unit 220 of the memory controller 200 encodes the user data to be written specified in the write request ( After step 1003), the encoded data is written to the memory chip 110-1, and when the writing is successful, a response indicating that the writing is successful is sent to the host device 2.

The control unit 220 of the memory controller 200 instructs the encoding circuit 241 to encode the user data to be written designated by the write request, and the encoding circuit 241 performs a process of encoding the user data to be written. After (Step 1003), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to write the encoded data to the memory chip 110-1, and the memory chip 110-1 via the memory I / F 250.
The data is written to (step 1401).

When the writing to the memory chip 110-1 is successful (step 1402: Yes), the control unit 220 of the memory controller 200 transmits a response indicating that the writing is successful to the host device 2 (step 1007). The control unit 220 of the memory controller 200
Whether or not the writing to the memory chip 110-1 is successful, for example, the memory chip 110
-1 to memory I / F2 from the memory chip 110-1
Judgment is made based on the response output via 50.

When the writing to the memory chip 110-1 is not successful (step 1402: No), the control unit 220 of the memory controller 200 sets the temperature of the memory controller 200 to
Obtained via the temperature sensor I / F 260 (step 803), and thereafter, according to the first embodiment, except that data is written to a physical address different from the physical address of the data write destination in step 1401. The same processing as the memory system is executed.

When the writing to the memory chip 110-1 is not successful (step 1402: No), the control unit 220 of the memory controller 200 sets the temperature of the memory controller 200 to
After being acquired via the temperature sensor I / F 260 (step 803), the memory controller 20
It is determined whether the temperature of 0 is higher than a predetermined third temperature (step 1004).

When the temperature of the memory controller 200 is not higher than the predetermined third temperature (step 10)
04: No), the control unit 220 of the memory controller 200 acquires memory chip temperature information from the memory chip 110-1 via the memory I / F 250 (step 805).

The control unit 220 of the memory controller 200 identifies the temperature of the memory chip 110-1 based on the memory chip temperature information acquired from the memory chip 110-1, and the memory chip 110
It is determined whether the temperature of −1 is higher than a predetermined fourth temperature (step 1005).

When the temperature of the memory chip 110-1 is not higher than the predetermined fourth temperature (step 100)
5: No), the controller 220 of the memory controller 200 executes the temperature raising process (step 807), returns to step 803, and again acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 ( Step 803).

When the temperature of the memory controller 200 is higher than the predetermined third temperature (step 1004)
: Yes) or when the temperature of the memory chip 110-1 is higher than a predetermined fourth temperature (
(Step 1005: Yes), the controller 220 of the memory controller 200 changes the physical address corresponding to the logical address specified by the write request, and reflects the changed physical address in the address conversion table (step 1403).

When the control unit 220 of the memory controller 200 reflects the changed physical address in the address conversion table (step 1403), the changed physical address is changed to step 140.
1 so that the physical address is different from the physical address where the data was written.

Thereafter, the control unit 220 of the memory controller 200 instructs the memory I / F 250 to write data to the physical address changed in Step 1403, and the memory I / F 25
Data is written to the memory chip 110-1 via 0 (step 1404).

According to the third embodiment described above, in the memory system 1, as in the first embodiment, even when the nonvolatile memory 110 is vulnerable to low-temperature operation, the data stored in the nonvolatile memory 110 is stored. Reliability can be improved.

Further, according to the third embodiment, in response to a write request from the host device 2, when the write to the memory chip 110 is successful, the process of acquiring the temperature of the memory controller 200 and the temperature of the memory chip 110 is performed. The temperature of the memory controller 200,
The latency is shorter than when the temperature of the memory chip 110 is acquired.

(Fourth embodiment)
FIG. 15 is a flowchart of the erasing process of a predetermined block in the nonvolatile memory 100 of the memory system according to the fourth embodiment. The flowchart of FIG. 15 will be described from the stage when the memory controller 200 has decided to erase a predetermined block of the nonvolatile memory 100. In FIG. 15, the same parts as those in FIG. In the description of the present embodiment, the description of the same configuration and operation as in the first embodiment will be omitted. Further, the appearance and configuration of the memory system 1 in the present embodiment are shown in FIGS.
The same shall apply.

In the present embodiment, description will be made assuming that the memory chip 110 including a predetermined block to be erased is the memory chip 110-1.

The memory system according to the fourth embodiment is different from the memory system according to the first embodiment in that the control unit 220 of the memory controller 200 erases a predetermined block of the nonvolatile memory 100. Memory controller 2
The predetermined block is erased without acquiring the temperature of 00 or the like, and the temperature or the like of the memory controller 200 is acquired when the erase is not successful.

The control unit 220 of the memory controller 200 deletes a predetermined block from the memory I / F2
50 (step 1501).

The control unit 220 of the memory controller 200 determines whether or not the block erase for the memory chip 110-1 is successful, for example, from the memory chip 110-1 via the memory I / F 250 in response to a block erase instruction for the memory chip 110-1. The determination is made based on the response output in step 1502 (step 1502).

When the block erase for the memory chip 110-1 is successful (step 1502: Yes), the control unit 220 of the memory controller 200 ends the flowchart shown in FIG. When the block erase for the memory chip 110-1 is successful, the control unit 220 of the memory controller 200 may reflect the block erase result on the management table for managing the erase block.

When the block erase for the memory chip 110-1 is not successful (step 1502: No), the control unit 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 (step 803). Thereafter, the same processing as that of the memory system according to the first embodiment is executed.

According to the fourth embodiment described above, in the memory system 1, as in the first embodiment, even if the nonvolatile memory 110 is vulnerable to low temperature operation, the stress of the memory cells of the nonvolatile memory 110 is reduced. Can be reduced.

Further, according to the fourth embodiment, when the erasure of the predetermined block is successful, the process of acquiring the temperature of the memory controller 200 and the temperature of the memory chip 110 is not executed, so the temperature of the memory controller 200, the memory chip Compared with the case where the temperature of 110 is acquired, the time required for block erasing is shortened.

(Fifth embodiment)
FIG. 16 is a flowchart of processing of the memory controller of the memory system according to the fifth embodiment. In FIG. 16, the same parts as those in FIG. In the description of the present embodiment, the description of the same configuration and operation as in the first embodiment will be omitted. The external appearance and configuration of the memory system 1 in the present embodiment are the same as those in FIGS.

The memory system according to the fifth embodiment is different from the memory system according to the first embodiment in that the control unit 220 of the memory controller 200 issues a request that requires access from the host device 2 to the nonvolatile memory 100. Regardless of receiving etc., memory controller 2
It is to acquire the temperature of 00 and the temperature of the memory chip 110 and execute the temperature raising process.

In the flowchart illustrated in FIG. 16, the control unit 220 of the memory controller 200 acquires the temperature of the memory controller 200 and the memory chip temperature information of the memory chip 110 at a predetermined timing, and performs a temperature increase process according to the acquired temperature. The process to be executed is shown. Here, for example, when the memory system 1 has not received a request from the host device 2, the memory controller 200 executes garbage collection, refresh, wear leveling, patrol read, etc. If not.

The controller 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 at a predetermined timing (step 803), and the acquired temperature of the memory controller 200 is greater than the predetermined seventh temperature. It is determined whether it is high (step 1601). The predetermined seventh temperature may be the same as or different from the predetermined first temperature, the predetermined third temperature, or the predetermined fifth temperature in the processing of the memory controller 200 of the first embodiment. It may be temperature.

When the temperature of the memory controller 200 is not higher than the predetermined seventh temperature (step 16)
01: No), the control unit 220 of the memory controller 200 includes the memory chip 110-1,
..., the memory I / F 250 is instructed to read the memory chip temperature information for each of the memory chips 110-N, and the respective memory chip temperature information is acquired via the memory I / F 250 (step 1602).

The control unit 220 of the memory controller 200 determines whether or not the memory chip 110 is higher than a predetermined eighth temperature among the memory chips 110-1,. Step 1603). The predetermined eighth temperature may be the same as or different from the predetermined second temperature, the predetermined fourth temperature, or the predetermined sixth temperature in the processing of the memory controller 200 of the first embodiment. It may be temperature. The predetermined eighth temperature may be the same as the predetermined seventh temperature or may be a different temperature.

The memory chip 110-1,..., The memory chip 110-N has a predetermined eighth temperature.
When there is no memory chip 110 higher than the above temperature (step 1603: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the temperature of the memory controller 200 is higher than a predetermined seventh temperature (step 1601)
: Yes), or when there is a memory chip 110 whose temperature is higher than a predetermined eighth temperature among the memory chips 110-1,..., Memory chip 110-N (step 1603).
: Yes), the flowchart shown in FIG. 16 ends.

In the flowchart shown in FIG. 16, the temperature of the memory controller 200 is not higher than a predetermined seventh temperature, and the memory chip 110-1,... As long as there is no memory chip 110 higher than the temperature, the control unit 220 of the memory controller 200 is supposed to continue to execute the temperature increase process. May be stopped.

For example, the control unit 220 of the memory controller 200 detects a timeout when the memory system 1 receives a request from the host apparatus 2 or when the memory controller 200 executes garbage collection, refresh, wear leveling, patrol read, or the like. May be. Further, when an arbitrary time elapses from an arbitrary timing, the memory controller 200 may detect a timeout.

In the flowchart shown in FIG. 16, the control unit 220 of the memory controller 200 includes the memory chip 110-1,..., The memory chip 110-N that has a memory chip 110 whose temperature is higher than a predetermined eighth temperature. Although the temperature raising process is not executed when it exists, the condition for not performing the temperature raising process may be changed as appropriate.

For example, the control unit 220 of the memory controller 200 includes the memory chip 110-1,.
The memory chip 110-N has a temperature higher than a predetermined eighth temperature.
The temperature raising process may not be executed when there are a predetermined number or more.

In addition, for example, the control unit 220 of the memory controller 200 includes the memory chip 110-1.
,..., The memory chip 110-N includes a predetermined first number or more of memory chips 110 having a temperature higher than a predetermined eighth temperature, and the memory chips 110-1,. The temperature raising process may not be executed when there are a predetermined second number or more of memory chips 110 whose temperature is higher than the predetermined ninth temperature in -N. Here, the predetermined ninth temperature is different from the predetermined eighth temperature, and the second number may be the same as or different from the first number.

According to the fifth embodiment described above, in the memory system 1, as in the first embodiment, even when the nonvolatile memory 110 is vulnerable to low temperature operation, the data stored in the nonvolatile memory 110 is stored. Reliability can be improved.

In addition, according to the fifth embodiment, the memory controller 200 does not receive a request from the host device 2 or does not execute garbage collection, refresh, wear leveling, patrol read, or the like. When processing for increasing the temperature of 200 and the temperature of the memory chip 110 is executed and a request is received from the host device 2, processing for increasing the temperature of the memory controller 200 and the temperature of the memory chip 110 is not executed. For this reason, when a request is received from the host device 2, the latency for the request of the host device 2 is shortened.

(Sixth embodiment)
FIG. 17 is a flowchart of data read processing from the nonvolatile memory 100 in response to a read request from the host device 2 of the memory system according to the sixth embodiment. FIG.
7, the same parts as those in FIG. In the description of this embodiment,
For the same configuration and operation as in the first embodiment, a duplicate description is omitted. The external appearance and configuration of the memory system 1 in the present embodiment are the same as those in FIGS.

In the present embodiment, as in the first embodiment, the memory chip 110 that is the access destination for the logical address specified by the read request from the host device 2 is described as the memory chip 110-1.

In the memory system according to the present embodiment, unlike the memory system according to the first embodiment, the control unit 220 of the memory controller 200 uses which physical address of which memory chip 110 to process a read request from the host device 2. After the process for solving whether to access (step 802), the data reading process or the temperature raising process from the memory chip 110 is performed based on the temperature of the memory controller 200 without acquiring the temperature of the memory chip 110. Run.

The control unit 220 of the memory controller 200 converts a logical address, which is an address specified by the read request, into a physical address, and accesses which physical address of which memory chip 110 to process the read request from the host device 2. Solving what to do (
Step 802) The temperature of the memory controller 200 is acquired via the temperature sensor I / F 260 (Step 803).

Thereafter, the controller 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined ninth temperature (step 1701). The predetermined ninth temperature may be the same as the predetermined first temperature or may be a different temperature.

When the temperature of the memory controller 200 is not higher than the predetermined ninth temperature (step 80)
4: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the temperature of the memory controller 200 is higher than a predetermined ninth temperature (step 1701)
: Yes), the memory controller 200 reads data from the memory chip 110-1 (step 808), and thereafter executes the same processing as the memory system according to the first embodiment.

FIG. 18 is a flowchart of a data write process to the nonvolatile memory 100 in response to a write request from the host device 2 of the memory system according to the sixth embodiment. This flowchart shows processing for receiving a data write request from the host device 2, writing data designated by the write request to the nonvolatile memory 100, and transmitting the write result to the host device 2. 18, the same parts as those in FIG. 10 are denoted by the same reference numerals.

In the memory system according to the present embodiment, unlike the memory system according to the first embodiment, the control unit 220 of the memory controller 200 encodes the user data to be written specified by the write request (step 802). Without acquiring the temperature of the memory chip 110, the data writing process or the temperature raising process to the memory chip 110 is executed based on the temperature of the memory controller 200.

The control unit 220 of the memory controller 200 determines a physical address corresponding to the logical address specified by the write request, and reflects the determined physical address in the address conversion table (step 1002). The controller 220 of the memory controller 200
The encoding circuit 241 is instructed to encode the writing target user data specified by the writing request, and the encoding circuit 241 encodes the writing target user data (step 1003).
).

In the present embodiment, the memory chip 110 corresponding to the physical address determined with respect to the logical address specified by the write request from the host 2 will be described as the memory chip 110-1.

Next, the control unit 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 (step 803).

Thereafter, the controller 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined tenth temperature (step 1801). Predetermined first
The temperature of 0 may be the same as the predetermined third temperature or may be a different temperature.

When the temperature of the memory controller 200 is not higher than the predetermined tenth temperature (step 1)
801: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the temperature of the memory controller 200 is higher than a predetermined tenth temperature (step 180)
1: Yes), the control unit 220 of the memory controller 200 writes the encoded data to the memory chip 110-1 via the memory I / F 250 (step 1006), and the subsequent processes are the same as those of the memory system according to the first embodiment. Execute the process.

FIG. 19 is a flowchart of an erasing process of a predetermined block in the nonvolatile memory 100 of the memory system according to the sixth embodiment. The flowchart of FIG. 19 will be described from the stage when the memory controller 200 has decided to erase a predetermined block of the nonvolatile memory 100. 19, the same parts as those in FIG. 12 are denoted by the same reference numerals.

In the present embodiment, description will be made assuming that the memory chip 110 including a predetermined block to be erased is the memory chip 110-1.

In the memory system according to the present embodiment, unlike the memory system according to the first embodiment, the control unit 220 of the memory controller 200 does not acquire the temperature of the memory chip 110, and based on the temperature of the memory controller 200. An erasing process or a temperature raising process for a predetermined block of the memory chip 110 is executed.

The control unit 220 of the memory controller 200 acquires the temperature of the memory controller 200 via the temperature sensor I / F 260 (step 803).

Thereafter, the control unit 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined eleventh temperature (step 1901). Predetermined first
The temperature of 1 may be the same as the predetermined fifth temperature or may be a different temperature.

When the temperature of the memory controller 200 is not higher than the predetermined eleventh temperature (step 1
901: No), the control unit 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory controller 200 is again set to the temperature sensor I /.
Obtained via F260 (step 803).

When the temperature of the memory controller 200 is higher than the predetermined eleventh temperature (step 190)
1: Yes), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to erase a predetermined block (step 1203).

According to the sixth embodiment described above, in the memory system 1, as in the first embodiment, even if the nonvolatile memory 110 is vulnerable to low-temperature operation, the stress of the memory cells of the nonvolatile memory 110 is reduced. The reliability of data stored in the non-volatile memory 110 and data read from the non-volatile memory 110 can be improved, and a read error from the non-volatile memory 110 and a write error to the non-volatile memory 110 can occur. The frequency can be reduced.

(Seventh embodiment)
FIG. 20 is a flowchart of data read processing from the nonvolatile memory 100 in response to a read request from the host device 2 of the memory system according to the seventh embodiment. FIG.
In FIG. 0, the same parts as those in FIG. In the description of this embodiment,
For the same configuration and operation as in the first embodiment, a duplicate description is omitted. The external appearance and configuration of the memory system 1 in the present embodiment are the same as those in FIGS.

In the memory system according to the present embodiment, unlike the memory system according to the first embodiment, the control unit 220 of the memory controller 200 uses which physical address of which memory chip 110 to process a read request from the host device 2. After the process of solving whether to access (step 802), without acquiring the temperature of the memory controller 200,
Based on the temperature of the memory chip 110, data reading processing or temperature rising processing from the memory chip 110 is executed.

The control unit 220 of the memory controller 200 converts a logical address, which is an address specified by the read request, into a physical address, and accesses which physical address of which memory chip 110 to process the read request from the host device 2. This is resolved (step 802).

In the present embodiment, as in the first embodiment, the memory chip 110 that is the access destination for the logical address specified by the read request from the host device 2 is described as the memory chip 110-1.

Read memory chip temperature information from the memory chip 110-1 to be accessed
/ F250 is instructed, and the memory chip temperature information is acquired from the memory chip 110-1 via the memory I / F250 (step 805).

Thereafter, the control unit 220 of the memory controller 200 determines whether or not the temperature of the memory chip 110-1 is higher than a predetermined twelfth temperature (step 2001). Predetermined 12th
The temperature may be the same as the predetermined second temperature or a different temperature.

When the temperature of the memory chip 110-1 is not higher than the predetermined twelfth temperature (step 80)
4: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 803, and the temperature of the memory chip 110-1 is again measured by the temperature sensor I / F.
It is acquired via 260 (step 805).

When the temperature of the memory chip 110-1 is higher than the predetermined twelfth temperature (step 2001)
: Yes), the memory controller 200 sends the memory chip 11 via the memory I / F 250.
Data is read from 0-1 (step 808), and thereafter the same processing as that of the memory system according to the first embodiment is executed.

FIG. 21 is a flowchart of a process of writing data to the nonvolatile memory 100 in response to a write request from the host device 2 of the memory system according to the seventh embodiment. This flowchart shows processing for receiving a data write request from the host device 2, writing data designated by the write request to the nonvolatile memory 100, and transmitting the write result to the host device 2. In FIG. 21, the same components as those in FIG. 10 are denoted by the same reference numerals.

In the memory system according to the present embodiment, unlike the memory system according to the first embodiment, the control unit 220 of the memory controller 200 encodes the user data to be written specified by the write request (step 802). Without acquiring the temperature of the memory controller 200, the data writing process or the temperature raising process to the memory chip 110 is executed based on the temperature of the memory chip 110.

When receiving a write request from the host device 2 (step 1001), the control unit 220 of the memory controller 200 determines a physical address corresponding to the logical address specified by the write request, and transfers the determined physical address to the address conversion table. Reflect (Step 1
002). Then, the control unit 220 of the memory controller 200 instructs the encoding circuit 241 to encode the user data to be written designated by the write request, and the encoding circuit 24.
1 encodes user data to be written (step 1003).

In the present embodiment, the memory chip 110 corresponding to the physical address determined with respect to the logical address specified by the write request from the host 2 will be described as the memory chip 110-1.

Next, the control unit 220 of the memory controller 200 accesses the memory chip 110 to be accessed.
-1 is instructed to the memory I / F 250 to read out the memory chip temperature information from the memory I / F.
Memory chip temperature information is acquired from the memory chip 110-1 via 250 (step 805).

Thereafter, the control unit 220 of the memory controller 200 determines whether or not the temperature of the memory chip 110-1 is higher than a predetermined thirteenth temperature (step 1801). Predetermined thirteenth
The temperature may be the same as the predetermined fourth temperature or a different temperature.

When the temperature of the memory chip 110-1 is not higher than the predetermined thirteenth temperature (step 18)
01: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 805, and the temperature of the memory chip 110-1 is set again to the memory I / F 25.
Obtained via 0 (step 805).

When the temperature of the memory chip 110-1 is higher than a predetermined thirteenth temperature (step 2101)
: Yes), the memory controller 200 writes the encoded data to the memory chip 110-1 (step 1006), and thereafter executes the same processing as the memory system according to the first embodiment.

FIG. 22 is a flowchart of a modification example of a process of writing data to the nonvolatile memory 100 in response to a write request from the host device 2 of the memory system according to the seventh embodiment. This flowchart shows processing for receiving a data write request from the host device 2, writing user data specified by the write request to the nonvolatile memory 100, and transmitting the write result to the host device 2. 22, the same parts as those in FIGS. 10, 11, and 21 are denoted by the same reference numerals.

In the memory system according to this modification, when the temperature of the memory chip 110-1 is not higher than the predetermined thirteenth temperature (step 2101: No), the control unit 220 of the memory controller 200 does not perform the temperature increasing process. And the temperature of the memory chip 110-2,..., The memory chip 110-N, which is a memory chip 110 different from the memory chip 110-1, is acquired (step 1101).

And the control part 220 of the memory controller 200 is the memory chip 110-2, ...
It is determined whether there is a memory chip whose temperature is higher than a predetermined thirteenth temperature among the memory chips 110-N (step 2201).

When there is no memory chip whose temperature is higher than the predetermined thirteenth temperature (step 220)
1: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807), returns to step 805, and again sets the temperature of the memory chip 110-1 to the memory I / O.
Obtained via F250 (step 805).

When there is a memory chip whose temperature is higher than a predetermined thirteenth temperature (step 2201)
: Yes), the controller 220 of the memory controller 200 changes the physical address corresponding to the logical address specified in the write request, and reflects the changed physical address in the address conversion table (step 1103).

In this modification, the memory chip 110 corresponding to the changed physical address is the memory chip 1.
10-2, that is, among the memory chips 110-2,..., The memory chip 110-2 is a memory chip 110 whose temperature is higher than a predetermined thirteenth temperature. This will be described assuming that there is.

When the controller 220 of the memory controller 200 reflects the changed physical address in the address conversion table (step 1103), the changed physical address is stored in the memory chip 11.
The address conversion table is changed so that the physical address corresponds to 0-2.

The control unit 220 of the memory controller 200 reflects the changed physical address in the address conversion table (step 1103), and then instructs the memory I / F 250 to write the encoded data to the memory chip 110-2. Then, data is written to the memory chip 110-2 via the memory I / F 250 (step 1006).

Next, the memory controller 200 transmits the data write result to the memory chip 110-2 to the host device 2 via the host I / F 210 (step 1007).

On the other hand, when the temperature of the memory chip 110-1 is higher than the predetermined thirteenth temperature (step 2101: Yes), the memory controller 200 transmits the encoded data to the memory chip 110-1 via the memory I / F 250. After writing (step 1006), processing similar to that of the memory system according to the first embodiment is executed.

In this modification, the physical address corresponding to the logical address designated by the write request of the host device 2 is determined before acquiring the memory chip temperature information (step 1002).
Instead of determining the physical address corresponding to the logical address specified in the write request before acquiring the memory chip temperature information, acquire the memory chip temperature information and write request based on the acquired memory chip temperature information The physical address corresponding to the logical address specified in (1) may be determined.

That is, in this modification, the memory chips 110-1,.
Memory chip temperature information is obtained, and when the temperature of the memory chip 110-1 is not higher than the predetermined thirteenth temperature, but the temperature of the memory chip 110-2 is higher than the predetermined thirteenth temperature, the memory chip 110-2 may be determined as the data write destination memory chip 110, and the physical address corresponding to the memory chip 110-2 may be reflected in the address conversion table.

FIG. 23 is a flowchart of the erasing process of a predetermined block in the nonvolatile memory 100 of the memory system according to the seventh embodiment. The flowchart of FIG. 23 will be described from the stage when the memory controller 200 has decided to erase a predetermined block of the nonvolatile memory 100. In FIG. 23, the same components as those in FIG.

In the present embodiment, description will be made assuming that the memory chip 110 including a predetermined block to be erased is the memory chip 110-1.

In the memory system according to the present embodiment, unlike the memory system according to the first embodiment, the memory controller 200 does not acquire the temperature of the memory controller 200,
Based on the temperature of the memory chip 110, an erasing process or a temperature raising process for a predetermined block of the memory chip 110 is executed.

The control unit 220 of the memory controller 200 acquires the temperature of the memory chip 110-1 via the memory I / F 250 (step 805).

Thereafter, the controller 220 of the memory controller 200 determines whether or not the temperature of the memory controller 200 is higher than a predetermined fourteenth temperature (step 2301). Predetermined first
The temperature of 4 may be the same as the predetermined sixth temperature or may be a different temperature.

When the temperature of the memory chip 110-1 is not higher than the predetermined 14th temperature (step 23)
01: No), the controller 220 of the memory controller 200 executes a temperature raising process (step 807).

The control unit 220 of the memory controller 200 executes the temperature raising process (step 807).
Thereafter, the process returns to step 805, and the temperature of the memory chip 110-1 is set again to the memory I / F 25.
Obtained via 0 (step 805).

When the temperature of the memory controller 200 is higher than the predetermined 14th temperature (step 230)
1: Yes), the control unit 220 of the memory controller 200 instructs the memory I / F 250 to erase a predetermined block (step 1203).

According to the seventh embodiment described above, in the memory system 1, as in the first embodiment, even if the nonvolatile memory 110 is vulnerable to low-temperature operation, the stress of the memory cells of the nonvolatile memory 110 is reduced. The reliability of data stored in the non-volatile memory 110 and data read from the non-volatile memory 110 can be improved, and a read error from the non-volatile memory 110 and a write error to the non-volatile memory 110 can occur. The frequency can be reduced.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof as well as included in the scope and gist of the invention.

DESCRIPTION OF SYMBOLS 1 ... Memory system 2 ... Host apparatus 3 ... System 4 ... Connector 100 ... Non-volatile memory 110 ... Memory chip 200 ... Memory controller 210 ... Host I / F
220 ... Control unit 230 ... Data buffer 240 ... Encoding / decoding unit 250 ... Memory I / F
260 ... Temperature sensor I / F
270 ... Internal bus 300 ... Temperature sensor 400 ... Board

Claims (10)

A non-volatile memory having a plurality of memory chips;
A controller for controlling the nonvolatile memory;
With
The controller is
A memory system that accesses the first memory chip when a temperature of the controller is higher than a first temperature or when a temperature of a first memory chip is higher than a second temperature among the plurality of memory chips. The controller has a temperature of the controller not higher than the first temperature; and
The memory system according to claim 1, wherein when the temperature of the first memory chip is not higher than the second temperature, a temperature raising process is executed. After the controller performs the temperature raising process, the controller temperature is the first temperature.
3. The memory system according to claim 1, wherein the first memory chip is accessed when the temperature of the first memory chip becomes higher than the second temperature or when the temperature of the first memory chip becomes higher than the second temperature. . 4. The memory system according to claim 1, wherein the access is a data read process from the first memory chip based on a read request received from a host device. 5. The controller includes an ECC circuit for encoding or decoding data,
The memory system according to claim 2, wherein the temperature raising process is to drive the ECC circuit. The ECC circuit includes an encoding circuit for encoding data;
The memory system according to claim 5, wherein the controller drives the ECC circuit by causing the encoding circuit to encode dummy data. The ECC circuit includes a decoding circuit for decoding the encoded data,
The controller causes the decoding circuit to decode the dummy data, thereby causing the EC to
The memory system according to claim 5, wherein the C circuit is driven. The controller encodes the data specified by the write request received from the host device by the encoding circuit,
The memory system according to claim 6, wherein the access is a process of writing the encoded data. The controller has a temperature of the controller not higher than the first temperature; and
When the temperature of the first memory chip is not higher than the second temperature, a second memory chip different from the first memory chip is determined as a memory chip that stores data specified by the write request. The memory system according to claim 8, wherein the encoded data is written to the second memory chip when the temperature of the second memory chip is higher than the second temperature. 4. The memory system according to claim 1, wherein the access is an erasing process of a block included in the first memory chip. 5.

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