JP7079927B2 - Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device - Google Patents

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Silicon carbide (SiC) semiconductors have a higher potential for insulation breakdown and lower on-resistance than conventional semiconductors using silicon (Si), and are therefore being developed as materials for next-generation semiconductor devices. There is. The p-type silicon carbide semiconductor device is expected to be used in an ultrahigh withstand voltage region, particularly by an IGBT (Insulated Gate Bipolar Transistor), a PiN (P-intrinsic-N diode) diode, or the like. Since the on-resistance of the semiconductor device is the sum of the resistance values, in order to reduce the on-resistance of the semiconductor device, the electrode should have a sufficiently low resistance ohmic connection with the SiC layer to lower the contact resistance than the SiC layer. Is required.

As a method of ohmic connection on the p-type SiC semiconductor layer, an aluminum (Al) -titanium (Ti) alloy layer (for example, see Non-Patent Document 1 below), a Ti layer, and an Al layer are formed on the p-type SiC semiconductor layer. Many methods of depositing in order and heat-treating at a high temperature of about 1000 ° C. have been reported.

Further, in Non-Patent Document 2 below, it is stated that p-type ohmic contacts cannot be obtained when the atomic composition ratio of the Al layer is less than 75 atomic% with respect to the total thickness of the Ti layer and the Al layer. In the reported example, an electrode forming condition was used in which the atomic composition ratio of the Al layer was more than 75 atomic% with respect to the total thickness of the Ti layer and the Al layer (see, for example, Non-Patent Documents 2 to 6 below). ..

Further, in the following Non-Patent Document 2, Non-Patent Document 3, and Non-Patent Document 4, the Al—Ti alloy layer, the Ti layer, and the Al layer react with the p-type SiC semiconductor layer to cause an interface layer (Ti ₃ SiC ₂ ). ) Is generated, and it is reported that this interface layer affects the ohmic properties.

Further, Patent Document 1 below describes that the Al ₃ Ti and the SiC layer react to form the Ti ₃ SiC ₂ layer, and in order to efficiently generate the interface layer (Ti ₃ SiC ₂ ), the interface layer (Ti 3 SiC 2) is formed. Heat treatment is performed at a temperature higher than the first reference temperature (686 ° C.) and lower than the second reference temperature (970 ° C.) to generate Al ₃ Ti at the interface, and then heat treatment is performed at a temperature higher than the second reference temperature (970 ° C.). The method of forming the interface layer (Ti ₃ SiC ₂ ) is shown.

Further, in Patent Document 2 below, an Al—Ti alloy having less Ti than Al in terms of mass ratio, or an Al / Ti, Ti / Al laminated structure is deposited on a p-type SiC layer, and then an Al—Ti alloy or Al / A method is described in which a protective film for preventing the evaporation and scattering of Al from the Ti laminated structure is formed, and then heat treatment is performed at a temperature exceeding the melting point of Al and alloyed to form an ohmic contact.

Japanese Unexamined Patent Publication No. 2008-78435 Japanese Unexamined Patent Publication No. 2012-99752

J. Crofton et al. "Finding the option Al-Ti alloy compatibility for us as an ohmic contact to p-type SiC" Solid-State Electronics 46 (2002) 109-113 O. Nakatska et al., "Low Response TiAl Ohmic Contacts with Multi-Layered Structurefor p-Type 4H-SiC" Materials Transactions, Vol. 43, No. 7 (2002) pp. 1684 to 1688 S. Tsukimoto et al. "Correlation behind the Electrical Properties and the Interfacial Microstructures of TiAl-Based Ohmic Contacts to p-Type4H 33, No. 5,2004 B. J. Johnson et al., "Mechanism of ohmic behavior of Al / Ti contacts to p-type 4H-SiC after annealing" J. Apple. Phys. Vol. 95 (2004) 5616-5620. A Frazzetto et al. "Structural and transport projects inalloyed Ti / Al Ohmic contact's formed on p-type Al-implanted 4H-SiC annealed against" Phys. D: Appl. Phys. 44 (2011) 255302 S. Tanimoto et al. "Ohmic Contact Structure and Fabrication Process Applicable to Practical SiC Devices Material" Material Science Forum Vols. 389-393 (2002) pp879-884 T. Abi-Tannous et al. "A Study on the Temperature of Ohmic Contact to p-Type SiC Based on Ti3SiC2 Phase" IEEE TRANSACTIONS ON ELECTRONDE. 63, NO. 6, JUNE2016 M. Maeda et al. "FORMATION OF Ti3SiC2 ON SiC BY CONTROLL OFINTERVACIAL REACTION BETWEEEN SiC AND Ti / Al MULTILAYER" Preprints of the System 82, pp. 224-225

As described above, by using an Al—Ti-based metal material, it is possible to form a low-resistance ohmic contact with the p-type SiC semiconductor layer, but conventional Al—Ti-based electrodes are non-patent documents. As described in No. 3, there is a problem that Al volatilizes during high temperature heat treatment and the surface of the electrode becomes rough. When considering application to a surface p-type electrode such as a PiN diode, this problem may cause a focus abnormality in the exposure process in the subsequent process, and in the mounting process on a module or the like, the wire bonding adheres closely. There was a risk of causing poor sex. When considering application to a back surface p-type electrode such as an n-type IGBT, there is a possibility that a suction problem may occur during wafer transfer in an exposure process or the like, which may hinder process flow.

In order to obtain ohmic contact with an Al—Ti electrode, high temperature heat treatment of about 1000 ° C is required, but if the absolute amount of the Al layer is large, the contact resistivity can be a low resistance value, but the surface p type. When an Al—Ti electrode is applied to the electrode, the Al melt diffuses in the field oxide film separated by the temperature change during the rapid heat treatment during the high temperature heat treatment, and there is a risk that the wiring will be short-circuited between the pattern electrodes. There was also.

Here, FIG. 27 is a diagram showing a photograph of the results of forming an Al—Ti based electrode of a conventional example using an n-type silicon carbide bulk dummy substrate. When heat-treated at a high temperature of 950 ° C. or higher using the Al—Ti electrode forming conditions as in the conventional example, Al droplets (for example, granules in FIG. 27) which are considered to be caused by evaporation and scattering of Al as shown in FIG. 27. Projection A) was seen in the electrode. The height difference of the Al droplet portion is large, and if process flow is performed after forming a p-type back surface electrode for a SiC wafer using such electrode conditions, adsorption problems will occur during wafer transfer, which will hinder process flow. It turned out to occur.

In the present invention, in order to solve the problems caused by the above-mentioned conventional technique, it is possible to achieve both low resistance ohmic contact resistance between the electrode and the p-type SiC layer, which cannot be realized by the conventional example, and suppression of surface roughness of the electrode. It is an object of the present invention to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. The silicon carbide semiconductor device is a first conductive type silicon carbide substrate and a second conductive type silicon carbide semiconductor provided on the main surface side of the silicon carbide substrate or on the side opposite to the main surface of the silicon carbide substrate. A layer and a second conductive type ohmic contact electrode arranged in contact with the silicon carbide semiconductor layer are provided. The ohmic contact electrode has a layer containing titanium and aluminum having a thickness of 20 nm or more and 150 nm or less, and the content of aluminum is between 50 atomic% and 75 atomic% with respect to the entire layer containing titanium and aluminum. be. The diameter of the main average particles in the 20 μm × 20 μm region of the aluminum-titanium alloy silicide constituting the ohmic contact electrode is 0.5 μm or more and 1.3 μm or less, and the height is 10 nm or more and 80 nm or less.

Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the root mean square roughness value of the entire 20 μm × 20 μm region of the ohmic contact electrode is 50 nm or less.

Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the maximum height difference with respect to the average surface of the entire 20 μm × 20 μm region of the ohmic contact electrode is 400 nm or less.

Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, a Ti ₃ SiC ₂ layer is formed at the interface between the silicon carbide semiconductor layer and the ohmic contact electrode.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, the first step of forming the second conductive type silicon carbide semiconductor layer on the main surface side of the first conductive type silicon carbide substrate or on the side opposite to the main surface of the silicon carbide substrate is performed. Next, a second step of forming a second conductive type ohmic contact electrode arranged in contact with the silicon carbide semiconductor layer is performed. In the second step, the layer containing titanium and aluminum in the ohmic contact electrode is 20 nm or more and 150 nm or less, and the content of aluminum is 50 atomic% to 75 atomic% with respect to the entire layer containing titanium and aluminum. The diameter of the main average particles in the 20 μm × 20 μm region of the aluminum-titanium alloy silicide formed between the two and constituting the ohmic contact electrode is 0.5 μm or more and 1.3 μm or less and the height is 10 nm or more and 80 nm or less. Form .

According to the above-mentioned invention, the film thickness or the content of the Al layer is reduced with respect to the Ti layer, and the total total film thickness of the Ti layer and the Al layer is thinned. Specifically, the layer containing Ti and Al is 20 nm or more and 150 nm or less, and the Al content of the Al layer is 50 atomic% to 75 atomic% with respect to the entire Ti layer and Al layer. As a result, the surface roughness of the electrode during heat treatment is suppressed, so when considering application to the p-type ohmic electrode on the front surface, the module does not cause focus abnormality in the subsequent exposure process. In the process of mounting on the or the like, it is possible to eliminate the possibility of causing poor adhesion of wire bonding. When considering the application to the p-type ohmic electrode on the back surface, it is possible to avoid the adsorption trouble at the time of wafer transfer in the exposure process and the like, and to eliminate the hindrance to the process flow.

According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, low resistance ohmic contact resistance between the electrode and the p-type SiC layer, which cannot be realized by the conventional example, and suppression of surface roughness of the electrode are achieved. It has the effect of being able to achieve both.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 4). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 5). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 4). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 5). It is a top view which shows the structure of the silicon carbide semiconductor device which concerns on Embodiments 1 and 2. It is a graph which shows the contact resistance by the impurity concentration of the p-type silicon carbide ion implantation layer with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a graph which shows the surface roughness with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a graph which shows the contact resistance by the impurity concentration of the p-type silicon carbide ion implantation layer with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is a graph which shows the surface roughness with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device which concerns on Embodiment 2. It is a graph which shows the contact resistance by the impurity concentration of the p-type silicon carbide ion implantation layer with respect to the Ti film thickness in the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a graph which shows the contact resistance according to the impurity concentration of the p-type silicon carbide ion implantation layer with respect to the Ti film thickness in the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is a graph which shows the surface roughness with respect to the Ti film thickness in the silicon carbide semiconductor device which concerns on Embodiment 1 and Embodiment 2. It is a table which shows the comparison result of the silicon carbide semiconductor device which concerns on Embodiment 1 and the silicon carbide semiconductor device by the prior art. It is a table which shows the comparison result of the silicon carbide semiconductor device which concerns on Embodiment 2 and the silicon carbide semiconductor device by the prior art. It is a figure which shows the atomic force microscope photograph of the Si surface of the silicon carbide semiconductor device of the comparative example 1-1. It is a graph which shows the profile of the surface roughness depth of the Si surface of the silicon carbide semiconductor device of the comparative example 1-1 (the 1). It is a figure which shows the atomic force microscope photograph of the surface of the silicon carbide semiconductor device of Embodiment 1. FIG. It is a graph which shows the profile of the surface roughness depth of the silicon carbide semiconductor device of Embodiment 1 (the 1). It is a figure which shows the atomic force microscope photograph of the C plane of the silicon carbide semiconductor device of the comparative example 1-1. It is a graph which shows the profile of the surface roughness depth of the C surface of the silicon carbide semiconductor device of the comparative example 1-1 (the 1). It is a figure which shows the atomic force microscope photograph of the surface of the silicon carbide semiconductor device of Embodiment 2. It is a graph which shows the profile of the surface roughness depth of the silicon carbide semiconductor device of Embodiment 2 (the 1). It is a figure which shows the photograph of the Al—Ti system electrode formation result of the conventional example using the n-type silicon carbide bulk dummy substrate. It is a figure which shows the photograph of the surface morphology observation experiment result of the Ti / Al layer using a silicon wafer.

Hereinafter, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the concentration of impurities is higher and the concentration of impurities is lower than that of the layer or region to which it is not attached, respectively. When the notations of n and p including + and-are the same, it indicates that the concentrations are close to each other, and the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

Here, FIG. 28 is a diagram showing photographs of the surface morphology observation experiment results of the Ti / Al layer using a silicon wafer. In FIG. 28, the inventor fixed the ratio of the Al layer to the Ti layer to 1: 4 with respect to the back surface of the silicon wafer to reduce the thickness of the Ti layer and change the total total thickness of the Ti layer and the Al layer. This is the result of an experiment in which the electrode surface was formed and observed after heat treatment at 1000 ° C. As shown in FIG. 28, it was found that the particle size of the Al droplet decreased as the thickness of the Ti layer decreased and the total film thickness of the Ti layer and the Al layer decreased.

When a transfer test was carried out with an exposure apparatus using Si wafers produced under these conditions, no transfer trouble occurred under the condition that the Ti layer thickness was 40 nm or less. Based on this result, a similar experiment was performed on a SiC wafer. By reducing the thickness of the Ti layer and reducing the total film thickness of the Ti layer and the Al layer, the particle size of the Al droplets could be reduced, and the surface morphology was improved. It turned out that it could be improved.

Based on the results of this experiment, the inventor further conducted an experiment with the silicon carbide semiconductor device of the following embodiments 1 and 2, and found a p-type ohmic electrode forming condition capable of achieving both low resistance ohmic contact and surface morphology. rice field.

Therefore, the inventor has made the Si surface (main surface, front surface) and C surface (opposite to the main surface) of the p-type SiC semiconductor layer under the condition that the total total thickness of the Ti layer and the Al layer is thinned. An experiment was conducted to evaluate the contact resistivity and surface morphology with respect to the side surface and the back surface). The silicon carbide semiconductor device according to the first embodiment below is a silicon carbide semiconductor device having both ohmic contact and surface morphology in which the Si surface of the p-type SiC semiconductor layer has low resistance, and the silicon carbide semiconductor according to the second embodiment. The device is a silicon carbide semiconductor device capable of achieving both ohmic contact and surface morphology in which the C surface of the p-type SiC semiconductor layer has low resistance.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 1, in the silicon carbide semiconductor device according to the first embodiment, an n-type Si surface 4H-SiC epitaxial layer 2 is formed on an n-type 4H-SiC (four-layer periodic hexagonal silicon carbide) substrate 1. , It has a p-type SiC ion injection layer 3 inside. Although only one type of p-type SiC ion-implanted layer 3 is shown in FIG. 1, it actually has four types of p-type SiC ion-implanted layer 3 as described later. A thermal oxide film 4 and a field oxide film 5 are formed on the p-type SiC ion implantation layer 3, and a p-type ohmic electrode 6 is formed at the openings of the thermal oxide film 4 and the field oxide film 5. An Al wiring electrode 7 is formed on the p-type ohmic electrode 6.

(Manufacturing method of silicon carbide semiconductor device according to the first embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. 2 to 6 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. First, an n-type 4H-SiC substrate 1 is prepared, and an n-type Si surface 4H having an ND-NA: 1.0 × 10 ¹⁶ cm ^-3 and a thickness of 10 μm is used on the n-type _{4H -} SiC substrate 1 by a CVD (Chemical Vapor Deposition) method. -The SiC epitaxial layer 2 is formed. Further, N _{D -} NA indicates the difference between the donor concentration and the acceptor concentration in the semiconductor layer. Here, the structure is as shown in FIG.

Next, although not shown for simplification, an alignment mark for alignment is formed on the n-type Si surface 4H-SiC epitaxial layer 2 by photolithography and etching.

Next, an oxide film mask that selectively implants ions is formed on the n-type Si surface 4H-SiC epitaxial layer 2, and after opening by photolithography and etching, Al ions are implanted to a depth of about 0.3 μm. After implanting onto the n-type Si surface 4H-SiC epitaxial layer 2 under the condition of a temperature in the range of 200 to 600 ° C. to form the p-type SiC ion implantation layer 3, the oxide film mask is removed. In this Al ion injection step, the maximum impurity concentration of the p-type SiC ion injection layer 3 is 1.0 × 10 ¹⁹ cm ^-3 , 3.0 × 10 ¹⁹ cm ^-3 , 1.0 × 10 ²⁰ cm ^-3 , 3. It is repeated 4 times so as to have 4 conditions of 0.0 × 10 ²⁰ cm ^-3 . Here, the structure is as shown in FIG.

Next, after forming a C (carbon) cap for preventing surface roughness, activation annealing is performed under conditions in the range of 1500 to 1800 ° C. to electrically activate the p-type SiC ion implantation layer 3. .. After that, the C cap is removed.

Next, after performing thermal oxidation under the condition of an oxidation temperature in the range of 800 to 1400 ° C., a sacrificial oxidation step of removing this by etching with hydrogen fluoride (HF) acid is performed. Next, thermal oxidation is performed again under the condition that the oxidation temperature is in the range of 800 to 1400 ° C. to form the thermal oxide film 4. Here, the structure is as shown in FIG.

Next, the field oxide film 5 is formed by the CVD method. Here, the structure is as shown in FIG. Next, the thermal oxide film 4 and the field oxide film 5 are opened at predetermined positions by sputtering and etching using hydrofluoric acid, and the layer containing Ti and Al is 20 nm or more and 150 nm or less, and the Ti layer and the Al layer are formed. A layer containing Ti and Al is deposited by vapor deposition or sputtering so that the Al content of the Al layer is between 50 atomic% and 87 atomic% with respect to the whole, and the Al layer / Ti layer / p is deposited by the lift-off method. A laminated structure to be the type SiC ion injection layer 3 is formed.

Next, RTA treatment is performed at a temperature of 950 ° C. or higher using an RTA (Rapid Thermal annealing) device to alloy the p-type ion implantation layer 3, the Ti layer, and the Al layer to form a p-type ohmic electrode 6. Here, the structure is as shown in FIG.

Finally, Al is formed by sputtering under the condition of a thickness in the range of 400 nm to 3.0 μm to form an Al wiring electrode 7 for photolithography and etching measurement, and the silicon carbide semiconductor device shown in FIG. 1 is completed.

(Embodiment 2)
FIG. 7 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. As shown in FIG. 7, in the silicon carbide semiconductor device according to the second embodiment, the n-type C surface 4H-SiC epitaxial layer 8 is formed on the n-type 4H-SiC substrate 1, and the p-type C surface 4H is further formed on the n-type C surface 4H-SiC epitaxial layer 8. -A SiC epitaxial layer 9 is formed, and a p-type SiC ion injection layer 3 is provided therein. Although only one type of p-type SiC ion-implanted layer 3 is shown in FIG. 7, it actually has four types of p-type SiC ion-implanted layer 3 as described later. A thermal oxide film 4 and a field oxide film 5 are formed on the p-type SiC ion implantation layer 3, and a p-type ohmic electrode 6 is formed at the openings of the thermal oxide film 4 and the field oxide film 5. An Al wiring electrode 7 is formed on the p-type ohmic electrode 6.

(Manufacturing method of silicon carbide semiconductor device according to the second embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described. 8 to 12 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment. First, an n-type 4H-SiC substrate 1 is prepared, and then an n-type _C surface 4H _- SiC epitaxial layer 8 having an ND-NA: 1.0 × 10 ¹⁶ cm ^-3 and a thickness of 10 μm is prepared on the n-type 4H-SiC substrate 1 by a CVD method. After that, a p-type _C surface 4H-SiC epitaxial layer 9 having NA- _ND : 2.0 × 10 ¹⁷ cm ^-3 and a thickness of 8 μm is formed. Further, NA _{- ND} indicates the difference between the acceptor concentration and the donor concentration in the semiconductor layer. Here, the structure is as shown in FIG.

Next, although not shown for simplification, an alignment mark for alignment is formed on the p-type C surface 4H-SiC epitaxial layer 9 by photolithography and etching.

Next, an oxide film mask that selectively implants ions is formed on the p-type C surface 4H-SiC epitaxial layer 9, and after opening by photolithography and etching, Al ions are implanted to a depth of 0.3 μm and the implantation temperature. After implanting onto the p-type C surface 4H-SiC epitaxial layer 9 under the condition of 200 to 600 ° C. to form the p-type SiC ion implantation layer 3, the oxide film mask is removed. In this Al ion implantation process, the maximum concentration is 1.0 × 10 ¹⁹ cm ^-3 , 3.0 × 10 ¹⁹ cm ^-3 , 1.0 × 10 ²⁰ cm ^-3 , 3.0 × 10 ²⁰ cm ^-3 . It is repeated 4 times so as to be a condition. Here, the structure is as shown in FIG.

Next, after forming a C cap for preventing surface roughness, activation annealing is performed under conditions in the range of 1500 to 1800 ° C. to electrically activate the p-type SiC ion implantation layer 3. After that, the C cap is removed.

Next, after performing thermal oxidation under the condition of an oxidation temperature in the range of 800 to 1400 ° C., a sacrificial oxidation step of removing this by etching with hydrofluoric acid is performed. Next, thermal oxidation is performed again under the condition that the oxidation temperature is in the range of 800 to 1400 ° C. to form the thermal oxide film 4. Here, the structure is as shown in FIG.

Next, the field oxide film 5 is formed by the CVD method. Here, the structure is as shown in FIG. Next, the thermal oxide film 4 and the field oxide film 5 are opened at predetermined positions by photolithography and etching using hydrofluoric acid, and the layer containing Ti and Al is 20 nm or more and 150 nm or less, and the Ti layer and the Al layer are formed. A layer containing Ti and Al is deposited by vapor deposition or sputtering so that the Al content of the Al layer is between 50 atomic% and 87 atomic% with respect to the whole, and the Al layer / Ti layer / p is deposited by the lift-off method. A laminated structure to be the type SiC ion injection layer 3 is formed.

Next, RTA treatment is performed at a temperature of 950 ° C. or higher using an RTA apparatus to alloy the p-type ion implantation layer 3, the Ti layer, and the Al layer to form a p-type ohmic electrode 6. Here, the structure is as shown in FIG.

Finally, Al is formed by sputtering under the condition of a thickness in the range of 400 nm to 3.0 μm to form an Al wiring electrode 7 for photolithography and etching measurement, and the silicon carbide semiconductor device shown in FIG. 7 is completed.

The experimental results of the silicon carbide semiconductor device according to the first embodiment and the second embodiment are shown below. Here, FIG. 13 is a top view showing the structure of the silicon carbide semiconductor device according to the first and second embodiments. In the experiment, the contact resistivity was evaluated at room temperature using a CTLM (Circular Transmission Line Model) pattern with a radius r of 200 μm and an electrode spacing l of 7 μm, 10 μm, 15 μm, 20 μm, 25 μm, and 30 μm. , The contact resistivity was calculated from the voltage value at 0.1 V. In the following experimental results, the contact resistivity is plotted as the average value of the pattern measurement results at 3 to 4 points.

The surface morphology was evaluated by scanning a region of 20 μm × 20 μm using an atomic force microscope (AFM) and using a root mean square (RMS) value.

First, the result of the Si surface of the p-type SiC semiconductor layer is shown. FIG. 14 is a graph showing the contact resistance of the p-type silicon carbide ion-implanted layer according to the impurity concentration with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device according to the first embodiment. In FIG. 14, the vertical axis represents contact resistance, the unit is Ωcm ² , the horizontal axis represents the atomic composition ratio of the Al layer, and the unit is atomic% (at%). The atomic composition ratio of the Al layer is the content of aluminum in the p-type ohmic electrode 6. The unit of the impurity concentration of the p-type silicon carbide ion implantation layer 3 is cm ^-3 .

In FIG. 14, the atomic composition ratio of the Al layer to the total thickness of the Ti layer and the Al layer is between 50 atomic% and 87 atomic% in a state where the thickness of the Ti layer is reduced and the total thickness is thinned. It is an experimental result of the contact resistivity change for each p-type ion injection concentration when it was changed by, and it is an experimental result when the thickness of the Ti layer was fixed at 20 nm.

As shown in FIG. 14, under all p-type ion injection concentration conditions, the contact resistivity decreases as the atomic composition ratio of the Al layer decreases from 87 atomic%, and the atomic composition ratio of the Al layer is around 65 atomic%. The experimental results that the contact resistivity tends to have the minimum point were obtained. Although not shown in FIG. 14, the same tendency was obtained under other Ti film thickness conditions.

Next, the results of surface morphology are shown. FIG. 15 is a graph showing the surface roughness with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device according to the first embodiment. In FIG. 15, the vertical axis represents the surface roughness RMS, the unit is nm, the horizontal axis represents the atomic composition ratio of the Al layer, and the unit is atomic%.

FIG. 15 shows the experimental results of the surface roughness change at a p-type ion implantation concentration of 3.0 × 10 ²⁰ cm ^-3 in which the atomic composition ratio of the Al layer was changed between 50 atomic% and 87 atomic%. .. The AFM evaluation is performed after the electrical characteristic evaluation, and the Al wiring electrode 7 is removed in advance by etching before the AFM evaluation.

As shown in FIG. 15, the change in surface roughness when the thickness of the Ti layer was fixed at 20 nm was relatively stable at a ratio lower than 81 atomic% when the atomic composition ratio of the Al layer was lowered.

Next, the result of the C plane of the p-type SiC semiconductor layer is shown. FIG. 16 is a graph showing the contact resistance of the p-type silicon carbide ion-implanted layer according to the impurity concentration with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device according to the second embodiment. In FIG. 16, the vertical axis represents contact resistance, the unit is Ωcm ² , the horizontal axis represents the atomic composition ratio of the Al layer, and the unit is atomic%.

In FIG. 16, the atomic composition ratio of the Al layer to the total thickness of the Ti layer and the Al layer is between 50 atomic% and 87 atomic% in a state where the thickness of the Ti layer is reduced and the total thickness is thinned. It is an experimental result of the contact resistivity change for each p-type ion injection concentration when it was changed by, and it is an experimental result when the thickness of the Ti layer was fixed at 20 nm. Here, the alloying of the SiC layer, the Ti layer, and the Al layer was carried out at 1000 ° C. for 2 minutes under heat treatment conditions in an Ar (argon) atmosphere.

As shown in FIG. 16, unlike the experimental results of the Si surface, the dependence of the contact resistivity change on the C surface was small, but the experiment of the first embodiment under all the p-type ion injection concentration and the Ti film thickness condition. Similar to the results, experimental results were obtained in which the atomic composition ratio of the Al layer was around 65 atomic% and the contact resistivity tended to have a minimum point.

FIG. 17 is a graph showing the surface roughness with respect to the atomic composition ratio of the Al layer in the silicon carbide semiconductor device according to the second embodiment. In FIG. 17, the vertical axis represents the surface roughness RMS, the unit is nm, the horizontal axis represents the atomic composition ratio of the Al layer, and the unit is atomic%.

FIG. 17 shows the experimental results of the surface roughness change at a p-type ion implantation concentration of 3.0 × 10 ²⁰ cm ^-3 in which the atomic composition ratio of the Al layer was changed between 50 atomic% and 87 atomic%. .. The AFM evaluation is performed after the electrical characteristic evaluation, and the Al wiring electrode 7 is removed in advance by etching before the AFM evaluation.

As shown in FIG. 17, the surface roughness of the Ti layer when the thickness of the Ti layer was fixed at 20 nm became larger at 75 atomic% as the atomic composition ratio of the Al layer was lowered, and the surface became rough, but 70 atoms. A relatively flat value was obtained in the range of% to 75 atomic%.

Based on the above experimental results, in many of the reports of conventional examples, it is said that p-type ohmic contacts cannot be obtained unless the atomic composition ratio of the Al layer is 75 atomic% or more with respect to the total thickness of the Ti layer and the Al layer. However, if the thickness of the Ti layer is reduced and the total film thickness is reduced, the resistance is low even if the atomic composition ratio of the Al layer to the total film thickness of the Ti layer and the Al layer is not 75 atomic% or more. It has been newly revealed that p-type ohmic contacts can be obtained.

Therefore, as in the first embodiment or the second embodiment, the atomic composition of the Al layer is relative to the total film thickness of the Ti layer and the Al layer in a state where the thickness of the Ti layer is reduced and the total film thickness is thinned. If the p-type aluminum electrode forming conditions are selected when the ratio is between 50 atomic% and 75 atomic%, it is possible to achieve both low resistance resistivity and suppression of surface roughness.

Next, in order to see the influence of the total thickness of the Ti layer and the Al layer, the silicon carbide semiconductor device was manufactured by the methods of the first and second embodiments, and the total thickness of the Ti layer and the Al layer was relative to the total thickness of the Ti layer and the Al layer. The atomic composition ratio of the Al layer is fixed between 50 atomic% and 75 atomic%, and the Ti film thickness is increased to 10 nm, 20 nm, 50 nm, 80 nm, and 100 nm, and the total film thickness is increased to increase the contact resistivity and surface roughness. Was evaluated.

The contact resistivity was evaluated at room temperature using a CTLM pattern (see FIG. 13) having a radius r of 200 μm and an electrode spacing l of 7 μm, 10 μm, 15 μm, 20 μm, 25 μm, and 30 μm, and the contact resistivity was 0.1 V. It was calculated from the voltage value of. In the following experimental results, the contact resistivity is plotted as the average value of the pattern measurement results at four locations. The surface morphology was evaluated by scanning a region of 20 μm × 20 μm using an atomic force microscope and using a root mean square roughness value.

First, the result of the Si surface of the p-type SiC semiconductor layer is shown. FIG. 18 is a graph showing the contact resistance of the p-type silicon carbide ion-implanted layer for each impurity concentration with respect to the Ti film thickness in the silicon carbide semiconductor device according to the first embodiment. In FIG. 18, the vertical axis represents contact resistance, the unit is Ωcm ² , the horizontal axis represents Ti film thickness, and the unit is nm. The unit of the impurity concentration of the p-type silicon carbide ion implantation layer 3 is cm ^-3 .

FIG. 18 shows the experimental results of the contact resistivity change for each p-type ion implantation concentration when the Ti film thickness was changed. Here, in the silicon carbide semiconductor device according to the first embodiment, ohmic contact could not be obtained when the Ti layer film thickness was 80 nm and the Ti layer film thickness was 100 nm. The contact resistivity increased significantly below the Ti layer of 20 nm, and did not change much between the Ti layer of 20 nm and the Ti layer of 50 nm. This is because it is stated in Non-Patent Document 2 of the conventional example that p-type ohmic contact cannot be obtained when the atomic composition ratio of the Al layer is less than 75 atomic% with respect to the total thickness of the Ti layer and the Al layer. It is consistent. The total film thickness used in Non-Patent Document 2 is 300 to 350 nm. Considering the experimental results of Examples 1 and 2, the atomic composition of the Al layer is obtained only when the total film thickness is reduced and the layer is thinned to some extent. It was suggested that p-type ohmic contacts with low resistance can be obtained even when the ratio is less than 75 atomic%.

Next, the result of the C plane of the p-type SiC semiconductor layer is shown. FIG. 19 is a graph showing the contact resistance of the p-type silicon carbide ion-implanted layer for each impurity concentration with respect to the Ti film thickness in the silicon carbide semiconductor device according to the second embodiment. In FIG. 19, the vertical axis represents contact resistance, the unit is Ωcm ² , the horizontal axis represents Ti film thickness, and the unit is nm.

FIG. 19 shows the experimental results of the contact resistivity change for each p-type ion implantation concentration when the Ti film thickness was changed. Here, in the silicon carbide semiconductor device according to the second embodiment, when the Ti layer thickness is 80 nm and the Ti layer thickness is 100 nm, the p-type ion implantation concentration is 1.0 × 10 ¹⁹ cm ^-3 , 3.0 × 10 ¹⁹ . Ohmic contact was not obtained with cm ^-3 . The contact resistivity also increased after the Ti film thickness was 20 nm.

Next, the results of surface morphology are shown. FIG. 20 is a graph showing the surface roughness with respect to the Ti film thickness in the silicon carbide semiconductor device according to the first embodiment and the second embodiment. In FIG. 20, the vertical axis indicates the surface roughness RMS, the unit is nm, the horizontal axis indicates the Ti film thickness, and the unit is nm.

FIG. 20 shows the experimental results of the surface roughness change when the p-type ion implantation concentration is 3.0 × 10 ²⁰ cm ^-3 when the Ti film thickness is changed. From FIG. 20, the surface roughness of the silicon carbide semiconductor device according to the first embodiment increased with a Ti film thickness of 20 nm as a boundary, and a slight decreasing tendency was observed from the Ti layer of 50 nm to the Ti layer of 100 nm. On the other hand, in the silicon carbide semiconductor device according to the second embodiment, the surface roughness decreased in proportion to the increase in the film thickness of the Ti layer, and the surface roughness of the Ti layer of 50 nm or more was about the same.

Summarizing the above experimental results, it can be said that low resistance p-type ohmic contact can be obtained even under the condition that the atomic composition ratio of the Al layer is less than 75 atomic% only when the total film thickness is reduced and the layer is thinned to some extent. It was suggested. Therefore, when the total maximum total film thickness of the Ti layer and the Al layer is set to about 150 nm or less as in the first embodiment or the second embodiment, low resistance resistivity and suppression of surface roughness can be achieved at the same time. it is conceivable that.

Hereinafter, as a comparative example with respect to the first embodiment and the second embodiment of the present invention, the Si surface is carbonized on the surface using the p-type ohmic electrode forming conditions of Non-Patent Document 3, Non-Patent Document 5, and Non-Patent Document 6. A silicon semiconductor device and a silicon carbide semiconductor device having a C surface surface were manufactured, and the contact resistance and surface roughness were evaluated.

FIG. 21 is a table showing the results of comparison between the silicon carbide semiconductor device according to the first embodiment and the silicon carbide semiconductor device according to the prior art. FIG. 22 is a table showing the results of comparison between the silicon carbide semiconductor device according to the second embodiment and the silicon carbide semiconductor device according to the prior art. In FIGS. 21 and 22, the surface roughness was evaluated by scanning a region of 20 μm × 20 μm and using a root mean square roughness value. The maximum height difference is the maximum height difference with respect to the average surface in the entire 20 μm × 20 μm region, the particle average diameter is the average of the diameters of the entire particles in the 20 μm × 20 μm region, and the particle average height is 20 μm. It is the average of the heights of the whole particles in the × 20 μm region.

Under the conditions of Comparative Example 1-1 (Non-Patent Document 3), ohmic characteristics were shown under all p-type ion implantation concentration conditions. As shown in FIG. 21, in the silicon carbide semiconductor device having a Si surface surface, the contact resistivity did not decrease uniformly in proportion to the p-type ion injection concentration, probably because the contact resistivity varied with respect to the p-type ion injection concentration condition. However, the contact resistivity was as low as 1.8 × 10 ^-5 to 3.1 × 10 ^-4 Ωcm ² . On the other hand, the surface roughness was as large as 123 nm and the surface was rough.

On the other hand, in the silicon carbide semiconductor device whose C surface is the surface, the electrode spacing of 7 μm and 10 μm is excluded from the calculation of contact resistivity because the electrode pattern diffuses in the field oxide film of the Al melt after the heat treatment and the electrode patterns are short-circuited. , 15 μm, 20 μm, 25 μm, 30 μm. As shown in FIG. 22, in the silicon carbide semiconductor device having the C surface surface, the contact resistivity uniformly decreases in proportion to the p-type ion injection concentration with respect to the p-type ion injection concentration condition, and the p-type ion injection concentration. At 3.0 × 10 ²⁰ cm ^-3 , the minimum contact resistivity was 1.4 × 10 ^-4 Ω cm ² . The surface roughness was 38.6 nm, which was rather large.

Under the conditions of Comparative Example 1-2 (Non-Patent Document 5), all the silicon carbide semiconductor devices having the Si surface surface have non-ohmic characteristics, and the p-type ion injection concentration even in the silicon carbide semiconductor devices having the C surface surface 1. Under the conditions of 0 × 10 ¹⁹ cm ^-3 and 3.0 × 10 ¹⁹ cm ^-3 , where the p-type ion injection concentration was slightly low, all had non-ohmic characteristics, and no ohmic characteristics could be obtained. The surface roughness was relatively good at 20.0 nm in the silicon carbide semiconductor device having the Si surface on the surface and 13.6 nm in the silicon carbide semiconductor device having the C surface on the surface.

Under the conditions of Comparative Example 1-3 (Non-Patent Document 6), the electrode patterns separated by the field oxide film after the heat treatment diffused in the field oxide film of the Al melt, short-circuited between the electrode patterns, and all the contact resistivityes. Could not be calculated. Further, the surface roughness was 79.0 nm in the silicon carbide semiconductor device having the Si surface as the surface, and 215.0 nm in the silicon carbide semiconductor device having the C surface as the surface, and the surface was rough.

On the other hand, under the conditions of the present invention, ohmic characteristics were exhibited under all p-type ion implantation concentration conditions. As shown in FIG. 21, in the first embodiment in which the Si surface is the surface, the contact resistivity uniformly decreases in proportion to the p-type ion implantation concentration with respect to the p-type ion implantation concentration condition, and the p-type ion implantation. When the concentration was 3.0 × 10 ²⁰ cm ^-3 , the minimum contact resistivity was 2.2 × 10 ^-5 Ω cm ² . The surface roughness was 17.9 nm, which was relatively good. As shown in FIG. 22, even in the second embodiment where the C surface is the surface, the contact resistivity uniformly decreases in proportion to the p-type ion injection concentration with respect to the p-type ion injection concentration condition, and the p-type ion injection. When the concentration was 3.0 × 10 ²⁰ cm ^-3 , the minimum contact resistivity was 3.7 × 10 ^-4 Ω cm ² . The surface roughness was relatively good at 20.0 nm. Further, the average diameter of the particles is not so different between the comparative example and the present invention, but in the average height of the particles of the present invention, the Si surface is 30.5 nm in the first embodiment and the C surface is the surface. In Form 2, a small value of 40.0 nm was obtained as compared with the comparative example. Further, the maximum height difference of the present invention was as small as 400 nm or less.

Here, FIG. 23A is a diagram showing an atomic force micrograph of the Si surface of the silicon carbide semiconductor device of Comparative Example 1-1. FIG. 23B is a graph showing the profile of the surface roughness depth of the Si surface of the silicon carbide semiconductor device of Comparative Example 1-1. Further, FIG. 24A is a diagram showing an atomic force micrograph of the surface of the silicon carbide semiconductor device of the first embodiment. FIG. 24B is a graph showing a profile of the surface roughness depth of the silicon carbide semiconductor device of the first embodiment.

Further, FIG. 25A is a diagram showing an atomic force microscope photograph of the C surface of the silicon carbide semiconductor device of Comparative Example 1-1. FIG. 25B is a graph showing the profile of the surface roughness depth of the C surface of the silicon carbide semiconductor device of Comparative Example 1-1. Further, FIG. 26A is a diagram showing an atomic force microscope photograph of the surface of the silicon carbide semiconductor device of the second embodiment. FIG. 26B is a graph showing a profile of the surface roughness depth of the silicon carbide semiconductor device of the second embodiment. Further, in FIGS. 23A, 24A, 25A, and 26A, the height difference on the surface of the silicon carbide semiconductor device is shown between the crosses of the white lines.

In FIGS. 23B, 24B, 25B, and 26B, the vertical axis indicates the height difference of the surface of the silicon carbide semiconductor device, the unit is nm, the horizontal axis indicates the position of the surface, and the unit is μm. .. The 0 position on the vertical axis indicates the average plane.

23A to 26B show the surface roughness depth profile when the p-type ion implantation concentration is 3.0 × 10 ²⁰ cm ^-3 . From FIGS. 23A to 26B, it can be confirmed that the surface roughness of the present invention is flatter than that of Comparative Example 1-1. From the above, under the conditions of the present invention, ohmic characteristics can be stably obtained without short-circuiting between patterns, contact resistivity of the same level as in the conventional example can be obtained, and surface roughness is suppressed to about 20.0 nm, which is relatively good. It was confirmed that it could be done.

As described above, according to the silicon carbide semiconductor device according to the first embodiment and the second embodiment, the film thickness or the content of the Al layer is reduced with respect to the Ti layer, and the total of the Ti layer and the Al layer is reduced. The total film thickness is thinned. Specifically, the thickness of the layer containing Ti and Al is 20 nm or more and 150 nm or less, and the Al content of the Al layer is 50 atomic% to 75 atomic% with respect to the entire Ti layer and Al layer. As a result, the surface roughness of the electrode during heat treatment is suppressed, so when considering application to the p-type ohmic electrode on the front surface, the module does not cause focus abnormality in the subsequent exposure process. In the process of mounting on the or the like, it is possible to eliminate the possibility of causing poor adhesion of wire bonding. When considering the application to the p-type ohmic electrode on the back surface, it is possible to avoid the adsorption trouble at the time of wafer transfer in the exposure process and the like, and to eliminate the hindrance to the process flow.

Further, since the absolute amount of Al related to alloying is reduced, there is no possibility that the Al melt diffuses in the film during the high temperature heat treatment due to the temperature change during the rapid heat treatment and the wiring is short-circuited between the pattern electrodes. As described above, in the present invention, low resistance ohmic contact resistance between the p-type ohmic electrode and the p-type SiC layer, which cannot be realized by the conventional example, and suppression of surface roughness can be achieved at the same time.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set variously according to the required specifications and the like. Further, each of the above-described embodiments is an example in all respects and is not limiting. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for high withstand voltage semiconductor devices used in power supply devices such as power conversion devices and various industrial machines.

1 n-type 4H-SiC substrate 2 n-type Si surface 4H-SiC epitaxial layer 3 p-type SiC ion injection layer 4 thermal oxide film 5 field oxide film 6 p-type ohmic electrode 7 Al wiring electrode 8 n-type C surface 4H-SiC epitaxial Layer 9 p-type C surface 4H-SiC epitaxial layer

Claims (5)

The first conductive type silicon carbide substrate and
A second conductive type silicon carbide semiconductor layer provided on the main surface side of the silicon carbide substrate or on the side opposite to the main surface of the silicon carbide substrate.
A second conductive type ohmic contact electrode arranged in contact with the silicon carbide semiconductor layer,
Equipped with
The ohmic contact electrode has a layer containing titanium and aluminum having a thickness of 20 nm or more and 150 nm or less, and the content of aluminum is between 50 atomic% and 75 atomic% with respect to the entire layer containing titanium and aluminum. Yes,
The aluminum-titanium alloy silicide constituting the ohmic contact electrode is characterized in that the diameter of the main average particles in the 20 μm × 20 μm region is 0.5 μm or more and 1.3 μm or less and the height is 10 nm or more and 80 nm or less . Silicon carbide semiconductor device. The silicon carbide semiconductor device according to claim 1, wherein the root mean square roughness value of the entire 20 μm × 20 μm region of the ohmic contact electrode is 50 nm or less. The silicon carbide semiconductor device according to claim 1 or 2, wherein the maximum height difference with respect to the average surface of the entire 20 μm × 20 μm region of the ohmic contact electrode is 400 nm or less. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein a Ti ₃ SiC ₂ layer is formed at the interface between the silicon carbide semiconductor layer and the ohmic contact electrode. The first step of forming the second conductive type silicon carbide semiconductor layer on the main surface side of the first conductive type silicon carbide substrate or on the side opposite to the main surface of the silicon carbide substrate.
The second step of forming the second conductive type ohmic contact electrode arranged in contact with the silicon carbide semiconductor layer, and
Including
In the second step, the layer containing titanium and aluminum in the ohmic contact electrode is 20 nm or more and 150 nm or less, and the content of aluminum is 50 atomic% to 75 atomic% with respect to the entire layer containing titanium and aluminum. The diameter of the main average particles in the 20 μm × 20 μm region of the aluminum-titanium alloy silicide formed between the two and constituting the ohmic contact electrode is 0.5 μm or more and 1.3 μm or less and the height is 10 nm or more and 80 nm or less. A method for manufacturing a silicon carbide semiconductor device, which comprises forming.

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