JP7078332B2 - Voltage control type virtual synchronous machine control device and voltage control type virtual synchronous machine - Google Patents

Voltage control type virtual synchronous machine control device and voltage control type virtual synchronous machine Download PDF

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JP7078332B2
JP7078332B2 JP2018169295A JP2018169295A JP7078332B2 JP 7078332 B2 JP7078332 B2 JP 7078332B2 JP 2018169295 A JP2018169295 A JP 2018169295A JP 2018169295 A JP2018169295 A JP 2018169295A JP 7078332 B2 JP7078332 B2 JP 7078332B2
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俊明 菊間
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特許法第30条第2項適用 一般社団法人電気学会 電力・エネルギー部門、平成30年電気学会 電力・エネルギー部門大会 論文集、第170頁-第171頁、平成30年8月31日Patent Law Article 30 Paragraph 2 Applicable General Incorporated Association Institute of Electrical Engineers of Japan Electricity and Energy Division, 2018 Institute of Electrical Engineers of Japan Electricity and Energy Division Conference Proceedings, pp. 170-page 171, August 31, 2018

本発明は、電圧制御型仮想同期機制御装置及び電圧制御型仮想同期機に関する。 The present invention relates to a voltage control type virtual synchronous machine control device and a voltage control type virtual synchronous machine.

近年、環境問題の点から太陽光発電システム等の自然エネルギーを用いた分散形電源の系統への導入が進んでおり、今後ますます増加するものと考えられる。再生可能エネルギーが系統にされる際、変換器を介して接続されることも多い。このため、再生可能エネルギーが増加すると系統に接続される同期機が減少し、代替として変換器が増加することになる。 In recent years, from the viewpoint of environmental problems, the introduction of distributed power sources using natural energy such as solar power generation systems has been progressing, and it is expected that the number will increase in the future. When renewable energy is systematized, it is often connected via transducers. Therefore, as the renewable energy increases, the number of synchronizers connected to the grid decreases, and the number of converters increases as an alternative.

このような変換器として一般的なベクトル制御に基づく電流制御のブロック図を図11に示す。図示する電力制御は、3相交流状態量を2相変換(αβ変換)し、さらに回転座標系に変換(DQ変換)する方式である。D軸(有効分)とQ軸(無効分)とを分離、独立して制御するため、両者が非干渉化できる。電力制御に関しては機器の用途ごとに異なる制御が用いられるが、図示のものはPordの定電力を出力する定電力制御のブロックを示す。 FIG. 11 shows a block diagram of current control based on vector control, which is common as such a converter. The power control shown in the figure is a method in which a three-phase AC state quantity is converted into a two-phase conversion (αβ conversion) and further converted into a rotating coordinate system (DQ conversion). Since the D-axis (effective component) and the Q-axis (invalid component) are controlled separately and independently, both can be made non-interfering. Regarding power control, different controls are used depending on the application of the device, but the one shown in the figure shows a block of constant power control that outputs a constant power of the pod .

図12はPLL(phase locked loop;位相同期回路)のブロック図である。このように、PLL位相θPLLと系統電圧(変換器用変圧器一次側電圧)との位相θとの差分Δθを算出し、この差を0にするように制御を行っている。 FIG. 12 is a block diagram of a PLL (phase locked loop). In this way, the difference Δθ between the PLL phase θ PLL and the phase θ S between the system voltage (transformer transformer primary side voltage) is calculated, and control is performed so that this difference is set to 0.

このように制御される変換器は電流制御系を持っており、系統擾乱時でも過電流を抑制することが可能である。 The converter controlled in this way has a current control system, and can suppress overcurrent even when the system is disturbed.

しかしながら、このように制御される変換器が多量に系統に接続されると、系統電圧変動の増大、系統内の慣性エネルギー量の低下、系統擾乱時の周波数変化幅、速度の増大などの不具合が生じる可能性がある。そこで、変換器に従来の同期機と同様な挙動をさせて系統を安定化さる仮想同期機制御が提案されている(例えば、非特許文献1参照)。 However, when a large number of converters controlled in this way are connected to the system, problems such as an increase in system voltage fluctuation, a decrease in the amount of inertial energy in the system, a frequency change width during system disturbance, and an increase in speed occur. It can occur. Therefore, a virtual synchronous machine control has been proposed in which the converter is made to behave in the same manner as the conventional synchronous machine to stabilize the system (see, for example, Non-Patent Document 1).

このような仮想同期機制御を具備する変換器(以下、仮想同期機と呼称することがある)としては、電圧制御型仮想同期機制御を具備するものがある。この電圧制御型仮想同期機制御を具備する仮想同期機を系統に接続した模式図を図13に示す。図示するように、仮想同期機(VSG)01は、模擬対象となる同期発電機が系統に接続される場合の挙動を模擬するように制御されるものである。なお、図13のインダクタンス02は、模擬対象の発電機のリアクトル成分を、変換器の連系リアクトルで代替したものである。 As a converter provided with such virtual synchronous machine control (hereinafter, may be referred to as a virtual synchronous machine), there is one provided with voltage control type virtual synchronous machine control. FIG. 13 shows a schematic diagram in which a virtual synchronous machine equipped with this voltage-controlled virtual synchronous machine control is connected to the system. As shown in the figure, the virtual synchronous machine (VSG) 01 is controlled so as to simulate the behavior when the synchronous generator to be simulated is connected to the grid. The inductance 02 in FIG. 13 is obtained by substituting the reactor component of the generator to be simulated with the interconnection reactor of the converter.

ここで、模擬対象の同期発電機の挙動は下記方程式を解くことによって実現される。

Figure 0007078332000001
Here, the behavior of the synchronous generator to be simulated is realized by solving the following equation.
Figure 0007078332000001

ここで、Porderは電力指令値、Pmesは変換器出力電力、Jは模擬発電機の慣性モーメント、ωは模擬発電機の回転子角速度、δは模擬発電機のすべり、Dは模擬発電機の制動係数を表す。 Here, Porder is the power command value, P mes is the converter output power, J is the inertial moment of the simulated generator, ω m is the rotor angle speed of the simulated generator, δ is the slip of the simulated generator, and D is the simulated power generation. Represents the braking coefficient of the machine.

上記方程式の解に基づいた制御の一例を図14に示す。 FIG. 14 shows an example of control based on the solution of the above equation.

このような電圧制御型仮想同期機は、電圧を制御して電圧源として動作するため、電流が制御できない。このため、系統擾乱時などには過電流が発生し、変換器停止となる虞がある。例えば、図13のインダクタンス02が0.2puの仮想同期機01の至近端で系統故障が発生した際、5.0pu以上の過電流が発生することが予想される。構想自体は変換器である仮想同期機01は、このような大電流に耐えることはできない。 Since such a voltage-controlled virtual synchronizer operates as a voltage source by controlling the voltage, the current cannot be controlled. Therefore, when the system is disturbed, an overcurrent may occur and the converter may stop. For example, when a system failure occurs at the nearest end of the virtual synchronous machine 01 having an inductance 02 of 0.2 pu in FIG. 13, it is expected that an overcurrent of 5.0 pu or more will occur. The virtual synchronous machine 01, which is a converter in the concept itself, cannot withstand such a large current.

崎元謙一他,「仮想同期機発電機によるインバータ連系形分散電源を含む系統の安定化制御」,電気学会論文誌B,Vol. 132, No. 4 pp. 341-349 (2012)Kenichi Sakimoto et al., "Stabilization Control of Systems Inverter-Connected Distributed Power Sources by Virtual Synchronizer Generator", IEEJ Transactions on Electrical Engineers of Japan B, Vol. 132, No. 4 pp. 341-349 (2012)

従来の仮想同期機制御を具備する変換器では、系統擾乱時など過電流が発生する虞がある場合、電圧制御型仮想同期機制御を停止し、電流制御を行う必要があるが、この場合、仮想同期機制御が停止するので、系統の安定には悪影響を与える。 In a converter equipped with conventional virtual synchronous machine control, when there is a risk of overcurrent occurring such as when the system is disturbed, it is necessary to stop the voltage control type virtual synchronous machine control and perform current control. Since the virtual synchronous machine control is stopped, the stability of the system is adversely affected.

本発明は、このような事情に鑑み、電圧制御型仮想同期機制御を具備する変換器において、電圧制御型仮想同期機制御を維持したまま過電流抑制を行うことができる電圧制御型仮想同期機制御装置及び電圧制御型仮想同期機を提供することを目的とする。 In view of such circumstances, the present invention is a voltage control type virtual synchronizer capable of suppressing overcurrent while maintaining voltage control type virtual synchronizer control in a converter provided with voltage control type virtual synchronizer control. It is an object of the present invention to provide a control device and a voltage control type virtual synchronous machine.

前記目的を達成する本発明の第1の態様は、変換器に対して電圧制御型仮想同期機制御を行う電圧制御型仮想同期機制御装置であって、電圧制御型仮想同期機制御を行う制御部を具備し、前記制御部は、当該制御部に入力される出力電圧指令値を補整する補整手段を具備し、前記補整手段は、前記出力電圧指令値と測定された系統電圧値とをD軸及びQ軸からなる回転座標系に変換し、前記系統電圧値を中心とする半径rの制御円をリミッタとして用い、前記出力電圧指令値が前記制御円の外に出たことを条件とし、前記制御円上又はその内側に存在する補整出力電圧指令値を前記出力電圧指令値とすることを特徴とする電圧制御型仮想同期機制御装置にある。 The first aspect of the present invention that achieves the above object is a voltage control type virtual synchronous machine control device that controls a voltage control type virtual synchronous machine with respect to a converter, and controls that perform voltage control type virtual synchronous machine control. The control unit includes a compensating means for compensating for an output voltage command value input to the control unit, and the compensating means has a D of the output voltage command value and the measured system voltage value. Converted to a rotational coordinate system consisting of an axis and a Q axis, a control circle having a radius r centered on the system voltage value is used as a limiter, and the condition is that the output voltage command value goes out of the control circle. The voltage-controlled virtual synchronous machine control device is characterized in that the compensation output voltage command value existing on or inside the control circle is set as the output voltage command value.

本発明の第2の態様は、前記補整出力電圧指令値が、前記制御円上で且つ前記系統電圧に近い点であることを特徴とする第1の態様に記載の電圧制御型仮想同期機制御装置にある。 The second aspect of the present invention is the voltage control type virtual synchronous machine control according to the first aspect, wherein the compensating output voltage command value is a point on the control circle and close to the system voltage. It is in the device.

本発明の第3の態様は、前記半径rが、前記電圧制御型仮想同期機制御が模擬している模擬発電機のリアクトル成分値から求められた値であることを特徴とする第1又は第2の態様に記載の電圧制御型仮想同期機制御装置にある。 A third aspect of the present invention is characterized in that the radius r is a value obtained from the reactor component value of the simulated generator simulated by the voltage control type virtual synchronous machine control. The voltage control type virtual synchronous machine control device according to the second aspect.

本発明の第4の態様は、前記補整手段は、前記出力電圧指令値のベクトルvVorderと前記系統電圧値のベクトルvVsysとの電圧差Vdiffがrより大きい場合に、前記出力電圧指令値Vorderと前記系統電圧値Vsysとの間にある電圧値Vconvであり且つ前記制御円上又はその内側に入る補整出力電圧ベクトルvVconv-revを決定し、この補整出力電圧ベクトルvVconv-revを前記補整出力電圧指令値とすることを特徴とする第1~3の何れか一つの態様に記載の電圧制御型仮想同期機制御装置にある。 A fourth aspect of the present invention is that the compensating means measures the output voltage command value when the voltage difference V diff between the vector vV order of the output voltage command value and the vector vV system of the system voltage value is larger than r. A compensating output voltage vector vV conv-rev which is a voltage value V conv between the V order and the system voltage value V sys and which is on or inside the control circle is determined, and this compensating output voltage vector vV conv- The voltage control type virtual synchronous machine control device according to any one of the first to third aspects, wherein rev is set to the compensating output voltage command value.

本発明の第5の態様は、前記補整出力電圧ベクトルvVconv-revが、前記出力電圧指令値VorderのベクトルvVorderと、前記系統電圧値VsysのベクトルvVsysとを結ぶ直線と前記制御円との交点へのベクトルであることを特徴とする第4の態様に記載の電圧制御型仮想同期機制御装置にある。 In a fifth aspect of the present invention, the compensating output voltage vector vV conv-rev has a straight line connecting the vector vV order of the output voltage command value Vorder and the vector vV sys of the system voltage value V sys , and the control thereof. The voltage-controlled virtual synchronous machine control device according to the fourth aspect, characterized in that it is a vector to an intersection with a circle.

本発明の第6の態様は、前記補整出力電圧ベクトルvVconv-revが、前記系統電圧値VsysのベクトルvVsys又は当該ベクトルを延長した直線と前記制御円との2つの交点のうち前記出力電圧指令値Vorderに近い電圧値を示すベクトルであることを特徴とする第4の態様に記載の電圧制御型仮想同期機制御装置にある。 A sixth aspect of the present invention is that the compensation output voltage vector vV conv-rev is the output of the vector vV system of the system voltage value V system or the intersection of the straight line extending the vector and the control circle. The voltage control type virtual synchronous machine control device according to a fourth aspect is characterized in that it is a vector indicating a voltage value close to a voltage command value Vorder .

本発明の第7の態様は、第1~6の何れか一つの態様に記載の電圧制御型仮想同期機制御装置を具備する変換器であることを特徴とする電圧制御型仮想同期機にある。 A seventh aspect of the present invention is the voltage control type virtual synchronous machine, which is a converter provided with the voltage control type virtual synchronous machine control device according to any one of the first to sixth aspects. ..

本発明によれば、電圧制御型仮想同期機制御を具備する変換器において、電圧制御型仮想同期機制御を維持したまま過電流抑制を行うことができる電圧制御型仮想同期機制御装置及び電圧制御型仮想同期機を実現することができる。 According to the present invention, in a converter provided with voltage-controlled virtual synchronous machine control, a voltage-controlled virtual synchronous machine control device and voltage control capable of suppressing overcurrent while maintaining voltage-controlled virtual synchronous machine control and voltage control. A type virtual synchronous machine can be realized.

実施形態1に係る電圧制御型仮想同期機の電圧制御型仮想同期機制御装置のブロック図。The block diagram of the voltage control type virtual synchronous machine control apparatus of the voltage control type virtual synchronous machine which concerns on Embodiment 1. FIG. 実施形態1に係る補整制御部の制御を概念的に示す説明図。An explanatory diagram conceptually showing the control of the compensation control unit according to the first embodiment. 実施形態1に係る電圧制御型仮想同期機制御装置の制御ブロック図。The control block diagram of the voltage control type virtual synchronous machine control apparatus which concerns on Embodiment 1. FIG. 実施形態2に係る補整制御部の制御を概念的に示す説明図。An explanatory diagram conceptually showing the control of the compensation control unit according to the second embodiment. 試験例のシミュレーションに使用した解析対象の解析対象系統の概略図。Schematic diagram of the analysis target system used for the simulation of the test example. シミュレーションで用いた簡略化のため変換器は平均化モデルを説明する説明図。For the sake of simplification used in the simulation, the transducer is an explanatory diagram explaining the averaging model. 瞬時値シミュレーション結果の波形表示箇所を示す図。The figure which shows the waveform display part of the instantaneous value simulation result. シミュレーションで用いた3LGシーケンス及び1LGシーケンスを示す図。The figure which shows the 3LG sequence and 1LG sequence used in the simulation. 3LGシーケンスのシミュレーション結果を示す図。The figure which shows the simulation result of a 3LG sequence. 1LGシーケンスのシミュレーション結果を示す図。The figure which shows the simulation result of 1LG sequence. 一般的なベクトル制御に基づく電流制御のブロック図。Block diagram of current control based on general vector control. PLLのブロック図。Block diagram of PLL. 電圧制御型仮想同期機制御を具備する仮想同期機を系統に接続した模式図。The schematic diagram which connected the virtual synchronous machine equipped with the voltage control type virtual synchronous machine control to the system. 方程式の解に基づいた仮想同期機制御の一例を示すブロック図。A block diagram showing an example of virtual synchronous machine control based on the solution of an equation.

以下、実施形態に基づいて本発明を詳細に説明する。 Hereinafter, the present invention will be described in detail based on the embodiments.

(実施形態1)
図1には、本発明の実施形態1に係る電圧制御型仮想同期機の電圧制御型仮想同期機制御装置のブロック図を示す。なお、電圧制御型仮想同期機制御装置は、一般的な変換器に組み込むことにより、過電流抑制する電圧制御型仮想同期機制御を具備する変換器として機能させるものである。なお、変換器自体は従来と同一であるから、ここでの説明は省略する。
(Embodiment 1)
FIG. 1 shows a block diagram of a voltage control type virtual synchronous machine control device of the voltage control type virtual synchronous machine according to the first embodiment of the present invention. The voltage control type virtual synchronous machine control device is incorporated into a general converter to function as a converter provided with voltage control type virtual synchronous machine control for suppressing overcurrent. Since the converter itself is the same as the conventional one, the description here will be omitted.

図1に示すように、電圧制御型仮想同期機制御装置1は、電圧制御型仮想同期機制御部10と、補整制御部20とからなる。 As shown in FIG. 1, the voltage control type virtual synchronous machine control device 1 includes a voltage control type virtual synchronous machine control unit 10 and a compensation control unit 20.

電圧制御型仮想同期機制御部10は、一般的な電圧制御型仮想同期機制御を行う制御部と同じ構成を有し、仮想同期機電圧指令値ベクトルvVorderと、仮想同期機の回転子位相角を受け取り座標変換する座標変換部11と、座標変換したデータに基づいてパルス幅制御のデューティ比を決定するPWM制御部12とを有する。本実施形態では、座標変換部11の前段に加算器13が設けられている。 The voltage control type virtual synchronous machine control unit 10 has the same configuration as the control unit that performs general voltage control type virtual synchronous machine control, and has the virtual synchronous machine voltage command value vector vV order and the rotor phase of the virtual synchronous machine. It has a coordinate conversion unit 11 that receives an angle and converts the coordinates, and a PWM control unit 12 that determines a duty ratio for pulse width control based on the coordinate-converted data. In the present embodiment, the adder 13 is provided in front of the coordinate conversion unit 11.

補整制御部20は、測定された系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとを受け取り、両者の電圧差Vdiffを求めると共に、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとを結ぶ直線と、系統電圧ベクトルvVsysを中心とする半径rの制御円Sとの交点を補整出力電圧ベクトルvVconv-revとし、仮想同期機電圧指令値ベクトルvVorderを始点とし補整出力電圧ベクトルvVconv-revを終点とする補整電圧ベクトルvVoccを求め、これを出力する補整電圧演算部21と、スイッチ素子22とを具備する。スイッチ素子22は、補整電圧演算部21で求めた電圧差Vdiffが前記制御円の半径rと同じ又は小さい場合にはオフとなり、加算器13へは何も出力せず、電圧差Vdiffが前記制御円の半径rより大きい場合にオンになって補整電圧演算部21からの出力である補整電圧ベクトルvVoccを加算器13に出力するように制御される。 The compensation control unit 20 receives the measured system voltage vector vV sys and the virtual synchronous machine voltage command value vector vV order , obtains the voltage difference V diff between them, and obtains the system voltage vector vV sys and the virtual synchronous machine voltage command value. The intersection of the straight line connecting the vector vV order and the control circle S with the radius r centered on the system voltage vector vV sys is the compensation output voltage vector vV conv-rev , and the virtual synchronous machine voltage command value vector vV order is the starting point. A compensating voltage vector vV occ having a compensating output voltage vector vV conv-rev as an end point is obtained, and a compensating voltage calculation unit 21 for outputting the compensating voltage vector vV occ and a switch element 22 are provided. The switch element 22 is turned off when the voltage difference V diff obtained by the compensating voltage calculation unit 21 is the same as or smaller than the radius r of the control circle, nothing is output to the adder 13, and the voltage difference V diff becomes. When it is larger than the radius r of the control circle, it is turned on and controlled to output the compensating voltage vector vV occ , which is the output from the compensating voltage calculation unit 21, to the adder 13.

これにより、電圧差Vdiffが前記制御円の半径rと同じ又は小さい場合には、補整制御部20から加算器13へは何も出力されないので、仮想同期機電圧指令値ベクトルvVorderがそのまま座標変換部11へ入力され、仮想同期機電圧指令値ベクトルvVorderがそのまま電圧制御型仮想同期機の出力電圧Vconvとなり、一方、電圧差Vdiffが前記制御円の半径rより大きい場合には補整電圧演算部21からの出力である補整電圧ベクトルvVoccが加算器13に出力されるので、仮想同期機電圧指令値ベクトルvVorderに補整電圧ベクトルvVoccが加算された補整出力電圧ベクトルvVconv-revが補整出力電圧指令値として座標変換部11へ出力され、この結果、補整出力電圧ベクトルvVconv-revが電圧制御型仮想同期機の出力電圧Vconvとなる。 As a result, when the voltage difference V diff is the same as or smaller than the radius r of the control circle, nothing is output from the compensation control unit 20 to the adder 13, so that the virtual synchronous machine voltage command value vector vV order is the coordinate as it is. It is input to the conversion unit 11, and the voltage command value vector vV order of the virtual synchronous machine becomes the output voltage V conv of the voltage control type virtual synchronous machine as it is, while the voltage difference V dim is compensated when it is larger than the radius r of the control circle. Since the compensating voltage vector vV occ , which is the output from the voltage calculation unit 21, is output to the adder 13, the compensating output voltage vector vV conv- in which the compensating voltage vector vV occ is added to the virtual synchronous machine voltage command value vector vV order . The rev is output to the coordinate conversion unit 11 as the compensation output voltage command value, and as a result, the compensation output voltage vector vV conv-rev becomes the output voltage V conv of the voltage control type virtual synchronous machine.

以上の制御を模式的に示すと図2のようになる。 The above control is schematically shown in FIG.

図2は、出力電圧指令値と測定された系統電圧値とをD軸及びQ軸からなる回転座標系に変換した系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderを回転座標軸に示したものであり、系統電圧ベクトルvVsysの終点である系統電圧値を中心とする半径rの制御円Sを示したものである。半径rは予め設定された設定値である。なお、DQ変換は仮想同期機の回転子位相基準で実施され、仮想同期機電圧指令値ベクトルvVorderは必ずD軸上に存在する。 FIG. 2 shows the system voltage vector vV system obtained by converting the output voltage command value and the measured system voltage value into a rotation coordinate system consisting of the D axis and the Q axis, and the virtual synchronous machine voltage command value vector vV order on the rotation coordinate axis. It shows the control circle S having a radius r centered on the system voltage value which is the end point of the system voltage vector vV sys . The radius r is a preset value. The DQ conversion is performed based on the rotor phase of the virtual synchronous machine, and the virtual synchronous machine voltage command value vector vV order always exists on the D axis.

図2(a)は、系統が比較的正常で、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとの電圧差Vdiffが小さく、仮想同期機電圧指令値ベクトルvVorderがそのまま出力電圧Vconvとなる状態を示す。 In FIG. 2A, the system is relatively normal, the voltage difference V diff between the system voltage vector vV system and the virtual synchronous machine voltage command value vector vV order is small, and the virtual synchronous machine voltage command value vector vV order is output as it is. The state where the voltage is V conv is shown.

図2(b)は、系統が擾乱して、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとの電圧差Vdiffが大きくなり、仮想同期機電圧指令値ベクトルvVorderが制御円Sの外に出た場合であり、仮想同期機電圧指令値ベクトルvVorderに補整電圧ベクトルvVoccが加算された補整出力電圧ベクトルvVconv-revが座標変換部11へ出力され、この結果、補整出力電圧ベクトルvVconv-revが電圧制御型仮想同期機の出力電圧Vconvとなるように制御される状態を示している。 In FIG. 2B, the system is disturbed, the voltage difference V diff between the system voltage vector vV system and the virtual synchronous machine voltage command value vector vV order becomes large, and the virtual synchronous machine voltage command value vector vV order is a control circle. In the case of going out of S, the compensating output voltage vector vV conv-rev obtained by adding the compensating voltage vector vV occ to the virtual synchronous machine voltage command value vector vV order is output to the coordinate conversion unit 11, and as a result, the compensating voltage vector vV conv-rev is output. It shows a state in which the output voltage vector vV conv-rev is controlled so as to be the output voltage V conv of the voltage control type virtual synchronous machine.

ここで、補整制御部20での制御をさらに具体的に説明する。
まず、仮想同期機電圧指令値Vorderと系統電圧Vsysの絶対値の差Vdiffを計算する。
Here, the control by the compensation control unit 20 will be described more specifically.
First, the difference V diff between the virtual synchronous machine voltage command value Volder and the absolute value of the system voltage V sys is calculated.

diff=|Vorder-VsysV diff = | V order -V systems |

次いで、絶対値の差Vdiffがrを超えていた場合、仮想同期機電圧指令値Vorderに補整電圧Vdcor、Vqcorを加える。補整電圧Vdcor、Vqcorは、補整電圧ベクトルvVocc-revに対応する。 Next, when the difference V diff of the absolute value exceeds r, the compensating voltage V coder and V qcor are added to the virtual synchronous machine voltage command value V order . The compensating voltage V docor and V qcor correspond to the compensating voltage vector vV occ-rev .

このとき加える補整電圧Vdcor、Vqcorは、最終的な電圧制御型仮想同期機の出力電圧Vconvが制御円S内に収まるように、仮想同期機電圧指令値Vorderからみて系統電圧値Vsys方向に補整を加えるものである。具体的な値としては以下の補整電圧Vdcor、VqcorをそれぞれD軸、Q軸電圧に加える。 The compensating voltages V coder and V qcor added at this time are system voltage values V as viewed from the virtual synchronous machine voltage command value volter so that the output voltage V conv of the final voltage control type virtual synchronous machine is within the control circle S. Compensation is added in the sys direction. As specific values, the following compensating voltages V dockor and V qcor are applied to the D-axis and Q-axis voltages, respectively.

補整電圧Vdcor、Vqcor(それぞれ、仮想同期機電圧指令値VorderのD軸電圧、Q軸電圧)を求める式(1)は以下の通りである。 The equation (1) for obtaining the compensating voltage V dockor and V qcor (D-axis voltage and Q-axis voltage of the virtual synchronous machine voltage command value Volder , respectively) is as follows.

dcor=(Vdsys-Vorder)×(Vdiff-r)/Vdiff
qcor=Vqsys×(Vdiff-r)/Vdiff ・・・(1)
V diff = (V diff -V order ) x (V diff -r) / V diff
V qcor = V qsys × (V diff -r) / V diff ... (1)

以上の実施形態1の補整制御部20を備える電圧制御型仮想同期機制御装置の制御ブロック図の一例を図3に示す。 FIG. 3 shows an example of a control block diagram of the voltage control type virtual synchronous machine control device including the compensation control unit 20 of the first embodiment.

図3は、図14の制御ブロック図の仮想同期機電圧指令値Vorderの代わりに、補整制御部20を介しての制御を付加したものである。図示するように、補整電圧演算部21は、系統電圧値Vdsys、Vqsysと、制御円Sの半径r及び仮想同期機電圧指令値Vorderが入力され、上記式(1)より、補整電圧Vdocc、Vqoccを求めて出力する。スイッチ素子22は、電圧補整フラグFdiffにより制御され、オン状態で補整電圧Vdocc、Vqoccを出力し、オフ状態では0を出力する。ここで、Vdiff>rであれば1でオンとなり、Vdiff≦rであれば0でオフとなる。加算器13は、スイッチ素子22がオン状態では、仮想同期機電圧指令値Vorderと補整電圧Vdocc、Vqoccとを加算してVdconv、Vqconvを出力し、スイッチ素子22がオフ状態では、仮想同期機電圧指令値VorderをそのままVdconv、Vqconvとして出力する。 FIG. 3 shows that the control via the compensation control unit 20 is added instead of the virtual synchronous machine voltage command value Volder in the control block diagram of FIG. As shown in the figure, the compensating voltage calculation unit 21 inputs the system voltage values V dsys and V qsys , the radius r of the control circle S, and the virtual synchronous machine voltage command value Volder , and the compensating voltage is input from the above equation (1). V docc and V qoc are obtained and output. The switch element 22 is controlled by the voltage compensation flag F diff , and outputs the compensation voltages V docc and V qoc in the on state, and outputs 0 in the off state. Here, if V diff > r, it is turned on by 1, and if V diff ≤ r, it is turned off by 0. When the switch element 22 is on, the adder 13 adds the virtual synchronous machine voltage command value Volder and the compensating voltage V docc and V qoc to output V doconv and V qconv , and when the switch element 22 is off, the adder 13 outputs V doconv and V qconv. , The virtual synchronous machine voltage command value Volder is output as it is as V dconv and V qconv .

なお、図3の例では、制御円Sの半径rを可変としており、過電流フラグFocにより、変換器電流が閾値以下ならr、閾値を超えるとrとなるように変更される。 In the example of FIG. 3, the radius r of the control circle S is variable, and is changed to r 1 when the converter current is equal to or less than the threshold value and r 2 when the converter current exceeds the threshold value by the overcurrent flag F oc .

以上説明した補整制御部20では、補整電圧演算部21で常に補整電圧ベクトルvVoccを求め、これを出力するようにし、電圧差Vdiffが半径rより大きい場合のみに、電圧制御型仮想同期機制御部10の加算器13へ補整電圧ベクトルvVoccを出力するようにしたが、補整制御はこれに限定されず、電圧差Vdiffが半径rより大きい場合のみに補整電圧ベクトルvVoccを求め、これを出力するようにしてもよい。 In the compensating control unit 20 described above, the compensating voltage calculation unit 21 always obtains the compensating voltage vector vV occ and outputs it, and the voltage control type virtual synchronous machine is used only when the voltage difference V diff is larger than the radius r. The compensating voltage vector vV occ is output to the adder 13 of the control unit 10, but the compensating control is not limited to this, and the compensating voltage vector vV occ is obtained only when the voltage difference V diff is larger than the radius r. This may be output.

また、電圧制御型仮想同期機制御部10で仮想同期機電圧指令値ベクトルvVorderが補整される場合に、仮想同期機電圧指令値ベクトルvVorderに加算器13で補整電圧ベクトルvVoccを加算するようにしたが、これに限定されず、補整が必要となる場合には、補整制御部20から補整出力電圧ベクトルvVconv-revを出力するようにし、仮想同期機電圧指令値ベクトルvVorderに替えて補整出力電圧ベクトルvVconv-revが座標変換部11に入力されるようにしてもよい。 Further, when the virtual synchronous machine voltage command value vector vV order is compensated by the voltage control type virtual synchronous machine control unit 10, the compensation voltage vector vV occ is added to the virtual synchronous machine voltage command value vector vV order by the adder 13. However, it is not limited to this, and when compensation is required, the compensation output voltage vector vV conv-rev is output from the compensation control unit 20 and replaced with the virtual synchronous machine voltage command value vector vV order . The compensating output voltage vector vV conv-rev may be input to the coordinate conversion unit 11.

さらに、電圧制御型仮想同期機制御部10の構成は特に限定されず、従来から公知の電圧制御型仮想同期機制御を行うものであればよい。 Further, the configuration of the voltage control type virtual synchronous machine control unit 10 is not particularly limited, and any conventionally known voltage control type virtual synchronous machine control may be used.

また、制御円Sの半径rは、過電流をどの程度抑制したいかなどにより決定されるが、電圧制御型仮想同期機制御が模擬している模擬発電機のリアクトル成分値を参照して求めるのが好ましい。 Further, the radius r of the control circle S is determined by how much the overcurrent is to be suppressed, and is obtained by referring to the reactor component value of the simulated generator simulated by the voltage control type virtual synchronous machine control. Is preferable.

例えば、リアクトル値がR(pu)の場合、r=R±20%程度とするのが好ましい。 For example, when the reactor value is R (pu), it is preferable that r = R ± 20%.

また、半径rは固定値でなくてもよく、系統の状態に合わせて変更するようにしてもよい。 Further, the radius r does not have to be a fixed value, and may be changed according to the state of the system.

(実施形態2)
上述した実施形態では、補整出力電圧ベクトルvVconv-revを、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとを結ぶ直線と、制御円Sとの交点としたが、これに限定されるものではない。本実施形態は、補整出力電圧ベクトルvVconv-revの他の例を示す。
(Embodiment 2)
In the above-described embodiment, the compensating output voltage vector vV conv-rev is defined as the intersection of the straight line connecting the system voltage vector vV sys and the virtual synchronous machine voltage command value vector vV order and the control circle S, but is limited to this. It is not something that will be done. This embodiment shows another example of the compensating output voltage vector vV conv-rev .

本実施形態の補整出力電圧ベクトルvVconv-revを図4に示す。図示するように、本実施形態の補整出力電圧ベクトルvVconv-revは、系統電圧値VsysのベクトルvVsys又は当該ベクトルを延長した直線と制御円Sとの2つの交点のうち出力電圧指令値Vorderに近い電圧値を示すベクトルとしたものである。 The compensated output voltage vector vV conv-rev of this embodiment is shown in FIG. As shown in the figure, the compensating output voltage vector vV conv-rev of the present embodiment is the vector vV system of the system voltage value V system or the output voltage command value among the two intersections of the straight line extending the vector and the control circle S. It is a vector showing a voltage value close to Vorder .

本実施形態は、補整出力電圧ベクトルvVconv-revを変更した以外は、基本的には、実施形態1と同様であり、仮想同期機電圧指令値ベクトルvVorderが制御円Sの外に出た場合に補整出力電圧ベクトルvVconv-revを出力するものであり、重複する説明は省略する。 This embodiment is basically the same as that of the first embodiment except that the compensating output voltage vector vV conv-rev is changed, and the virtual synchronous machine voltage command value vector vV order goes out of the control circle S. In this case, the compensation output voltage vector vV conv-rev is output, and duplicate description will be omitted.

本実施形態の補整出力電圧ベクトルvVconv-revの具体的な求めからは以下の通りである。 The specific determination of the compensating output voltage vector vV conv-rev of the present embodiment is as follows.

図4の場合、仮想同期機電圧指令値Vorderが制御円S内に収まるように、零点から系統電圧値Vsys方向に延長するものである。具体的な値としては以下の補整電圧Vdcor、VqcorをそれぞれD軸、Q軸電圧に加える。 In the case of FIG. 4, the virtual synchronous machine voltage command value Vorder is extended from the zero point in the system voltage value Vsys direction so as to be within the control circle S. As specific values, the following compensating voltages V dockor and V qcor are applied to the D-axis and Q-axis voltages, respectively.

dconv=Vdsys×(|Vsys|+|r|)/|Vsys
qconv=Vqsys×(|Vsys|+|r|)/|Vsys
V dconv = V dsys × (| V system | + | r |) / | V system |
V qconv = V qsys × (| V system | + | r |) / | V system |

なお、補整出力電圧ベクトルvVconv-revの決定の仕方はこれに限定されず、制御円S内に収まる補整出力電圧ベクトルvVconv-revとすればよいが、電圧制御型仮想同期機制御を行いながら補整するという趣旨から、制御円S内で電圧値ができるだけ仮想同期機電圧指令値Vorderに近いものとするのが好ましく、この観点からは制御円S上が好ましい。また、補整の趣旨から、仮想同期機電圧指令値Vorderと系統電圧値Vsysとの間で制御円S内で電圧値が仮想同期機電圧指令値Vorderに近いものとするのが好ましい。 The method of determining the compensating output voltage vector vV conv-rev is not limited to this, and the compensating output voltage vector vV conv-rev that fits within the control circle S may be used, but voltage-controlled virtual synchronous machine control is performed. However, for the purpose of compensating, it is preferable that the voltage value in the control circle S is as close as possible to the virtual synchronous machine voltage command value Volder , and from this viewpoint, it is preferable on the control circle S. Further, for the purpose of compensation, it is preferable that the voltage value within the control circle S between the virtual synchronous machine voltage command value Volder and the system voltage value V sys is close to the virtual synchronous machine voltage command value Volder .

(試験例)
本発明の効果を検証するため、瞬時値シミュレーションによる動作検証を行った。なお、シミュレーションには瞬時値解析プログラムであるXTAP(eXpandable Transient Analysis Program)を使用してシミュレーションを実施した。
(Test example)
In order to verify the effect of the present invention, operation verification was performed by instantaneous value simulation. The simulation was carried out using XTAP (eXpandable Transient Analysis Program), which is an instantaneous value analysis program.

図5にシミュレーションに使用した解析対象の解析対象系統の概略図を示す。仮想同期機制御を具備する変換器設備として、変換器直流側には理想電圧源を接続したものを使用している。本来は,変換器直流側には電池や、分散型電源や、直流送電網を介したほかの交流系統などの諸設備が想定されるが、本試験では、電圧型仮想同期機制御の過電流抑制のみ検証する目的からこれらの設備を理想化し、理想電圧源で代替した。 FIG. 5 shows a schematic diagram of the analysis target system used in the simulation. As a converter equipment equipped with virtual synchronous machine control, an ideal voltage source is connected to the DC side of the converter. Originally, various facilities such as batteries, distributed power supplies, and other AC systems via the DC transmission network are assumed on the DC side of the converter, but in this test, the overcurrent controlled by the voltage-type virtual synchronizer is assumed. These facilities were idealized for the purpose of verifying only suppression, and replaced with an ideal voltage source.

交流系統は無限大母線模擬の電圧源と短絡容量模擬の抵抗とリアクトルにより構成されている。ここで、短絡容量比は2回線時6.93に設定した。交流側の事故地点は変換器至近端とし、交流事故は事故回線を遮断器により開放することで除去した。 The AC system consists of a voltage source simulating an infinite bus, a resistance simulating a short circuit capacity, and a reactor. Here, the short-circuit capacity ratio was set to 6.93 for two lines. The accident point on the AC side was set to the nearest end of the converter, and the AC accident was eliminated by opening the accident line with a circuit breaker.

なお、計算の簡略化のため変換器は平均化モデルを使用している。平均化モデルとは、図6(a)に示す詳細な変換器モデルのようにスイッチングを模擬せず、図6(b)に示すように、スイッチング周期を平均化区間としてリプルを平均化するモデルである。回路規模の削減に加えて、計算時間刻みの延伸も可能であり、計算量の軽減効果は高い。 The converter uses an averaging model to simplify the calculation. The averaging model is a model that does not simulate switching as in the detailed converter model shown in FIG. 6A, but averages ripples with the switching period as the averaging interval as shown in FIG. 6B. Is. In addition to reducing the circuit scale, it is possible to extend the calculation time increments, and the effect of reducing the amount of calculation is high.

表1に計算に用いた各種条件を示す。また、図7に瞬時値シミュレーション結果の波形表示箇所を示す。本シミュレーションにおいて各系統擾乱はそれぞれ3パターンの制御で実施している。なお、過電流制御ありは実施形態1を模したものであり、制御円Sは実施形態1のものである。 Table 1 shows various conditions used in the calculation. Further, FIG. 7 shows the waveform display location of the instantaneous value simulation result. In this simulation, each system disturbance is controlled by three patterns. It should be noted that the presence of overcurrent control mimics the first embodiment, and the control circle S is that of the first embodiment.

Case a: 過電流抑制制御無
Case b: 過電流抑制制御有(制御円Sの半径rが0.2pu固定)
Case c: 過電流抑制制御有(定常時制御円Sの半径rが0.2pu、1.2puを超える過電流発生時半径rが0.1pu)
Case a: No overcurrent suppression control
Case b: With overcurrent suppression control (radius r of control circle S is fixed at 0.2pu)
Case c: With overcurrent suppression control (radius r of steady-state control circle S is 0.2pu, radius r when overcurrent exceeds 1.2pu is 0.1pu)

Figure 0007078332000002
Figure 0007078332000002

図8(a)には、3相地絡事故(3LG)のシーケンスを示す。3LG発生から交流遮断器が開放されるまでの時間を0.1秒(5サイクル)に設定している。交流事故は事故回線を開放することによって除去される。 FIG. 8A shows a sequence of a three-phase ground fault (3LG). The time from the generation of 3LG to the opening of the AC circuit breaker is set to 0.1 seconds (5 cycles). AC accidents are eliminated by opening the accident line.

図8(b)には、1相地絡事故(1LG)シーケンスを示す。1LG発生から交流遮断器が開放されるまでの時間を0.1秒(5サイクル)に設定している。交流事故は事故回線を開放することによって除去され、このとき事故回線は3相共に開放されるものとする。 FIG. 8B shows a one-phase ground fault (1LG) sequence. The time from the generation of 1LG to the opening of the AC circuit breaker is set to 0.1 seconds (5 cycles). The AC accident is eliminated by opening the accident line, and at this time, the accident line shall be opened for all three phases.

以上の条件でシミュレーションを実施した結果を図9及び図10に示す。 The results of the simulation under the above conditions are shown in FIGS. 9 and 10.

図9は、3LG発生時のVsys、Iconvの拡大図であり、(a)~(c)は、上述したCase a~cに対応している。(a)の過電流抑制制御がない場合、変換器には最大9.19puの過電流が流れた(変換器電流定格1458Apeak)が、これに対し、(b)、(c)のcase b、cの過電流抑制制御ありの場合、それぞれ1.58pu、1.37puとなり、過電流抑制効果が確認できた。 FIG. 9 is an enlarged view of V systems and I conv when 3LG occurs, and (a) to (c) correspond to the above-mentioned Cases a to c. In the absence of the overcurrent suppression control of (a), a maximum of 9.19 pu of overcurrent flowed through the converter (converter current rating of 1458 Apeak), whereas in contrast to the case b of (b) and (c), When the overcurrent suppression control of c was performed, the values were 1.58pu and 1.37pu, respectively, and the overcurrent suppression effect could be confirmed.

図10は、1LG発生時のVsys、Iconvの拡大図であり、(a)~(c)は、上述したCase a~cに対応している。(a)の過電流抑制制御がない場合、変換器には最大2.94puの過電流が流れたが、これに対し、case b、cの過電流抑制制御ありの場合、それぞれ1.64pu、1.45puとなり、過電流抑制効果が確認された。 FIG. 10 is an enlarged view of V systems and I conv when 1 LG is generated, and (a) to (c) correspond to the above-mentioned Cases a to c. In the case of (a) without the overcurrent suppression control, a maximum of 2.94pu of overcurrent flowed through the converter, whereas in the case of case b and c with the overcurrent suppression control, 1.64pu and 1.64pu, respectively. It was 1.45 pu, and the overcurrent suppression effect was confirmed.

1 電圧制御型仮想同期機制御装置
10 電圧制御型仮想同期機制御部
11 座標変換部
12 PWM制御部
13 加算器
20 補整制御部
21 補整電圧演算部
22 スイッチ素子
1 Voltage control type virtual synchronous machine control device 10 Voltage control type virtual synchronous machine control unit 11 Coordinate conversion unit 12 PWM control unit 13 Adder 20 Compensation control unit 21 Compensation voltage calculation unit 22 Switch element

Claims (7)

変換器に対して電圧制御型仮想同期機制御を行う電圧制御型仮想同期機制御装置であって、
電圧制御型仮想同期機制御を行う制御部を具備し、
前記制御部は、当該制御部に入力される出力電圧指令値を補整する補整手段を具備し、
前記補整手段は、前記出力電圧指令値と測定された系統電圧値とをD軸及びQ軸からなる回転座標系に変換し、前記系統電圧値を中心とする半径rの制御円をリミッタとして用い、前記出力電圧指令値が前記制御円の外に出たことを条件とし、前記制御円上又はその内側に存在する補整出力電圧指令値を前記出力電圧指令値とすることを特徴とする電圧制御型仮想同期機制御装置。
It is a voltage control type virtual synchronous machine control device that controls the voltage control type virtual synchronous machine for the converter.
Equipped with a control unit that controls a voltage-controlled virtual synchronous machine,
The control unit includes a compensation means for compensating for an output voltage command value input to the control unit.
The compensating means converts the output voltage command value and the measured system voltage value into a rotational coordinate system consisting of the D axis and the Q axis, and uses a control circle having a radius r centered on the system voltage value as a limiter. , The voltage control is characterized in that the compensated output voltage command value existing on or inside the control circle is set as the output voltage command value, provided that the output voltage command value is outside the control circle. Type virtual synchronous machine control device.
前記補整出力電圧指令値が、前記制御円上で且つ前記系統電圧値に近い点であることを特徴とする請求項1記載の電圧制御型仮想同期機制御装置。 The voltage control type virtual synchronous machine control device according to claim 1, wherein the compensation output voltage command value is on the control circle and close to the system voltage value. 前記半径rが、前記電圧制御型仮想同期機制御が模擬している模擬発電機のリアクトル成分値から求められた値であることを特徴とする請求項1又は2記載の電圧制御型仮想同期機制御装置。 The voltage control type virtual synchronizer according to claim 1 or 2, wherein the radius r is a value obtained from the reactor component value of the simulated generator simulated by the voltage control type virtual synchronizer control. Control device. 前記補整手段は、前記出力電圧指令値のベクトルvVorderと前記系統電圧値のベクトルvVsysとの電圧差Vdiffがrより大きい場合に、前記出力電圧指令値Vorderと前記系統電圧値Vsysとの間にある電圧値Vconvであり且つ前記制御円上又はその内側に入る補整出力電圧ベクトルvVconv-revを決定し、この補整出力電圧ベクトルvVconv-revを前記補整出力電圧指令値とすることを特徴とする請求項1~3の何れか一項に記載の電圧制御型仮想同期機制御装置。 When the voltage difference V diff between the vector vV order of the output voltage command value and the vector vV sys of the system voltage value is larger than r, the compensating means has the output voltage command value V order and the system voltage value V sys . A compensating output voltage vector vV conv-rev which is a voltage value V conv between and is on or inside the control circle is determined, and this compensating output voltage vector vV conv-rev is used as the compensating output voltage command value. The voltage control type virtual synchronous machine control device according to any one of claims 1 to 3, wherein the voltage control type virtual synchronous machine control device is characterized. 前記補整出力電圧ベクトルvVconv-revが、前記出力電圧指令値VorderのベクトルvVorderと、前記系統電圧値VsysのベクトルvVsysとを結ぶ直線と前記制御円との交点へのベクトルであることを特徴とする請求項4記載の電圧制御型仮想同期機制御装置。 The compensating output voltage vector vV conv-rev is a vector to the intersection of the straight line connecting the vector vV order of the output voltage command value V order and the vector vV sys of the system voltage value V sys and the control circle. The voltage control type virtual synchronous machine control device according to claim 4, wherein the voltage control type virtual synchronous machine control device is characterized. 前記補整出力電圧ベクトルvVconv-revが、前記系統電圧値VsysのベクトルvVsys又は当該ベクトルを延長した直線と前記制御円との2つの交点のうち前記出力電圧指令値Vorderに近い電圧値を示すベクトルであることを特徴とする請求項4記載の電圧制御型仮想同期機制御装置。 The compensating output voltage vector vV conv-rev is a voltage value close to the output voltage command value Volder at the intersection of the vector vV system of the system voltage value V system or the straight line extending the vector and the control circle. The voltage control type virtual synchronous machine control device according to claim 4, wherein the vector indicates the above. 請求項1~6の何れか一項に記載の電圧制御型仮想同期機制御装置を具備する変換器であることを特徴とする電圧制御型仮想同期機。 A voltage control type virtual synchronizer comprising the voltage control type virtual synchronizer control device according to any one of claims 1 to 6.
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JP2011193606A (en) 2010-03-12 2011-09-29 Toshiba Corp Solar power generation system
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