JP2020043688A - Voltage control type virtual synchronous machine control device and voltage control type virtual synchronous machine - Google Patents

Voltage control type virtual synchronous machine control device and voltage control type virtual synchronous machine Download PDF

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JP2020043688A
JP2020043688A JP2018169295A JP2018169295A JP2020043688A JP 2020043688 A JP2020043688 A JP 2020043688A JP 2018169295 A JP2018169295 A JP 2018169295A JP 2018169295 A JP2018169295 A JP 2018169295A JP 2020043688 A JP2020043688 A JP 2020043688A
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俊明 菊間
Toshiaki Kikuma
俊明 菊間
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Central Research Institute of Electric Power Industry
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Abstract

To provide a voltage control type virtual synchronous machine control device and a voltage control type virtual synchronous machine which can suppress overcurrent as maintaining voltage control type virtual synchronous machine control in a converter equipped with the voltage control type virtual synchronous machine control.SOLUTION: A voltage control type virtual synchronous machine control device performs voltage control type virtual synchronous machine control to a converter, and is equipped with a control part which performs the voltage control type virtual synchronous machine control, in which the control part is equipped with compensation means for compensating an output voltage command value to be input in the control part, the compensation means converts the output voltage command value and a measured system voltage value into a rotary coordinate system consisting of a D axis and a Q axis, uses a control circle with a radius r centering on the system voltage value as a limiter, and considers the compensated output voltage command value existing on the control circle or its inside as the output voltage command value on condition that the output voltage command value is outside the control circle.SELECTED DRAWING: Figure 1

Description

本発明は、電圧制御型仮想同期機制御装置及び電圧制御型仮想同期機に関する。   The present invention relates to a voltage controlled virtual synchronous machine control device and a voltage controlled virtual synchronous machine.

近年、環境問題の点から太陽光発電システム等の自然エネルギーを用いた分散形電源の系統への導入が進んでおり、今後ますます増加するものと考えられる。再生可能エネルギーが系統にされる際、変換器を介して接続されることも多い。このため、再生可能エネルギーが増加すると系統に接続される同期機が減少し、代替として変換器が増加することになる。   In recent years, due to environmental issues, the introduction of distributed power sources using natural energy such as solar power generation systems into the grid has been progressing, and it is expected that the number will increase further in the future. When renewable energy is systemized, it is often connected via a converter. For this reason, when the renewable energy increases, the number of synchronous machines connected to the grid decreases, and as an alternative, the number of converters increases.

このような変換器として一般的なベクトル制御に基づく電流制御のブロック図を図11に示す。図示する電力制御は、3相交流状態量を2相変換(αβ変換)し、さらに回転座標系に変換(DQ変換)する方式である。D軸(有効分)とQ軸(無効分)とを分離、独立して制御するため、両者が非干渉化できる。電力制御に関しては機器の用途ごとに異なる制御が用いられるが、図示のものはPordの定電力を出力する定電力制御のブロックを示す。 FIG. 11 shows a block diagram of current control based on general vector control as such a converter. The illustrated power control is a method in which a three-phase AC state quantity is converted into a two-phase (αβ conversion) and further converted into a rotating coordinate system (DQ conversion). Since the D axis (effective part) and the Q axis (ineffective part) are controlled separately and independently, both can be made non-interfering. Regarding power control, different control is used for each application of the device, but the illustrated one shows a block of constant power control that outputs constant power of Port .

図12はPLL(phase locked loop;位相同期回路)のブロック図である。このように、PLL位相θPLLと系統電圧(変換器用変圧器一次側電圧)との位相θとの差分Δθを算出し、この差を0にするように制御を行っている。 FIG. 12 is a block diagram of a PLL (phase locked loop). Thus, calculates the difference Δθ between the phase theta S and PLL phase theta PLL and the system voltage (primary voltage transducers transformer), control is performed so that the difference to zero.

このように制御される変換器は電流制御系を持っており、系統擾乱時でも過電流を抑制することが可能である。   The converter controlled in this way has a current control system, and can suppress overcurrent even at the time of system disturbance.

しかしながら、このように制御される変換器が多量に系統に接続されると、系統電圧変動の増大、系統内の慣性エネルギー量の低下、系統擾乱時の周波数変化幅、速度の増大などの不具合が生じる可能性がある。そこで、変換器に従来の同期機と同様な挙動をさせて系統を安定化さる仮想同期機制御が提案されている(例えば、非特許文献1参照)。   However, if many converters controlled in this way are connected to the system, problems such as an increase in system voltage fluctuation, a decrease in the amount of inertial energy in the system, a frequency change width during system disturbance, and an increase in speed will occur. Can occur. Therefore, virtual synchronous machine control has been proposed in which a converter behaves in the same manner as a conventional synchronous machine to stabilize the system (for example, see Non-Patent Document 1).

このような仮想同期機制御を具備する変換器(以下、仮想同期機と呼称することがある)としては、電圧制御型仮想同期機制御を具備するものがある。この電圧制御型仮想同期機制御を具備する仮想同期機を系統に接続した模式図を図13に示す。図示するように、仮想同期機(VSG)01は、模擬対象となる同期発電機が系統に接続される場合の挙動を模擬するように制御されるものである。なお、図13のインダクタンス02は、模擬対象の発電機のリアクトル成分を、変換器の連系リアクトルで代替したものである。   As a converter having such a virtual synchronous machine control (hereinafter, sometimes referred to as a virtual synchronous machine), there is a converter having a voltage-controlled virtual synchronous machine control. FIG. 13 is a schematic diagram in which a virtual synchronous machine having the voltage-controlled virtual synchronous machine control is connected to a system. As shown in the figure, a virtual synchronous machine (VSG) 01 is controlled so as to simulate a behavior when a synchronous generator to be simulated is connected to a system. Note that the inductance 02 in FIG. 13 is obtained by replacing the reactor component of the generator to be simulated with the interconnection reactor of the converter.

ここで、模擬対象の同期発電機の挙動は下記方程式を解くことによって実現される。

Figure 2020043688
Here, the behavior of the synchronous generator to be simulated is realized by solving the following equation.
Figure 2020043688

ここで、Porderは電力指令値、Pmesは変換器出力電力、Jは模擬発電機の慣性モーメント、ωは模擬発電機の回転子角速度、δは模擬発電機のすべり、Dは模擬発電機の制動係数を表す。 Where P order is the power command value, P mes is the converter output power, J is the moment of inertia of the simulated generator, ω m is the rotor angular velocity of the simulated generator, δ is the slip of the simulated generator, and D is the simulated power generation. Indicates the braking coefficient of the machine.

上記方程式の解に基づいた制御の一例を図14に示す。   FIG. 14 shows an example of control based on the solution of the above equation.

このような電圧制御型仮想同期機は、電圧を制御して電圧源として動作するため、電流が制御できない。このため、系統擾乱時などには過電流が発生し、変換器停止となる虞がある。例えば、図13のインダクタンス02が0.2puの仮想同期機01の至近端で系統故障が発生した際、5.0pu以上の過電流が発生することが予想される。構想自体は変換器である仮想同期機01は、このような大電流に耐えることはできない。   Since such a voltage-controlled virtual synchronous machine operates as a voltage source by controlling a voltage, the current cannot be controlled. For this reason, an overcurrent may be generated at the time of system disturbance or the like, and the converter may be stopped. For example, when a system failure occurs near the virtual synchronous machine 01 having an inductance 02 of 0.2 pu in FIG. 13, an overcurrent of 5.0 pu or more is expected to occur. The virtual synchronous machine 01 whose concept is itself a converter cannot withstand such a large current.

崎元謙一他,「仮想同期機発電機によるインバータ連系形分散電源を含む系統の安定化制御」,電気学会論文誌B,Vol. 132, No. 4 pp. 341-349 (2012)Kenichi Sakimoto et al., "Stabilization Control of Grid Including Inverter-Linked Distributed Power Supply Using Virtual Synchronous Generator", IEEJ Transactions on Electronics, B, Vol.

従来の仮想同期機制御を具備する変換器では、系統擾乱時など過電流が発生する虞がある場合、電圧制御型仮想同期機制御を停止し、電流制御を行う必要があるが、この場合、仮想同期機制御が停止するので、系統の安定には悪影響を与える。   In a converter equipped with the conventional virtual synchronous machine control, when there is a risk of occurrence of overcurrent such as at the time of system disturbance, it is necessary to stop the voltage control type virtual synchronous machine control and perform current control. Since the control of the virtual synchronous machine is stopped, the stability of the system is adversely affected.

本発明は、このような事情に鑑み、電圧制御型仮想同期機制御を具備する変換器において、電圧制御型仮想同期機制御を維持したまま過電流抑制を行うことができる電圧制御型仮想同期機制御装置及び電圧制御型仮想同期機を提供することを目的とする。   In view of such circumstances, the present invention provides a voltage-controlled virtual synchronous machine capable of performing overcurrent suppression while maintaining the voltage-controlled virtual synchronous machine control in a converter including the voltage-controlled virtual synchronous machine control. An object of the present invention is to provide a control device and a voltage controlled virtual synchronizer.

前記目的を達成する本発明の第1の態様は、変換器に対して電圧制御型仮想同期機制御を行う電圧制御型仮想同期機制御装置であって、電圧制御型仮想同期機制御を行う制御部を具備し、前記制御部は、当該制御部に入力される出力電圧指令値を補整する補整手段を具備し、前記補整手段は、前記出力電圧指令値と測定された系統電圧値とをD軸及びQ軸からなる回転座標系に変換し、前記系統電圧値を中心とする半径rの制御円をリミッタとして用い、前記出力電圧指令値が前記制御円の外に出たことを条件とし、前記制御円上又はその内側に存在する補整出力電圧指令値を前記出力電圧指令値とすることを特徴とする電圧制御型仮想同期機制御装置にある。   A first aspect of the present invention that achieves the above object is a voltage-controlled virtual synchronous machine control device that performs voltage-controlled virtual synchronous machine control on a converter, wherein the control performs voltage-controlled virtual synchronous machine control. A control unit, wherein the control unit includes compensation means for compensating an output voltage command value input to the control unit, wherein the compensation means converts the output voltage command value and the measured system voltage value into D. Converted to a rotating coordinate system consisting of an axis and a Q axis, using a control circle having a radius r centered on the system voltage value as a limiter, on condition that the output voltage command value goes out of the control circle, A voltage-controlled virtual synchronous machine control device is characterized in that a compensated output voltage command value existing on or inside the control circle is used as the output voltage command value.

本発明の第2の態様は、前記補整出力指令値が、前記制御円上で且つ前記系統電圧に近い点であることを特徴とする第1の態様に記載の電圧制御型仮想同期機制御装置にある。   A second aspect of the present invention is the voltage-controlled virtual synchronous machine control device according to the first aspect, wherein the compensated output command value is a point on the control circle and close to the system voltage. It is in.

本発明の第3の態様は、前記半径rが、前記電圧制御型仮想同期機制御が模擬している模擬発電機のリアクトル成分値から求められた値であることを特徴とする第1又は第2の態様に記載の電圧制御型仮想同期機制御装置にある。   According to a third aspect of the present invention, the radius r is a value obtained from a reactor component value of a simulation generator simulated by the voltage-controlled virtual synchronous machine control, According to a second aspect, there is provided the voltage-controlled virtual synchronous machine control device.

本発明の第4の態様は、前記補整手段は、前記出力電圧指令値のベクトルvVorderと前記系統電圧値のベクトルvVsysとの電圧差Vdiffがrより大きい場合に、前記出力電圧指令値Vorderと前記系統電圧値Vsysとの間にある電圧値Vconvであり且つ前記制御円上又はその内側に入る補整出力電圧ベクトルvVconv−revを決定し、この補整出力電圧ベクトルvVconv−revを前記補整出力電圧指令値とすることを特徴とする第1〜3の何れか一つの態様に記載の電圧制御型仮想同期機制御装置にある。 In a fourth aspect of the present invention, when the voltage difference V diff between the vector vV order of the output voltage command value and the vector vV sys of the system voltage value is larger than r, the compensating means is configured to output the command value of the output voltage command value. V order and the determining the compensation output voltage vector vV conv-rev to and a voltage value V conv entering the control circle or inside thereof lying between the system voltage value V sys, the compensation output voltage vector vV Conv- The voltage-controlled virtual synchronous machine control device according to any one of the first to third aspects, wherein rev is the corrected output voltage command value.

本発明の第5の態様は、前記補整出力電圧ベクトルvVconv−revが、前記出力電圧指令値VorderのベクトルvVorderと、前記系統電圧値VsysのベクトルvVsysとを結ぶ直線と前記制御円との交点へのベクトルであることを特徴とする第4の態様に記載の電圧制御型仮想同期機制御装置にある。 A fifth aspect of the present invention, the compensation output voltage vector vV conv-rev is, the control and vector vV order of the output voltage command value V order, the straight line connecting the vector vV sys of the system voltage value V sys A voltage-controlled virtual synchronous machine control device according to a fourth aspect, wherein the vector is a vector to an intersection with a circle.

本発明の第6の態様は、前記補整出力電圧ベクトルvVconv−revが、前記系統電圧値VsysのベクトルvVsys又は当該ベクトルを延長した直線と前記制御円との2つの交点のうち前記出力電圧指令値Vorderに近い電圧値を示すベクトルであることを特徴とする第4の態様に記載の電圧制御型仮想同期機制御装置にある。 A sixth aspect of the present invention, the compensation output voltage vector vV conv-rev is, the output of the two intersection points of the straight line and the control circle extended vector vV sys or the vector of the system voltage value V sys A voltage-controlled virtual synchronous machine control device according to a fourth aspect, wherein the vector is a vector indicating a voltage value close to the voltage command value V order .

本発明の第7の態様は、第1〜6の何れか一つの態様に記載の電圧制御型仮想同期機制御装置を具備する変換器であることを特徴とする電圧制御型仮想同期機にある。   According to a seventh aspect of the present invention, there is provided a voltage-controlled virtual synchronous machine comprising a converter including the voltage-controlled virtual synchronous machine control device according to any one of the first to sixth aspects. .

本発明によれば、電圧制御型仮想同期機制御を具備する変換器において、電圧制御型仮想同期機制御を維持したまま過電流抑制を行うことができる電圧制御型仮想同期機制御装置及び電圧制御型仮想同期機を実現することができる。   ADVANTAGE OF THE INVENTION According to this invention, in the converter provided with the voltage control type virtual synchronous machine control, the voltage control type virtual synchronous machine control apparatus and the voltage control which can perform overcurrent suppression, maintaining the voltage control type virtual synchronous machine control Type virtual synchronous machine can be realized.

実施形態1に係る電圧制御型仮想同期機の電圧制御型仮想同期機制御装置のブロック図。FIG. 2 is a block diagram of a voltage-controlled virtual synchronous machine control device of the voltage-controlled virtual synchronous machine according to the first embodiment. 実施形態1に係る補整制御部の制御を概念的に示す説明図。FIG. 4 is an explanatory diagram conceptually showing control of a compensation control unit according to the first embodiment. 実施形態1に係る電圧制御型仮想同期機制御装置の制御ブロック図。FIG. 2 is a control block diagram of the voltage-controlled virtual synchronous machine control device according to the first embodiment. 実施形態2に係る補整制御部の制御を概念的に示す説明図。FIG. 9 is an explanatory diagram conceptually showing control of a compensation control unit according to the second embodiment. 試験例のシミュレーションに使用した解析対象の解析対象系統の概略図。The schematic diagram of the analysis target system of the analysis object used for the simulation of the test example. シミュレーションで用いた簡略化のため変換器は平均化モデルを説明する説明図。FIG. 9 is an explanatory diagram for explaining an averaging model for a converter used for simulation for simplification. 瞬時値シミュレーション結果の波形表示箇所を示す図。The figure which shows the waveform display location of an instantaneous value simulation result. シミュレーションで用いた3LGシーケンス及び1LGシーケンスを示す図。The figure which shows the 3LG sequence and 1LG sequence used in the simulation. 3LGシーケンスのシミュレーション結果を示す図。The figure which shows the simulation result of a 3LG sequence. 1LGシーケンスのシミュレーション結果を示す図。The figure which shows the simulation result of 1LG sequence. 一般的なベクトル制御に基づく電流制御のブロック図。FIG. 2 is a block diagram of current control based on general vector control. PLLのブロック図。FIG. 2 is a block diagram of a PLL. 電圧制御型仮想同期機制御を具備する仮想同期機を系統に接続した模式図。The schematic diagram which connected the virtual synchronous machine provided with the voltage control type virtual synchronous machine control to the system. 方程式の解に基づいた仮想同期機制御の一例を示すブロック図。FIG. 3 is a block diagram showing an example of virtual synchronous machine control based on the solution of the equation.

以下、実施形態に基づいて本発明を詳細に説明する。   Hereinafter, the present invention will be described in detail based on embodiments.

(実施形態1)
図1には、本発明の実施形態1に係る電圧制御型仮想同期機の電圧制御型仮想同期機制御装置のブロック図を示す。なお、電圧制御型仮想同期機制御装置は、一般的な変換器に組み込むことにより、過電流抑制する電圧制御型仮想同期機制御を具備する変換器として機能させるものである。なお、変換器自体は従来と同一であるから、ここでの説明は省略する。
(Embodiment 1)
FIG. 1 is a block diagram of a voltage-controlled virtual synchronous machine control device for a voltage-controlled virtual synchronous machine according to Embodiment 1 of the present invention. The voltage-controlled virtual synchronous machine control device is incorporated in a general converter to function as a converter having a voltage-controlled virtual synchronous machine control for suppressing an overcurrent. Since the converter itself is the same as the conventional one, the description here is omitted.

図1に示すように、電圧制御型仮想同期機制御装置1は、電圧制御型仮想同期機制御部10と、補整制御部20とからなる。   As shown in FIG. 1, the voltage-controlled virtual synchronous machine control device 1 includes a voltage-controlled virtual synchronous machine control unit 10 and a compensation control unit 20.

電圧制御型仮想同期機制御部10は、一般的な電圧制御型仮想同期機制御を行う制御部と同じ構成を有し、仮想同期機電圧指令値ベクトルvVorderと、仮想同期機の回転子位相角を受け取り座標変換する座標変換部11と、座標変換したデータに基づいてパルス幅制御のデューティ比を決定するPWM制御部12とを有する。本実施形態では、座標変換部11の前段に加算器13が設けられている。 The voltage-controlled virtual synchronous machine control unit 10 has the same configuration as a control unit that performs general voltage-controlled virtual synchronous machine control, and includes a virtual synchronous machine voltage command value vector vV order and a rotor phase of the virtual synchronous machine. It has a coordinate conversion unit 11 that receives a corner and converts the coordinates, and a PWM control unit 12 that determines the duty ratio of the pulse width control based on the coordinate-converted data. In the present embodiment, an adder 13 is provided before the coordinate transformation unit 11.

補整制御部20は、測定された系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとを受け取り、両者の電圧差Vdiffを求めると共に、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとを結ぶ直線と、系統電圧ベクトルvVsysを中心とする半径rの制御円Sとの交点を補整出力電圧ベクトルvVconv−revとし、仮想同期機電圧指令値ベクトルvVorderを始点とし補整出力電圧ベクトルvVconv−revを終点とする補整電圧ベクトルvVoccを求め、これを出力する補整電圧演算部21と、スイッチ素子22とを具備する。スイッチ素子22は、補整電圧演算部21で求めた電圧差Vdiffが前記制御円の半径rと同じ又は小さい場合にはオフとなり、加算器13へは何も出力せず、電圧差Vdiffが前記制御円の半径rより大きい場合にオンになって補整電圧演算部21からの出力である補整電圧ベクトルvVoccを加算器13に出力するように制御される。 The compensation control unit 20 receives the measured system voltage vector vV sys and the virtual synchronous machine voltage command value vector vV order , obtains a voltage difference V diff between the two, and also obtains the system voltage vector vV sys and the virtual synchronous machine voltage command value. An intersection of a straight line connecting the vector vV order and a control circle S having a radius r centered on the system voltage vector vV sys is defined as a corrected output voltage vector vV conv-rev , and a virtual synchronous machine voltage command value vector vV order is defined as a starting point. It comprises a compensation voltage calculation unit 21 for obtaining a compensation voltage vector vV occ having the compensation output voltage vector vV conv-rev as an end point and outputting the compensation voltage vector vV occ , and a switch element 22. The switch element 22 is turned off when the voltage difference V diff obtained by the compensation voltage calculation unit 21 is equal to or smaller than the radius r of the control circle, does not output anything to the adder 13, and the voltage difference V diff is is controlled to output a compensation voltage vector vV occ is output from the compensation voltage calculation unit 21 is turned on to the adder 13 is greater than the radius r of the control circle.

これにより、電圧差Vdiffが前記制御円の半径rと同じ又は小さい場合には、補整制御部20から加算器13へは何も出力されないので、仮想同期機電圧指令値ベクトルvVorderがそのまま座標変換部11へ入力され、仮想同期機電圧指令値ベクトルvVorderがそのまま電圧制御型仮想同期機の出力電圧Vconvとなり、一方、電圧差Vdiffが前記制御円の半径rより大きい場合には補整電圧演算部21からの出力である補整電圧ベクトルvVoccが加算器13に出力されるので、仮想同期機電圧指令値ベクトルvVorderに補整電圧ベクトルvVoccが加算された補整出力電圧ベクトルvVconv−revが補整出力指令値として座標変換部11へ出力され、この結果、補整出力電圧ベクトルvVconv−revが電圧制御型仮想同期機の出力電圧Vconvとなる。 Accordingly, when the voltage difference V diff is equal to or smaller than the radius r of the control circle, nothing is output from the compensation control unit 20 to the adder 13, and the virtual synchronous machine voltage command value vector vV order is used as it is as the coordinates. Input to the converter 11, the virtual synchronous machine voltage command value vector vV order becomes the output voltage V conv of the voltage-controlled virtual synchronous machine as it is, while if the voltage difference V diff is larger than the radius r of the control circle, compensation is performed. since the compensation voltage vector vV occ is output from the voltage calculating portion 21 is output to the adder 13, compensation virtual synchronous machine voltage command value vector vV order voltage vector vV occ is summed compensated output voltage vector vV Conv- rev is output to the coordinate conversion unit 11 as a compensated output command value. As a result, the compensated output voltage vector vV conv-rev is the output voltage V conv of the voltage controlled virtual synchronous machine.

以上の制御を模式的に示すと図2のようになる。   The above control is schematically shown in FIG.

図2は、出力電圧指令値と測定された系統電圧値とをD軸及びQ軸からなる回転座標系に変換した系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderを回転座標軸に示したものであり、系統電圧ベクトルvVsysの終点である系統電圧値を中心とする半径rの制御円Sを示したものである。半径rは予め設定された設定値である。なお、DQ変換は仮想同期機の回転子位相基準で実施され、仮想同期機電圧指令値ベクトルvVorderは必ずD軸上に存在する。 FIG. 2 shows a system voltage vector vV sys and a virtual synchronous machine voltage command value vector vV order obtained by converting the output voltage command value and the measured system voltage value into a rotating coordinate system including the D axis and the Q axis on the rotating coordinate axis. And shows a control circle S having a radius r and centered on the system voltage value which is the end point of the system voltage vector vV sys . The radius r is a preset value. The DQ conversion is performed on the basis of the rotor phase of the virtual synchronous machine, and the virtual synchronous machine voltage command value vector vV order always exists on the D axis.

図2(a)は、系統が比較的正常で、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとの電圧差Vdiffが小さく、仮想同期機電圧指令値ベクトルvVorderがそのまま出力電圧Vconvとなる状態を示す。 FIG. 2A shows that the system is relatively normal, the voltage difference V diff between the system voltage vector vV sys and the virtual synchronous machine voltage command value vector vV order is small, and the virtual synchronous machine voltage command value vector vV order is output as it is. This shows a state where the voltage becomes Vconv .

図2(b)は、系統が擾乱して、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとの電圧差Vdiffが大きくなり、仮想同期機電圧指令値ベクトルvVorderが制御円Sの外に出た場合であり、仮想同期機電圧指令値ベクトルvVorderに補整電圧ベクトルvVoccが加算された補整出力電圧ベクトルvVconv−revが座標変換部11へ出力され、この結果、補整出力電圧ベクトルvVconv−revが電圧制御型仮想同期機の出力電圧Vconvとなるように制御される状態を示している。 In FIG. 2B, the system is disturbed, the voltage difference V diff between the system voltage vector vV sys and the virtual synchronous machine voltage command value vector vV order becomes large, and the virtual synchronous machine voltage command value vector vV order becomes the control circle. In this case, the corrected output voltage vector vV conv-rev obtained by adding the corrected voltage vector vV oc to the virtual synchronous machine voltage command value vector vV order is output to the coordinate conversion unit 11, and as a result, the correction is performed. It shows a state in which the output voltage vector vV conv-rev is controlled to be the output voltage V conv of the voltage-controlled virtual synchronous machine.

ここで、補整制御部20での制御をさらに具体的に説明する。
まず、仮想同期機電圧指令値Vorderと系統電圧Vsysの絶対値の差Vdiffを計算する。
Here, the control in the compensation control unit 20 will be described more specifically.
First, a difference V diff between the virtual synchronous machine voltage command value V order and the absolute value of the system voltage V sys is calculated.

diff=|Vorder−VsysV diff = | V order −V sys |

次いで、絶対値の差Vdiffがrを超えていた場合、仮想同期機電圧指令値Vorderに補整電圧Vdcor、Vqcorを加える。補整電圧Vdcor、Vqcorは、補整電圧ベクトルvVocc−revに対応する。 Next, when the absolute value difference V diff exceeds r, the compensation voltages V dcor and V qcor are added to the virtual synchronous machine voltage command value V order . The compensation voltages V dcor and V qcor correspond to the compensation voltage vector vVocc-rev .

このとき加える補整電圧Vdcor、Vqcorは、最終的な電圧制御型仮想同期機の出力電圧Vconvが制御円S内に収まるように、仮想同期機電圧指令値Vorderからみて系統電圧値Vsys方向に補整を加えるものである。具体的な値としては以下の補整電圧Vdcor、VqcorをそれぞれD軸、Q軸電圧に加える。 The compensation voltages V dcor and V qcor added at this time are determined based on the virtual synchronous machine voltage command value V order so that the final output voltage V conv of the voltage controlled virtual synchronous machine falls within the control circle S. The correction is performed in the sys direction. As specific values, the following compensation voltages V dcor and V qcor are added to the D-axis and Q-axis voltages, respectively.

補整電圧Vdcor、Vqcor(それぞれ、仮想同期機電圧指令値VorderのD軸電圧、Q軸電圧)を求める式(1)は以下の通りである。 Equation (1) for calculating the compensation voltages V dcor and V qcor (the D-axis voltage and the Q-axis voltage of the virtual synchronous machine voltage command value V order , respectively) is as follows.

dcor=(Vdsys−Vorder)×(Vdiff−r)/Vdiff
qcor=Vqsys×(Vdiff−r)/Vdiff ・・・(1)
V dcor = (V dsys -V order ) × (V diff -r) / V diff
V qcor = V qsys × (V diff -r) / V diff ··· (1)

以上の実施形態1の補整制御部20を備える電圧制御型仮想同期機制御装置の制御ブロック図の一例を図3に示す。   FIG. 3 shows an example of a control block diagram of the voltage-controlled virtual synchronous machine control device including the compensation control unit 20 according to the first embodiment.

図3は、図14の制御ブロック図の仮想同期機電圧指令値Vorderの代わりに、補整制御部20を介しての制御を付加したものである。図示するように、補整電圧演算部21は、系統電圧値Vdsys、Vqsysと、制御円Sの半径r及び仮想同期機電圧指令値Vorderが入力され、上記式(1)より、補整電圧Vdocc、Vqoccを求めて出力する。スイッチ素子22は、電圧補整フラグFdiffにより制御され、オン状態で補整電圧Vdocc、Vqoccを出力し、オフ状態では0を出力する。ここで、Vdiff>rであれば1でオンとなり、Vdiff≦rであれば0でオフとなる。加算器13は、スイッチ素子22がオン状態では、仮想同期機電圧指令値Vorderと補整電圧Vdocc、Vqoccとを加算してVdconv、Vqconvを出力し、スイッチ素子22がオフ状態では、仮想同期機電圧指令値VorderをそのままVdconv、Vqconvとして出力する。 FIG. 3 is obtained by adding control via the compensation control unit 20 instead of the virtual synchronous machine voltage command value V order in the control block diagram of FIG. As shown in the figure, the compensation voltage calculation unit 21 receives the system voltage values V dsys and V qsys , the radius r of the control circle S and the virtual synchronous machine voltage command value V order, and calculates the compensation voltage from the above equation (1). V docc and V qoc are obtained and output. The switch element 22 is controlled by the voltage compensation flag F diff and outputs compensation voltages V docc and V qoc in the on state, and outputs 0 in the off state. Here, if V diff > r, it turns on at 1; if V diff ≤r, it turns off at 0. The adder 13, the switch element 22 is turned on, the virtual synchronous machine voltage command value V order the compensation voltage V DocC, V Qocc and an addition to V Dconv, outputs V QCONV, the switch element 22 is OFF state , And outputs the virtual synchronous machine voltage command value V order as V dconv and V qconv as they are.

なお、図3の例では、制御円Sの半径rを可変としており、過電流フラグFocにより、変換器電流が閾値以下ならr、閾値を超えるとrとなるように変更される。 In the example of FIG. 3, the radius r of the control circle S is variable, and is changed by the overcurrent flag F oc so that the converter current becomes r 1 if the converter current is equal to or less than the threshold, and r 2 if the converter current exceeds the threshold.

以上説明した補整制御部20では、補整電圧演算部21で常に補整電圧ベクトルvVoccを求め、これを出力するようにし、電圧差Vdiffが半径rより大きい場合のみに、電圧制御型仮想同期機制御部10の加算器13へ補整電圧ベクトルvVoccを出力するようにしたが、補整制御はこれに限定されず、電圧差Vdiffが半径rより大きい場合のみに補整電圧ベクトルvVoccを求め、これを出力するようにしてもよい。 In the compensation control unit 20 described above, the compensation voltage calculation unit 21 always calculates the compensation voltage vector vV occ and outputs the compensation voltage vector vV occ. Only when the voltage difference V diff is larger than the radius r, the voltage control type virtual synchronous machine is used. was designed to output a compensation voltage vector vV occ to the adder 13 of the control unit 10, correction control is not limited to this, the voltage difference V diff seek compensation voltage vector vV occ only if larger radius r, This may be output.

また、電圧制御型仮想同期機制御部10で仮想同期機電圧指令値ベクトルvVorderが補整される場合に、仮想同期機電圧指令値ベクトルvVorderに加算器13で補整電圧ベクトルvVoccを加算するようにしたが、これに限定されず、補整が必要となる場合には、補整制御部20から補整出力電圧ベクトルvVconv−revを出力するようにし、仮想同期機電圧指令値ベクトルvVorderに替えて補整出力電圧ベクトルvVconv−revが座標変換部11に入力されるようにしてもよい。 Further, when the virtual synchronous machine voltage command value vector vV order is compensated by the voltage-controlled virtual synchronous machine control unit 10, the compensated voltage vector vVocc is added by the adder 13 to the virtual synchronous machine voltage command value vector vV order. However, the present invention is not limited to this. If compensation is required, the compensation output voltage vector vV conv-rev is output from the compensation control unit 20 and replaced with the virtual synchronous machine voltage command value vector vV order . Thus, the corrected output voltage vector vVconv -rev may be input to the coordinate conversion unit 11.

さらに、電圧制御型仮想同期機制御部10の構成は特に限定されず、従来から公知の電圧制御型仮想同期機制御を行うものであればよい。   Further, the configuration of the voltage-controlled virtual synchronous machine control unit 10 is not particularly limited, and may be any as long as it performs conventionally known voltage-controlled virtual synchronous machine control.

また、制御円Sの半径rは、過電流をどの程度抑制したいかなどにより決定されるが、電圧制御型仮想同期機制御が模擬している模擬発電機のリアクトル成分値を参照して求めるのが好ましい。   Further, the radius r of the control circle S is determined depending on how much overcurrent is to be suppressed. However, the radius r is determined by referring to the reactor component value of the simulated generator simulated by the voltage-controlled virtual synchronous machine control. Is preferred.

例えば、リアクトル値がR(pu)の場合、r=R±20%程度とするのが好ましい。   For example, when the reactor value is R (pu), it is preferable that r = R ± 20%.

また、半径rは固定値でなくてもよく、系統の状態に合わせて変更するようにしてもよい。   Further, the radius r may not be a fixed value and may be changed according to the state of the system.

(実施形態2)
上述した実施形態では、補整出力電圧ベクトルvVconv−revを、系統電圧ベクトルvVsysと仮想同期機電圧指令値ベクトルvVorderとを結ぶ直線と、制御円Sとの交点としたが、これに限定されるものではない。本実施形態は、補整出力電圧ベクトルvVconv−revの他の例を示す。
(Embodiment 2)
In the above-described embodiment, the compensated output voltage vector vV conv-rev is the intersection of the control circle S with the straight line connecting the system voltage vector vV sys and the virtual synchronous machine voltage command value vector vV order , but is not limited to this. It is not something to be done. This embodiment shows another example of the compensated output voltage vector vV conv-rev .

本実施形態の補整出力電圧ベクトルvVconv−revを図4に示す。図示するように、本実施形態の補整出力電圧ベクトルvVconv−revは、系統電圧値VsysのベクトルvVsys又は当該ベクトルを延長した直線と制御円Sとの2つの交点のうち出力電圧指令値Vorderに近い電圧値を示すベクトルとしたものである。 FIG. 4 shows the compensated output voltage vector vVconv -rev of the present embodiment. As shown, the adjusting an output voltage vector vV conv-rev of the present embodiment, the output voltage command value of the two intersection points of the straight line and the control circle S was extended vector vV sys or the vector of the system voltage value V sys This is a vector indicating a voltage value close to V order .

本実施形態は、補整出力電圧ベクトルvVconv−revを変更した以外は、基本的には、実施形態1と同様であり、仮想同期機電圧指令値ベクトルvVorderが制御円Sの外に出た場合に補整出力電圧ベクトルvVconv−revを出力するものであり、重複する説明は省略する。 This embodiment is basically the same as the first embodiment except that the compensated output voltage vector vV conv-rev is changed, and the virtual synchronous machine voltage command value vector vV order goes out of the control circle S. In this case, the corrected output voltage vector vV conv-rev is output, and a duplicate description will be omitted.

本実施形態の補整出力電圧ベクトルvVconv−revの具体的な求めからは以下の通りである。 The specific calculation of the compensated output voltage vector vVconv -rev in the present embodiment is as follows.

図4の場合、仮想同期機電圧指令値Vorderが制御円S内に収まるように、零点から系統電圧値Vsys方向に延長するものである。具体的な値としては以下の補整電圧Vdcor、VqcorをそれぞれD軸、Q軸電圧に加える。 In the case of FIG. 4, the virtual synchronous machine voltage command value V order is extended in the direction of the system voltage value V sys from the zero point so that the virtual synchronous machine voltage command value V order falls within the control circle S. As specific values, the following compensation voltages V dcor and V qcor are added to the D-axis and Q-axis voltages, respectively.

dconv=Vdsys×(|Vsys|+|r|)/|Vsys
qconv=Vqsys×(|Vsys|+|r|)/|Vsys
V dconv = V dsys × (| V sys | + | r |) / | V sys |
V qconv = V qsys × (| V sys | + | r |) / | V sys |

なお、補整出力電圧ベクトルvVconv−revの決定の仕方はこれに限定されず、制御円S内に収まる補整出力電圧ベクトルvVconv−revとすればよいが、電圧制御型仮想同期機制御を行いながら補整するという趣旨から、制御円S内で電圧値ができるだけ仮想同期機電圧指令値Vorderに近いものとするのが好ましく、この観点からは制御円S上が好ましい。また、補整の趣旨から、仮想同期機電圧指令値Vorderと系統電圧値Vsysとの間で制御円S内で電圧値が仮想同期機電圧指令値Vorderに近いものとするのが好ましい。 The method of determining the compensated output voltage vector vV conv-rev is not limited to this, and may be a compensated output voltage vector vV conv-rev that falls within the control circle S. It is preferable that the voltage value within the control circle S be as close as possible to the virtual synchronous machine voltage command value V order from the viewpoint of compensation while the control circle S is used. Further, for the purpose of compensation, it is preferable that the voltage value is close to the virtual synchronous machine voltage command value V order within the control circle S between the virtual synchronous machine voltage command value V order and the system voltage value V sys .

(試験例)
本発明の効果を検証するため、瞬時値シミュレーションによる動作検証を行った。なお、シミュレーションには瞬時値解析プログラムであるXTAP(eXpandable Transient Analysis Program)を使用してシミュレーションを実施した。
(Test example)
In order to verify the effect of the present invention, operation verification by instantaneous value simulation was performed. The simulation was performed using an instantaneous value analysis program, XTAP (eXpandable Transient Analysis Program).

図5にシミュレーションに使用した解析対象の解析対象系統の概略図を示す。仮想同期機制御を具備する変換器設備として、変換器直流側には理想電圧源を接続したものを使用している。本来は,変換器直流側には電池や、分散型電源や、直流送電網を介したほかの交流系統などの諸設備が想定されるが、本試験では、電圧型仮想同期機制御の過電流抑制のみ検証する目的からこれらの設備を理想化し、理想電圧源で代替した。   FIG. 5 shows a schematic diagram of an analysis target system used in the simulation. As the converter equipment provided with the virtual synchronous machine control, one having an ideal voltage source connected to the converter DC side is used. Originally, various equipment such as a battery, a distributed power source, and other AC systems via a DC power transmission network is assumed on the converter DC side. These facilities were idealized for the purpose of verifying only suppression, and replaced with ideal voltage sources.

交流系統は無限大母線模擬の電圧源と短絡容量模擬の抵抗とリアクトルにより構成されている。ここで、短絡容量比は2回線時6.93に設定した。交流側の事故地点は変換器至近端とし、交流事故は事故回線を遮断器により開放することで除去した。   The AC system includes a voltage source simulating an infinite bus, a resistor and a reactor simulating a short-circuit capacity. Here, the short-circuit capacity ratio was set to 6.93 for two lines. The accident point on the AC side was near the converter, and the AC accident was eliminated by opening the accident line with a circuit breaker.

なお、計算の簡略化のため変換器は平均化モデルを使用している。平均化モデルとは、図6(a)に示す詳細な変換器モデルのようにスイッチングを模擬せず、図6(b)に示すように、スイッチング周期を平均化区間としてリプルを平均化するモデルである。回路規模の削減に加えて、計算時間刻みの延伸も可能であり、計算量の軽減効果は高い。   Note that the converter uses an averaging model to simplify the calculation. The averaging model is a model that does not simulate switching as in the detailed converter model shown in FIG. 6A, but averages ripples using a switching cycle as an averaging section as shown in FIG. 6B. It is. In addition to the reduction in the circuit scale, the calculation time can be extended in increments, and the effect of reducing the amount of calculation is high.

表1に計算に用いた各種条件を示す。また、図7に瞬時値シミュレーション結果の波形表示箇所を示す。本シミュレーションにおいて各系統擾乱はそれぞれ3パターンの制御で実施している。なお、過電流制御ありは実施形態1を模したものであり、制御円Sは実施形態1のものである。   Table 1 shows various conditions used for the calculation. FIG. 7 shows the waveform display locations of the instantaneous value simulation results. In this simulation, each system disturbance is implemented by controlling three patterns. Note that with overcurrent control is a model of the first embodiment, and the control circle S is that of the first embodiment.

Case a: 過電流抑制制御無
Case b: 過電流抑制制御有(制御円Sの半径rが0.2pu固定)
Case c: 過電流抑制制御有(定常時制御円Sの半径rが0.2pu、1.2puを超える過電流発生時半径rが0.1pu)
Case a: No overcurrent suppression control
Case b: With overcurrent suppression control (radius r of control circle S is fixed at 0.2pu)
Case c: With overcurrent suppression control (radius r of control circle S in steady state is 0.2 pu, radius r when overcurrent occurs exceeding 1.2 pu is 0.1 pu)

Figure 2020043688
Figure 2020043688

図8(a)には、3相地絡事故(3LG)のシーケンスを示す。3LG発生から交流遮断器が開放されるまでの時間を0.1秒(5サイクル)に設定している。交流事故は事故回線を開放することによって除去される。   FIG. 8A shows a sequence of a three-phase ground fault (3LG). The time from the occurrence of 3LG to the opening of the AC circuit breaker is set to 0.1 second (5 cycles). AC accidents are eliminated by opening accident lines.

図8(b)には、1相地絡事故(1LG)シーケンスを示す。1LG発生から交流遮断器が開放されるまでの時間を0.1秒(5サイクル)に設定している。交流事故は事故回線を開放することによって除去され、このとき事故回線は3相共に開放されるものとする。   FIG. 8B shows a one-phase ground fault (1LG) sequence. The time from the occurrence of 1 LG to the opening of the AC circuit breaker is set to 0.1 second (5 cycles). The AC accident is eliminated by opening the accident line, and at this time, the accident line is opened for all three phases.

以上の条件でシミュレーションを実施した結果を図9及び図10に示す。   9 and 10 show the results of the simulation performed under the above conditions.

図9は、3LG発生時のVsys、Iconvの拡大図であり、(a)〜(c)は、上述したCase a〜cに対応している。(a)の過電流抑制制御がない場合、変換器には最大9.19puの過電流が流れた(変換器電流定格1458Apeak)が、これに対し、(b)、(c)のcase b、cの過電流抑制制御ありの場合、それぞれ1.58pu、1.37puとなり、過電流抑制効果が確認できた。 FIG. 9 is an enlarged view of V sys and I conv when 3LG occurs, and (a) to (c) correspond to Cases a to c described above. In the absence of the overcurrent suppression control of (a), a maximum of 9.19 pu overcurrent flowed in the converter (converter current rating of 1458 Apeek), whereas the cases (b) and (c) of case b, In the case where the overcurrent suppression control of c was performed, the respective values were 1.58 pu and 1.37 pu, and the overcurrent suppression effect was confirmed.

図10は、1LG発生時のVsys、Iconvの拡大図であり、(a)〜(c)は、上述したCase a〜cに対応している。(a)の過電流抑制制御がない場合、変換器には最大2.94puの過電流が流れたが、これに対し、case b、cの過電流抑制制御ありの場合、それぞれ1.64pu、1.45puとなり、過電流抑制効果が確認された。 FIG. 10 is an enlarged view of V sys and I conv when one LG occurs, and (a) to (c) correspond to Cases a to c described above. When there is no overcurrent suppression control of (a), an overcurrent of a maximum of 2.94 pu flows through the converter. On the other hand, when overcurrent suppression control of case b and c is performed, 1.64 pu, It was 1.45 pu, and an overcurrent suppressing effect was confirmed.

1 電圧制御型仮想同期機制御装置
10 電圧制御型仮想同期機制御部
11 座標変換部
12 PWM制御部
13 加算器
20 補整制御部
21 補整電圧演算部
22 スイッチ素子
REFERENCE SIGNS LIST 1 voltage-controlled virtual synchronous machine control device 10 voltage-controlled virtual synchronous machine control unit 11 coordinate conversion unit 12 PWM control unit 13 adder 20 compensation control unit 21 compensation voltage calculation unit 22 switch element

Claims (7)

変換器に対して電圧制御型仮想同期機制御を行う電圧制御型仮想同期機制御装置であって、
電圧制御型仮想同期機制御を行う制御部を具備し、
前記制御部は、当該制御部に入力される出力電圧指令値を補整する補整手段を具備し、
前記補整手段は、前記出力電圧指令値と測定された系統電圧値とをD軸及びQ軸からなる回転座標系に変換し、前記系統電圧値を中心とする半径rの制御円をリミッタとして用い、前記出力電圧指令値が前記制御円の外に出たことを条件とし、前記制御円上又はその内側に存在する補整出力電圧指令値を前記出力電圧指令値とする
ことを特徴とする電圧制御型仮想同期機制御装置。
A voltage-controlled virtual synchronous machine control device that performs voltage-controlled virtual synchronous machine control on a converter,
A control unit that performs voltage control type virtual synchronous machine control is provided,
The control unit includes a compensation unit that compensates an output voltage command value input to the control unit,
The compensation means converts the output voltage command value and the measured system voltage value into a rotating coordinate system including a D axis and a Q axis, and uses a control circle having a radius r centered on the system voltage value as a limiter. Voltage control characterized in that the output voltage command value is out of the control circle, and a compensated output voltage command value existing on or inside the control circle is the output voltage command value. Type virtual synchronous machine controller.
前記補整出力指令値が、前記制御円上で且つ前記系統電圧値に近い点であることを特徴とする請求項1記載の電圧制御型仮想同期機制御装置。   The voltage-controlled virtual synchronous machine control device according to claim 1, wherein the compensation output command value is a point on the control circle and close to the system voltage value. 前記半径rが、前記電圧制御型仮想同期機制御が模擬している模擬発電機のリアクトル成分値から求められた値であることを特徴とする請求項1又は2記載の電圧制御型仮想同期機制御装置。   3. The voltage-controlled virtual synchronous machine according to claim 1, wherein the radius r is a value obtained from a reactor component value of a simulated generator simulated by the voltage-controlled virtual synchronous machine control. Control device. 前記補整手段は、前記出力電圧指令値のベクトルvVorderと前記系統電圧値のベクトルvVsysとの電圧差Vdiffがrより大きい場合に、前記出力電圧指令値Vorderと前記系統電圧値Vsysとの間にある電圧値Vconvであり且つ前記制御円上又はその内側に入る補整出力電圧ベクトルvVconv−revを決定し、この補整出力電圧ベクトルvVconv−revを前記補整出力電圧指令値とする
ことを特徴とする請求項1〜3の何れか一項に記載の電圧制御型仮想同期機制御装置。
When the voltage difference V diff between the vector vV order of the output voltage command value and the vector vV sys of the system voltage value is larger than r, the compensating means is configured to output the output voltage command value V order and the system voltage value V sys and a voltage value V conv and the determined control circle or compensate the output voltage vector vV conv-rev entering inside, the compensation output voltage command value of this compensation output voltage vector vV conv-rev located between the The voltage-controlled virtual synchronous machine control device according to any one of claims 1 to 3, wherein
前記補整出力電圧ベクトルvVconv−revが、前記出力電圧指令値VorderのベクトルvVorderと、前記系統電圧値VsysのベクトルvVsysとを結ぶ直線と前記制御円との交点へのベクトルであることを特徴とする請求項4記載の電圧制御型仮想同期機制御装置。 It said compensation output voltage vector vV conv-rev is, is the vector to the intersection of the vector vV order of the output voltage command value V order, and the straight line and the control circle connecting the vector vV sys of the system voltage value V sys 5. The voltage controlled virtual synchronous machine control device according to claim 4, wherein: 前記補整出力電圧ベクトルvVconv−revが、前記系統電圧値VsysのベクトルvVsys又は当該ベクトルを延長した直線と前記制御円との2つの交点のうち前記出力電圧指令値Vorderに近い電圧値を示すベクトルであることを特徴とする請求項4記載の電圧制御型仮想同期機制御装置。 Said compensation output voltage vector vV conv-rev is, the system voltage value the voltage value close to the output voltage command value V order of the two intersections between the vector vV sys or linear and the control circle extending the vector of V sys The voltage-controlled virtual synchronous machine control device according to claim 4, wherein the vector is a vector indicating the following. 請求項1〜6の何れか一項に記載の電圧制御型仮想同期機制御装置を具備する変換器であることを特徴とする電圧制御型仮想同期機。   A voltage-controlled virtual synchronous machine, comprising: a converter including the voltage-controlled virtual synchronous machine control device according to claim 1.
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