JP7063518B2 - Power-on reset circuit and semiconductor device - Google Patents

Description

The present invention relates to a power-on reset circuit and a semiconductor device.

The power-on-reset circuit is a circuit that automatically resets the powered circuit when the power is turned on and then releases the power-on reset circuit. That is, the power-on reset circuit has a function of resetting the powered circuit until the power supply voltage stabilizes and releasing the reset state when the power supply voltage stabilizes.

As a conventional technique of a power-on reset circuit, for example, one disclosed in Patent Document 1 is known. The power-on reset circuit disclosed in Patent Document 1 releases a reset when the first monitoring circuit for monitoring the power supply voltage and the power supply voltage monitored by the first monitoring circuit exceed the first predetermined value. It has an output circuit that outputs a signal and a control circuit that consumes less current than the first monitoring circuit, and the control circuit is monitored by a second monitoring circuit that monitors the power supply voltage and a second monitoring circuit. When the power supply voltage exceeds the second predetermined value higher than the first predetermined value, the suppression circuit that suppresses the current flowing through the first monitoring circuit and the power supply voltage monitored by the second monitoring circuit It is provided with a compensation circuit that compensates for the output of the reset release signal when the second predetermined value is exceeded. The power-on reset circuit according to Patent Document 1 aims at reducing current consumption.

Japanese Unexamined Patent Publication No. 2011-234241

By the way, in the power-on reset circuit, since there are a wide variety of powered circuits to be power-on reset, there are various problems peculiar to the power-on reset circuit. For example, the voltage of the power-on reset signal sent from the power-on reset circuit to the powered circuit (hereinafter, may be referred to as "reset voltage") or the voltage for releasing the power-on reset (hereinafter, referred to as "reset release voltage"). There are), widening the selection range, and suppressing variations in the reset voltage or reset release voltage (hereinafter, may be referred to as "reset voltage, etc.").

First, problems related to the expansion of the selection range such as the reset voltage will be described. For example, consider a case where the reset release voltage is set to about 1.2V. Here, as the reset release voltage, a voltage generated when a predetermined current is passed through a diode made of MOS (Metal Oxide Semiconductor) or a diode made of bipolar transistor is used. In this case, since the threshold value of the MOS transistor is about 0.7V, a larger current must be passed in order to output about 1.2V. That is, the current increases during normal operation. Further, since it is difficult to reset at a high voltage, an IC (Integrated Circuit) may be required exclusively for resetting, for example, for resetting the microcomputer itself.

On the other hand, there are the following problems with respect to variations in the reset voltage and the like. That is, the reset voltage and the like may vary due to variations in the elements or due to design problems (designs for which suppression of element variations cannot be considered, etc.). When it is necessary to suppress variations in the reset voltage and the like, it is necessary to adjust the reset voltage and the reset release voltage for each sample, that is, trimming. In particular, under the trend of lowering the voltage of semiconductor integrated circuits, considering the power supply specifications of the powered circuit, the voltage that can actually be operated, etc., there is a concern that the yield may deteriorate due to the variation of the reset voltage and the like. In this case, trimming is indispensable. However, it is very difficult to trim while performing a reset. Trimming is generally performed by setting a predetermined circuit constant or the like with a trimming code, but since the latch circuit such as the CPU (Central Processing Unit) inside the power-supplied circuit is reset during the reset, the trimming code is read. Because it cannot be done.

It is conceivable to avoid the above problem by using a fuse. The fuse physically cuts the wiring and the resistance due to polysilicon and records it. Therefore, the trimming code can be read even during reset before and during reset without passing through a latch circuit such as a flip-flop. However, the method using a fuse has a problem that the manufacturing process is complicated because a test step for trimming and a step of cutting the fuse are added to the manufacturing process. There is also the problem of increased test costs. Further, since the fuse has a relatively large area, there is a problem that the layout area increases.

Here, with reference to FIG. 11, a power-on reset circuit according to a comparative example corresponding to a wide voltage range and a wide power supply voltage start-up inclination (unit: V / s: Voltage per second: power supply voltage rise speed) will be described. .. FIG. 11A shows a circuit diagram of the power-on reset circuit 100 using the threshold voltage of the MOS diode for generating the reset signal. As shown in FIG. 11, the power-on reset circuit 100 includes a P-channel type MOS field-effect transistor (hereinafter referred to as “MeOH transistor”) P100, a current source (current source) CS1, and an inverter INV100.

The source of the polyclonal transistor P100 is connected to the power supply VDDL, the gate is connected to the ground, and the drain is connected to the input of the inverter INV100 and the current source CS1. The current source CS1 is connected so as to flow into the ground. out01a01 represents an output node of the inverter INV100, and node01a01 represents a connection node (input node of the inverter INV100) between the polyclonal transistor P100 and the current source CS1. In this example, a mode using the threshold voltage of the MOS diode will be described as an example, but the present invention is not limited to this, and a mode using the threshold voltage of the bipolar diode may be used.

Generally, the threshold voltage of a MOS diode or a bipolar diode changes depending on the current flowing through the MOS diode or the bipolar diode. Then, when the power supply voltage becomes a voltage equal to or higher than the threshold voltage of the MOS diode or the bipolar diode, the reset to the powered circuit is released.

Next, the operation of the power-on reset circuit 100 will be described with reference to FIGS. 11B, 11C, and 11D. 11 (b), (c), and (d) show voltage waveforms of each part of the power-on reset circuit 100 shown in FIG. 11 (a). That is, FIG. 11A shows the relationship between the power supply VDDL and the threshold voltage VT of the polyclonal transistor P100, FIG. 11C shows the waveform of the node node01a01, and FIG. 11D shows the waveform of the output node out01a01. ing.

While the power supply VDDL is rising and is equal to or lower than the threshold voltage VT of the polyclonal transistor P100, the polyclonal transistor P100 is not turned on. Therefore, since the current source CS1 is turned on more strongly than the polyclonal transistor P100, the node node01a01 is at a low level (hereinafter, “L”) as shown in FIG. 11 (c). Further, when the power supply VDDL rises and the power supply VDDL becomes equal to or higher than the threshold voltage VT of the polyclonal transistor P100, the polyclonal transistor P100 is turned on and a current of the current source CS1 or higher is passed. As a result, the node node01a01 becomes a high level (hereinafter, “H”). At that time, L is output from the output node out01a01.

As a result, the signal due to the voltage change of the node node01a01 becomes a signal that outputs L when the power supply VDDL is low and outputs H when the power supply VDDL exceeds the threshold voltage VT.
Therefore, since the voltage change of the node node01a01 can be regarded as a signal for notifying the start of the power supply VDDL, this signal can be used as a power-on reset signal of the power supply VDDL (a signal that automatically resets when the power is turned on). .. The power-on reset circuit 100 is like the power-on reset circuit 100A shown in FIG. 11 (e) by using an N-channel type MOS field effect transistor (hereinafter, “MOS FET transistor”) N100, a current source CS2, and an inverter 101. It may be configured as.

According to the power-on reset circuit 100 shown in FIG. 11A, a relatively simple circuit configuration can be made, and in principle, resetting can be performed regardless of the rising speed of the power supply voltage. However, the problem is that the threshold voltage of the polyclonal transistor is about 0.7V. That is, this means that the voltage of the power supply VDDL at the time of releasing the power-on reset is around 0.7V, which means that the voltage of the power supply VDDL of about 0.7V is assumed when the rising speed of the power supply voltage is slow. Means that the logic circuit must start working. For example, when the voltage of the power supply VDDL during normal operation is 1.2V, the power-on reset release at 0.7V is too low as the release voltage. If two MOS transistors are connected in series and a two-threshold voltage method is used, the voltage of the power supply VDDL at the time of canceling the power-on reset needs to be 1.4V. In this case, the power-on reset is canceled regardless of the voltage of the power supply VDDL. Will not be done. There is also a means to increase the current flowing through the polyclonal transistor to make the threshold voltage VT of the polyclonal transistor about 0.9V, but in order to raise the threshold voltage VT, it is necessary to increase the current of the current source on the order of 100 times. be. That is, there is a problem that the current consumption during normal operation increases.

In this regard, the power-on reset circuit disclosed in Patent Document 1 is intended to reduce current consumption, but the voltage value itself of the power-on reset signal is not a problem.

The present invention has been made to solve the above-mentioned problems, and can generate a power-on reset signal and a reset release signal having a wide selection range and a higher voltage, and further eliminates the need for trimming as much as possible. It is an object of the present invention to provide a power-on reset circuit capable of reducing current consumption and a semiconductor device.

The power-on reset circuit according to the present invention is a power-on reset circuit that supplies a reset signal to a power-supplied circuit when a power supply is started, and uses a difference in voltage input to a pair of input units to control a voltage. A reference voltage generation unit including a differential unit that outputs and an output unit that feeds back a reference voltage generated using the control voltage to one of the pair of input units, and the control voltage that changes with the start of the power supply. It is provided with a comparison unit that performs a comparison operation with respect to the reference voltage to generate a reset release signal and supplies the reset release signal to the power supply circuit.

The semiconductor device according to the present invention comprises the above power-on reset circuit and a powered circuit to which power is supplied from the power supply and a reset signal is supplied from the power-on reset circuit when the power supply is started. It is prepared.

According to the present invention, it is possible to generate a power-on reset signal and a reset release signal having a wide selection range and a higher voltage, further eliminating the need for trimming as much as possible and reducing the current consumption. It has the effect of being able to provide a reset circuit and a semiconductor device.

(A) is a circuit diagram showing an example of the configuration of the power-on reset circuit according to the first embodiment, and (b) to (d) are diagrams showing operation waveforms of each part. (A) is an equivalent block diagram of the power-on reset circuit according to the first embodiment, and (b) compares the temperature fluctuation characteristic of the power-on reset signal with the temperature fluctuation characteristic of the power-on reset signal according to the prior art. It is a graph shown by. (A) and (b) are circuit diagrams showing a modification of the power-on reset circuit according to the first embodiment. (A) is a circuit diagram showing an example of the configuration of the power-on reset circuit according to the second embodiment, and (b) and (c) are diagrams showing operation waveforms of each part. (A) and (b) are diagrams for explaining the effect of hysteresis, and (c) is an equivalent block diagram of the power-on reset circuit according to the second embodiment. (A) is a circuit diagram showing an example of the configuration of the power-on reset circuit according to the third embodiment, (b) to (d) are diagrams showing operation waveforms of each part, and (e) is the third embodiment. It is an equivalent block diagram of the power-on reset circuit which concerns on. It is a circuit diagram which shows the modification of the power-on reset circuit which concerns on 3rd Embodiment. (A) is a circuit diagram showing an example of the configuration of the power-on reset circuit according to the fourth embodiment, and (b) to (d) are diagrams showing operation waveforms of each part. (A) is an equivalent block diagram of the power-on reset circuit according to the fourth embodiment, and (b) is an equivalent block diagram showing a modified example of the power-on reset circuit according to the fourth embodiment. (A) is a circuit diagram showing an example of the configuration of the power-on reset circuit according to the fifth embodiment, (b) to (d) are diagrams showing operation waveforms of each part, and (e) is the fifth embodiment. It is an equivalent block diagram of the power-on reset circuit which concerns on. (A) is a circuit diagram of a power-on reset circuit according to a comparative example, (b) to (d) are operation waveforms of each part, and (e) is a circuit diagram of a power-on reset circuit according to another comparative example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the present embodiment, as an example, a power-on reset circuit for detecting the voltage of the power supply VDDL of the logic system will be described as an example. As a feature of the logic system, it is necessary to initialize the logic circuit (release the power-on reset) after the voltage of the power supply VDDL becomes high to some extent. Here, the reason for resetting the power supply of the logic system is that the output of the level shifter is undefined because the latch circuit such as the flip-flop and the storage circuit constituting the logic system circuit are undefined in the initial state. In this embodiment, a case where the logic system power supply is reset will be described as an example, but the power-on reset circuit according to the present embodiment can also be used as a reset circuit for an analog power supply.

[First Embodiment]
The power-on reset circuit and the semiconductor device according to the present embodiment will be described with reference to FIGS. 1 to 3.

FIG. 1 shows a power-on reset circuit (hereinafter, “POR circuit”) 10 according to the present embodiment. As shown in FIG. 1 (a), the POR circuit 10 includes the polyclonal transistors P1, P2, P3, P4, the nanotube transistors N1, N2, N3, N4, N5, and the capacitance C1. In addition, the display such as "5um / 2um" shown in FIG. 1A shows an example of the size of the transistor, and each means "gate width / gate length".

The drain of the MIMO transistor N1 is connected to the drain of the polyclonal transistor P1, the drain of the MIMO transistor N2 is connected to the drain of the epitaxial transistor P2, and the sources of each of the nanotube transistors N1 and N2 are connected to the drain of the MIMO transistor N3. .. The gate of the NMOS transistor N1 is connected to ground (grounded), and the gate of the N Each source of the polyclonal transistors P1 and P2 is connected to the power supply VDDL, and the gate and drain of the polyclonal transistor P2 are connected to each other. The source of the IGMP transistor N3 is connected to the ground, and a bias voltage bias is applied to the gate of the nanotube transistor N3. The P-type MOS transistors P1 and P2 form a current mirror circuit, and the EtOAc transistors N1, N2 and N3 form a differential amplifier having the P-type MOS transistors P1 and P2 as a load and the MOSFET transistor N3 as a current source. There is. As will be described later, this differential amplifier has a function of generating a reference voltage vref (1V) and a pgate signal (corresponding to the "control voltage" according to the present invention) for generating a por signal which is a power-on reset signal. Hereinafter, this differential amplifier is referred to as a "differential unit 70". In the following description, the voltage of "node vref (1V)" is referred to as "reference voltage vref (1V)", the voltage of "node por" is referred to as "por signal", and the voltage of "node pgate" is referred to as "node pgate". It is called a "voltage signal". Further, a reference voltage that does not specify a voltage is called a "reference voltage vref".

The source of the ProLiant transistor P3 is connected to the power supply VDDL, the drain is connected to the gate of the MIMO transistor N2 and the drain of the MIMO transistor N4, and the gate is the voltage of the connection between the drain of the epitaxial transistor P1 and the drain of the MIMO transistor N1. A transistor signal is being supplied. The drain of the IGMP transistor N4 is connected to the drain of the polyclonal transistor P3 and the gate of the Now country transistor N2, the source is connected to the ground, and the bias voltage bias is supplied to the gate. That is, the nanotube transistor N4 acts as a current source. The polyclonal transistor P3 and the nanotube transistor N4 constitute an output unit 71 that outputs a reference voltage vref (1V) with a pgate signal as an input. In that sense, the differential unit 70 and the output unit 71 may be collectively referred to as a “reference voltage generation unit”. In other words, the reference voltage generator can be regarded as a negative feedback amplifier that generates the reference voltage vref (1V).

The source of the epitaxial transistor P4 is connected to the power supply VDDL, the drain is connected to the drain of the MIMO transistor N5, and the pgate signal is supplied to the gate. The drain of the IGMP transistor N5 is connected to the drain of the polyclonal transistor P4, the source is connected to ground, and the bias voltage bias is supplied to the gate. The polyclonal transistor P4 and the nanotube transistor N5 constitute a comparison unit 72 that performs a comparison operation between the pgate signal and the reference voltage vref (1V) and outputs a por signal that is a power-on reset signal.

FIG. 2A is a block diagram equivalently representing the POR circuit 10. As shown in FIG. 2A, in the POR circuit 10, one input IN1 is connected to ground, the reference voltage Vref (1V) is fed back to the other input IN2, and the por signal, which is a power-on reset signal, is output. Can be regarded as a circuit to do. The por signal is connected to a powered circuit which is a target circuit for power-on reset (not shown), and power-on reset is performed for the powered circuit.

As shown in FIG. 1A, in the POR circuit 10 according to the present embodiment, the MOSFET transistor N1 is a depletion type MOS field effect transistor (hereinafter, “DMOS”), and the MOSFET transistor N2 is a low threshold type MOS electric field. It is referred to as an effect transistor (hereinafter referred to as "LVT MOSFET"). The MOSFET is a MOS transistor in which an inversion layer is formed when the gate-source voltage VGS is 0 V, and the threshold voltage VT is generally negative.
On the other hand, the LVT µ is an enhancement type, and the threshold voltage VT is positive, but is lower than the standard threshold voltage VT. In the present embodiment, as an example, the threshold voltage VT of the NMOS transistor N1 (DMOS) is about −0.5 V, and the threshold voltage VT of the N

By configuring the differential stage with the NOTE transistors having different threshold voltage VTs in this way, it is possible to configure a circuit that generates the difference of the threshold voltage VT as the reference voltage. That is, the differential portion 70 of the POR circuit 10 has a difference (0.45V- (0.45V-) between the threshold voltage VT (= −0.5V) of the Now's transistor N1 and the threshold voltage VT (= 0.45V) of the norm transistor N2. -0.5V) = 0.95V≈1V) is output as the reference voltage vref. The voltage value of the reference voltage vref generated from the POR circuit 10 and the voltage value of the por signal can be adjusted by changing the threshold voltage VT of the nanotube transistors N1 and N2. For example, as the HCl transistor N2, a Normal VT µ whose threshold voltage VT is a standard value may be used instead of the LVT Transistor. If, for example, a Normal VT country having a threshold voltage VT of about 0.7 V is used as the IGMP transistor N2, the reference voltage vref of about 1 V can be set to about 1.3 V (see the POR circuit 10B shown in FIG. 3 (b)). .. Alternatively, the LVT monomers and the NORmalVT µ may be combined as the nanotube transistors N1 and N2. In this case, it is particularly suitable for lowering the voltage value of the reference voltage vref and the voltage value of the por signal.

FIGS. 1 (b), 1 (c), and 1 (d) show operation waveforms of each part of the POR circuit 10 as the power supply VDDL rises from the ground (0 V). FIG. 1B shows the position of the reference voltage vref (1V). As shown in FIG. 1 (c), the pgate signal changes substantially 0V until the power supply VDDL reaches vref (1V), and changes following the power supply of the power supply VDDL after reaching vref (1V). Further, as shown in FIG. 1D, the por signal rises at a predetermined position (for example, a position where the reference voltage vref (1V) is about 0.9V), and the voltage value rises as the power supply VDDL rises. , When the power supply VDDL reaches vref (1V), it goes down. That is, as the power supply VDDL rises, a por signal, which is a pulse-shaped power-on reset signal, is generated. In this case, the peak value of the por signal is about 1V.
As will be described later, in the POR circuit 10, the pgate signal has a predetermined voltage value due to the circuit configuration, and does not drop to 0V.

Hereinafter, the reason why the above-mentioned pgate signal and por signal are generated will be described. The differential unit 70 of the POR circuit 10 uses a characteristic that when the power supply VDDL is 1V (= voltage value of the reference voltage vref (1V)) or less, the epitaxial transistor P3 is turned on by a negative feedback configuration. That is, when the power supply VDDL is 1 V or less, the pgate signal is lowered in order to turn on the polyclonal transistor P3. Here, when the threshold voltage VT of the HCl transistor N2 (LVT Now) is expressed as "1 LVT", the pgate signal can be expressed by the following (Equation 1).
pgate = vref-1LVT ・ ・ ・ (Equation 1)
Here, the voltage between the source and drain of the nanotube transistor N2 is set to 0V. Further, it is considered that vref = VDDL (the reference voltage vref follows the power supply VDDL) in the voltage region to which the reset is applied.
That is, since vref = VDDL and the pgate signal is the drain terminal output of the HCl transistor N2, the pgate signal will not be less than the voltage represented by (Equation 1) which is the source voltage of the Now's transistor N2. .. The capacitance C1 shown in FIG. 1 is a capacitance for phase compensation.

In other words, when the start-up speed of the power supply is slow, it is preferable that the polyclonal transistor P3 is LVT FIGURE in view of the fact that VDDL = vref. This is because the voltage of the pgate signal does not drop below the source voltage of the MIMO transistor N2, and there is a possibility that the polyclonal transistor P3 cannot be turned on. However, this does not apply when a normal VT µ is used as the NaCl transistor N7 as in the POR circuit 10B shown in FIG. 3 (b). This is because the voltage of the pgate signal of the POR circuit 10B is lower than that when the IGMP transistor N2 is set to LVT µ, so that it is considered that the polyclonal transistor P3 can be strongly turned on. The POR circuit 10B is useful when, for example, the LVT MOS is not desired to be used due to reasons such as manufacturing process.

The operation of the POR circuit 10 will be described in more detail. As described above, in the region where the power supply VDDL does not reach 1V, the polyclonal transistor P3 is fully turned on in order to output the reference voltage vref (1V). That is, in the region where the power supply VDDL does not reach 1V, the pgate signal is lowered, so that the balance between the polyclonal transistor P3 and the IGMP transistor N4 is lost. That is, the polyclonal transistor P3 causes a current larger than the bias current of the Now Princess transistor N4. On the other hand, when the power supply VDDL exceeds 1V, the vref (1V) can output 1V, so that the pgate signal tries to turn off the polyclonal transistor P3. That is, a stable state exists in the pgate signal, and the stable state is a state in which the polyclonal transistor P3 can flow a current in equilibrium with the bias current of the MIMO transistor N4, and the gate voltage of the polyclonal transistor P3 at that time. Is the stable point of the page signal.

Therefore, if the pgate signal is compared with the bias current, a power supply detection signal, that is, a power-on reset signal can be created. It is the comparison unit 72 that makes this comparison. That is, in the region where the power supply VDDL is lower than 1V, the current of the polyclonal transistor P4 is superior to the bias current of the MIMO transistor N5. .. Then, the por signal, which is the power-on reset signal output from the node por, does not become a stable output at about 1 V, and is along the digital signal as shown in FIG. 1 (d), that is, 0 V or the power supply VDDL. It becomes a signal having a voltage. The peak value of the POR signal shown in FIG. 1 (d) is about 1 V. As shown in FIG. 1 (a), it is preferable that the OFDM transistor N5 in the comparison unit has a larger transistor size and a higher ability as a current source than the polyclonal transistor P4. Instead of increasing the transistor size of the nanotube transistor N5, the transistor size of the polyclonal transistor P5 may be increased as in the POR circuit 10A shown in FIG. 3 (a).

The differential amplifier composed of the nanotube transistors N1, N2, and N3 of the differential unit 70 is basically used by feeding back (in a negative feedback configuration). In this embodiment, the gate of the Now's transistor N1 (DMOS) is connected to the ground, but it may be connected to another reference voltage (vref'). In that case, the reference voltage vref, which is the output voltage of the output unit 71, is vref + vref', which is the voltage obtained by adding another reference voltage vref'to the VT difference reference voltage due to the nanotube transistors N1 and N2.

As described in detail above, according to the power-on reset circuit 10 according to the present embodiment, it is possible to configure a power-on reset circuit that can be reset at a voltage of about 1 V at the rising edge of the power supply VDDL. Further, even if the power supply VDDL is started slowly, it can be reset. Further, the reset can be applied even when the reference voltage vref is equal to the power supply VDDL due to the low power supply VDDL (when the reference voltage vref changes along the power supply VDDL). However, in this case, it is preferable to use the polyclonal transistor P3 as the LVT polyclonal. Further, the power-on reset circuit 10 has a feature that it is automatically (autonomously) activated when bias is supplied.

Further, according to the power-on reset circuit 10 according to the present embodiment, there is a feature that the temperature fluctuation of the por signal, which is the power-on reset signal, is small (the temperature fluctuation characteristic is flat). FIG. 2B compares the temperature fluctuation characteristic S1 of the power-on reset signal por according to the present embodiment with the power-on reset signal S2 according to the prior art. While the power-on reset signal S2 according to the prior art decreases with temperature (temp), the power-on reset signal S1 according to the present embodiment is substantially flat. This is because the differential portion 70 of the power-on reset circuit 10 uses a circuit that generates a VT difference reference voltage. That is, in the VT difference reference voltage generation circuit, the temperature fluctuations of both threshold voltage VT cancel each other out, and the temperature fluctuation becomes very small. When the temperature characteristic of the por signal is close to flat, there is an advantage that the reset can be applied at almost the same voltage even if the ambient temperature changes. Further, according to the power-on reset circuit 10 according to the present embodiment, since it is not necessary to use a resistor, the circuit can be configured to be very small, which contributes to the reduction of the layout area and the cost reduction.

Further, the power-on reset circuit 10 according to the present embodiment has a feature that the reset release voltage can be increased. A high reset release voltage is advantageous in preventing runaway of the power supply circuit, for example, and being able to raise the reset release voltage is very useful in designing an LSI (Large Scale Integration) system. In addition, the reset voltage can be increased by about 0.3V compared to the power-on reset circuit that uses one VT (about 0.7V) of the conventional normal VT Now, including temperature fluctuations such as low temperature. However, there is a margin of 0.1V or more (see FIG. 2B). Further, by using a combination of DMOS (NMOS transistor N1) and normalVT MOS ( It has the feature that it can be raised.

[Second Embodiment]
A power-on reset circuit and a semiconductor device according to the present embodiment will be described with reference to FIGS. 4 and 5. This embodiment is a form in which a hysteresis circuit is added to the power-on reset circuit 10 according to the above embodiment. Therefore, the same reference numerals are given to the same configurations, and detailed description thereof will be omitted.

FIG. 4 shows the POR circuit 20 according to the present embodiment. The POR circuit 20 has a configuration in which a hysteresis circuit HIS1 and inverters INV1 and INV2 are added to the POR circuit 10. The inverter INV1 and the inverter INV2 are connected in series, and the output of the inverter INV1 is a node por and the output of the inverter INV2 is a node por. The node por is an output node of the power-on reset signal, and the node por is an output node of the inverted signal (auxiliary signal) of the power-on reset signal.

The hysteresis circuit HIS1 is configured to include the polyclonal transistors P6 and P7. The source of the polyclonal transistor P6 is connected to the drain of the epitaxial transistor P7, the drain is connected to the drain of the polyclonal transistor P4, and the gate is connected to the node pgate. The source of the FIGURE transistor P7 is connected to the power supply VDDL and the gate is connected to the node horn. The POR circuit 20 has a configuration in which a hysteresis circuit HIS1 is added to a comparison unit 72 including a polyclonal transistor P4 and an NaCl transistor N5.

In the present embodiment, the Schmitt trigger circuit is configured by the comparison unit 72 including the epitaxial transistor P4 and the nanotube transistor N5 and the hysteresis circuit HIS1 (see the equivalent block diagram of FIG. 5C). The Schmitt trigger circuit is a circuit in which the output state changes with hysteresis with respect to a change in the input voltage, and the threshold value for determining the output differs depending on whether the input voltage rises or falls. In other words, the Schmitt trigger circuit has a dead zone with a predetermined width near the threshold value for the input. In this embodiment, a Schmitt trigger circuit is used to suppress frequent switching of the output when noise is superimposed on the input.

That is, as shown in FIG. 5A, when noise having a certain voltage width is superimposed on the input, the input near the threshold value frequently crosses the threshold value (reference voltage vref (1V)) from above and below. Therefore, the output switches frequently (fluttering, a phenomenon called "chattering"). When chattering occurs at the output, there are concerns about an increase in current consumption or an unexpected malfunction in the system to which the output is connected. On the other hand, since the POR circuit 20 has a hysteresis function, a weak latch is applied to the input, and the current state is maintained for as long as possible. As a result, the output is switched at a voltage separated by a predetermined width from the node vref (1V) voltage, which is the original reset voltage. A voltage separated by a predetermined width has a high threshold when the input voltage is increased from 0V, and conversely, a low threshold when the input voltage is decreased toward the reference voltage of vref (1V). That is.

FIG. 5B is a diagram conceptually showing the operation of the above-mentioned Schmitt trigger circuit. As shown in FIG. 5B, in the Schmitt trigger circuit, the threshold value when the input rises toward the threshold value is higher than the original threshold value for the input on which noise is superimposed, and conversely, the input is the threshold value. The threshold value when descending in the direction toward is a VTL lower than the original threshold value. At this time, if (VTH-VTL) is set to be equal to or larger than the noise width, the input does not stay near the original threshold value, so that the chattering of the output is eliminated as shown in FIG. 5 (b).

FIG. 4B shows the operation waveform of the POR circuit 20. As shown in FIG. 4B, in the direction in which the power supply VDDL rises, the por signal does not switch immediately even if the pgate signal reaches the reference voltage vref (1V), and the por signal is increased by a predetermined voltage α before the por signal. Is output. This is because when the pgate signal rises and the input of the inverter INV1 becomes H, the gate of the polyclonal transistor P7 becomes L and the polyclonal transistor P7 is turned on, and the polyclonal transistor P6 is added to the polyclonal transistor P4 which is the load of the node pgate. This is because it becomes heavy and tries to maintain H.

Although FIG. 4B also shows the case where the power supply VDDL is lowered, since the POR circuit 20 does not provide hysteresis in the direction in which the power supply VDDL is lowered, the por signal is provided at the reference voltage vref (1V). Goes down. Although the hysteresis function is sufficient only in the direction in which the power supply VDDL rises, the hysteresis function may be provided in the direction in which the power supply VDDL rises. By the above operation, the por signal of the POR circuit 20 becomes the voltage waveform shown in FIG. 4 (c).

[Third Embodiment]
The power-on reset circuit 30 according to the present embodiment will be described with reference to FIGS. 6 and 7. In this embodiment, a mirror circuit is added to the differential portion, and the operating point of the node pgate in the POR circuit according to the above embodiment is changed. That is, in the POR circuit 30, the polyclonal transistors P8 and P9 and the nanotube transistors N10 and N11 are added to the POR circuit 10 shown in FIG. 1 (a).

As shown in FIG. 6 (a), the source of the polyclonal transistor P8 is connected to the power supply VDDL, the gate is connected to the drain of the nanotube transistor N1, and the drain is connected to the drain of the nanotube transistor N10. The drain and gate of the MIMO transistor N10 are short-circuited and connected to the bias voltage bias, and the source is connected to the ground. The polyclonal transistor P8 and the nanotube transistor N10 are one mirror circuit for the differential unit 70 including the nanotube transistors N1, N2, and N3. Further, the source of the polyclonal transistor P9 is connected to the power supply VDDL, the gate is connected to the drain of the MIMO transistor N2, and the drain is connected to the drain of the nanotube transistor N11. The gate of the IGMP transistor N11 is connected to the bias voltage bias and the source is connected to ground. The polyclonal transistor P9 and the nanotube transistor N11 are the other mirror circuit for the differential unit 70 including the nanotube transistors N1, N2, and N3.

In the POR circuit 30, the pgate signal is taken out from the drain of the polyclonal transistor P9. The configuration of the output unit 71 including the epitaxial transistor P3 and the nanotube transistor N4, and the comparison unit 72 including the polyclonal transistor P4 and the nanotube transistor N5 is the same as that of the POR circuit 10 shown in FIG. 1 (a). Therefore, the POR circuit 30 is represented by an equivalent block diagram as shown in FIG. 6 (e), which is the same as the equivalent block diagram of the POR circuit 10 shown in FIG. 2 (a).

6 (b), (c), and (d) show the operation waveform of the POR circuit 30. As described above, in the POR circuit 10 shown in FIG. 1A, when the power supply VDDL is 1V or less, which is the reference voltage vref (1V), the pgate signal can be represented by (Equation 1). That is, since the node pgate is taken out from the drain of the nanotube transistor N2, assuming that the drain-source voltage of the Now's transistor N2 is about 0 V, the voltage vref-represented by (Equation 1), which is the source voltage of the nanotube transistor N2. It cannot be less than 1 LVT (0.45 V). That is, in the POR circuit 10, since the pgate signal does not actually drop to 0V, there is a concern that the polyclonal transistor P3 cannot be sufficiently turned on.

However, in the POR circuit 30, since the signal obtained by mirroring (folding back) the output of the differential unit 70 is used as the pgate signal, the voltage limitation due to the µtransistor N2 in the POR circuit 10 is eliminated. That is, the pgate signal can be lowered to 0V. As a result, 0V can be applied to the gate of the polyclonal transistor P3, and the polyclonal transistor P3 can be fully turned on.

As described above, in the POR circuit 10, the polyclonal transistor P3 is preferably an LVT polyclonal. This was intended to turn on the polyclonal transistor P3 even under the condition that the pgate signal does not drop below the source voltage of the nanotube transistor N2. However, in the POR circuit 30, since the pgate signal can be lowered to 0V (or to the vicinity of 0V), it is not necessary to use the LVT epitope as the polyclonal transistor P3, and it can be made into, for example, a normalVT epitope.

On the other hand, in the POR circuit 10B shown in FIG. 3 (b), since the NORmalVT µ is adopted as the MIMO transistor N7, there is a possibility that it is not necessary to use the LVT FIGURE as the FIGURE transistor P3. However, in the case of the POR circuit 10B, if the threshold voltage VT is higher in the normal VT polyclonal than in the normal VT µ due to element variation or the like, there is a concern that the ProLiant cannot be turned on by the decrease of the threshold voltage VT of the IGMP of the differential stage. .. In a normal manufacturing process, it is assumed that the threshold voltage VT of the MIMO and the threshold voltage VT of the polyclonal are close to each other, so it may be necessary to consider a margin for this concern.

Further consideration will be given to the above points with reference to FIG. 7. FIG. 7 shows a POR circuit 30A which is another form of the POR circuit 30 according to the present embodiment. In the POR circuit 30A, the norm transistor N2 of the POR circuit 30 is replaced with the normal VT nanotube transistor N7. That is, the configuration of the differential unit 70 is the same as that in FIG. 3 (b). In the case of the POR circuit 30A, the pgate signal is output regardless of the voltage of the source of the HCl transistor N7, that is, it can be set to almost 0V. As a result, even in the POR circuit 30A, the polyclonal transistor P3 is fully turned on.

In short, unlike the POR circuit 10, a positive relationship is not required between the threshold voltage VT of the NaCl transistor N2 and the threshold voltage VT of the polyclonal transistor P3. Therefore, the POR according to the present embodiment is not required. According to the circuit 30, it is very useful from the viewpoint of margin design, from the viewpoint of flexibility of voltage selection, and from the viewpoint of low voltage operation. However, in terms of circuit operation, it is necessary to consider that the voltage value of the reference voltage vref is higher than the threshold voltage VT of the polyclonal transistor P3.

[Fourth Embodiment]
The power-on reset circuit according to the present embodiment will be described with reference to FIGS. 8 and 9. As shown in FIG. 8A, the POR circuit 40 according to the present embodiment is a POR circuit 30A shown in FIG. 7 in which the portion of the nanotube transistor N4 is replaced with a series circuit of the resistors R1 and R2. .. The reference voltage vref (1.3V) is taken out from the connection point between the resistance R1 and the resistance R2. The value of the reference voltage vref (1.3V) is 1.3V. 8 (b), (c), and (d) show waveforms of each part of the POR circuit 40.

In the present embodiment, the resistance value of the resistance R1 and the resistance value of the resistance R2 are equalized (the ratio of the resistance value of the resistance R1 to the resistance value of the resistance R2 is 1: 1). In this case, as shown in FIG. 8B, the voltage of the node vr, which is the source of the polyclonal transistor P3, is 2.6V. Therefore, the POR circuit 40 is represented by an equivalent block diagram as shown in FIG. 9A. In the POR circuit 40, when the power supply VDDL is activated, half of the voltage of the power supply VDDL is fed back to the gate of the MIMO transistor N7. As a result, as shown in FIG. 8 (c), the polyclonal transistor P3 should be turned on until the input voltage of the nanotube transistor N7 of the differential unit 70 reaches 1.3 V of the reference voltage vref (1.3 V). Therefore, the pgate signal maintains 0V. After the power supply VDDL reaches the reference voltage vref (1.3V), the pgate signal rises following the voltage of the power supply VDDL. On the other hand, as shown in FIG. 8D, the por signal reaches 2.6V when the power supply VDDL reaches the reference voltage vref (1.3V), and then the current source of the norm transistor N5 becomes dominant. It drops to 0V.

As described above, in the POR circuit 40 according to the present embodiment, the reset release voltage can be increased by feeding back the voltage divided by the resistance ladder by the resistors R1 and R2 to the differential unit. For example, as described above, when the resistance value of the resistor R1 and the resistance value of the resistor R2 are set to 1: 1 and the reference voltage vref to be fed back is 1.3V, the reset can be released at 2.6V. That is, the reset release voltage can be increased. Further, the reset release voltage can be selected by changing the ratio of the resistance value of the resistor R1 and the resistance value of the resistor R2. This enables more flexible voltage selection. Since the POR circuit 40 has a configuration in which the voltage is divided by a resistor and the current is throttled, it is assumed that a resistor having a relatively large resistance value is used. Therefore, it is preferable to consider the adoption / rejection including other embodiments in consideration of the layout area and the like.

Further, as shown in FIG. 9 (b), a resistor outlet may be selected by using three or more resistors. For example, by providing a circuit having a configuration in which the reset voltage is increased during reset and the reset voltage is decreased when the reset is released, the degree of freedom in the selection range of the reset voltage and the reset release voltage is further increased.

[Fifth Embodiment]
The power-on reset circuit according to the present embodiment will be described with reference to FIG. 10. In this embodiment, a band gap due to a bipolar transistor is used to generate a reference voltage, and DMOS is not used. 10 (a) is a circuit diagram showing a POR circuit 50 according to the present embodiment, FIGS. 10 (b), 10 (c) and 10 (d) are operation waveforms of each part of the POR circuit 50, and FIG. 10 (e) is. The equivalent block diagram of the POR circuit 50 is shown respectively.

In each of the above embodiments, a reference voltage generation unit using DMOS is adopted. The DMOS is characterized in that it has a negative threshold voltage VT, and in each of the above embodiments, the reference voltage is generated by taking advantage of this feature. However, on the other hand, it is naturally necessary that the manufacturing process includes a DMOS forming step. Therefore, there is a drawback that the number of masks in the manufacturing process increases accordingly. That is, if the reference voltage can be generated without using DMOS, the manufacturing process can be further simplified and the cost can be reduced.

As shown in FIG. 10 (a), the POR circuit 50 is configured by adding a bandgap portion 73 to the POR circuit 30A shown in FIG. 7 and replacing the DBMS transistor N1 of the DMOS with the µ transistor N12 of the normal VT Now. .. Further, in the POR 50, since a relatively large current flows in the portion of the polyclonal transistor P3, it is changed to the large size polyclonal transistor P10.

The bandgap portion 73 includes NPN transistors BN1, BN2, BN3, BN4, and resistors R6, R7, and R8. The bandgap unit 73 is a circuit unit that uses the bandgap of the semiconductor to generate a reference voltage vref (2.4V) in which temperature fluctuations and power supply fluctuations are suppressed in the node vref (2.4V). In the present embodiment, the NPN transistors BN1 and BN2 form one two-stage diode, and the NPN transistors BN3 and BN4 form the other two-stage diode. Further, in the present embodiment, the NPN transistors BN1 and BN2 are each composed of one diode (indicated as m = 1 in FIG. 10A), and the NPN transistors BN3 and BN4 are composed of n parallel diodes. (In FIG. 10A, it is expressed as m = n).

In the bandgap portion 73, the node a and the node b operate so as to be a virtual short (imaginary short), and as a result, the current I1 flows on the side of the NPN transistor BN1 and the current I2 flows on the side of the NPN transistor BN3. .. As a result, a reference voltage vref (2.4V) in which temperature fluctuations and power supply voltage fluctuations are suppressed is generated. The voltage value of the reference voltage vref (2.4V) is 2.4V, but this voltage can be changed by the number of vertically stacked NPN transistors (diodes).

As shown in FIG. 10C, the pgate signal related to the POR circuit 50 is 0V until the voltage of the power supply VDDL reaches the reference voltage vref (2.4V), but becomes the reference voltage vref (2.4V). After reaching it, it changes according to the power supply VDDL. Further, as shown in FIG. 10D, the por signal changes following the power supply VDDL when the power supply VDDL reaches a predetermined value, and the pgate signal becomes the reference voltage vref (2.4V). At that point, it drops to 0V. The reset release voltage according to this embodiment is about 2.4V, that is, the peak value of the por signal shown in FIG. 10D is about 2.4V.

According to the power-on reset circuit 50 according to the present embodiment, since DMOS is not used, the number of masks can be reduced, and as a result, the manufacturing process is further simplified. Further, the area can be reduced by directly controlling the current of the bias current source with another bias source or the like. Further, the reset release voltage can be changed by changing the number of stages of the vertically stacked diodes of the bandgap portion 73. Furthermore, if the design is made to suppress manufacturing variations by taking advantage of the characteristics of the bandgap reference, it is possible to suppress the influence of variations. That is, the reset voltage and reset release voltage systems can be set to about ± 50 mV or about ± 100 mV without trimming. Thereby, for example, even if the operable voltage is 1.5 V or more and the operating specification is 1.6 V or more, the reset can be released at 1.55 V ± 50 mV.

In each of the above embodiments, the respective embodiments have been described as independent, but they may be combined as appropriate. For example, the POR circuit 50 may be provided with a hysteresis circuit included in the POR circuit 20. As a result, chattering is suppressed, and a POR circuit having an expanded selection range of reset voltage and reset release voltage can be obtained. Alternatively, if the POR circuits 40 and 50 are combined, the selection range of the reset voltage and the reset release voltage is further expanded.

In the above embodiment, an embodiment using an operation of turning on the ProLiant of the output stage (for example, the polyclonal transistor P3 of the output unit 71 shown in FIG. 1A) as the power supply VDDL starts up has been described as an example. However, the present invention is not limited to this, and a mode may be used in which an operation of turning off the µ of the output stage is used. That is, in each of the above-described embodiments, the output of the differential unit 70 is connected to the epitopes (NMR transistors P3 and P4) of the output stage, but the output of the differential unit 70 is connected to the MIMO. Just do it. According to such a configuration, in the region where the voltage of the power supply VDDL is low, the IGMP of the output stage is turned off, and after the voltage of the power supply VDDL exceeds the reference voltage vref, the IGMP of the output stage is turned on. Further, in each of the above embodiments, the mode of generating the voltage of each part with reference to the ground has been described as an example, but the present invention is not limited to this, and the mode of generating the voltage of each part with reference to a predetermined power supply voltage may be used.

10, 10A, 10B, 20, 30, 30A, 40, 40A, 50 Power-on reset circuit (POR circuit)
70 Differential section 71 Output section 72 Comparison section 73 Band gap section 100, 100A Power-on reset circuit BN1 to BN4 NPN transistor C1 Capacity R1 to R8 Resistance CS1, CS2 Current source HIS1 hysteresis circuit INV1, INV2 Inverter INV100, INV101 Inverter N1 to N12 N-channel type MOS field effect transistor (NMOS transistor)
P1 to P10 P-channel type MOS field effect transistor (MeOH transistor)
P100 P-channel type MOS field effect transistor (MeOH transistor)
N100 N-channel type MOS field effect transistor (MOS FET transistor)
por power-on reset signal vref reference voltage VDDL power supply

Claims (11)

It is a power-on reset circuit that supplies a reset signal to the powered circuit when the power is started.
It includes a pair of input units consisting of a first transistor and a second transistor, and outputs a control voltage using the difference between the voltage input to the first transistor and the voltage input to the second transistor . A reference voltage generation unit including a differential unit and an output unit that feeds back a reference voltage generated using the control voltage to one transistor of the pair of input units.
A comparison unit that performs a comparison operation between the control voltage and the reference voltage, which changes with the start of the power supply, generates a reset release signal, and supplies the power supply circuit.
Power-on reset circuit with. The comparison unit is connected to a third transistor to which the control voltage is input while being connected to the power supply, and a first unit connected to the third transistor and a low voltage side power supply having a voltage lower than the voltage of the power supply. The reset signal is output from the connection point between the third transistor and the first current source.
In the reset signal, the voltage of the reset signal is determined by the third transistor until the power supply reaches the reference voltage, and after the voltage exceeds the reference voltage, the reset signal is transmitted by the first current source. The power-on reset circuit according to claim 1, wherein the voltage is determined. The first current source is composed of a fourth transistor.
The power-on reset circuit according to claim 2, wherein the size of the fourth transistor is larger than the size of the third transistor. The output unit includes a fifth transistor connected to the power supply and to which the control voltage is input, and a second current source connected to the fifth transistor and the low voltage side power supply. The power-on reset circuit according to claim 2 or 3 , wherein the voltage at the connection point between the third transistor and the second current source is fed back to one transistor of the pair of input units as the reference voltage. The output unit has a fifth transistor connected to the power supply and to which the control voltage is input, and a plurality of series-connected resistances connected between the fifth transistor and the low voltage side power supply. Including, the voltage of at least one connection point of the plurality of connection points between the plurality of resistors is fed back to one transistor of the pair of input units as the reference voltage.
The power-on reset circuit according to claim 2 or 3. It further includes a hysteresis unit that is connected to the output terminal of the comparison unit and that is input to the control voltage and operates so as to shift the voltage of the reference voltage with respect to the control voltage.
The power-on reset circuit according to any one of claims 1 to 5 . The differential unit includes a mirror circuit including a first pair of transistors connected to the pair of input transistor transistors and a second pair of transistors connected to the first pair of transistors. The power-on reset circuit according to any one of claims 1 to 6 , wherein the control voltage is output from one output terminal of the first pair of transistors . The power-on reset circuit according to any one of claims 1 to 7 , wherein the reference voltage is generated by using the difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor. The power-on reset circuit according to claim 8 , wherein one of the first transistor and the second transistor is a depletion type field effect transistor and the other is a low threshold voltage type field effect transistor. In the reference voltage generator, two bandgap circuits in which one or more resistors and one or more diodes are connected in series are connected in parallel, and a bandgap connected to the output unit. 1 to claims, wherein the connection points between the one or more resistors of each of the two bandgap circuits and the one or more diodes are each fed back to the pair of inputs. 7. The power-on reset circuit according to any one of 7. The power-on reset circuit according to any one of claims 1 to 10 .
A power supply circuit to which power is supplied from the power supply and a reset signal is supplied from the power-on reset circuit when the power supply is started.
A semiconductor device equipped with.

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