JP7056609B2 - Semiconductor wafer for resistivity calibration for use in CV measurement and its manufacturing method - Google Patents

Description

In the present invention, a depletion layer is formed on the main surface of a semiconductor wafer, and the applied voltage dependence (hereinafter referred to as CV characteristic) of the capacity of the depletion layer (hereinafter referred to as the depletion layer capacity) is measured to measure the dopant of the semiconductor wafer. In a method of measuring a concentration and converting the value into a resistance, the present invention relates to a semiconductor wafer for resistance calibration for calibrating the obtained resistance and a method for manufacturing the same.

In order to evaluate the electrical characteristics of a semiconductor wafer, a method of forming a depletion layer on the main surface of the wafer and measuring the capacity of the depletion layer is generally performed. For example, resistivity, which is one of the electrical characteristics, is obtained by measuring and converting the dopant concentration of a semiconductor wafer, and the distribution of the dopant concentration in the depth direction is obtained by measuring the CV characteristics ( For example, Non-Patent Document 1).

FIG. 4 is a schematic diagram of a conventional CV characteristic measuring device. A method of measuring CV characteristics will be described with reference to this figure. First, the wafer 101 to be measured is placed on a metal stage 103 that serves as a back surface electrode. A vacuum suction hole 110 connected to the vacuum pump 109 is formed in the stage 103, and the wafer 101 is fixed by being vacuum sucked in the vacuum suction hole 110. The wafer 101 to be measured may be a mirror surface wafer, an epitaxial wafer, or the like, and here, a case where a normal mirror surface wafer is used as a measurement target wafer is shown.

A shot key electrode 102 is formed on the surface of the wafer 101. In the case of a p-type silicon epitaxial wafer, the Schottky electrode 102 can be formed by vacuum-depositing samarium, for example, using a commercially available vacuum vapor deposition apparatus. The CV characteristic measuring device 100 for performing this measurement is installed in a shield box 108 set so that the object to be measured has an earth potential in order to prevent electrical noise generated during the measurement.

Next, the measuring probe 104 is brought into contact with the shotkey electrode 102 formed on the main surface of the wafer 101. A capacitance meter 105 and a pulse voltage generator 106 are connected to the probe 104, and the capacitance meter 105 and the pulse voltage generator 106 are connected to a control computer 107. In the measurement of CV characteristics, a pulse voltage generator 106 generates a stepwise changing voltage, and the voltage is applied to the wafer 101 through a probe 104 in contact with the Schottky electrode 102, while the capacitance meter 105 inside the wafer 101. This is done by measuring the depletion layer capacity of the depletion layer 111 that spreads to.

ここで、Ｎ（Ｗ）は深さＷにおけるシリコンウェーハ中のドーパント濃度、ｑは電荷素量、ε_Ｓｉはシリコンの誘電率、Ｖは印加電圧、Ｃは空乏層容量、Ａはショットキー電極面積である。すなわち、印加電圧Ｖに対してｄ（Ｃ^－２）／ｄＶをプロットすることにより、シリコンウェーハ中のドーパント濃度（抵抗率）の深さ方向の分布（プロファイル）を測定する。その際、印加する電圧はショットキー接合に対して逆バイアスになるようにする。すなわち、ｐ型シリコン単結晶ウェーハの場合は、正の電圧を印加することによりシリコン内部に空乏層が拡がる。空乏層の深さ方向の幅は印加する電圧に比例して大きくなるため、印加電圧を変化させることで深さ方向の情報を得ることができる。なお、この測定は、ウェーハ表面に酸化膜を形成し、その上に電極を形成した、いわゆるＭＯＳ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構造のウェーハに対しても可能である。一般的に、ドーパント濃度から抵抗率、または、抵抗率からドーパント濃度への換算は、公知の換算式（非特許文献４）を用いて換算することができる。 In general, the following relational expression holds for the applied voltage and the amount of change in the depletion layer capacity (for example, Non-Patent Document 2).

Here, N (W) is the dopant concentration in the silicon wafer at the depth W, q is the charge element amount, ε _Si is the dielectric constant of silicon, V is the applied voltage, C is the depletion layer capacity, and A is the Schottky electrode area. Is. That is, by plotting d (C ^-2 ) / dV with respect to the applied voltage V, the distribution (profile) of the dopant concentration (resistivity) in the silicon wafer in the depth direction is measured. At that time, the applied voltage is set to have a reverse bias with respect to the Schottky junction. That is, in the case of a p-type silicon single crystal wafer, the depletion layer expands inside the silicon by applying a positive voltage. Since the width of the depletion layer in the depth direction increases in proportion to the applied voltage, information in the depth direction can be obtained by changing the applied voltage. This measurement is also possible for a wafer having a so-called MOS (Metal Oxide Semiconductor) structure in which an oxide film is formed on the surface of the wafer and electrodes are formed on the oxide film. Generally, the conversion from the dopant concentration to the resistivity or from the resistivity to the dopant concentration can be converted using a known conversion formula (Non-Patent Document 4).

When measuring the resistivity of a wafer based on these principles, CV measurement is performed on a wafer having a known resistivity (hereinafter referred to as a resistivity calibration wafer) obtained in advance by a well-known resistivity measuring method. It is necessary to understand the relationship between the measured value of the dopant concentration obtained by the above and the known resistivity, and to prepare a calibration curve. Then, the dopant concentration (resistivity) obtained from the CV measurement of the wafer to be measured is converted using the above calibration curve to obtain a normal resistivity.
As the resistivity calibration wafer, for example, a semiconductor wafer whose resistivity is determined by measuring the resistivity by a four-probe method (method described in Non-Patent Document 3) can be used.

Edited by Akira Usami "Semiconductor Device Process Evaluation Technology" Realize Co., Ltd. (issued on September 11, 1990), p38-p44 Corona Publishing Co., Ltd. March 15, 1982 First Edition Crystal Evaluation (Authors: Shinji Ito, Nao Otsuka), p243-p246 SEMI MF84-0312 (Repproved 0718): Test Method for Measuring Resistivity of Silicon Wafers with an In-line Four-point Probe SEMI MF723-0307 (Reproaded 0412): PRACTICE FOR CONVERSION BETWEEEN RESISTIVITY AND DOPANT OR CARRIER DENSITY FOR BORON-DOPED, PHOSPHORUS-DOPED

As described above, the normal resistivity is obtained by converting the dopant concentration (resistivity) obtained from the CV measurement of the wafer to be measured by the calibration curve created by using the resistivity calibration wafer. rice field. However, it is a resistivity calibration wafer whose resistivity is determined by the 4-probe method, and it is confirmed that the resistivity in the depth direction is flat (uniform) by the spreading resistance method (SR method). Even when the resistivity is measured by CV, mainly when the resistivity of the resistivity calibration wafer is high, the distribution of the dopant concentration in the depth direction obtained by the CV measurement is along with the depth from the wafer surface. There is a problem that the increased or decreased shape is measured (that is, the measurement result indicating that the resistivity in the depth direction is not uniform is obtained). As a result, there is a problem that the dopant concentration changes when the measurement depth position of the CV measurement changes, and the dopant concentration cannot be uniquely determined.

The present invention has been made in view of the above problems, and is used for resistivity calibration in which the distribution of the dopant concentration in the depth direction obtained by CV measurement and the distribution of the dopant concentration in the depth direction by another measurement method match. It provides a semiconductor wafer and provides a method capable of accurately calibrating the resistivity.

In order to achieve the above object, the present invention is a resistivity calibration semiconductor wafer for use in CV measurement.
In the region where the depletion layer expands when the semiconductor wafer for resistance calibration is measured by CV, the slope of the distribution of the dopant concentration measured by the CV measurement in the depth direction and the depth of the dopant concentration by another measuring method. Provided is a semiconductor wafer for resistance calibration for use in CV measurement, which is characterized in that the inclination of the distribution in the direction is consistent with the slope of the distribution.

In such a case, the slope of the distribution of the dopant concentration in the depth direction measured by the CV measurement and the slope of the distribution of the dopant concentration in the depth direction by other measurement methods match, so that the calibration is accurate. It becomes possible to create a curve, and the resistance can be calibrated accurately.

At this time, it is preferable that the distribution of the dopant concentration in the depth direction is flat.

In such a case, the resistivity obtained by measuring the wafer by another measuring method can be uniquely determined as the resistivity of the CV measurement regardless of the measurement depth position of the CV measurement. ..

At this time, a dopant element having the same conductivity as the bulk of the resistivity calibrating semiconductor wafer is placed on the back surface so that the back electrode in the CV measurement and the back surface of the resistivity calibrating semiconductor wafer are in ohmic contact. It is preferable that the back surface has a high-concentration impurity layer contained in a higher concentration than the bulk.

With such a case, the depletion layer capacitance formed on the surface can be measured more reliably and accurately in the CV measurement, and the resistivity can be calibrated more accurately.

At this time, it is preferable that the resistivity of the high-concentration impurity layer on the back surface is 0.1 Ωcm or less.

With such a case, it is possible to more reliably make ohmic contact between the back surface electrode in the CV measurement and the back surface of the resistivity calibration semiconductor wafer.

Further, the present invention is a method for manufacturing a semiconductor wafer for resistivity calibration for use in CV measurement.
The process of preparing a semiconductor wafer and
The process of cutting out sample wafers of different areas from the prepared semiconductor wafers,
The process of performing CV measurement using the cut out sample wafer and
In the CV measurement, the slope of the distribution of the obtained dopant concentration in the depth direction is based on the relationship between the slope of the distribution of the dopant concentration obtained for each sample wafer in the depth direction and the area of the sample wafer. The minimum area of the sample wafer that matches the slope of the distribution of the dopant concentration in the depth direction by other measurement methods is obtained, and the semiconductor wafer having an area larger than that area is manufactured as a semiconductor wafer for resistance calibration. Provided is a method for manufacturing a semiconductor wafer for resistance calibration for use in CV measurement.

With such a method, the slope of the distribution of the dopant concentration in the depth direction measured by the CV measurement of the manufactured wafer and the slope of the distribution of the dopant concentration in the depth direction by other measurement methods match. Therefore, it is possible to create an accurate calibration curve, and it is possible to accurately calibrate the resistance.

At this time, it is preferable that the semiconductor wafer to be prepared is a wafer in which the distribution of the dopant concentration in the depth direction is flat.

With such a method, the resistivity obtained by measuring the wafer by another measurement method is uniquely used as the resistivity of the CV measurement regardless of the measurement depth position of the CV measurement of the manufactured wafer. Can be decided.

In the case of the semiconductor wafer for resistance calibration of the present invention, the slope of the distribution of the dopant concentration in the depth direction measured by CV measurement coincides with the slope of the distribution of the dopant concentration in the depth direction by another measurement method. Therefore, it is possible to create an accurate calibration curve, and it is possible to accurately calibrate the resistance.

It is sectional drawing of an example of the semiconductor wafer for resistivity calibration of this invention. It is a figure which shows the procedure of an example of the manufacturing method of the semiconductor wafer for resistivity calibration of this invention. It is a figure which shows the dopant concentration profile measurement result of Example 2 and the comparative example 1. FIG. It is a schematic diagram of the conventional CV characteristic measuring apparatus.

As described above, even when the resistivity in the depth direction is confirmed to be uniform (flat) by CV measurement, mainly when the resistivity of the resistivity calibration wafer is high (for example). (10 Ω · cm or more) has a problem that the dopant concentration changes when the measurement depth position of the CV measurement changes, and the dopant concentration (resistivity) cannot be uniquely determined.

[Semiconductor wafer for resistivity calibration]
As a result of repeated ingenuity, the present inventor matches the slope of the distribution of the dopant concentration in the depth direction measured by CV measurement with the slope of the distribution of the dopant concentration in the depth direction by another measurement method. If this is the case, it has been found that the dopant concentration can be uniquely determined and can be suitably used as a semiconductor wafer for resistance calibration, and the present invention has been completed.

That is, the present invention is a resistivity calibration semiconductor wafer for use in CV measurement.
In the region where the depletion layer expands when the semiconductor wafer for resistance calibration is measured by CV, the slope of the distribution of the dopant concentration measured by the CV measurement in the depth direction and the depth of the dopant concentration by another measuring method. It is a semiconductor wafer for resistivity calibration for use in CV measurement, which is characterized in that the inclination of the distribution in the direction is the same.

In such a case, the slope of the distribution of the dopant concentration in the depth direction measured by the CV measurement and the slope of the distribution of the dopant concentration in the depth direction by other measurement methods match, so that the calibration is accurate. Curves can be created and the resistance can be calibrated accurately.

At this time, it is preferable that the distribution of the dopant concentration in the depth direction is flat. In such a case, the distribution of the dopant concentration in the depth direction is flat (the slope is almost zero), that is, the dopant concentration in the depth direction is almost constant (preferably a variation of about ± 3%). Therefore, regardless of the measurement depth position of the CV measurement, the resistance obtained by measuring the wafer surface by the four-probe method can be uniquely determined as the resistance of the CV measurement.

At this time, a dopant element having the same conductivity as the bulk of the resistivity calibrating semiconductor wafer is placed on the back surface so that the back electrode in the CV measurement and the back surface of the resistivity calibrating semiconductor wafer are in ohmic contact. It is preferable that the back surface has a high-concentration impurity layer contained in a higher concentration than the bulk.

When CV measurement is performed on a wafer with high resistivity, even if the actual dopant concentration distribution in the depth direction is uniform, the cause is that the dopant concentration obtained by CV measurement increases or decreases with depth. Because the resistivity of the wafer is high, the influence of the series resistance Rs generated in series with the depletion layer capacitance Cd formed under the shotkey electrode formed on the wafer surface side, or in series with the depletion layer capacitance Cd. The combined capacitance with the depletion layer capacitance Cb formed on the back surface side will be measured, and it is conceivable that only Cd cannot be measured correctly.

As a result of diligent studies by the present inventor, the larger the area of the wafer to be measured, the smaller the inclination of the dopant concentration in the depth direction, and finally, when the area exceeds a certain area, a completely flat dopant profile is obtained. I found that it was possible. On the other hand, it has been found that the slope of the dopant concentration does not decrease even if the thickness of the wafer is reduced.

In the case of the influence of the series resistance Rs, since Rs becomes smaller as the wafer thickness becomes thinner, the gradient of the dopant concentration should become smaller as the wafer thickness becomes thinner, so that the distribution of the dopant concentration in the depth direction becomes inclined. The cause is that the contact between the back surface electrode (stage) 103 of the CV characteristic measuring device shown in FIG. 4 and the semiconductor wafer for resistance calibration does not become ohmic contact, so that a depletion layer is formed on the back surface of the semiconductor wafer for resistance calibration. , The combined capacity of the depletion layer capacity Cd formed under the shotkey electrode formed on the front surface side of the semiconductor wafer for resistance calibration and the depletion layer capacity Cb formed on the back surface side in series with each other is measured. It was found that the cause was that only the measurement could not be performed correctly.

As described above, the depletion layer capacity Cd formed on the front surface and the depletion layer capacity Cb formed on the back surface are series components, and the measured capacity Cm is

1 / Cm = 1 / Cd + 1 / Cb ... (3)

Will be.

As is clear from the above equation (3), if Cb is sufficiently larger than Cd, more specifically, preferably, if it is 100 times or more, Cm≈Cd, so that accurate Cd can be measured. Become. That is, the influence of the depletion layer capacity formed on the back surface can be ignored.

In this way, if accurate Cd measurement becomes possible, the slope of the distribution of the dopant concentration measured by CV measurement in the depth direction and the depth of the dopant concentration by other measurement methods such as the SR method and the SIMS method. Since the slope of the distribution in the direction matches, the resistance can be calibrated accurately.
For the coincidence of inclinations in the present invention, it is preferable that the difference between the inclinations of the two is within ± 5%.

A high-concentration impurity layer on the back surface is formed on the back surface of the semiconductor wafer so that the back surface electrode and the back surface of the semiconductor wafer for resistivity calibration have ohmic contact with each other so that the impurity elements having the same conductive type as the bulk of the semiconductor wafer have a higher concentration than the bulk. As a result, the inverse number of the depletion layer capacity Cb on the back surface of the resistivity calibration semiconductor wafer becomes zero, and Cm = Cd (measured capacity = depletion layer capacity formed on the surface) so that accurate Cd can be measured. Become.

Further, at this time, in particular, if the resistivity of the high-concentration impurity layer on the back surface is set to 0.1 Ωcm or less, ohmic contact can be obtained more reliably.

Hereinafter, embodiments of the semiconductor wafer for resistivity calibration of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

FIG. 1 shows a cross-sectional view of an example of a semiconductor wafer for resistivity calibration of the present invention. Hereinafter, the resistivity calibration semiconductor wafer 10 of the present invention will be described with reference to FIG. On the back surface of the silicon single crystal wafer 1, a back surface high-concentration impurity layer 2 in which a dopant element having the same conductive type as the bulk of the silicon single crystal wafer 1 has a higher concentration than the bulk is formed.

As the dopant element that becomes the same conductive type as the bulk, for example, when the conductive type of the bulk is n type, As, P, Sb are typical elements, but in addition to this, the conductive type becomes n type. It may be an element.

On the other hand, when the bulk conductive type is p-type, B and Al are typical elements, but other elements may be used as long as the conductive type is p-type. As a method of introducing these elements on the back surface and reducing the resistivity of the introduced region, a generally widely known ion implantation method or heat diffusion method can be used.

The resistance of the back surface high-concentration impurity layer 2 may be determined by obtaining ohmic contact with the back surface electrode in the CV measurement. Specifically, the wafer on which the back surface high-concentration impurity layer 2 is formed is measured by CV and the obtained dopant concentration is obtained. It suffices to determine so that the inclination of the distribution in the depth direction of is the same as the inclination of the distribution of the dopant concentration in the depth direction by another measuring method. Specifically, it is desirable that the resistivity of the back surface high-concentration impurity layer 2 is 0.1 Ωcm or less.

Dopant impurities may be introduced to the wafer surface when the back surface high-concentration impurity layer 2 is formed. In that case, the impurity layer introduced to the surface can be removed by chemically etching or polishing the surface. good.

[Manufacturing method of semiconductor wafer for resistivity calibration]
Further, the present inventors performed CV measurement by shaking the wafer area using a semiconductor wafer, and obtained the relationship between the gradient of the distribution of the dopant concentration obtained for each area in the depth direction and the wafer area. The minimum area of the wafer in which the inclination of the distribution of the dopant concentration in the depth direction and the inclination of the distribution of the dopant concentration in the depth direction by another measurement method match is obtained, and the semiconductor wafer having an area equal to or larger than that area is obtained. It has been found that when used as a semiconductor wafer for resistance calibration for CV measurement, the dopant concentration can be uniquely determined, and a wafer which can be suitably used as a semiconductor wafer for resistance calibration can be manufactured.

That is, the present invention is a method for manufacturing a semiconductor wafer for resistivity calibration for use in CV measurement.
The process of preparing a semiconductor wafer and
The process of cutting out sample wafers of different areas from the prepared semiconductor wafers,
The process of performing CV measurement using the cut out sample wafer and
In the CV measurement, the slope of the distribution of the obtained dopant concentration in the depth direction is based on the relationship between the slope of the distribution of the dopant concentration obtained for each sample wafer in the depth direction and the area of the sample wafer. The minimum area of the sample wafer that matches the slope of the distribution of the dopant concentration in the depth direction by other measurement methods is obtained, and the semiconductor wafer having an area larger than that area is manufactured as a semiconductor wafer for resistance calibration. This is a method for manufacturing a semiconductor wafer for resistance calibration for use in CV measurement.

With such a method, the slope of the distribution of the dopant concentration in the depth direction measured by the CV measurement of the manufactured wafer and the slope of the distribution of the dopant concentration in the depth direction by other measurement methods match. Therefore, it is possible to create an accurate calibration curve, and it is possible to accurately calibrate the resistance.

As described above, when the depletion layer capacitance Cb formed on the back surface side in series with the depletion layer capacitance Cd formed by the Schottky electrode formed on the front surface side of the wafer affects the measurement of Cd, it is obtained by CV measurement. The depth distribution of the dopant concentration obtained results in the dopant concentration increasing or decreasing with depth, even though the dopant concentration of the wafer under test measured by other methods is uniform in the depth direction. Become.

Conversely, a wafer having a flat dopant concentration distribution in the depth direction is measured, and the result is that the dopant concentration distribution in the depth direction becomes flat (in the case of a wafer having a distribution in the depth direction of the dopant concentration, CV. If the measurement shows that the distribution of the dopant concentration in the depth direction and the slope of the distribution of the dopant concentration in the depth direction match by another method), it means that Cd is evaluated correctly. As described above, in order to correctly evaluate Cd, the condition of Cd << Cb is necessary, and more specifically, it is preferable that Cb is approximately 100 times or more of Cd.

The depletion layer capacity Cb on the back surface is

Cb = ε _{Si AB} / _WB ... (4)

Given in. Here, _AB and _WB are the area of the back surface of the wafer and the width of the depletion layer generated by the contact between the back surface of the wafer and the back surface electrode of the CV characteristic measuring device, respectively.

As is clear from the above equation (4), the depletion layer capacity Cb on the back surface is proportional to the area _AB on the back surface of the wafer. Therefore, if the area _AB on the back surface is sufficiently increased, the Cb becomes large. Therefore, using sample wafers of different areas cut out from semiconductor wafers, the wafer area is shaken to perform CV measurement, and the relationship between the slope of the depth distribution of the dopant concentration obtained for each area and the sample wafer area is determined. The minimum area of the sample wafer in which the slope of the distribution of the obtained dopant concentration in the depth direction and the slope of the distribution of the dopant concentration in the depth direction by another measurement method match is obtained, and the area is larger than that area. If a semiconductor wafer is used, accurate Cd can be measured.

At this time, it is preferable that the semiconductor wafer to be prepared is a wafer in which the distribution of the dopant concentration in the depth direction is flat. With such a method, the resistivity obtained by measuring the wafer by another measurement method is uniquely used as the resistivity of the CV measurement regardless of the measurement depth position of the CV measurement of the manufactured wafer. Can be decided.

FIG. 2 shows a procedure of an example of a method for manufacturing a semiconductor wafer for resistivity calibration of the present invention.

First, as Step 1, a plurality of wafers manufactured under the same manufacturing conditions and having a uniform dopant concentration over the entire wafer in the depth direction are prepared (step of preparing a semiconductor wafer).

Specifically, a wafer obtained by measuring the depth distribution of the dopant concentration by the spreading resistance method (SR method), the SIMS method, or another method and confirming that the dopant concentration distribution is uniform in the depth direction is used. be able to.

Next, in Step 2, a sample wafer having a different area is cut out from the prepared semiconductor wafer (step of cutting out the sample wafer).

Then, in Step 3, a shot key electrode is formed in the center of the cut-out sample wafer by a thin-film deposition method. The Schottky electrode can be formed, for example, in the case of a p-type silicon wafer by vacuum-depositing samarium using a commercially available vacuum vapor deposition apparatus. When the conductive type of the sample is n type, Au may be vapor-deposited. The sample wafer on which the shotkey electrode is formed in this way is used as a sample for CV measurement.

Next, in Step 4, the CV measurement of the CV measurement sample is performed (step of performing the CV measurement), and the distribution of the dopant concentration in the depth direction is measured. Here, the slope ΔN of the distribution of the dopant concentration in the depth direction can be calculated, for example, by using the following equation (5).

ΔN = {N (W1) -N (W2)} / {W2-W1} ... (5)

Here, N (W1) is the impurity concentration at the depth W1.
N (W2) is the impurity concentration at the depth W2.
W1> W2.

Next, in Step 5, the minimum area of the sample wafer whose inclination becomes zero is obtained from the relationship between the area of the sample wafer used for the CV measurement sample and the inclination of the dopant concentration in the depth direction. A semiconductor wafer having an area larger than the area obtained in this way is manufactured and used as a semiconductor wafer for resistivity calibration.

Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples of the present invention, but the present invention is not limited to these Examples.

(Embodiment 1)
Prepare a silicon wafer made from a p-type, 200 mm diameter silicon single crystal block having a resistivity of 30 Ω · cm measured in advance by the 4-probe method, and first cut out a 5 mm × 5 mm square sample and spread it. The dopant concentration distribution in the depth direction was measured by the resistivity method, and it was confirmed that the dopant concentration was flat in the depth direction (variation within ± 3% from the surface to a depth of 10 μm, zero inclination). Then, four samples having a size of 30 mm × 30 mm square were cut out.

Of the cut out samples having a size of 30 mm × 30 mm square, the first sample was used as it was as sample A for CV measurement (Comparative Example 1). For the remaining three samples, B (boron) was implanted into the back surface of the sample using the ion implantation method (hereinafter referred to as the I / I method), and the resistivity was 1, 0.1, 0.01 Ωcm, respectively. The implantation amount of B was shaken so as to be the same, and then the activation heat treatment was performed at 1000 ° C. for 1 minute, and the sample B (Comparative Example 2), the sample C (Example 1), and the sample D (Example 2) were obtained, respectively. bottom.

Then, a samarium electrode having a radius of 1 mm was formed on one surface (surface) of sample A and the opposite surface (surface) in which B was injected by the I / I method (samples B to D) with a vacuum vapor deposition machine. These silicon wafers were placed on a CV characteristic measuring device and fixed by vacuum suction. Then, the probe was brought into contact with the samarium electrode and CV measurement was performed to obtain a depth distribution of the dopant concentration. The slope ΔN of the obtained dopant concentration distribution in the depth direction was evaluated using the above equation (5).

FIG. 3 shows the measurement results of the distribution (dopant concentration profile) in the depth direction of the dopant concentrations of Sample A and Sample D. The dopant concentration of sample A (Comparative Example 1) is inclined so that the depth increases, and the dopant concentration distribution cannot be accurately measured (that is, the dopant concentration measured by the spreading resistance method). It can be seen that it does not match the slope of the distribution in the depth direction (slope zero). On the other hand, in Sample D (Example 2), the dopant concentration is flat in the depth direction, and it can be seen that the dopant concentration distribution can be measured accurately. The reason why the dopant concentration was tilted in sample A is that the resistivity on the back surface of the sample is as high as 30 Ωcm (same as bulk), and the contact with the back electrode of the CV characteristic measuring device is not ohmic contact, so a depletion layer is formed on the back surface. It affected the measurement of the depletion layer capacitance Cd formed under the Schottky electrode on the surface.

As a result of confirming the presence or absence of the inclination of the dopant concentration profile in the depth direction for the remaining samples, in sample B (Comparative Example 2), the deeper the depth, the higher the dopant concentration and the inclination occurred. On the other hand, it was found that the distribution of the dopant concentration in the depth direction of the sample C (Example 1) of the present invention was almost flat, and Cd could be measured accurately.

In the first embodiment, an example using a silicon wafer having a dopant concentration flat (zero inclination) in the depth direction is shown, but the present invention is not limited to this, and the silicon wafer having a dopant concentration having an inclination is shown. The present invention can be applied even when the above is used. In that case, the slope of the distribution of the dopant concentration in the depth direction by the spreading resistance method and the slope of the distribution of the dopant concentration in the depth direction measured by the CV measurement. If it can be confirmed that the above is the same, it can be determined that the wafer corresponds to the semiconductor wafer for resistivity calibration used for the CV measurement of the present invention.

(Embodiment 2)
From a silicon wafer manufactured from the same ingot as in Example 1, 30 mm × 30 mm square (Sample E: Comparative Example 3), 50 mm × 50 mm square (Sample F: Example 3), and 100 mm × 100 mm square (Sample G). : Example 4) was cut out, and a samarium electrode having a radius of 1 mm was formed in the center of one surface of samples E to G by a vacuum vapor deposition machine. This silicon wafer was placed on a CV characteristic measuring device and fixed by vacuum suction. Then, the probe was brought into contact with the samarium electrode, CV measurement was performed, and the distribution of the dopant concentration in the depth direction was obtained.

As a result of evaluating the inclination of the obtained dopant concentration distribution in the depth direction, the dopant concentration of Sample E (Comparative Example 3) was inclined so that the deeper the depth, the higher the dopant concentration, as in Comparative Example 1. It was found that the dopant concentration distribution could not be measured accurately (that is, it did not match the slope (zero slope) of the distribution of the dopant concentration in the depth direction measured by the spreading resistance method).

On the other hand, in both Sample F (Example 3) and Sample G (Example 4), the dopant concentration was almost flat in the depth direction, and it was found that the dopant concentration distribution could be measured accurately. .. From this, in the case of the present embodiment, if the area is 2500 mm ² or more, the area of the back surface of the sample in contact with the back surface electrode of the CV characteristic measuring device becomes large, and the depletion layer capacity Cb formed on the back surface is on the front surface. It is considered that the influence on the Cd measurement can be ignored because the capacity of the depletion layer formed under the formed Schottky electrode is sufficiently larger than the Cd.

As described above, according to the first embodiment, according to the present invention, by reducing the resistivity of the back surface of the semiconductor wafer, the depletion layer capacity Cb generated by the contact between the back surface electrode of the CV characteristic measuring device and the back surface of the semiconductor wafer It became clear that the outbreak could be completely prevented.

Further, from the second embodiment, even if the resistivity of the back surface of the semiconductor wafer remains the same as that of the bulk, the depletion layer capacity Cb formed on the back surface side can be increased by increasing the contact area with the back surface electrode. As a result, it became clear that the influence on the measurement of the depletion layer capacitance Cd formed on the surface can be ignored, and only Cd can be measured accurately. That is, a sample in which the inclination of the distribution of the dopant concentration in the depth direction by the CV measurement and the inclination of the distribution of the dopant concentration in the depth direction by another measurement method match by the method for manufacturing the semiconductor wafer for resistance calibration of the present invention. It has been clarified that the minimum area of the wafer should be obtained, and a semiconductor wafer having an area larger than that area should be manufactured as a semiconductor wafer for resistivity calibration.

As a result, since the distribution of the dopant concentration in the depth direction can be accurately measured, the distribution of the dopant concentration in the depth direction obtained by the CV measurement and the distribution of the dopant concentration in the depth direction by other measurement methods can be obtained. It was shown that they can be suitably used as a method for manufacturing a semiconductor wafer for resistivity calibration used for CV measurement and a semiconductor wafer for resistivity calibration.

The present invention is not limited to the above embodiment. The above-described embodiment is an example, and any one having substantially the same structure as the technical idea described in the claims of the present invention and having the same effect and effect is the present invention. Is included in the technical scope of.

1 ... Semiconductor wafer, 2 ... High-concentration impurity layer on the back surface,
10 ... Semiconductor wafer for resistivity calibration,
100 ... CV characteristic measuring device, 101 ... wafer,
102 ... Shot key electrode, 103 ... Stage,
104 ... probe, 105 ... capacitance meter,
106 ... pulse voltage generator, 107 ... control computer,
108 ... Shield box, 109 ... Vacuum pump,
110 ... Vacuum suction hole, 111 ... Depletion layer.

Claims (5)

A semiconductor wafer for resistivity calibration for use in CV measurement.
In the region where the depletion layer expands when the semiconductor wafer for resistance calibration is measured by CV, the slope of the distribution of the dopant concentration measured by the CV measurement in the depth direction and the depth of the dopant concentration by another measuring method. It matches the slope of the distribution in the direction .
Dopant elements of the same conductive type as the bulk of the resistivity calibrating semiconductor wafer are placed on the back surface from the bulk so that the back surface electrode in the CV measurement and the back surface of the resistivity calibrating semiconductor wafer are in ohmic contact. A semiconductor wafer for resistivity calibration for use in CV measurement, which is characterized by having a high-concentration impurity layer on the back surface containing a high concentration . The semiconductor wafer for resistivity calibration according to claim 1, wherein the distribution of the dopant concentration in the depth direction is flat. The semiconductor wafer for resistivity calibration for use in the CV measurement according to claim 1 or 2 , wherein the resistivity of the back surface high-concentration impurity layer is 0.1 Ωcm or less. A method for manufacturing a semiconductor wafer for resistivity calibration for use in CV measurement.
The process of preparing a semiconductor wafer and
The process of cutting out sample wafers of different areas from the prepared semiconductor wafers,
The process of performing CV measurement using the cut out sample wafer and
In the CV measurement, the slope of the distribution of the obtained dopant concentration in the depth direction is based on the relationship between the slope of the distribution of the dopant concentration obtained for each sample wafer in the depth direction and the area of the sample wafer. The minimum area of the sample wafer that matches the slope of the distribution of the dopant concentration in the depth direction by other measurement methods is obtained, and the semiconductor wafer having an area larger than that area is manufactured as a semiconductor wafer for resistance calibration. A method for manufacturing a semiconductor wafer for resistance calibration for use in CV measurement. The method for manufacturing a semiconductor wafer for resistivity calibration according to claim 4 , wherein the semiconductor wafer to be prepared is a wafer having a flat distribution in the depth direction of the dopant concentration.

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