JP7052309B2 - Reflective liquid crystal display device - Google Patents

Description

The present invention relates to a reflective liquid crystal display device and relates to a reflective liquid crystal display device suitable for improving the quality of black display.

A subframe drive method is known as one of the halftone display methods in a liquid crystal display device. In the subframe drive method, which is a type of time axis modulation method, a predetermined period (for example, in the case of a moving image, one frame, which is a display unit of one image) is divided into a plurality of subframes to obtain gradations to be displayed. Pixels are driven by a combination of subframes according to the situation. The displayed gradation is determined by the ratio of the driving period of the pixel to a predetermined period, and this ratio is specified by the combination of subframes.

In some liquid crystal display devices that employ a subframe drive system, each pixel is composed of a master latch and a slave latch, a liquid crystal display element, and a plurality of switching transistors.

In this pixel, when 1-bit first data is applied to the input terminal of the master latch through the first switching transistor and the row selection signal applied via the row scan line becomes active, the first switching transistor is activated. It turns on and the first data is written to the master latch.

When the writing of data to the master latch provided in all the pixels is completed, the second switching transistor provided in all the pixels is turned on within the subframe period. As a result, the data of the master latch provided in all the pixels is read out all at once and written in the slave latch, and the data written in the slave latch is applied to the pixel electrodes of the liquid crystal display element. In each subframe period, the same processing is performed for all pixels. As a result, each pixel can perform a desired gradation display by combining a plurality of subframes constituting one frame.

The periods of the plurality of subframes constituting one frame are pre-allocated to the same or different predetermined periods. For example, in the case of displaying the maximum gradation (displaying white) in each pixel, the display is performed in all of a plurality of subframes constituting one frame, and the minimum gradation is displayed (displaying black). Is not displayed in all of the plurality of subframes constituting one frame, and when other gradation display is performed, the subframe to be displayed is selected according to the gradation to be displayed. The liquid crystal display device adopting this conventional method uses digital data indicating gradation as input data, and also adopts a digital drive system having a two-stage latch configuration (see, for example, Patent Document 1).

Japanese Patent No. 5733154

However, in the liquid crystal display device disclosed in Patent Document 1, it is considered that the frame electrode of the frame portion provided so as to surround the outer periphery of the image display portion is a solid electrode, and due to the influence thereof, the frame electrode is provided on the image display portion. There was a possibility that the level of black displayed by each pixel and the level of black displayed by the frame portion would be different. Therefore, there is a possibility that the black displayed by the frame portion is emphasized blacker than the black displayed by each pixel provided in the image display portion. As a result, for example, when viewing a projector, the black displayed by the frame part is overemphasized than the black displayed by the image display part even if the same level of black is displayed. As a result, there is a problem that the quality of the image is deteriorated.

The present invention has been made in view of the above points, and an object of the present invention is to provide a reflective liquid crystal display device capable of improving the quality of black display.

The reflective liquid crystal display device according to one aspect of the present invention is provided so as to surround an image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions partitioned in a matrix and an outer periphery of the image display unit. Each of the electrode arrangement regions includes a frame portion in which a plurality of frame electrodes are arranged in a plurality of electrode arrangement regions partitioned in a matrix, and each of the electrode arrangement regions includes a reflective electrode of the pixel occupying the pixel arrangement region. The frame electrodes are arranged so that the difference is within 5% based on the area ratio.

The reflective liquid crystal display device according to one aspect of the present invention is provided so as to surround an image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions partitioned in a matrix and an outer periphery of the image display unit. Each of the electrode arrangement regions includes a frame portion in which a plurality of frame electrodes are arranged in a plurality of electrode arrangement regions partitioned in a matrix, and each of the electrode arrangement regions includes a reflection electrode of the pixel occupying the pixel arrangement region. The frame electrodes are arranged so that the difference is within 30% with respect to the peripheral length.

According to the present invention, it is possible to provide a reflective liquid crystal display device capable of improving the quality of black display.

It is a block diagram which shows the liquid crystal display device which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the specific structure of the pixel provided in the liquid crystal display device shown in FIG. 1. It is a circuit diagram which shows the specific structure of the inverter which constitutes the 1st data holding part provided in the pixel shown in FIG. It is a schematic cross-sectional view of the pixel shown in FIG. It is a timing chart which shows the operation of the liquid crystal display device shown in FIG. It is a figure which shows the relationship between the applied voltage (RMS voltage) of a liquid crystal, and the gray scale value of a liquid crystal. It is a schematic plan view of the liquid crystal display device shown in FIG. 1. It is a schematic plan view of the reflection electrode of a pixel provided in the liquid crystal display device which concerns on a comparative example, and the frame electrode. FIG. 3 is an enlarged schematic plan view of the reflected electric electrode of the pixel shown in FIG. 8 and the frame electrode. It is a schematic plan view of the reflection electrode of the pixel provided in the liquid crystal display device shown in FIG. 1 and the frame electrode. It is a schematic cross-sectional view of the reflection electrode of the pixel shown in FIG. 10 and the frame electrode. It is an enlarged schematic plan view of the reflection electrode of the pixel shown in FIG. 10 and the frame electrode. It is a figure which shows the relationship between the difference of the aperture ratio of each of a reflection electrode and the frame electrode, and the difference of the black level displayed by each of an image display part and a frame part. It is a schematic plan view of the reflection electrode of the pixel provided in the liquid crystal display device which concerns on Embodiment 2, and the frame electrode. It is a schematic cross-sectional view of the reflection electrode of a pixel shown in FIG. 14 and a frame electrode. It is an enlarged schematic plan view of the reflection electrode of the pixel shown in FIG. 14 and the frame electrode. FIG. 3 is a schematic plan view of a pixel reflection electrode and a frame electrode provided in the liquid crystal display device according to the third embodiment. It is an enlarged schematic plan view of the reflection electrode of the pixel shown in FIG. 17 and the frame electrode. It is a figure which shows the relationship between the difference in the perimeter of each of a reflection electrode and the frame electrode, and the difference of the black level displayed by each of an image display part and a frame part.

<Embodiment 1>
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a reflective liquid crystal display device 10 according to the first embodiment.
As shown in FIG. 1, the reflective liquid crystal display device 10 includes an image display unit 11, a timing generator 13, a vertical shift register 14, a data latch circuit 15, and a horizontal driver 16. The horizontal driver 16 includes a horizontal shift register 161, a latch portion 162, and a level shifter / pixel driver 163.

The image display unit 11 has a plurality of pixels 12 regularly arranged in each of the plurality of pixel arrangement areas partitioned in a matrix.

The plurality of pixels 12 have m (m is a natural number of 2 or more) row scanning lines g1 to gm extending in the row direction (X direction) with one end connected to the vertical shift register 14, and a level shifter / pixel driver 163. N (n is a natural number of 2 or more) column data lines d1 to dn, one ends of which are connected to each other and extend in the column direction (Y direction), are arranged in a two-dimensional matrix at a plurality of intersections. Has been done. All the pixels 12 in the image display unit 11 are commonly connected to the trigger lines trig and trigb whose one end is connected to the timing generator 13.

It should be noted that the forward rotation trigger pulse TRI transmitted by the forward rotation trigger pulse trigger line trig and the reverse rotation trigger pulse TRIB transmitted by the reverse rotation trigger pulse trigger line trigb always have an inverse logic value relationship (complementary relationship). be.

The timing generator 13 receives external signals such as the vertical synchronization signal Vst, the horizontal synchronization signal Hst, and the basic clock CLK output from the host device 20 as input signals, and based on these external signals, the AC conversion signals FR and V. It generates various internal signals such as start pulse VST, H start pulse HST, clock signal VCK, HCK, latch pulse LT, and trigger pulse TRI, TRIB.

The AC signal FR is a signal whose polarity is inverted for each subframe, and is supplied to the common electrode of the liquid crystal display element in the pixel 12 constituting the image display unit 11 as a common electrode voltage Vcom described later.

The start pulse VST is a pulse signal output at the start timing of each subframe described later, and the switching of subframes is controlled by this start pulse VST.

The start pulse HST is a pulse signal output to the horizontal shift register 161 at the start timing of the horizontal shift register 161.

The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register 14, and the vertical shift register 14 performs a shift operation at the timing of the clock signal VCK.

The clock signal HCK is a shift clock in the horizontal shift register 161 and is a signal for shifting data with a width of 32 bits.

The latch pulse LT is a pulse signal output at the timing when the horizontal shift register 161 finishes shifting the data corresponding to the number of pixels in one row in the horizontal direction.

The forward rotation trigger pulse TRI and the reverse rotation trigger pulse TRIB are pulse signals supplied to all the pixels 12 in the image display unit 11 via the trigger lines rig and trigb, respectively.

Here, the forward rotation trigger pulse TRI and the reverse rotation trigger pulse TRIB are output from the timing generator 13 after data is written to the first data holding unit in all the pixels 12 in the image display unit 11 in a certain subframe period. Will be done. As a result, during the subframe period, the data held in the first data holding unit in all the pixels 12 in the image display unit 11 are collectively transferred to the second data holding unit in the corresponding pixel 12. To.

The vertical shift register 14 transfers the V start pulse VST supplied at the start timing of each subframe according to the clock signal VCK, and sequentially and exclusively supplies the row scan signal to the row scan lines g1 to gm in 1H units. .. As a result, the row scanning lines are sequentially selected one by one in 1H units from the row scanning line g1 at the top of the image display unit 11 to the row scanning line gm at the bottom.

The data latch circuit 15 latches 32-bit width data in units of 1 subframe supplied from an external circuit (not shown) based on the basic clock CLK from the host device 20, and then horizontally shifts in synchronization with the basic clock CLK. Output to register 161.

The reflective liquid crystal display device 10 divides one frame of a video signal into a plurality of subframes having a display period shorter than one frame period of the video signal, and performs gradation display by combining these subframes. ing. Therefore, the above-mentioned external circuit converts the gradation data indicating the gradation of each pixel into a plurality of 1-bit subframe data corresponding to the plurality of subframes. Further, the above-mentioned external circuit collectively supplies subframe data for 32 pixels belonging to the same subframe to the data latch circuit 15 as 32-bit width data.

When the horizontal shift register 161 is viewed as a processing system for 1-bit serial data, the shift is started by the start pulse HST supplied from the timing generator 13 at the initial stage of 1H, and the 32-bit width data supplied from the data latch circuit 15 is used. Is shifted in synchronization with the clock signal HCK.

When the horizontal shift register 161 finishes shifting the data for n bits, which is the same as the number of pixels n for one row of the image display unit 11, the latch unit 162 synchronizes with the latch pulse LT supplied from the timing generator 13. The data for n bits (that is, the subframe data for n pixels) supplied in parallel from the horizontal shift register 161 is latched and output to the level shifter of the level shifter / pixel driver 163. When the data transfer of the latch unit 162 is completed, the start pulse HST is output again from the timing generator 13, and the horizontal shift register 161 resumes the shift of 32-bit width data from the data latch circuit 15 according to the clock signal HCK.

The level shifter of the level shifter / pixel driver 163 shifts the signal level of n subframe data corresponding to one row of n pixels transferred from the latch unit 162 to the liquid crystal drive voltage amplitude. The pixel driver of the level shifter / pixel driver 163 outputs n subframe data corresponding to n pixels in one row after the level shift in parallel to n column data lines d1 to dn.

The horizontal driver 16 outputs subframe data toward the pixels of the row selected as the data writing target in one horizontal scanning period, and the pixels of the row selected as the data writing target in the next one horizontal scanning period. Subframe data shift for this is done in parallel. Then, in a certain horizontal scanning period, n subframe data corresponding to n pixels in one row are output as data signals in parallel and simultaneously on n column data lines d1 to dn, respectively.

Of the plurality of pixels 12 constituting the image display unit 11, the n pixels 12 in one row selected by the row scanning signal from the vertical shift register 14 are one row output all at once from the level shifter / pixel driver 163. The n subframe data of the minute is sampled via the n column data lines d1 to dn and written to the first data holding unit described later in each pixel 12.

The details of the pixel 12 will be described later, but in the pixel 12, the inverted data of the input data held in the storage unit SM1 is applied to the reflection electrode PE. That is, the pixel 12 has a function of inverting the input data supplied from the level shifter / pixel driver 163.

(Specific configuration of pixel 12)
Subsequently, a specific configuration of the pixel 12 will be described.
FIG. 2 is a circuit diagram showing a specific configuration of the pixel 12.

As shown in FIG. 2, the pixel 12 is one of the row scanning lines g1 to gm (hereinafter referred to as row scanning line g) and any of the column data lines d1 to dn (hereinafter referred to as column data line d). ) And are provided at the intersection.

The pixel 12 includes a SRAM cell 201, a DRAM cell 202, and a liquid crystal display element LC. The SRAM cell 201 is composed of a switch SW1 which is a first switch and a storage unit SM1 which is a first data holding unit. The DRAM cell 202 is composed of a switch SW2 which is a second switch and a storage unit DM2 which is a second data holding unit. The liquid crystal display element LC has a known structure in which a liquid crystal LCM is filled and enclosed in a space between a reflective electrode PE, which is a pixel electrode having light reflection characteristics arranged so as to be separated from each other, and a common electrode CE having light transmission. Is.

(Structure of SRAM Cell 201)
The switch SW1 is composed of, for example, an N-channel MOS transistor (hereinafter referred to as an HCl transistor) MN1. In the NaCl transistor MN1 constituting the switch SW1, the source is connected to the input terminal (node a) of the storage unit SM1, the drain is connected to the column data line d, and the gate is connected to the row scan line g.

The storage unit SM1 is a self-holding memory composed of two inverters INV11 and INV12 in which one output terminal is connected to the other input terminal. More specifically, the input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NOTE transistor MN1 constituting the switch SW1. The input terminal of the inverter INV12 is connected to the output terminal of the switch SW2 and the inverter INV11.

FIG. 3 is a circuit diagram showing a specific configuration of the inverter INV11.
As shown in FIG. 3, the inverter INV11 has a P-channel MOS transistor (hereinafter referred to as a polyclonal transistor) MP11 and an nanotube transistor MN11 connected in series, and inverts the input signals supplied to the respective gates, respectively. It is a known CMOS inverter that outputs from the drain of. Similarly, the inverter INV12 is a known CMOS inverter which has a photoresist transistor MP12 and an NaCl transistor MN12 connected in series, inverts an input signal supplied to each gate, and outputs the input signal from each drain.

Here, the drive capacities of the inverters INV11 and INV12 are different. Specifically, among the inverters INV11 and INV12 constituting the storage unit SM1, the drive capability of the transistors MP11 and MN11 in the inverter INV11 which is the input side when viewed from the switch SW1 is the inverter which is the output side when viewed from the switch SW1. It is larger than the drive capacity of the transistors MP12 and MN12 in the INV12. As a result, data is easily propagated from the column data line d to the storage unit SM1 via the switch SW1, while data is less likely to be propagated from the storage unit DM2 to the storage unit SM1 via the switch SW2.

Further, the drive capability of the Now's transistor MN1 constituting the switch SW1 is larger than the drive capability of the Now No. transistor MN12 constituting the inverter INV12. As a result, for example, when the storage unit SM1 stores data indicating the H level on the column data line d, the current flowing from the column data line d to the input terminal (node a) of the storage unit SM1 via the switch SW1 is generated. Since the current is larger than the current flowing from the input terminal of the storage unit SM1 to the ground voltage terminal GND via the nanotube transistor MN12, the data can be accurately stored in the storage unit SM1.

(Structure of DRAM Cell 202)
The switch SW2 is a known transmission gate composed of an nanotube transistor MN2 and a polyclonal transistor MP2 connected in parallel. More specifically, in the HCl transistor MN2 and the polyclonal transistor MP2, each source is commonly connected to the output terminal of the storage unit SM1, and each drain is connected to the input terminal of the storage unit DM2 and the reflection electrode PE of the liquid crystal display element LC. It is a common connection. The gate of the MIMO transistor MN2 is connected to the trigger line trig for the forward rotation trigger pulse, and the gate of the polyclonal transistor MP2 is connected to the trigger line trigb for the inverting trigger pulse.

For example, the switch SW2 is turned on when the forward rotation trigger pulse supplied via the trigger line trigger is H level (the reverse rotation trigger pulse supplied via the trigger line trigger is L level), and is turned on from the storage unit SM1. The read data is transferred to the storage unit DM2 and the reflection electrode PE. Further, the switch SW2 is turned off when the forward rotation trigger pulse supplied via the trigger line trigger is at L level (the reverse rotation trigger pulse supplied via the trigger line trigger is at H level), and the storage unit SM1 is turned off. The stored data is not read.

Since the switch SW2 is a known transmission gate, it can transfer a wide range of voltages from the ground voltage GND to the power supply voltage VDD in the ON state. More specifically, when the voltage applied from the storage unit SM1 to the source of the transistors MN2 and MP2 is the ground voltage GND level (L level), the source and drain of the polyclonal transistor MP2 do not conduct, but instead of the SOI transistor MN2. Sources and drains can be conducted with low resistance. On the other hand, when the voltage applied from the storage unit SM1 to the source of the transistors MN2 and MP2 is the power supply voltage VDD level (H level), the source / drain of the MIMO transistor MN2 does not conduct, but the source / drain of the polyclonal transistor MP2 is It can conduct with low resistance. As described above, in the switch SW2, since the source and drain of the transmission gate can be conducted with low resistance, a wide range of voltage from the ground voltage GND to the power supply voltage VDD can be transferred in the ON state.

The storage unit DM2 is composed of the capacity C1. The capacitance C1 includes, for example, a MIM (Metal Insulator Metal) capacitance that forms a capacitance between wirings, a Diffusion capacitance that forms a capacitance between a substrate and polysilicon, or a PIP (Poly) that forms a capacitance between two-layer polysilicon. Insulator Poly) capacity and the like can be used.

When the switch SW2 is turned on, the data stored in the storage unit SM1 is read out and transferred to the capacitance C1 in the storage unit DM2 and the reflective electrode PE via the switch SW2. As a result, the data stored in the storage unit DM2 is rewritten.

Here, when the switch SW2 is turned on, the data held in the capacitance C1 also affects the input gate of the inverter INV12 constituting the storage unit SM1. However, since the drive capacity of the inverter INV11 is larger than the drive capacity of the inverter INV12, the inverter INV11 rewrites the data of the capacity C1 before the inverter INV12 is affected by the data of the capacity C1. Therefore, the data in the storage unit SM1 is not unintentionally rewritten by the retained data in the capacity C1.

As described above, the reflective liquid crystal display device 10 according to the present embodiment uses the pixel 12 having one SRAM cell and one DRAM cell, as compared with the case of using the pixel having two SRAM cells. The number of transistors constituting the pixel is reduced to realize the miniaturization of the pixel.

In the present embodiment, the case where the switch SW2 is composed of the polyclonal transistor MP2 and the EtOAc transistor MN2 has been described, but the present invention is not limited to this. The switch SW2 can be appropriately changed to a configuration in which any one of the polyclonal transistor MP2 and the NaCl transistor MN2 is provided. In that case, only one of the trigger lines rig and rigb will be provided.

The reflective liquid crystal display device 10 can not only realize miniaturization of pixels by reducing the number of transistors constituting the pixels, but also has storage units SM1 and DM2 and a reflective electrode PE as elements as described below. Pixels can be miniaturized by effectively arranging them in the height direction. Hereinafter, it will be described in detail with reference to FIG.

(Cross-sectional structure of pixel 12)
FIG. 4 is a schematic cross-sectional view showing a main part of the pixel 12. Further, in FIG. 4, a case where the capacitance C1 is configured by the MIM forming the capacitance between the wirings will be described as an example.

As shown in FIG. 4, N wells 101 and P wells 102 are formed on the silicon substrate 100.

On the N-well 101, the polyclonal transistor MP2 of the switch SW2 and the polyclonal transistor MP11 of the inverter INV11 are formed. More specifically, on the N well 101, a common diffusion layer serving as a source of the photoresist transistors MP2 and MP11 and two diffusion layers serving as drains are formed, and the common diffusion layer and the two diffusion layers are formed. Polysilicon serving as a gate for each of the photoresist transistors MP2 and MP11 is formed on the channel region between them via the gate oxide film.

An CAUTIONtransistor MN2 of the switch SW2 and an nanotube transistor MN11 of the inverter INV11 are formed on the P well 102. More specifically, a common diffusion layer serving as a source and two diffusion layers serving as drains are formed on the P well 102, and the common diffusion layer and the two diffusion layers are formed. Polysilicon serving as a gate for each of the nanotube transistors MN2 and MN11 is formed on the channel region between them via the gate oxide film.

The device separation oxide film 103 is formed between the active region (diffusion layer and channel region) on the N well and the active region on the P well.

Above the transistors MP2, MP11, MN2, and MN11, an interlayer insulating film 105 is interposed between the metals, and the first metal 106, the second metal 108, the third metal 110, the MIM electrode 112, the fourth metal 114, and the like. The fifth metal 116 is laminated.

The fifth metal 116 constitutes a reflective electrode PE formed for each pixel.

Each diffusion layer constituting each drain of the transistors MN2 and MP2 has a contact 118, a first metal 106, a through hole 119a, a second metal 108, a through hole 119b, a third metal 110, a through hole 119c, and a fourth metal 114. And, it is electrically connected to the fifth metal 116 via the through hole 119e. Further, each diffusion layer constituting each drain of the transistors MN2 and MP2 has a contact 118, a first metal 106, a through hole 119a, a second metal 108, a through hole 119b, a third metal 110, a through hole 119c, and a fourth metal. It is electrically connected to the MIM electrode 112 via the 114 and the through hole 119d. That is, each source of the transistors MN2 and MP2 constituting the switch SW2 is electrically connected to the reflection electrode PE and the MIM electrode 112.

The reflective electrode PE (fifth metal 116) is arranged so as to be separated from the common electrode CE which is a transparent electrode via a passivation film (PSV) 117 which is a protective film formed on the upper surface thereof. A liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE. The liquid crystal display element LC is composed of the reflective electrode PE, the common electrode CE, and the liquid crystal LCM between them.

Here, the MIM electrode 112 is formed on the third metal 110 via the interlayer insulating film 105. The capacitance C1 is configured by the MIM electrode 112, the third metal 110, and the interlayer insulating film 105 between them. Therefore, the switches SW1 and SW2 and the storage unit SM1 are formed by using the first metal 106 and the second metal 108, which are the first and second layer wirings, and the transistor, whereas the storage unit DM2 has them. It will be formed using the third metal 110 and the MIM electrode 112, which are the upper layers. That is, the switches SW1 and SW2, the storage unit SM1, and the storage unit DM2 are formed of different layers.

Light from a light source (not shown) passes through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 116), is reflected, travels backward in the original incident path, and is emitted through the common electrode CE. ..

As described above, the reflective liquid crystal display device 10 uses the fifth metal 116, which is the fifth layer wiring, as the reflection electrode PE, and the third metal 110, which is the third layer wiring, as a part of the storage unit DM2. By using the first metal 106 and the second metal 108, which are the first and second layer wiring, and the transistor as the storage unit SM1, the storage unit SM1, the storage unit DM2, and the reflective electrode PE are effectively arranged in the height direction. Therefore, the pixels can be further miniaturized. Thereby, for example, pixels having a pitch of 3 μm or less can be configured by a transistor having a power supply voltage of 3.3 V. By using the pixels having a pitch of 3 μm or less, it is possible to realize a liquid crystal display panel having a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction and 2000 pixels in the vertical direction.

(Operation of reflective liquid crystal display device 10)
Next, the operation of the reflective liquid crystal display device 10 will be described with reference to FIG.
FIG. 5 is a timing chart showing the operation of the reflective liquid crystal display device 10.

As described above, in the reflective liquid crystal display device 10, the row scanning lines g1 to gm are sequentially selected one by one in 1H units by the row scanning signal from the vertical shift register 14, so that the image display unit 11 is configured. Data is written in the plurality of pixels 12 in units of n pixels in one row commonly connected to the selected row scanning line. Then, when the data is written to all of the plurality of pixels 12 constituting the image display unit 11, the data of all the pixels 12 are read out all at once based on the trigger pulses TRI and TRIB (more specifically, more specifically). The data of the storage unit SM1 in all the pixels 12 is transferred to the storage unit DM2 and the reflection electrode PE all at once).

FIG. 5A shows changes in the subframe data stored in each pixel 12. The vertical axis represents the line number and the horizontal axis represents the time. As shown in FIG. 5A, the boundary line of the subframe data is downward-sloping. This means that the larger the line number of the pixel, the later the subframe data is written. The period from one end to the other end of this boundary line corresponds to the writing period of the subframe data. Note that B0b, B1b, and B2b indicate inverted data of subframe data of bits B0, B1, and B2, respectively.

FIG. 5B shows the output timing (rising timing) of the trigger pulse TRI. The trigger pulse TRIB is omitted because it always indicates a value obtained by logically inverting the trigger pulse TRI. FIG. 5C schematically shows the bits of the subframe data applied to the reflective electrode PE. FIG. 5D shows the change in the value of the common electrode voltage Vcom. FIG. 5 (E) shows the change in the voltage applied to the liquid crystal LCM.

First, since the switch SW1 is turned on in the pixel 12 selected by the row scan signal, the forward rotation subframe data of the bit B0 output from the horizontal driver 16 to the column data line d is sampled by the switch SW1 and stored in the storage unit. Written in SM1. Similarly, the forward rotation subframe data of the bit B0 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11. After that, the H level trigger pulse TRI (and the L level trigger pulse TRIB) are simultaneously supplied to all the pixels 12 constituting the image display unit 11 (time T1).

As a result, the switches SW2 of all the pixels 12 are turned on, so that the normal rotation subframe data of the bit B0 stored in the storage unit SM1 is collectively transferred to the storage unit DM2 through the switch SW2 and held, and the bits are stored. The normal rotation subframe data of B0 is applied to the reflection electrode PE. Here, as can be seen from FIG. 5 (C), the retention period of the normal rotation subframe data of the bit B0 by the storage unit DM2 (the application period of the normal rotation subframe data of the bit B0 to the reflection electrode PE). Is one subframe period from the time when the trigger pulse TRI reaches the H level (time T1) to the time when the trigger pulse TRI reaches the H level again (time T2).

Here, when the bit value of the subframe data is "1", that is, at the H level, the power supply voltage VDD (here 3.3 V) is applied to the reflective electrode PE, and when the bit value is "0", that is, at the L level. A ground voltage GND (0V) is applied to the reflective electrode PE. On the other hand, a free voltage can be applied to the common electrode CE as the common electrode voltage Vcom without being limited by the ground voltage GND and the power supply voltage VDD, and the H level forward trigger pulse TRI can be input. Synchronously, the common electrode voltage Vcom is controlled to switch to a predetermined voltage. In this example, the common electrode voltage Vcom is only the threshold voltage Vtt of the liquid crystal display rather than 0V during the subframe period in which the normal rotation subframe data of the bit B0 is applied to the reflective electrode PE, as shown in FIG. 5 (D). Set to a low voltage.

The liquid crystal display element LC performs gradation display according to the applied voltage of the liquid crystal LCM, which is the absolute value of the difference voltage between the applied voltage of the reflecting electrode PE and the common electrode voltage Vcom. Therefore, during the subframe period (time T1 to T2) in which the normal rotation subframe data of the bit B0 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is the subframe data as shown in FIG. 5 (E). When the bit value is "1", it becomes 3.3V + Vtt (= 3.3V- (-Vtt)), and when the bit value of the subframe data is "0", it becomes + Vtt (= 0V- (-Vtt)). ..

FIG. 6 shows the relationship between the applied voltage (RMS voltage) of the liquid crystal display and the gray scale value of the liquid crystal display.
Referring to FIG. 6, in the gray scale value curve, the black gray scale value corresponds to the RMS voltage of the threshold voltage Vtt of the liquid crystal, and the white gray scale value corresponds to the saturation voltage Vsat (= 3.3 V + Vtt) of the liquid crystal. It is shifted to correspond to the RMS voltage. It is possible to match the grayscale value to the effective part of the LCD response curve. Therefore, as described above, the liquid crystal display element LC displays white when the applied voltage of the liquid crystal LCM is (3.3 V + Vtt), and displays black when the applied voltage is + Vtt.

Returning to FIG. 5, during the subframe period (time T1 to T2) in which the liquid crystal display element LC displays the normal rotation subframe data of the bit B0, the storage unit SM1 of all the pixels 12 constituting the image display unit 11 is used. Writing of the inverted subframe data of bit B0 is sequentially started. Then, when the inverted subframe data of the bit B0 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11, then the H level is applied to all the pixels 12 constituting the image display unit 11. Trigger pulse TRI (and L level trigger pulse TRIB) are simultaneously supplied (time T2).

As a result, since the switches SW2 of all the pixels 12 are turned on, the inverted subframe data of the bit B0 stored in the storage unit SM1 is collectively transferred to the storage unit DM2 through the switch SW2 and held, and the bit B0 is stored. The inverted subframe data of is applied to the reflective electrode PE. Here, as can be seen from FIG. 5 (C), the retention period of the inverted subframe data of the bit B0 by the storage unit DM2 (the period of applying the inverted subframe data of the bit B0 to the reflective electrode PE) is set. It is one subframe period from the time when the trigger pulse TRI reaches the H level (time T2) to the time when the trigger pulse TRI reaches the H level again (time T3). Here, since the inverted subframe data of bit B0 always has an inverse logical value relationship with the forward rotation subframe data of bit B0, when the forward rotation subframe data of bit B0 is "1", it is "0", and the bit. When the normal rotation subframe data of B0 is "0", it is "1".

On the other hand, the common electrode voltage Vcom is higher than 3.3V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the inverted subframe data of the bit B0 is applied to the reflecting electrode PE, as shown in FIG. 5 (D). Set to voltage. Therefore, during the subframe period (time T2 to T3) in which the inverted subframe data of bit B0 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is −Vtt when the bit value of the subframe data is “1”. (= 3.3V- (3.3V + Vtt)), and when the bit value of the subframe data is "0", it becomes -3.3V-Vtt (= 0V- (3.3V + Vtt)).

For example, when the bit value of the forward rotation subframe data of the bit B0 is "1", the bit value of the inverted subframe data of the bit B0 subsequently applied becomes "0". At this time, the applied voltage of the liquid crystal LCM becomes − (3.3V + Vtt), and the direction of the potential is reversed but the absolute value is the same as compared with the case where the normal rotation subframe data of the bit B0 is applied. .. Therefore, the pixel 12 displays white even when the inverted subframe data of the bit B0 is applied, as in the case of applying the normal rotation frame data of the bit B0. When the bit value of the forward rotation subframe data of the bit B0 is "0", the bit value of the inverted subframe data of the bit B0 subsequently applied becomes "1". At this time, the applied voltage of the liquid crystal LCM becomes −Vtt, and the direction of the potential is opposite to that when the normal rotation subframe data of the bit B0 is applied, but the absolute value is the same. Therefore, the pixel 12 displays black even when the inverted subframe data of the bit B0 is applied, as in the case of applying the normal rotation frame data of the bit B0.

Therefore, as shown in FIG. 5 (E), the pixel 12 displays the same gradation in the complementary bits B0b of the bit B0 and the bit B0 during the two subframe periods of the times T1 to T3, and the liquid crystal LCM displays the same gradation. Since the AC drive in which the potential direction is inverted for each subframe is performed, seizure of the liquid crystal LCM can be prevented.

Subsequently, during the subframe period (time T2 to T3) in which the liquid crystal display element LC displays the inverted subframe data of the bit B0, the forward rotation subframe data of the bit B1 is written to the storage unit SM1 of all the pixels 12. Are started sequentially. Then, when the normal rotation subframe data of the bit B1 is written to the storage unit SM1 of all the pixels 12 of the image display unit 11, then the H level trigger is applied to all the pixels 12 constituting the image display unit 11. Pulse TRI (and L-level trigger pulse TRIB) are supplied simultaneously (time T3).

As a result, the switches SW2 of all the pixels 12 are turned on, so that the normal rotation subframe data of the bit B1 stored in the storage unit SM1 is collectively transferred to the storage unit DM2 through the switch SW2 and held. The normal rotation subframe data of bit B1 is applied to the reflection electrode PE. Here, as can be seen from FIG. 5 (C), the retention period of the normal rotation subframe data of the bit B1 by the storage unit DM2 (the application period of the normal rotation subframe data of the bit B1 to the reflection electrode PE). Is one subframe period from the time when the trigger pulse TRI reaches the H level (time T3) to the time when the trigger pulse TRI reaches the H level again (time T4).

On the other hand, the common electrode voltage Vcom is a voltage in which the normal rotation subframe data of the bit B1 is applied to the reflective electrode PE during the subframe period, which is lower than 0V by the threshold voltage Vtt of the liquid crystal display as shown in FIG. 5 (D). Is set to. Therefore, during the subframe period (time T3 to T4) in which the normal rotation subframe data of the bit B1 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is the subframe data as shown in FIG. 5 (E). When the bit value is "1", it becomes 3.3V + Vtt (= 3.3V- (-Vtt)), and when the bit value of the subframe data is "0", it becomes + Vtt (= 0V- (-Vtt)). ..

Subsequently, during the subframe period (time T3 to T4) in which the liquid crystal display element LC displays the normal rotation subframe data of the bit B1, the bit B1 for the storage unit SM1 of all the pixels 12 constituting the image display unit 11 Writing of the inverted subframe data of is started sequentially. Then, when the inverted subframe data of the bit B1 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11, then the H level is applied to all the pixels 12 constituting the image display unit 11. Trigger pulse TRI (and L level trigger pulse TRIB) are simultaneously supplied (time T4).

As a result, since the switches SW2 of all the pixels 12 are turned on, the inverted subframe data of the bit B1 stored in the storage unit SM1 is collectively transferred to the storage unit DM2 through the switch SW2 and held, and the bit B1 is stored. The inverted subframe data of is applied to the reflective electrode PE. Here, as can be seen from FIG. 5 (C), the retention period of the inverted subframe data of the bit B1 by the storage unit DM2 (the period of applying the inverted subframe data of the bit B1 to the reflection electrode PE) is set. It is one subframe period from the time when the trigger pulse TRI reaches the H level (time T4) to the time when the trigger pulse TRI reaches the H level again (time T5). Here, the inverted subframe data of the bit B1 always has an inverse logical value relationship with the normal rotation subframe data of the bit B1.

On the other hand, the common electrode voltage Vcom is higher than 3.3V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the inverted subframe data of the bit B1 is applied to the reflecting electrode PE, as shown in FIG. 5 (D). Set to voltage. Therefore, during the subframe period (time T4 to T5) in which the inverted subframe data of the bit B1 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is −Vtt when the bit value of the subframe data is “1”. (= 3.3V- (3.3V + Vtt)), and when the bit value of the subframe data is "0", it becomes -3.3V-Vtt (= 0V- (3.3V + Vtt)).

As a result, as shown in FIG. 5 (E), the pixel 12 displays the same gradation in the complementary bits B1b of the bit B1 and the bit B1 during the two subframe periods of the times T3 to T5, and the liquid crystal LCM. Since the AC drive in which the potential direction of is reversed for each subframe is performed, it is possible to prevent the liquid crystal LCM from burning. The same operation is repeated for bit B2 and subsequent bits.

In this way, the reflective liquid crystal display device 10 performs gradation display by combining a plurality of subframes.

The display periods of the bit B0 and the complementary bit B0b are the same first subframe period, and the display periods of the bit B1 and the complementary bit B1b are also the same second subframe period, but the first one. The subframe period and the second subframe period are not always the same. Here, as an example, the second subframe period is set to twice the first subframe period. Further, as shown in FIG. 5E, the third subframe period, which is each display period of the bit B2 and the complementary bit B2b, is set to twice the second subframe period. The same is true for other subframe periods. The length of each subframe period and the number of subframes can be arbitrarily set according to the specifications of the system and the like.

(Detailed explanation of the frame portion 21)
Subsequently, the frame portion 21 will be described. The frame portion 21 is a portion that displays black in the outer frame area (frame area) of the image displayed by the image display unit 11 when the image is enlarged and projected by, for example, a projector or the like.

FIG. 7 is a schematic plan view of the reflective liquid crystal display device 10. As shown in FIG. 7, in the reflective liquid crystal display device 10, the image display unit 11 is provided on the chip CHP1, and the frame portion 21 is provided so as to surround the outer periphery of the image display unit 11. Although not shown, a horizontal driver 16 for driving each pixel 12, a vertical shift register 14, a timing generator 13, a data latch circuit 15, and the like are formed in the lower layer of the frame electrode G1 of the frame portion 21. .. Further, a plurality of pads PD1 are provided around the outer periphery of the chip CHP1. Each functional block on the chip CHP1 is connected to, for example, an FPC (Flexible Printed Circuit) via a plurality of pads PD1 and bonding wires, and an image display unit 11 is generated by a control signal from a host device configured by the FPC. The image is displayed by the frame portion 21, and black is displayed by the frame portion 21.

First, the frame portion 51, which is a comparative example of the frame portion 21, will be described.
FIG. 8 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device according to the comparative example, and the frame electrode G5 of the frame portion 51. In the example of FIG. 8, only the reflection electrodes PE of the plurality of pixels 12 provided at the corners of the image display unit 11 and the frame electrodes G5 of the frame portion 51 provided around the reflection electrodes PE are shown.

As shown in FIG. 8, the frame electrode G5 is a solid electrode that spreads without gaps over the entire surface of the frame portion 51, and is formed in the same layer as the reflective electrode PE of the pixel 12. A common electrode CE is arranged so as to be separated from each other on the upper layer of the frame electrode G5, and a liquid crystal LCM is filled and sealed between the common electrode CE and the frame electrode G5. The liquid crystal display element LC_B is composed of the common electrode CE, the frame electrode G5, and the liquid crystal LCM.

Here, the same voltage Vcom as that of the common electrode CE is applied to the frame electrode G5. As a result, the potential difference between the frame electrode G5 and the common electrode CE becomes 0 V, so that black is displayed on the frame portion 51.

The level of black displayed by the frame portion 51 may be the same as the level of black displayed by the image display unit 11 so as not to interfere with the improvement of the quality of the image displayed by the image display unit 11. preferable. However, in reality, the black displayed by the frame portion 51 is displayed blacker than the black displayed by the image display unit 11. Therefore, in the reflective liquid crystal display device on which the frame portion 51 is mounted, there is a problem that the image quality is deteriorated because, for example, the black displayed by the frame portion 51 is overemphasized.

This problem is caused by the aperture ratio of the reflective electrode PE of the pixel 12 (the ratio of the arrangement area of the reflective electrode PE to the pixel arrangement region A1) and the aperture ratio of the frame electrode G5 of the frame portion 51 (an electrode equivalent to the pixel arrangement region A1). This is due to the difference between the ratio of the arrangement area of the frame electrode G5 to the arrangement area A5). Hereinafter, description will be made with reference to FIG.

First, since the reflective electrode PE of the pixel 12 needs to be formed separately from the reflective electrode PE of the adjacent pixel 12, a pixel gap is formed between the reflective electrode PEs. As a result, the aperture ratio of the reflective electrode PE of the pixel 12 decreases. Specifically, the aperture ratio of the reflective electrode PE of the pixel 12 is when the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 is 3.8 μm and the pixel gap L2 is 0.2 μm. , 89.75% (see the left figure in FIG. 9).

On the other hand, the frame electrode G5 of the frame portion 51 is a solid electrode that spreads without a gap over the entire frame portion 51, as described above. Therefore, the aperture ratio of the frame electrode G5 becomes 100% (see the right figure of FIG. 9).

Therefore, even when the same level of black gradation voltage is applied to each of the reflective electrode PE and the frame electrode G5, the black level displayed by each pixel 12 of the image display unit 11 and the frame due to the difference in aperture ratio. The level of black displayed by the unit 51 is different from that of the black level.

More specifically, the light vertically incident on the liquid crystal display elements LC and LC_B passes through the liquid crystal LCM, is reflected vertically by the reflection electrode PE and the frame electrode G5, is modulated by the liquid crystal LCM, and then emits light. Will be done. For example, when displaying black, the deflection direction of light is shifted by 90 degrees as a phase difference by modulation by a liquid crystal LCM. As a result, the progress of light is blocked, so that black is displayed. Here, since the aperture ratios of the reflective electrode PE and the frame electrode G5 that reflect light are different between each pixel 12 of the image display unit 11 and the frame portion 51, the amount of light modulated by the liquid crystal LCM is different. As a result, the displayed black levels are different from each other.

Next, the frame portion 21 according to the present embodiment will be specifically described.
FIG. 10 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 and the plurality of frame electrodes G1 of the frame unit 21. In the example of FIG. 10, only the reflection electrodes PE of the plurality of pixels 12 provided at the corners of the image display unit 11 and the plurality of frame electrodes G1 of the frame portion 21 provided around the reflection electrodes PE are shown. Has been done.

As shown in FIG. 10, the frame portion 21 has a plurality of frame electrodes G1 regularly arranged in each of the plurality of electrode arrangement regions A2 partitioned in a matrix. The electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged. These plurality of frame electrodes G1 are formed in the same layer as the reflective electrode PE of the pixel 12.

A common electrode CE is arranged so as to be separated from each other on the upper layer of each frame electrode G1, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G1. The liquid crystal display element LC_B is composed of the common electrode CE, the frame electrode G1, and the liquid crystal LCM.

Each frame electrode G1 is composed of a rectangular main body portion G1a in a plan view and two connecting portions G1b provided so as to project from one side of the main body portion and another side orthogonal to the main body portion G1a. There is. Each frame electrode G1 is electrically connected to an adjacent frame electrode G1 by a connecting portion G1b. Thereby, the applied voltage of all the frame electrodes G1 of the frame portion 21 can be made the same.

Here, the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G1. As a result, the potential difference between each frame electrode G1 and the common electrode CE becomes 0 V, so that black is displayed on the frame portion 21.

FIG. 11 is a schematic cross-sectional view obtained by cutting out the AA' portion of the schematic plan view shown in FIG.
As shown in FIG. 11, in the frame portion 21, the liquid crystal display element including the frame electrode G1 and the circuit portion in the lower layer than the frame electrode G1 are electrically separated and formed. Therefore, the same voltage Vcom as the common electrode CE can be supplied to the frame electrode G1 regardless of the circuit portion in the lower layer than the frame electrode G1. Since the other cross-sectional structures are the same as those described in FIG. 4, the description thereof will be omitted.

The level of black displayed by the frame portion 21 is as close as possible to the level of black displayed by the image display unit 11 so as not to interfere with the improvement of the quality of the image displayed by the image display unit 11 (ideal). The same) is preferable.

Therefore, in the present embodiment, the aperture ratio of the frame electrode G1 (the ratio of the arrangement area of the frame electrode G1 to the electrode arrangement area A2 equivalent to the pixel arrangement area A1) is set to the aperture ratio of the reflective electrode PE of each pixel 12. It is as close as possible to (ideally the same) the ratio of the arrangement area of the reflective electrode PE to the pixel arrangement area A1). Hereinafter, description will be made with reference to FIG.

First, the aperture ratio of the reflective electrode PE of the pixel 12 is 89.75 when the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 is 3.8 μm and the pixel gap L2 is 0.2 μm. % (See the left figure in FIG. 12).

On the other hand, the aperture ratio of the frame electrode G1 is 89.68, assuming that the length L1 of one side of the square electrode arrangement region A2 is 3.8 μm, the gap L3 is 0.28 μm, and the width L4 of the connecting portion G1b is 1 μm. % (See the right figure in FIG. 12). This is close to the aperture ratio of 89.75% of the reflective electrode PE of the pixel 12.

As described above, in the reflective liquid crystal display device 10 according to the present embodiment, the aperture ratio of each frame electrode G1 is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the present embodiment can bring the black level displayed by the frame portion 21 closer to the black level displayed by the image display unit 11, so that the image quality can be improved. Deterioration can be prevented. In other words, the reflective liquid crystal display device 10 according to the present embodiment can make the level of black displayed by each of the frame portion 21 and the image display unit 11 uniform, so that the image does not give a sense of discomfort to the user. It can be displayed.

(Experimental result)
FIG. 13 is an experimental result showing the relationship between the difference in aperture ratio between the reflective electrode PE and the frame electrode G1 and the difference in the black level displayed by each of the image display unit 11 and the frame unit 21. As shown in the experimental results of FIG. 13, the smaller the difference in aperture ratio between the reflective electrode PE and the frame electrode G1, the smaller the difference in black level displayed by the image display unit 11 and the frame unit 21. When the difference in aperture ratio between the reflective electrode PE and the frame electrode G1 (the difference in the aperture ratio of the frame electrode G1 based on the aperture ratio of the reflective electrode PE) becomes 5% or less, the image display unit 11 and The difference in black level displayed by each of the frame portions 21 has apparently disappeared.

<Embodiment 2>
FIG. 14 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 according to the second embodiment, and the plurality of frame electrodes G2 of the frame portion 31. .. The frame portion 31 corresponds to the frame portion 21, and the frame electrode G2 corresponds to the frame electrode G1. In the example of FIG. 14, only the reflection electrodes PE of the plurality of pixels 12 provided at the corners of the image display unit 11 and the plurality of frame electrodes G2 of the frame portion 31 provided around the reflection electrodes PE are shown. Has been done.

As shown in FIG. 14, the frame portion 31 has a plurality of frame electrodes G2 regularly arranged in each of the plurality of electrode arrangement regions A2 partitioned in a matrix. The electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged. These plurality of frame electrodes G2 are formed in the same layer as the reflective electrode PE of the pixel 12.

A common electrode CE is arranged so as to be separated from each other on the upper layer of each frame electrode G2, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G2. The liquid crystal display element LC_B is composed of the common electrode CE, the frame electrode G2, and the liquid crystal LCM.

Each frame electrode G2 has the same shape as the reflective electrode PE of the pixel 12 in a plan view. Each frame electrode G2 is electrically connected to the adjacent frame electrodes G2 by wiring of a circuit portion formed in a lower layer of the frame electrodes G2. Thereby, the applied voltage of all the frame electrodes G2 of the frame portion 31 can be made the same.

Here, the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G2. As a result, the potential difference between each frame electrode G2 and the common electrode CE becomes 0 V, so that black is displayed on the frame portion 31.

FIG. 15 is a schematic cross-sectional view taken out from the BB' portion of the schematic plan view shown in FIG.
As shown in FIG. 15, in the frame portion 31, adjacent frame electrodes G2 are electrically connected to each other via a fourth metal 114 and a through hole 119e formed in a lower layer of the frame electrodes G2. .. Thereby, the applied voltage of all the frame electrodes G2 of the frame portion 31 can be made the same. The fourth metal 114 and the circuit portion in the lower layer are electrically separated from each other. Therefore, the same voltage Vcom as the common electrode CE can be supplied to the frame electrode G2 regardless of the circuit portion in the lower layer. Since the other cross-sectional structures are the same as those described in FIG. 4, the description thereof will be omitted.

The level of black displayed by the frame unit 31 is as close as possible to the level of black displayed by the image display unit 11 so as not to interfere with the improvement of the quality of the image displayed by the image display unit 11 (ideal). The same) is preferable.

Therefore, in the present embodiment, the aperture ratio of the frame electrode G2 (the ratio of the arrangement area of the frame electrode G2 to the electrode arrangement area A2 equivalent to the pixel arrangement area A1) is set to the aperture ratio of the reflective electrode PE of each pixel 12. It is as close as possible to (ideally the same) the ratio of the arrangement area of the reflective electrode PE to the pixel arrangement area A1). Hereinafter, description will be made with reference to FIG.

First, the aperture ratio of the reflective electrode PE of the pixel 12 is 89.75 when the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 is 3.8 μm and the pixel gap L2 is 0.2 μm. % (See the left figure in FIG. 16).

Further, the aperture ratio of the frame electrode G2 is 89.75% when the length L1 of one side of the square electrode arrangement region A2 is 3.8 μm and the pixel gap L2 is 0.2 μm (right figure of FIG. 16). reference). This is the same as the aperture ratio of the reflective electrode PE of the pixel 12 of 89.75%.

As described above, in the reflective liquid crystal display device 10 according to the second embodiment, the aperture ratio of each frame electrode G2 is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the second embodiment can bring the black level displayed by the frame portion 31 closer to the black level displayed by the image display unit 11, so that the image quality can be improved. Deterioration can be prevented. In other words, the reflective liquid crystal display device 10 according to the second embodiment can make the level of black displayed by each of the frame portion 31 and the image display portion 11 uniform, so that an image that does not give a sense of discomfort to the user can be obtained. It can be displayed.

<Embodiment 3>
Before explaining the frame portion 41 provided in the reflective liquid crystal display device 10 according to the third embodiment, the frame portion 51 will be described again.

As described above, the level of black displayed by the frame portion 51 is the level of black displayed by the image display unit 11 so as not to interfere with the improvement of the quality of the image displayed by the image display unit 11. It is preferable that it is the same as. However, in reality, the black displayed by the frame portion 51 is displayed blacker than the black displayed by the image display unit 11. Therefore, in the liquid crystal display device on which the frame portion 51 is mounted, there is a problem that the image quality is deteriorated because, for example, the black displayed by the frame portion 51 is overemphasized.

This problem is caused not only by the difference between the aperture ratio of the reflective electrode PE of the pixel 12 and the aperture ratio of the frame electrode G5 of the frame portion 51, but also the peripheral length of the reflective electrode PE per the pixel arrangement region A1. This is due to the difference between the length of the edge portion) and the peripheral length of the frame electrode G5 per the electrode arrangement region A5. Hereinafter, description will be made with reference to FIG.

First, since the reflective electrode PE of the pixel 12 needs to be formed separately from the reflective electrode PE of the adjacent pixel 12, a pixel gap is formed between the reflective electrode PE of the pixel 12. As a result, the peripheral length of the reflective electrode PE of the pixel 12 increases. Specifically, the peripheral length of the edge portion of the reflective electrode PE of the pixel 12 is 3.8 μm for the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 and 0.2 μm for the pixel gap L2. In the case of, it becomes 14.44 μm (see the left figure of FIG. 9).

On the other hand, the frame electrode G5 of the frame portion 51 is a solid electrode that spreads without a gap over the entire frame portion 51, as described above. Therefore, the peripheral length of the edge portion of the frame electrode G5 is 0 μm (see the right figure of FIG. 9).

Therefore, even when the same level of black gradation voltage is applied to each of the reflective electrode PE and the frame electrode G5, the black level displayed by each pixel 12 of the image display unit 11 and the frame are due to the difference in peripheral length. The level of black displayed by the unit 51 is different from that of the black level.

More specifically, the light vertically incident on the liquid crystal display elements LC and LC_B passes through the liquid crystal LCM, is reflected vertically by the reflection electrode PE and the frame electrode G5, is modulated by the liquid crystal LCM, and then emits light. Will be done. For example, when displaying black, the deflection direction of light is shifted by 90 degrees as a phase difference by modulation by a liquid crystal LCM. As a result, the progress of light is blocked, so that black is displayed. Here, since the peripheral lengths (lengths of the edge portions) of the reflective electrode PE and the frame electrode G5 that reflect light are different between each pixel 12 of the image display unit 11 and the frame portion 51, diffuse reflection at the edge portion occurs. The degrees will be different, and as a result, the levels of black displayed will be different from each other. For example, if the length of the edge portion is long, the amount of diffused reflection increases, so that the reflected light that is different from the deflection direction of the light increases, and as a result, the displayed black becomes brighter. On the other hand, when the length of the edge portion is short, the amount of diffuse reflection is small, so that the reflected light different from the deflection direction of the light is reduced, and as a result, the displayed black is darkened.

Next, the frame portion 41 according to the present embodiment will be specifically described.
FIG. 17 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 and the plurality of frame electrodes G3 of the frame unit 41. In the example of FIG. 17, only the reflection electrodes PE of the plurality of pixels 12 provided at the corners of the image display unit 11 and the plurality of frame electrodes G3 of the frame portion 41 provided around the reflection electrodes PE are shown. Has been done.

As shown in FIG. 17, the frame portion 41 has a plurality of frame electrodes G3 regularly arranged in each of the plurality of electrode arrangement regions A2 partitioned in a matrix. The electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged. These plurality of frame electrodes G3 are formed in the same layer as the reflective electrode PE of the pixel 12.

A common electrode CE is arranged so as to be separated from each other on the upper layer of each frame electrode G3, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G3. The liquid crystal display element LC_B is composed of the common electrode CE, the frame electrode G3, and the liquid crystal LCM.

Each frame electrode G3 is composed of a rectangular main body portion G3a in a plan view and two connecting portions G3b provided so as to project from one side of the main body portion and another side orthogonal to the main body portion G3a. There is. Each frame electrode G3 is electrically connected to an adjacent frame electrode G3 by a connecting portion G3b. Thereby, the applied voltage of all the frame electrodes G3 of the frame portion 41 can be made the same.

Here, the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G3. As a result, the potential difference between each frame electrode G3 and the common electrode CE becomes 0 V, so that black is displayed on the frame portion 41.

The level of black displayed by the frame unit 41 is as close as possible to the level of black displayed by the image display unit 11 so as not to interfere with the improvement of the quality of the image displayed by the image display unit 11 (ideal). The same) is preferable.

Therefore, in the present embodiment, the peripheral length of the frame electrode G3 is made as close as possible to the peripheral length of the reflective electrode PE of each pixel 12 (ideally, they are the same). Hereinafter, description will be made with reference to FIG.

First, the peripheral length of the reflective electrode PE of the pixel 12 is 14.44 μm, assuming that the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 is 3.8 μm and the pixel gap L2 is 0.2 μm. (See the left figure in FIG. 18).

On the other hand, the aperture ratio of the frame electrode G1 is 14.44 μm when the length L1 of one side of the square electrode arrangement region A2 is 3.8 μm, the gap L3 is 0.28 μm, and the width L4 of the connecting portion G1b is 1 μm. (See the right figure in FIG. 18). This is the same length as the peripheral length of the reflective electrode PE of the pixel 12.

As described above, in the reflective liquid crystal display device 10 according to the third embodiment, the peripheral length (length of the edge portion) of each frame electrode G3 is made as close as possible to the peripheral length of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the third embodiment can bring the black level displayed by the frame portion 41 closer to the black level displayed by the image display unit 11, so that the image quality can be improved. Deterioration can be prevented. In other words, the reflective liquid crystal display device 10 according to the third embodiment can make the level of black displayed by each of the frame portion 31 and the image display portion 11 uniform, so that an image that does not give a sense of discomfort to the user can be obtained. It can be displayed.

(Experimental result)
FIG. 19 is an experimental result showing the relationship between the difference in the peripheral lengths of the reflective electrode PE and the frame electrode G3 and the difference in the black level displayed by each of the image display unit 11 and the frame unit 41. As shown in the experimental results of FIG. 19, the smaller the difference in the peripheral lengths of the reflective electrode PE and the frame electrode G3, the smaller the difference in the black level displayed by the image display unit 11 and the frame unit 41. Then, when the difference in the peripheral lengths of the reflective electrode PE and the frame electrode G3 (the difference in the peripheral length of the frame electrode G3 based on the peripheral length of the reflective electrode PE) becomes 30% or less, the image display unit 11 and the image display unit 11 and The difference in black level displayed by each of the frame portions 41 has apparently disappeared.

As described above, in the reflective liquid crystal display device 10 according to the first to third embodiments, the aperture ratio of each frame electrode is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the third embodiment can bring the black level displayed by the frame portion closer to the black level displayed by the image display portion, so that the image quality is deteriorated. Can be prevented. In other words, the reflective liquid crystal display device 10 according to the third embodiment can make the level of black displayed by each of the frame portion and the image display portion uniform, so that an image that does not give a sense of discomfort to the user is displayed. be able to.

10 Reflective liquid crystal display 11 Image display 12 pixels 13 Timing generator 14 Vertical shift register 15 Data latch circuit 16 Horizontal driver 20 Upper device 21 Frame 31 Frame frame 41 Frame 100 Silicon substrate 101 N-well 102 P-well 103 Element separation Oxide film 105 Interlayer insulating film 106 1st metal 108 2nd metal 110 3rd metal 112 MIM electrode 114 4th metal 116 5th metal 117 Passion film (PSV)
118 Contact 119a to 119e Through hole 161 Horizontal shift register 162 Latch part 163 Level shifter / pixel driver 164 Latch circuit 1641 to 1643 Latch circuit group 201 SRAM cell 202 DRAM cell d1 to dn Column data line dL, dM, dR Column data line group g1 ~ Gm line scanning line transistor, transistor trigger line BF1 buffer C1 capacity CE common electrode CHP1 chip DM2 storage unit G1 to G3 frame electrode G1a, G3a main unit G1b, G3b connection unit INV11, INV12 inverter LC, LC_B , MN2 EtOAc Transistor MN11, MN12 NOTE Transistor MN21, MN22 Integrator Transistor MP2 ProLiant Transistor MP11, MP12 ProLiant Transistor MP21, MP22 ProLiant Transistor PE Reflection Electrode SM1 Storage SW1, SW2 Switch SW21, SW22 Switch

Claims (2)

An image display unit in which a plurality of pixels having reflective electrodes are arranged in a plurality of pixel arrangement areas partitioned in a matrix, and an image display unit.
A picture frame portion provided so as to surround the outer periphery of the image display portion and having a plurality of frame electrodes arranged in a plurality of electrode arrangement regions partitioned in a matrix.
Equipped with
Each picture frame electrode is
The rectangular body and
A connecting portion provided so as to protrude from a part of the outer periphery of the main body portion,
Have,
The difference between the opening ratio of the reflecting electrode, which is the ratio of the reflecting electrode to the pixel arrangement region, and the opening ratio of the frame electrode, which is the ratio of the frame electrode to the electrode arrangement region, is 5% or less. In addition, the gap between the reflective electrodes is such that the ratio of the difference between the peripheral length of the reflective electrode and the peripheral length of the frame electrode is within 30% based on the peripheral length of the reflective electrode. The plurality of frame electrodes having a width of a gap between the main bodies larger than the width are arranged.
Reflective liquid crystal display device. Each of the frame electrodes is formed so as to have the same peripheral length as the peripheral length of each of the reflective electrodes.
The reflective liquid crystal display device according to claim 1.

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