JP7028680B2 - Transmitter, receiver, transmitter and receiver - Google Patents

Description

The present disclosure relates to communication devices and communication methods.

IEEE 802.11 is one of the wireless LAN related standards, and among them, for example, there are IEEE802.11ad standard and IEEE802.11ay standard (hereinafter referred to as "11ad standard" and "11ay standard") (for example, non-patent). See Ref. 1-3).

When the number of data symbols contained in the code word is less than the number of data symbols contained in the OFDM (Orthogonal Frequency Division Multiplexing) symbol, "interleave processing" for rearranging the data symbols within the OFDM symbol is applied. Interleaving distributes the data symbols contained in the codeword over a wide frequency range, thus improving the communication quality in the frequency selective channel.

IEEE 802.11TM -2016 pp. 2436-2496 IEEE 802.11-17 / 0589r0 IEEE 802.11-17 / 0597r1

However, when the codeword is fragmented and arranged in multiple OFDM symbols, the interleave pattern such that the fragmented codeword is arranged in a wide frequency domain has not been sufficiently examined, so the frequency selection is performed. Communication quality may deteriorate in the sex channel.

One aspect of the present disclosure is a simple configuration in which codewords fragmented into a plurality of OFDM symbols can be interleaved so as to be arranged in a wide frequency domain, improving communication quality in a frequency selective channel. It contributes to the provision of a transmitting device, a receiving device, a transmitting method, and a receiving method that can be made to operate.

The transmitter according to one aspect of the present disclosure includes an interleaver circuit that interleaves the first to Nth codewords, an OFDM modulation circuit that converts the interleaved first to Nth codewords into an OFDM signal, and the like. The interleaver circuit comprises a transmission circuit for transmitting an OFDM signal, the number of data symbols included in the first code word is smaller than the number of data symbols included in the second code word, and the interleaver circuit is provided. Writing is performed in ascending order from the first code word to the Nth code word, and reading is started from the second code word.

The receiving device according to one aspect of the present disclosure includes a receiving circuit that receives an OFDM signal including the first to N codewords interleaved in the transmitting device, and the interleaved first to Nth from the OFDM signal. A DFT circuit that extracts the codeword of the above and a deinterleaver circuit that deinterleaves the interleaved first to Nth codewords, and the number of data symbols included in the first codeword is The interleaved first to Nth codewords, which are less than the number of data symbols contained in the second codeword, are the first to Nth codewords in the interleaver circuit of the transmitter. The code words are written in ascending order, and reading is started from the second code word to generate the code word.

In the transmission method according to one aspect of the present disclosure, the first to Nth codewords are interleaved, the interleaved first to Nth codewords are converted into an OFDM signal, and the OFDM signal is transmitted. The number of data symbols included in the first codeword is smaller than the number of data symbols included in the second codeword, and the first codeword is written in ascending order from the first codeword to the Nth codeword, and the second codeword is written. Reading is started from the code word of.

The receiving method according to one aspect of the present disclosure receives an OFDM signal including the first to N codewords interleaved in the transmitting device, and receives the interleaved first to N codewords from the OFDM signal. Is extracted, the interleaved first to Nth codewords are deinterleaved, and the number of data symbols contained in the first codeword is less than the number of data symbols contained in the second codeword. , The interleaved first to Nth codewords are written in ascending order from the first codeword to the Nth codeword in the interleaver circuit of the transmitter, and from the second codeword. Read is started and generated.

It should be noted that these comprehensive or specific embodiments may be realized in a system, an apparatus, a method, an integrated circuit, a computer program, or a recording medium, and the system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium may be realized. It may be realized by any combination of.

According to one aspect of the present disclosure, with a simple configuration, codewords fragmented into a plurality of OFDMs can be interleaved so as to be arranged in a wide frequency domain, and communication quality in a frequency selective channel can be improved. Can be improved.

Further advantages and effects in one aspect of the present disclosure will be apparent from the specification and drawings. Such advantages and / or effects are provided by some embodiments and the features described in the specification and drawings, respectively, but not all need to be provided in order to obtain one or more identical features. There is no.

A block diagram showing a configuration example of a communication device according to the first embodiment. The figure which shows the operation example of the interleaver which concerns on Embodiment 1. The figure which shows another operation example of the interleaver which concerns on Embodiment 1. A flowchart showing the procedure of interleaving according to the first embodiment. A flowchart showing the procedure of interleaving according to the first embodiment. A flowchart showing the procedure of interleaving according to the first embodiment. The figure schematically explaining the writing operation of the interleaver which concerns on Embodiment 1. The figure schematically explaining the read operation of the interleaver which concerns on Embodiment 1. The figure which shows an example of the address table which concerns on Embodiment 1. The figure which shows the relationship between the two-dimensional array of interleave and a code word in OFDM symbol 0 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 0 which concerns on Embodiment 1. The figure which shows the relationship between the two-dimensional array of interleave and a code word in OFDM symbol 1 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 1 which concerns on Embodiment 1. The figure which shows the relationship between the two-dimensional array of interleave and a code word in OFDM symbol 2 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 2 which concerns on Embodiment 1. A flowchart showing another procedure of interleaving according to the first embodiment. A flowchart showing another procedure of interleaving according to the first embodiment. A flowchart showing another procedure of interleaving according to the first embodiment. The figure schematically explaining the read operation of the interleaver in OFDM symbol 1 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 1 which concerns on Embodiment 1. The figure schematically explaining the writing operation of the interleaver when the writing start position is changed in the OFDM symbol 1 which concerns on Embodiment 1. The figure schematically explaining the read operation of the interleaver when the writing start position is changed in the OFDM symbol 1 which concerns on Embodiment 1. The figure schematically explaining the read operation of the interleaver when the read start position in the OFDM symbol 2 which concerns on Embodiment 1 is set. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 2 which concerns on Embodiment 1. The figure which shows an example of the value of idx1 (n) and idx2 (n, 1) in OFDM symbol 1 which concerns on Embodiment 1. A block diagram showing a configuration example of the interleaver according to the first embodiment. A block diagram showing another configuration example of the interleaver according to the first embodiment. The figure which shows an example of the value of idx3 (n) and idx4 (n, 1) in OFDM symbol 1 which concerns on Embodiment 1. A block diagram showing another configuration example of the interleaver according to the first embodiment. The figure which shows the correspondence example of the data subcarrier order and the subcarrier number which concerns on Embodiment 1. The figure schematically explaining another operation example of the interleaver in OFDM symbol 0 which concerns on Embodiment 1. The figure schematically explaining another operation example of the interleaver in OFDM symbol 1 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 0 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 1 which concerns on Embodiment 1. The figure schematically explaining another operation example of the interleaver in OFDM symbol 0 which concerns on Embodiment 1. The figure schematically explaining another operation example of the interleaver in OFDM symbol 1 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 0 which concerns on Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 1 which concerns on Embodiment 1. The figure schematically explaining another operation example of the interleaver in OFDM symbol 0 which concerns on Embodiment 1. The figure schematically explaining another operation example of the interleaver in OFDM symbol 1 which concerns on Embodiment 1. A flowchart showing an interleaving procedure according to a modified example of the first embodiment. The figure which shows an example of the cyclic shift which concerns on the modification of Embodiment 1. The figure which shows the distribution of the data symbol of each code word in OFDM symbol 1 which concerns on the modification of Embodiment 1. Block diagram showing a configuration example of the communication device according to the second embodiment A block diagram showing a configuration example of the deinterleaver according to the second embodiment. A timing chart showing an example of the operation of the row counter and the column counter according to the second embodiment.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

In the 11ay standard, LDPC (Low Density Parity Check) coding is used, and rate matching (adjustment of codeword size) is not performed. Therefore, in the 11ay standard, the calculation amount (complexity of calculation and circuit scale) of the coding and decoding processing per transmission bit can be kept constant, and the circuit scale or power consumption can be reduced.

On the other hand, in the 11ay standard, the number of bits contained in the OFDM symbol and the number of LDPC-encoded bits (codeword size) do not have a multiple or divisor relationship. Therefore, the code word may be divided and included in different OFDM symbols, and the performance (communication quality) may deteriorate depending on the interleaving method.

Also, in the 11ay standard, because of the wide band (for example, up to 8.64GHz), the number of subcarriers and bits in one OFDM symbol is large, while the LDPC-encoded bits are used to reduce the amount of coding and decoding calculations. The number is small (the codeword size is small). Therefore, in the 11ay standard, small codewords are divided, and the problem of performance deterioration due to the inability to disperse codewords over a wide range within the band is likely to occur.

In another standard, for example LTE, the bandwidth is small, such as 100MHz, and the codeword size is large, such as 6144 bits. Therefore, in LTE, even if the codeword is divided, the codeword data can be distributed in a sufficiently wide range within the band. In LTE, rate matching (puncturing) can be performed using a turbo code so that the codeword size matches the OFDM symbol size or the codewords are distributed. Therefore, 11ay as described above. The same problem as the standard does not occur. However, since puncturing (discarded on the transmitter side) encodes and decodes bits that are not transmitted, the circuit scale and power consumption increase.

Further, in other standards, for example, the 11ad standard, the codeword size is a divisor of the number of bits that can be included in the OFDM symbol, so that the codeword is not divided.

Therefore, in the present disclosure, even when the codeword is divided into a plurality of OFDM symbols as in the 11ay standard, the codeword is distributed over a wide frequency domain and the codeword can be arranged to improve the communication quality. explain.

(Embodiment 1)
[Communication device configuration]
FIG. 1 is a diagram showing an example of a configuration of a communication device. The communication device 100 includes a MAC (Medium Access Control) control circuit 101, an FEC (Forward Error Correction) coding circuit 102, a modulation circuit 103, an interleaver 104, an OFDM modulation circuit 105, a transmission RF circuit 106, a transmission antenna array 107, and a reception. Antenna array 111, receive RF circuit 112, synchronization circuit 113, DFT (Discrete Fourier Transform) circuit 114, equalization circuit 115, deinterleaver 116, demodulation circuit 117, FEC decoding circuit 118, channel estimation circuit 119. It is a configuration including.

In the communication device 100, the MAC control circuit 101, the FEC coding circuit 102, the modulation circuit 103, the interleaver 104, the OFDM modulation circuit 105, the transmission RF circuit 106, and the transmission antenna array 107 constitute, for example, a transmission device. The receiving antenna array 111, the receiving RF circuit 112, the synchronization circuit 113, the DFT circuit 114, the equalization circuit 115, the deinterleaver 116, the demodulation circuit 117, the FEC decoding circuit 118, and the channel estimation circuit 119 constitute, for example, a receiving device. ..

The MAC control circuit 101 generates transmission data based on the data input from the application processor (not shown) and inputs the transmission data to the FEC coding circuit 102. Further, the MAC control circuit 101 determines transmission parameters (for example, radio channel to be used, transmission data size, number of channel bonds, LDPC coding method, antenna directivity, etc.), and based on the determined transmission parameters, the FEC code. It controls the conversion circuit 102, the modulation circuit 103, the interleaver 104, the OFDM modulation circuit 105, the transmission RF circuit 106, and the transmission antenna array 107 (not shown).

Further, the MAC control circuit 101 determines the reception parameters (for example, the radio channel to be used, the number of channel bonds, the reception power threshold, the antenna directivity, etc.), and based on the determined reception parameters, the receive antenna array 111 and the receive RF. It controls the circuit 112, the synchronization circuit 113, the DFT circuit 114, the equalization circuit 115, the deinterleaver 116, the demodulator circuit 117, the FEC decoding circuit 118, and the channel estimation circuit 119 (not shown). The MAC control circuit 101 receives the received data from the FEC decoding circuit 118 and outputs it to an application processor (not shown).

The FEC coding circuit 102 adds an error detection code, bit scrambles, and error correction coding to the transmitted data. As an example, a CRC (Cyclic Redundancy Check) code is used as the error detection code. In bit scramble, the FEC coding circuit 102 generates a pseudo-random sequence, an M sequence, or a Gold sequence as an example, and performs XOR (exclusive OR) on the transmitted data. In the error correction code, an LDPC code, a turbo code, or a Reed-Solomon code is used as an example.

The modulation circuit 103 data-modulates the data (bit series) output by the FEC coding circuit 102 and converts it into a data symbol. Modulation methods include, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), SQPSK (Spread QPSK), 16QAM (16-value Quadrature Amplitude Modulation), 64QAM (64-value QAM), 64NUC (64-value Non-). Uniform Constellation) is used.

The interleaver 104 rearranges the order of data symbols in a block of data symbols (such as a codeword) containing a plurality of data symbols according to a certain rule. Details of the interleaver 104 will be described later.

The OFDM modulation circuit 105 converts the codeword interleaved in the interleaver 104 into an OFDM signal. Specifically, the Fourier modulation circuit 105 inserts a pilot symbol into a block of rearranged data symbols output by the interleaver 104, and sets the frequency (called a subcarrier) for transmitting each data symbol and pilot symbol. It is determined, each data symbol and pilot symbol are placed in the subcarrier (called subcarrier mapping), IDFT (Inverse Discrete Fourier Transform) is performed, and a time domain signal sequence (called OFDM symbol) is generated.

Further, the OFDM modulation circuit 105 copies the data in the latter half of the OFDM symbol and adds it before the OFDM symbol (referred to as CP (Cyclic Prefix) addition). Further, the OFDM modulation circuit 105 adjusts the amplitude near the beginning and the end of the OFDM symbol to which CP is added and applies a filter (referred to as a window function). The CP may be called a GI (Guard Interval).

The communication device 100 includes a preamble generation circuit (not shown) and a header signal generation circuit that generate a time domain signal sequence related to a preamble, a header, and a beam forming training sequence in addition to the time domain signal sequence generated by the OFDM modulation circuit 105. (Not shown), beam forming training sequence signal generation circuit (not shown) may be provided. The preamble, header, and beamforming training sequence may be input to the OFDM modulation circuit 105 in the same manner as the block of data symbols, subcarrier mapping, IDFT may be performed, and an OFDM symbol may be generated.

Further, the communication device 100 combines a time region signal sequence generated by the OFDM modulation circuit 105 and a time region signal sequence related to a preamble, a header, and a beam forming training sequence to generate a PHY frame (not shown). ) May be provided after the OFDM modulation circuit 105.

The transmission RF circuit 106 converts the time region signal sequence output by the OFDM modulation circuit 105 and the PHY frame generation circuit (not shown) into an analog signal using a D / A converter, and converts it into a radio region signal (for example, a 60 GHz band signal). It modulates (called up-conversion) and amplifies the power.

The transmitting antenna array 107 includes one or more antenna elements, and transmits a signal output by the transmitting RF circuit 106 as a radio signal. The transmitting antenna array 107 is, for example, a phased array antenna.

The receiving antenna array 111 includes one or more antenna elements and receives a radio signal. The receiving antenna array 111 is, for example, a phased array antenna.

The receiving RF circuit 112 amplifies the radio signal received by the receiving antenna array 111 (AGC, Automatic Gain Control, and automatic gain adjustment are performed), and demodulates the radio region signal into a baseband signal (called down-conversion). , Converted to a digital signal using an A / D converter and input to the synchronization circuit 113.

The synchronization circuit 113 performs preamble signal detection, symbol timing detection, and carrier frequency offset correction for the signal output by the reception RF circuit 112.

The DFT circuit 114 extracts a plurality of interleaved codewords from the OFDM symbol (OFDM signal). Specifically, the DFT circuit 114 removes the CP from the signal output by the synchronization circuit 113, and extracts the received OFDM symbol data. Further, the DFT circuit 114 performs DFT on the received OFDM symbol data and converts it into a frequency domain received signal.

The equalization circuit 115 uses the reception pilot symbol signal included in the frequency domain reception signal and the channel information (referred to as the channel estimation matrix) output by the channel estimation circuit 119 (described later) to receive the reception included in the frequency domain reception signal. Corrects the frequency characteristics of the data subcarrier signal.

The equalization circuit 115 may perform receive diversity synthesis, maximum ratio synthesis, and MIMO (Multi-Input Multi-Output) signal separation processing.

The equalization circuit 115 is, for example, ZF (Zero-Forcing) method, MMSE (Minimum Mean Square Error) method, MLD (Maximum Likelihood Detection) method, MRC (Maximum Ratio Combining) method, MMSE-IRC (MMSE Interference Rejection Combining). ) Method may be used.

The deinterleaver 116 rearranges (deinterleaves) the received data subcarrier signal after frequency correction output by the equalization circuit 115. As the sorting rule used by the deinterleaver 116, a rule opposite to the sorting rule used by the interleaver 104 may be used. The deinterleaver 116 may perform a process of rearranging the data symbols rearranged by the interleaver 104 in the original order. The details of the deinterleaver 116 will be described later.

The demodulation circuit 117 demodulates, for example, BPSK, QPSK, SQPSK, 16QAM, 64QAM, and 64NUC modulation signals and converts them into a bit data series.

The FEC decoding circuit 118 performs error correction decoding (using an LDPC decoder and a turbo decoder as an example) and descramble (reverse scramble) processing on a bit data series. The FEC decoding circuit 118 outputs the data obtained by performing error correction decoding and descramble to the MAC control circuit 101.

The channel estimation circuit 119 calculates a channel estimation matrix using the received preamble signal and pilot subcarrier signal.

The communication device 100 may include a header receiving circuit (not shown) that receives a header signal and performs equalization, demodulation, and FEC decoding.

[Operation of interleaver]
<Operation example 1>
The operation of the interleaver 104 will be described with reference to FIG. As an example, the LDPC codeword size (represented as "L _CW ") is 672 bits, the modulation method is 16QAM, the number of bits per symbol (represented as "N _CBPS ") is 4, and the number of data subcarriers (represented as "N _SD "). The case where (expressed as) is 336 subcarriers will be described.

The number of data symbols per codeword is calculated by L _CW / N _CBPS , which is 168 symbols in the example of FIG. That is, in FIG. 2, the number of data subcarriers (N _SD = 336) is a multiple (double) of the number of data symbols per codeword (L _CW / N _CBPS = 168). Therefore, the interleaver 104 sorts the data each time a data symbol corresponding to two codewords (336 symbols in total) is input, and obtains data of 336 subcarriers (corresponding to one OFDM symbol). Output.

In FIG. 2, the interleaver 104 rearranges the data symbols as follows. First, the interleaver 104 arranges the first data symbol of the first code word (referred to as code word 1; the same applies hereinafter) to the first subcarrier (for example, the data subcarrier having the lowest frequency). Next, the interleaver 104 sets the data symbol at the beginning of the second codeword (referred to as codeword 2; the same applies hereinafter) to the second subcarrier (for example, the data sub having the next lowest frequency after the first subcarrier). Place in the carrier).

When the data symbol of codeword 1 is represented by d (0) to d (167) and the data symbol of codeword 2 is represented by d (168) to d (335), the interleaver 104 represents the data symbol d (idx (idx (idx)). k)) is placed in the subcarrier number k. idx (k) is calculated by Equation 1.

In Equation 1, "mod" in the first term represents a modulo operation, and the second term can be expressed as a floor function (the second term in Equation 1 can be expressed as a floor function: floor (x), and does not exceed x. Find the largest integer).

In FIG. 2, the case where the number of data subcarriers (N _SD ) is twice the number of data symbols per code word (L _CW / N _CBPS ) has been described, but as in FIG. 2, the data subcarriers have been described. If the number (N _SD ) is a multiple of the number of data symbols per codeword (L _CW / N _CBPS ), the interleaver 104 places the data symbol d (idx (k)) in the subcarrier number k. .. idx (k) is calculated by Equation 2.

Equation 2 is expressed as in Equation 3 using variables N _x and N _y . The variables N _x and N _y are defined by Equations 4 and 5.

Further, in FIG. 2 and Equation 1, Equation 2, and Equation 3, the case where the interleaver 104 takes out one data symbol for each code word and arranges it from the beginning of the subcarrier (idx (k) = 0) has been described. However, the interleaver 104 may take out N _S data symbols (called data symbol groups) for each codeword and place them from the beginning of the subcarrier (idx (k) = 0) (process N _S symbols one by one, ). N _S may be, for example, 8 or any other value.

The interleaver 104 may maintain the order of the data symbols in the data symbol group before and after the interleave processing. Further, the interleaver 104 may rearrange the order of the data symbols in the data symbol group before and after the interleave processing according to a certain rule.

If the interleaver 104 processes _NS symbols at a time, the interleaver 104 places the data symbol d (idx (k)) in the subcarrier number k. idx (k) is calculated by Equation 6, Equation 7, Equation 8, and Equation 9.

The difference between Equation 7 and Equation 3 is that the value of N _y used in Equation 7 is 1/1 N _S compared to N _y used in Equation 3 (see Equation 9). When the equation 6 is used, the interleaver 104 may transfer (for example, write to the memory) N _S data symbols together. Further, when the equation 6 is used, the interleaver 104 may calculate one interleave address for each _NS data symbol. Further, when the equation 6 is used, since the values of N _x and N _y are small, the calculation of the equation 6 becomes easy, so that the circuit scale can be reduced and the processing speed (throughput) of the circuit can be increased.

The equation 6 may be expressed as in the equation 10 using the variables i and j. Equation 11 represents the relationship between i, j and k.

<Operation example 2>
FIG. 3 shows another example showing the operation of the interleaver 104. In FIG. 3, the LDPC code word size (expressed as L _CW ) is 672 bits, the modulation method is 16QAM, the number of bits per symbol (expressed as _{NC BPS} ) is 4, and the number of data subcarriers (expressed as N _SD ) is 728. The subcarrier and processing unit ( _NS ) are 8 symbols. In addition, CW represents a code word.

The N _S data symbols are called "data symbol groups", and the N _S subcarriers are called "subcarrier groups". In FIG. 3, one codeword contains 168 (= L _CW / N _CBPS ) data symbols. Therefore, one codeword contains 21 (= L _CW / N _CBPS / N _S ) data symbol groups. Also, in FIG. 3, the 1OFDM symbol contains 728 (= N _SD ) data subcarriers. Therefore, one OFDM symbol contains 91 (= N _SD / N _S ) subcarrier groups.

In FIG. 3, unlike FIG. 2, the number of data subcarriers is not a multiple of the number of symbols per codeword. In this case, the interleaver 104 uses Equation 12 instead of Equation 8 to calculate N _x .

The right-hand side of the equation 12 represents a ceiling function (the right-hand side of the equation 12 can also be expressed as a ceiling function: ceiling (x), and the smallest integer greater than or equal to x is obtained).

Compared to Equation 8, Equation 12 has an additional sealing function, so even if N _SD is not divisible by L _CW / N _CBPS , N _x becomes an integer.

4A, 4B, and 4C are examples of a flowchart showing a procedure in which the interleaver 104 performs interleaving according to the present embodiment. The interleaving procedure is schematically described using a two-dimensional array (see below).

FIG. 4A is a method for directly embodying a procedure using a two-dimensional array. Further, FIG. 4B is a method suitable for modifying the procedure of FIG. 4A and embodying it by using a one-dimensional memory (for example, RAM) instead of the two-dimensional array. FIG. 4C is a method of pre-calculating the interleaved address in FIG. 4B to reduce the circuit scale.

FIG. 4A is a flowchart showing the procedure of the operation in which the interleaver 104 performs interleaving using N _x and N _y calculated by using equations 12 and 9. Further, FIGS. 5A and 5B are diagrams schematically illustrating the operation of the interleaver 104 of FIG. 4A.

In FIGS. 5A and 5B, d (k) represents the kth data symbol group (k is an integer of 0 or more and L _SD / N _S -1 or less). When the hth data symbol is expressed as c (h) (h is an integer of 0 or more and N _SD -1 or less), the series of data symbols represented by d (k) is {c (k × N _S ), c (k × N _S +1), c (k × N _S +2), ..., c (k × N _S + N _S -2), c (k × N _S + N _S -1)} including.

In step S1001 of FIG. 4A, the interleaver 104 calculates (determines) the values of N _x and N _y using the formulas 12 and 9. 5A and 5B illustrate the operation of the interleaver 104 of FIG. 4A using a two-dimensional array of N _x rows and N _y columns. Therefore, N _x is called the "number of rows" of the two-dimensional array, and N _y is called the "number of columns" of the two-dimensional array. The interleaver 104 may implement a two-dimensional array using a memory or a register array. That is, the interleaver 104 has a memory size of N _x × N _y .

In step S1002, the interleaver 104 writes the data symbol group d (k) in the row direction of the two-dimensional array (see FIG. 5A). The interleaver 104 writes N _y data symbol groups d (0) to d (N _y -1) to the row number 0 of the two-dimensional array, and from N _y data symbol groups d (N _y ). Write d (2N _y -1) to line number 1 of the two-dimensional array. The interleaver 104 writes to each line in the same manner, and the line number N _x -1 (last line; line number 4 in FIG. 5A) contains N _y or less data symbol groups d ((N _x -1)). × Write d (N _SD / N _S -1) from N _y ).

In step S1003, the interleaver 104 writes dummy data to the remaining elements in the last row. For example, if the data symbol is an 8-bit binary number, the minimum negative value may be dummy data, such as 1000_0000 (-128 in decimal). The interleaver 104 may leave the remaining elements in the last line empty instead of writing dummy data.

In step S1004, the interleaver 104 discards dummy data and reads out the data symbol group d (k) in the column direction of the two-dimensional array. In FIG. 5B, the columns of the data symbol group read by the interleaver 104 are, for example, {d (0), d (21), d (42), d (63), d (84), d (1), d (22), d (43), d (64), d (85), d (2), ..., d (81), d (19), d (40), d (61), d (82), d (20), d (41), d (62), d (83)}.

FIG. 4B is a flowchart showing another procedure in which the interleaver 104 performs interleaving in FIG. FIG. 4B uses a procedure different from that of FIG. 4A, but a similar data symbol sequence is output. In FIG. 4B, the same reference numerals are given to the same operations as those in FIG. 4A.

In step S1001 of FIG. 4B, the interleaver 104 calculates (determines) the number of rows N _x and the number of columns N _y using equations 12 and 9 in the same manner as in step S1001 of FIG. 4A.

In step S1101, the interleaver 104 calculates the block interleaved address id x0 (i) (i is an integer of 0 or more and N _x × N _y -1 or less) using the equation 13A.

Equation 13A is the same calculation equation as Equation 7, but the range of values of the index i is different, and instead of 0 or more and N _SD / N _S -1 or less, it is 0 or more and N _x × N _y -1 or less. ..

In step S1102, the interleaver 104 is a sequence of block interleaved addresses calculated in step S1101 {idx0 (0), idx0 (1), ..., idx0 (N _x × N _y -2), idx0 (N _x ×). From N _y -1)}, remove the value greater than or equal to the number of data symbol groups (N _SD / N _S ) (that is, the block interleaved address idx0 (i) greater than or equal to the index i = N _SD / N _S ), and the sequence of interleaved addresses. Generate {idx1 (0), idx1 (1), ..., idx1 (N _SD / N _S -2), idx1 (N _SD / N _S -1)}.

In step S1103, the interleaver 104 writes the data symbol group d (k) to memory (not shown) using ascending address. The interleaver 104 writes the data symbol group d (k) to the address k in memory.

In step S1104, the interleaver 104 reads the data symbol group from the memory using the interleaved address idx1 (k) generated in step S1102. For example, the interleaver 104 sets the read address to the value of idx1 (0), reads the data symbol group from the memory, and sets it as the head data of the subcarrier group. That is, the data symbol group (d (idx1 (k)) stored in the address idx1 (k) in the memory is arranged at the position of the subcarrier group number k.

In FIG. 4B, the columns of the data symbol group read by the interleaver 104 are, for example, {d (idx1 (0)), d (idx1 (1)), d (idx1 (2)), ..., d ( idx1 (k)), ..., d (idx1 (N _SD / N _S -2)), d (idx1 (N _SD / N _S -1))}.

FIG. 4C is a flowchart showing another procedure in which the interleaver 104 performs interleaving in FIG. FIG. 4C uses a procedure different from that of FIGS. 4A and 4B, but outputs a similar data symbol sequence. In FIG. 4C, the same reference numerals are given to the same operations as those in FIG. 4B.

In step S1202, the interleaver 104 calculates the interleaved address idx1 (k) from the number of data subcarriers N _SD and the codeword size L _CW . The interleaver 104 may calculate the interleave address idx1 (k) using the same procedure as in steps S1001 to S1102 of FIG. 4B.

Further, the interleaver 104 may calculate the interleave address idx1 (k) in advance for each combination of the number of data subcarriers N _SD and the code word size L _CW and store it as a table (“address table”). Call). The address table may be stored in ROM (Read Only Memory), RAM (Random Access Memory), registers, or the like.

FIG. 5C is a table showing an example of an address table. The address table of FIG. 5C is used when the number of data symbol groups N _SD / N _S is 91 and the code word size L _CW is 672.

According to the address table of FIG. 5C, as an example, when the value of k is 0, the value of idx1 (k) is 0, and when the value of k is 1, the value of idx1 (k) is 21.

In FIG. 4C, steps S1103 and S1104 are similar to those in FIG. 4B.

In FIG. 4C, the columns of the data symbol group read by the interleaver 104 are, for example, {d (idx1 (0)), d (idx1 (1)), d (idx1 (2)), ..., d ( It becomes like idx1 (N _SD / N _S -2)), d (idx1 (N _SD / N _S -1))}. Here, according to the address table of FIG. 5C, the values of idx1 (0) to idx1 (N _SD / N _S -1) are determined. Therefore, the column of the data symbol group read by the interleaver 104 is {d as an example. (0), d (21), d (42), ..., d (62), d (83))}. That is, it is the same as the series of data symbol groups obtained by the procedure of FIG. 4A.

6A shows the two-dimensional array (write and read) of FIGS. 5A and 5B and the code word (CW) when interleaving the data symbol group corresponding to the OFDM symbol number 0 (OFDM symbol 0) of FIG. It is a figure which shows the relationship of.

In FIG. 6A, the data symbol group of codeword 1 (CW1) is arranged in row 0 of the two-dimensional array. Similarly, the data symbol group of the codeword j + 1 (j is an integer of 0 or more and N _x -1 or less) is arranged at the line number j of the two-dimensional array. In the last row (line number N _x -1), the data symbol group may not be placed in the entire row. Some data symbol groups of codeword N _x (codeword 5 (CW5) in FIG. 6A) are included in the last line of OFDM symbol 0, and the remaining data symbol groups of codeword 5 (CW5) are as follows: It may be included in the first line of OFDM symbol 1. The method of arranging the data in OFDM symbol 1 will be described later (see FIG. 7A).

In FIG. 6A, since different codeword data symbol groups are arranged for each row, when the interleaver 104 reads data in the column direction (steps S1004, 4B, 4C of FIGS. 5B and 4A). (See S1104), two consecutive data symbol groups are data symbol groups contained in different codewords.

Therefore, for example, when signal quality deterioration occurs in a continuous frequency band (a constant frequency range narrower than the transmission band) due to multipath in a communication path, the data symbol group whose quality has deteriorated is distributed to a plurality of codewords. Therefore, the quality between the code words can be made uniform, and the deterioration of the packet error rate can be prevented. That is, since the interleaver 104 can prevent quality deterioration from concentrating on the data symbol group included in a specific code word, it is possible to improve the error rate after error correction.

Further, according to the arrangement of FIG. 6A and the address table of FIG. 5C, the data symbol group of the code word 1 has a rank (k) of 0,5,10,15,20,25,30,35,39 after reading. , 43,47,51,55,59,63,67,71,75,79,83,87. Note that k = 0 corresponds to a low frequency data subcarrier, and k = 90 corresponds to a high frequency data subcarrier.

FIG. 6B is a diagram showing the distribution of the data symbol of each codeword in the frequency domain at OFDM symbol number 0 (OFDM symbol 0). In the arrangement of FIG. 6A, the interleaver 104 widely distributes the data symbols of codeword 1, codeword 2, codeword 3, and codeword 4 from low frequency data subcarriers to high frequency data subcarriers. Can be placed.

As described above, the interleaver 104 can disperse and arrange the data symbol group included in each codeword widely from the low frequency data subcarrier to the high frequency data subcarrier. As a result, for example, when the reception quality varies from frequency to frequency due to the multipath of the communication path, it is possible to prevent the quality deterioration from concentrating on the data symbol group included in a specific code word. The error rate can be improved.

Next, FIG. 7A shows the two-dimensional array (write and read) of FIGS. 5A and 5B and the code word (in the case of interleaving the data symbol group corresponding to the OFDM symbol number 1 (OFDM symbol 1) of FIG. 3). It is a figure which shows the relationship with CW).

In FIG. 7A, the interleaver 104 places the remaining data symbol groups in codeword 5 (CW5) that were not included in OFDM symbol 0 at line number 0. If the data symbol group of CW5 placed at row number 0 is smaller than the size of row number 0 (number of columns N _y ), the interleaver 104 will use the remaining elements of row number 0 (d (14) to d (14) in FIG. 7A). In (20)), the data symbol group of CW6 is arranged in order from the beginning of CW. The interleaver 104 writes the remaining data symbol groups of CW6 that were not written in line number 0 from the beginning of line number 1.

Similarly, the interleaver 104 started writing the data symbol group in the middle of a row (for example, the column with column number 14, that is, the column with d (14)) for each codeword, moved to the next row, and started writing. Write to the column immediately before the column (for example, column number 13). In FIG. 7A, the interleaver 104 writes the 14 data symbol groups in the first half of the codeword (eg CW9) in the line immediately before and in the last line of the last line, and the remaining 7 data symbol groups in the second half to the next OFDM symbol (eg, CW9). Write to OFDM symbol 2).

FIG. 7B is a diagram showing the distribution of the data symbol of each codeword in OFDM symbol 1 in the frequency domain. Since the interleaver 104 starts reading from d (0) in FIG. 7A, the data symbols of codeword 6, codeword 7, and codeword 8 are transferred from the low frequency data subcarrier to the high frequency data subcarrier. Can be widely distributed and arranged.

As described above, the interleaver 104 can disperse and arrange the data symbol group included in each codeword widely from the low frequency data subcarrier to the high frequency data subcarrier. As a result, for example, when the reception quality varies from frequency to frequency due to the multipath of the communication path, it is possible to prevent the quality deterioration from concentrating on the data symbol group included in a specific code word. The error rate can be improved.

Next, FIG. 8A shows the two-dimensional array (write and read) of FIGS. 5A and 5B and the code word (in the case of interleaving the data symbol group corresponding to the OFDM symbol number 2 (OFDM symbol 2) of FIG. 3). It is a figure which shows the relationship with CW).

In FIG. 8A, as in FIG. 7A, the interleaver 104 starts writing from the remaining latter 7 data symbol groups of the final codeword (CW9) contained in the previous OFDM symbol (OFDM symbol 1), and sequentially writes the codewords. Write. Therefore, the interleaver 104 can disperse and arrange the data symbol group included in each codeword widely from the low frequency data subcarrier to the high frequency data subcarrier.

In FIG. 7A (OFDM symbol 1), the data symbol group at the beginning of each code word is arranged in column number 14. This is because the number of remaining data symbol groups in the final codeword (CW5) in the previous OFDM symbol (OFDM symbol 0) is 14. Further, in FIG. 8A (OFDM symbol 2), the data symbol group at the head of each code word is arranged in column number 7. This is because the number of remaining data symbol groups in the final codeword (CW9) in the previous OFDM symbol (OFDM symbol 1) is 7. Further, in FIG. 6A (OFDM symbol 0), the data symbol group at the head of each code word is arranged in column number 0. This is because the number of remaining data symbol groups in the last codeword in the previous OFDM symbol (not shown) is zero.

FIG. 8B is a diagram showing the distribution of the data symbol of each codeword in OFDM symbol 2 in the frequency domain. Since the interleaver 104 starts reading from d (0) in FIG. 8A, the data symbols of the codeword 10, the codeword 11, the codeword 12, and the codeword 13 are read from the low frequency data subcarrier to the high frequency data. It can be widely distributed and placed across subcarriers.

As described above, the column number in which the data symbol group at the beginning of each codeword is arranged is different for each OFDM symbol, but the interleaver 104 circulates and writes the data symbol group of each codeword with respect to the column number ( That is, when the write position reaches the final position, it returns to the first column and continues writing), and the data symbol group contained in each codeword is widely distributed from the low frequency data subcarrier to the high frequency data subcarrier. Can be placed. As a result, for example, when the reception quality varies from frequency to frequency due to the multipath of the communication path, it is possible to prevent the quality deterioration from concentrating on the data symbol group included in a specific code word. The error rate can be improved.

<Operation example 3>
9A, 9B, and 9C are flowcharts showing another procedure in which the interleaver 104 performs interleaving. In FIGS. 9A, 9B, and 9C, the same processing steps as those in FIGS. 4A, 4B, and 4C are designated by the same reference numerals, and the description thereof will be omitted. The difference between FIGS. 9A, 9B and 9C and FIGS. 4A, 4B and 4C is that the read start position is changed for each OFDM symbol.

In step S2003 of FIG. 9A, the interleaver 104 calculates the position of the first symbol of the code word and sets it as the read start position.

For example, when interleaving the OFDM symbol 0, the interleaver 104 has a row number 0 and a column number 0 (the position of d (0) in FIG. 6A) because the position of the first symbol of the code word 1 is the row number 0. , Column number 0 is set as the read start position. That is, the interleaver 104 sets the same read start position as in FIG. 5B for OFDM symbol 0.

Further, for example, in the interleaver 104, when interleaving the OFDM symbol 1, the position of the first symbol of the code word 6 is the row number 0 and the column number 14 (the position of d (14) in FIG. 7A). Set number 0 and column number 14 as the read start position. That is, the interleaver 104 sets a read start position different from that in FIG. 5B in OFDM symbol 1.

Here, the first symbol of the code word 5 is included in OFDM symbol 0 (FIG. 6A) and is not included in OFDM symbol 1 (FIG. 7A). Therefore, when interleaving the OFDM symbol 1, the interleaver 104 does not use the code word 5 (for example, the position of d (0) in FIG. 7A) but the first symbol position of the code word 6 (d (14) in FIG. 7A). Position) is calculated and set to the read start position.

That is, as shown in FIG. 10A, in the first to Nth codewords (codewords 5 to 9 in FIG. 10A) included in the OFDM symbol 1, the number of data symbols included in the codeword 5 is the codeword. If it is less than the number of data symbols contained in 6, interleaver 104 starts writing in ascending order from codeword 5 and reading from codeword 6. As shown in FIG. 10A, in the OFDM symbol 1, at least the number of data symbols (21 symbols) included in the code word 6 including the read start position is N of the memory size of N _x × N _y of the interleaver 104. Equal to _y (that is, the number of columns).

Further, when interleaving the OFDM symbol 1, the interleaver 104 calculates the position of the first symbol of the code word 6 and sets it at the read start position, and the data at the beginning of each code word (for example, d (14), d). (35), d (56), d (77)) may be read first.

In other words, the interleaver 104 may set the read start position by selecting the code word to be input first, including the first data symbol in each OFDM symbol.

As a result, the data symbols in each codeword contained in the OFDM symbols are read out in the same order as they were written. That is, the order of the data symbols in each codeword is maintained before and after interleaving. Therefore, the processing of the front stage and the rear stage of the interleaver 104 and the deinterleaver 116 becomes easy, and the circuit scale can be reduced.

For example, the equalization circuit 115 in the previous stage of the deinterleaver 116 may perform the equalization processing according to the order of the subcarriers. In this case, each codeword included in the output of the deinterleaver 116 is output with the data symbol at the beginning of the codeword first, and is output in the order of the data symbols in the codeword. As a result, the demodulation circuit 117 and the FEC decoding circuit 118 in the subsequent stage of the deinterleaver 116 can easily divide the code word. For example, the data symbol and the demodulated data are stored in another memory by dividing each codeword number, and it becomes easy to perform LDPC decoding for each codeword, and the circuit scale and processing delay can be reduced.

Further, for example, in the interleaver 104, when interleaving the OFDM symbol 2, the position of the first symbol of the code word 10 is the row number 0 and the column number 7 (the position of d (7) in FIG. 8A). Set number 0 and column number 7 as the read start position. That is, the interleaver 104 sets a read start position different from that in FIG. 5B in OFDM symbol 2.

In step S2004 of FIG. 9A, the interleaver 104 starts from the read start position set in step S2003, discards dummy data, and reads data in the column direction.

FIG. 10A is a diagram schematically showing a read-out process when the interleaver 104 performs interleaving of the OFDM symbol 1 as an example of the process of S2004.

In FIG. 10A, the interleaver 104 starts reading from the read start position (position of d (14)) set in step S2003 and reads in the column direction. When the read position reaches the last row of the last column (position of d (83), excluding dummy data), the interleaver 104 moves the read position to row number 0 and column number 0, and reads in the column direction. continue.

The interleaver 104 determines the position immediately before returning to the read start position (the position of d (76)) as the read final position, and when the read position reaches the read final position, completes the read process in step S2004.

FIG. 10B is a diagram showing the distribution of the data symbols of each codeword included in OFDM symbol 1 in the frequency domain when the interleaver 104 interleaves using the procedure of FIG. 9A.

In FIG. 10B, as in FIG. 7B, the interleaver 104 widely distributes the data symbols of codeword 6, codeword 7, and codeword 8 from the low frequency data subcarriers to the high frequency data subcarriers. Can be placed.

Further, in FIG. 10B, unlike FIG. 7B, the data symbol of codeword 5 (second half 14 data symbol group) is distributed in high frequency subcarriers, and the data symbol of codeword 9 (first half 14 data symbol group) is distributed. It is distributed in low frequency subcarriers.

That is, the interleaver 104 includes the first half 7 data symbol group of codeword 5 in OFDM symbol 0 and is placed in a low frequency subcarrier as shown in FIG. 6B when using the procedures of FIGS. 9A, 9B and 9C. Then, the latter 14 data symbol groups of codeword 5 are included in OFDM symbol 1 and placed in high frequency subcarriers as shown in FIG. 10B.

Therefore, the data symbol group of codeword 5 is placed in the low frequency subcarriers in OFDM symbol 0 and in the high frequency subcarriers in OFDM symbol 1. That is, unlike other codewords, the data symbol group for codeword 5 is spread across multiple OFDM symbols, but like other codewords, it has low frequency data subcarriers to high frequency in the frequency range. Widely distributed across data subcarriers.

Note that the interleaver 104 may change the data write start position according to the OFDM symbol number in step S1002 instead of changing the read start position according to the OFDM symbol number in step S2003 as shown in FIG. 10A. good.

FIG. 11A is a diagram illustrating a procedure in which the interleaver 104 changes the data writing start position according to the OFDM symbol number to perform writing.

In FIG. 11A, the interleaver 104 writes the data symbol group in the row direction in the same manner as in FIG. 5A, but the column number at which the writing is started is set to 7. As a result, in FIG. 11A, the head data symbol groups of CW6, CW7, CW8, and CW9 are arranged in column number 0.

In FIG. 11A, the interleaver 104 determines the write start column number so that the first symbol of CW6 is arranged in the column number 0. However, the interleaver 104 instead writes dummy data before CW5 in row number 0 (from column number 0 to column number 6) so that the first symbol of CW6 is placed in column number 0. You can do it.

FIG. 11B is a diagram showing a method of reading out a data symbol group after the interleaver 104 writes by the method shown in FIG. 11A. The interleaver 104 skips the element in which the data was not written (or the element in which the dummy data was written) in FIG. 11A, and reads the data symbol group in the column direction. That is, in FIG. 11B, the interleaver 104 reads out the data symbol group in the column direction with the row number 1 and the column number 0 (the position of d (14)) as the read start position.

The sequence of data symbol groups output by the interleaver 104 by the method of FIGS. 11A and 11B is the same as the sequence output by the method of FIG. 10A. Therefore, the effects obtained by the methods of FIGS. 11A and 11B are the same as those of the method of FIG. 10A. In the present embodiment, the method described below may be similarly modified as shown in FIGS. 11A and 11B, but since the effects are the same, the description thereof will be omitted.

FIG. 12 is a diagram showing a read-out process when the interleaver 104 interleaves the OFDM symbol 2 as an example of the process of S2004.

In FIG. 12, the interleaver 104 starts from the read start position (position of d (7)) set in step S2003, and reads in the column direction as in FIG. 10A.

As shown in FIG. 12, in the first to Nth codewords (codewords 9 to 13 in FIG. 12) included in the OFDM symbol 2, the number of data symbols included in the codeword 9 is the codeword 10. Less than the number of data symbols included. In this case, the interleaver 104 starts writing from codeword 9 in ascending order and starts reading from codeword 10.

FIG. 13 is a diagram showing the distribution of the data symbols of each codeword included in OFDM symbol 2 in the frequency domain when the interleaver 104 interleaves using the procedure of FIG. 9A.

In FIG. 13, similar to FIG. 8B, the interleaver 104 transfers the data symbols of codeword 10, codeword 11, codeword 12, and codeword 13 from low frequency data subcarriers to high frequency data subcarriers. Can be widely distributed and arranged.

Further, in FIG. 13, unlike FIG. 7B, the data symbols of the codeword 9 are distributed in the high frequency subcarriers.

When using the procedure of FIGS. 9A, 9B, 9C, the interleaver 104 includes the first 14 data symbol groups of codeword 9 in OFDM symbol 2 and places them in a low frequency subcarrier as shown in FIG. 10B. The latter 7 data symbol groups of codeword 9 are included in OFDM symbol 3 and placed in high frequency subcarriers as shown in FIG.

Therefore, the data symbol group of codeword 9 is placed in the low frequency subcarriers in OFDM symbol 0 and in the high frequency subcarriers in OFDM symbol 1. That is, unlike other codewords, the data symbol group for codeword 9 is spread across multiple OFDM symbols, but like other codewords, low frequency data subcarriers to high frequency data in the frequency region. Widely distributed across subcarriers.

The reading process when the interleaver 104 interleaves the OFDM symbol 0 using the process of step S2004 is the same as the process of step S1004 of FIG. 4A (see FIG. 5B).

FIG. 9B is a flowchart showing another procedure in which the interleaver 104 performs interleaving in FIG. FIG. 9B uses a procedure different from that of FIG. 9A, but a similar data symbol sequence is output. In FIG. 9B, the same processing as in FIG. 4B is assigned the same number, and the description thereof will be omitted.

In step S1001, the interleaver 104 may calculate N _x and N _y using equations 13B and 13C instead of equations 12 and 9.

The interleaver 104 may calculate N _x , N _y using the formulas 13B and 13C when N _x , N _y calculated by the formulas 12 and 9 are not integers (described later).

In step S2103 of FIG. 9B, the interleaver 104 calculates the position of the first symbol in the OFDM symbol and sets it as the read start position (n_offset) in the same manner as in step S2003 (FIG. 9A).

The method of calculating the value of n_offset will be described in detail. The interleaver 104 uses Equation 14 to calculate the value of k ^(q) _offset .

k ^(q) _offset is the final code contained in the previous OFDM symbol (OFDM symbol q-1) in the OFDM symbol number (q) (q is an integer greater than or equal to 0, for example, OFDM symbol 0 corresponds to q = 0). Represents the number of words in the current OFDM symbol (OFDM symbol q) that are not included in the previous OFDM symbol.

For example, in OFDM symbol 0 (q = 0) of FIG. 6A, k ⁽⁰⁾ _offset can be expressed as Equation 15.

Further, in the OFDM symbol 1 (q = 1) of FIG. 7A, the k ⁽¹⁾ _offset can be expressed as Equation 16.

Further, in the OFDM symbol 2 (q = 2) of FIG. 8A, the k ⁽²⁾ _offset can be expressed as Eq. 17.

The interleaver 104 may calculate the value of k ^(q) _offset by using the equation 18 instead of the equation 14.

Since the equation 18 is a recurrence equation and the number of multiplications and divisions is smaller than that of the equation 14, the interleaver 104 can reduce the amount of calculation, the circuit scale, and the power consumption.

Next, the interleaver 104 calculates the value of N _L using Equation 19.

N _L in Equation 19 represents the number of data symbol groups contained in the last row of the two-dimensional array. For example, in FIG. 6A, the value of N _L is 7 because the last row contains 7 data symbol groups from d (84) to d (90). In Equation 19, the length of the last row (corresponding to N _L ) of OFDM symbol 0 in FIG. 6A is changed from the row length ( _Ny ) to row number 0 of OFDM symbol 1 (q = 1) in FIG. 7A. The value of _NL is calculated by using the value obtained by subtracting the number of symbol groups (corresponding to floor (k ⁽¹⁾ _offset / N _S )) of the codeword 5 included.

The interleaver 104 calculates the value of the read start position (n_offset) using the formula 20A. Since the value of n_offset depends on the OFDM symbol number (q), it may be expressed as n ^(q) _offset or n_offset (q).

The value of n_offset (q) represents the number of data symbol groups contained in the column before the column containing the read start position in the two-dimensional array. For example, in FIG. 10A, the number of data symbol groups included in the column (column containing d (0) to d (13)) before the column including the read start position ( column containing d (14)) is 63. Therefore, the value of n_offset (1) is 63.

Further, in the equation 20A, the first equation and the second equation are selected depending on whether the value of floor (k ^(q) _offset / _NS ) is _NL or less or exceeds _NL . In the first equation (when the value of floor (k ^(q) _offset / N _S ) is N _L or less), as shown in FIGS. 10B and 12, the column including the read start position has the data symbol group in the last row. It is used when the column is not included (in FIGS. 10B and 12, the column does not include any of d (84) to d (90)).

In the second equation (when the value of floor (k ^(q) _offset / N _S ) exceeds _NL ), the column containing the read start position contains the data symbol group in the last row (Fig. 10B and Fig. 10B). In 12, it is used in the case of (a column containing any one of d (84) to d (90)) (not shown).

As described above, in step S2103, the interleaver 104 has shown a method of calculating the read start position from the formula 14 using the formula 20A.

Although the method of calculating the read start position by the interleaver 104 has been described in FIG. 9A, the row number 0, which is the read start position calculated in step S2003, is defined as the j ^(q) _offset column, and j ⁽ q). ⁾ The value of _offset may be calculated using Equation 20B.

Using the values of k ⁽⁰⁾ _offset, k ⁽¹⁾ _{offset, and} k ⁽²⁾ _offset calculated using Equation 15, Equation 16, and Equation 17, j ⁽⁰⁾ _offset, j ⁽¹⁾ _offset, j ^{( 2)} The _offset values are calculated as 0, 14, and 7, respectively. This value means that the read start position in FIG. 6A (OFDM symbol 0), FIG. 10A (OFDM symbol 1), and FIG. 12 (OFDM symbol 2) is column number 0,14,7.

In step S2104 of FIG. 9B, the interleaver 104 reads from the memory using the address idx2 that is cyclically shifted from the interleaved address idx1 using n_offset (q). idx2 is calculated by Equation 21.

That is, the interleaver 104 shifts the interleaved address generated according to the interleave size according to the number of data symbols included in the code word included in the previous OFDM symbol (for example, the code word 5 in FIG. 10A). Is used to read the code word 6 including the read start position.

FIG. 9C is a flowchart showing another procedure in which the interleaver 104 performs interleaving in FIG. FIG. 9C uses a procedure different from that of FIGS. 9A and 9B, but outputs a similar data symbol sequence. In FIG. 9C, the same processing as in FIGS. 9B and 4C is assigned the same number, and the description thereof will be omitted.

Similar to the case where the address calculation of FIG. 4B is replaced with the address table lookup in FIG. 4C, the address calculation of FIG. 4B (steps S1001, S1101, S1102) may be replaced with the address table lookup in FIG. 9C (FIG. 4C). See the description in step S1202).

In FIG. 9C, the procedure for reading the data symbol group is the same as in FIG. 9B (steps S2103 and S2104).

The interleaver 104 may calculate the value of idx2 using the address table of idx1 (as an example, FIG. 5C) instead of calculating using the equation 21 in step S2104 of FIG. 9C. For example, in FIG. 10A, when n is 87 and n_offset (1) is 63, the value of idx2 (87,1) is calculated as 13 by Equation 22.

This means that the symbol block group d (13) is read out at the 87th position in FIG. 10A. In this way, the interleaver 104 defines d (idx2 (n, q)) as the nth data to be read in the OFDM symbol number q.

FIG. 14 is a table showing an example of the value of idx2 (n, 1) in OFDM symbol 1 (q = 1).

As described above, the interleaver 104 includes the data symbol group of the first half of the codeword 5 in OFDM symbol 0 when the procedure of FIGS. 4A, 4B and 4C is used, and as shown in FIG. 6B, the interleaver 104 is a low frequency sub. It is placed on a carrier, the data symbol group in the latter half of the codeword 5 is included in OFDM symbol 1, and it is placed on a low frequency subcarrier as shown in FIG. 6B.

Therefore, since the data symbol group of the code word 5 is arranged in the low frequency subcarrier in both OFDM symbol 0 and OFDM symbol 1, the distribution is biased. Thereby, for example, when the deterioration of the signal quality of the low frequency subcarrier is large as compared with the high frequency subcarrier, the error rate of the codeword 5 is increased as compared with other codewords.

On the other hand, when using the procedure of FIG. 9A, FIG. 9B, and FIG. 9C, the interleaver 104 includes the data symbol group of the first half of the code word 5 in OFDM symbol 0 and arranges it in a low frequency subcarrier as shown in FIG. 6B. The data symbol group in the latter half of the code word 5 can be included in the OFDM symbol 1 and placed in a high frequency subcarrier as shown in FIG. 10B.

Therefore, the data symbol group of the codeword 5 is arranged in the low frequency subcarrier in OFDM symbol 0 and in the high frequency subcarrier in OFDM symbol 1. Unlike other codewords, it is placed across multiple OFDM symbols, but like other codewords, it is widely distributed in the frequency domain.

As a result, the communication device 100 equalizes the error rate for each codeword, reduces the packet error rate, and increases the data throughput even when the number of data subcarriers is not a multiple of the number of symbols per codeword. be able to.

This is effective, for example, in millimeter-wave high-speed communication (including 11ad standard and 11ay standard) in which channel variation between OFDM symbols is small due to a short OFDM symbol length (for example, 291 nanoseconds).

For example, if the signal quality degradation of the low frequency subcarriers is greater than that of the high frequency subcarriers, the data symbol group of codeword 5 distributed on the low frequency side of OFDM symbol 0 will be significantly affected by the quality degradation, but OFDM. In the data symbol group of code word 5 distributed in the high frequency subcarrier of symbol 1, the influence of quality deterioration is small. In the FEC decoding circuit 118 of the receiving device, the data symbol group of the code word 5 of the OFDM symbol 0 and the data symbol group of the code word 5 of the OFDM symbol 1 are combined to perform error correction decoding to perform error correction decoding of the low frequency subcarrier. The effect of signal quality deterioration can be reduced and the error rate can be reduced.

FIG. 15 is a diagram showing an example of the configuration of the interleaver 104 (interleaver 104a). Interleaver 104a performs interleaving according to the procedure shown in FIG. 9B.

The interleaver 104a has a memory 1040, an address counter 1041, an N _x , N _y calculation circuit 1042, an OFDM symbol number counter 1043, a shift amount calculation circuit 1044, a block interleaved address idx0 generation circuit 1045, an interleaved address idx1 generation circuit 1046, and an address shift. Equipped with circuit 1047.

The MAC control circuit 101 inputs parameters such as the number of channel bonding (N _CB ), the number of data subcarriers (N _SD ), the LDPC codeword size (L _CW ), and the number of bits per symbol (N _CBPS ) to the interleaver 104a. do.

The modulation circuit 103 inputs data symbols subjected to data modulation (for example, 16QAM) to the interleaver 104a for each data symbol group (each _NS symbol).

The memory 1040 of the interleaver 104a is composed of, for example, RAM or a register array.

The address counter 1041 of the interleaver 104a generates an address for writing the data of the data symbol group to the memory 1040 by using, for example, an ascending order address. For example, the address counter 1041 generates an address so as to write the data symbol group d (n, q) to the address n (corresponding to step S1103 in FIG. 9B).

The N _x , N _y calculation circuit 1042 of the interleaver 104a calculates the number of rows N _x and the number of columns N _y of the two-dimensional array using the equations 13B and 13C, and the shift amount calculation circuit 1044 and the block interleave address id x0. Input to the generation circuit 1045 (corresponding to step S1001 in FIG. 9B).

The OFDM symbol number counter 1043 of the interleaver 104a determines the value of the OFDM symbol number (q) according to the number of symbols (not shown) input from the modulation circuit 103, and inputs the value to the shift amount calculation circuit 1044.

The shift amount calculation circuit 1044 of the interleaver 104a calculates the value of n_offset (q) using the equations 14, 19, and 20A (corresponding to step S2103 in FIG. 9B).

The block interleaved address idx0 generation circuit 1045 of the interleaver 104a calculates idx0 (i) using the equation 13A (corresponding to step S1101 in FIG. 9B).

The interleaved address idx1 generation circuit 1046 of the interleaver 104a calculates idx1 (n) using the procedure of step 1102 of FIG. 9B.

The address shift circuit 1047 of the interleaver 104a calculates idx2 (n, q) using the equation 21 (corresponding to step S2104 in FIG. 9B). The interleaver 104a reads a data symbol group from the memory 1040 using idx2 (n, q) generated by the address shift circuit 1047 as a read address, and outputs the data symbol group to the OFDM modulation circuit 105.

The deinterleaver 116 may be configured by using the output (idx2 (n, q)) of the address shift circuit 1047 as the write address and the output of the address counter 1041 as the read address in the interleaver 104a.

FIG. 16 is a diagram showing another example of the configuration of the interleaver 104 (interleaver 104b). In FIG. 16, the same components as those in FIG. 15 are given the same reference numerals, and the description thereof will be omitted. The interleaver 104a of FIG. 15 performs interleaving processing by using the data symbol group number (n) as the write address and using the address corresponding to the interleave method as the read address. On the other hand, the interleaver 104b in FIG. 16 performs interleaving processing by using an address corresponding to the interleaving method as the write address and using the data symbol group number (n) as the read address.

The interleaver 104b of FIG. 16 has a different configuration from the interleaver 104a of FIG. 15, but the same interleaving result can be obtained. As will be described later, the deinterleaved address table memory 1048 may sequentially generate corresponding interleaved addresses in response to the input of the data symbol group from the modulation circuit 103, and the address shift circuit 1047a can be performed by addition and modulo processing. Therefore, the circuit configuration is simple and the power consumption can be reduced.

The address counter 1041a generates a data symbol group number (n) according to the output of the modulation circuit 103.

The deinterleaved address memory 1048 calculates the deinterleaved address idx3 (n) so that idx3 (n) satisfies Equation 23.

The idx3 (n) satisfying the equation 23 satisfies the equation 24.

From Equations 23 and 24, idx3 (n, q) is a reverse lookup address for idx1 (n, q).

The deinterleaved address memory 1048 may store the address table for calculating idx3 (n) in, for example, ROM or RAM, and calculate idx3 (n).

The address shift circuit 1047a calculates the interleaved address idx4 (n, q) whose read initial value has been adjusted by using the equation 25.

The interleaver 104 corresponds to advancing the read position by n_offset (q) in FIG. 10A, and the equation 25 means that the write position is delayed by n_offset (q), both of which have the same effect.

The idx4 (n, q) generated by the address shift circuit 1047a satisfies equations 26 and 27. idx4 (n, q) is the reverse address of idx2 (n, q).

FIG. 17 shows an example of idx3 (n) and idx4 (n, 1) values corresponding to the example of idx1 (n) values shown in FIG. In FIG. 14, for example, the value of idx1 (4) was 84. Correspondingly, the value of idx3 (84) is 4. Further, in FIG. 14, for example, the value of idx2 (6,1) was 57. Correspondingly, the value of idx4 (57,1) is 6.

The address counter 1041a generates a data symbol group number (n). The address counter 1041a, for example, generates an ascending order address (n = 0,1, ..., floor (N _SD / N _S ) -1).

The interleaver 104b writes the data symbol group to the memory using the address (idx4 (n, q)) generated by the address shift circuit 1047a, and reads the data symbol group from the memory using the address generated by the address counter 1041a. To perform interleaving.

The correspondence between the interleaver 104b of FIG. 16 and FIG. 10A will be described. The interleaver 104b considers the reading order, such that the data to be read first is address 0 and the data to be read next is address 1, and the data symbol group is set according to the interleaving procedure (FIGS. 9A, 9B, 9C). Interleaving is realized by controlling the writing position.

For example, in FIG. 10A, d (14) is written to address 0 in order to read the data symbol group d (14) first. That is, the interleaver 104b calculates the write address so that idx4 (14,1) = 0.

FIG. 18 is a diagram showing another example of the configuration of the interleaver 104 (interleaver 104c). FIG. 18 includes an example of the configuration of the OFDM modulation circuit 105 (OFDM modulation circuit 105a). In FIG. 18, the same components as those in FIGS. 15 and 16 are designated by the same reference numerals, and the description thereof will be omitted.

Unlike the interleaver 104b, the interleaver 104c inputs the address idx4 (n, q) calculated by the address shift circuit 1047a to the OFDM modulation circuit 105a. Further, the interleaver 104c does not have to have the memory 1040 and the address counter 1041a.

Further, the modulation circuit 103 may input the data symbol group to the OFDM modulation circuit 105a instead of the interleaver 104c. The communication device 100 uses the write address calculated by the interleaver 104c, so that the OFDM modulation circuit 105a substantially performs the interleave processing.

The OFDM modulation circuit 105a includes a data subcarrier address calculation circuit 1051, a memory 1052, a pilot and guard subcarrier insertion circuit 1053, an address generation circuit 1054, an IDFT circuit 1055, a CP addition and a window function circuit 1056.

The data subcarrier address calculation circuit 1051 of the OFDM modulation circuit 105a calculates the subcarrier number (k) according to the data subcarrier rank (r) after interleaving. The data subcarrier order (r) after interleaving means, for example, the order of reading data in FIGS. 5B, 10A, and 12.

For example, in FIG. 10A, the data subcarrier ranks of the data symbols included in the data symbol group d (14) range from 0 to _NS -1, and the data subcarrier ranks of the data symbols included in the data symbol group d (35). Is from N _S to 2 N _S -1. The interleaver 104c defines the data subcarrier rank of the data symbol group d (n) as idx4 (n, q) × N _S to idx4 (n, q) × N _S + N _S -1.

FIG. 19 shows an example of the correspondence (referred to as subcarrier mapping) between the data subcarrier rank (r) and the subcarrier number (k). The subcarrier mapping may take different values depending on the number of channel bonding (N _CB ), the number of DFT points (N _DFT ), the number of data subcarriers (N _SD ), and the channel number (ch). FIG. 19 is an example when N _CB = 2, N _DFT = 1024, N _SD = 728, and the channel number is 9.

The range of the value of the subcarrier number k is -N _DFT / 2 or more and N _DFT / 2-1 or less (in the example of FIG. 19, -512 or more and 511 or less). In FIG. 19, subcarriers in which k is less than -383 and more than 383 are referred to as guard bands or guard subcarriers. The value of the guard subcarrier symbol is set to 0. In FIG. 19, a subcarrier having a value of k of -1,0,1 is referred to as a DC subcarrier. The value of the symbol of the DC subcarrier is set to 0.

Further, a value of k other than the guard subcarrier and the DC subcarrier and not shown in FIG. 19 is referred to as a pilot subcarrier. The subcarrier number k of the pilot subcarrier is, for example, {-372, -350, -328, -306, -284, -262, -240, -218, -196, -174, -152, -130, -108, -86, -64, -42, -20, -3, 7, 24, 46, 68, 90, 112, 134, 156, 178, 200, 222, 244, 266, 288, 310, 332, 354, 376}.

The data subcarrier address calculation circuit 1051 writes the data symbol c (h, q) to the memory 1052 according to the subcarrier number (k) calculated from the data subcarrier rank (r). Here, c (h, q) represents the hth (h is an integer of 0 or more and less than NSD) data symbol in the OFDM symbol number q. The number n of the data symbol group d (n, q) including the data symbol c (h, q) is calculated by Equation 28.

The data subcarrier address calculation circuit 1051 writes, for example, the data of the subcarrier k to the address k + N _DFT / 2 of the memory 1052.

In the communication device 100, the interleaver 104c calculates the interleaved address idx4 (n, q) for the data symbol group d (k, q) including the data symbol c (h, q). The OFDM modulation circuit 105a changes the data rank of the data symbols included in the data symbol group d (k, q) from idx4 (n, q) × N _S to idx4 (n, q) × N _S + N _S -1. Based on this, the subcarrier number k is calculated, and the data symbol is written to the address corresponding to the subcarrier number in the memory 1052.

The pilot and guard subcarrier insertion circuit 1053 calculates the positions of the guard subcarrier and the DC subcarrier, and writes them to the memory 1052 with the symbol value set to 0. Further, the pilot and guard subcarrier insertion circuit 1053 calculates the subcarrier number of the pilot subcarrier and writes the value of the predetermined pilot symbol to the memory 1052.

The address generation circuit 1054 generates an address for reading subcarrier data (which may include a data subcarrier, a DC subcarrier, a pilot subcarrier, and a guard subcarrier) from the memory 1052 for the IDFT circuit 1055 to perform IDFT. The address generation circuit 1054 may generate an ascending order address or a bit reverse order address according to the circuit configuration of the IDFT circuit 1055.

The IDFT circuit 1055 performs an inverse discrete Fourier transform on the subcarrier data read from the address generated by the address generation circuit 1054, and converts the subcarrier data into a time domain signal. CP addition and window function circuit 1056 adds CP to the time domain signal and applies the window function.

As described above, since the interleaver 104c of FIG. 18 does not require a memory 1040 as compared with the interleaver 104b of FIG. 16, the circuit scale and power consumption can be reduced, and the processing delay can be reduced.

<Operation example 4>
20 and 21 are diagrams showing another example in which the interleaver 104 performs interleaving. In FIGS. 20 and 21, since the number of symbols per codeword ( _{L CW} / N _CBPS ) is not a multiple of the number of symbols per data symbol group (NS), the data symbol group contains data symbols of a plurality of codewords. A case where they are mixed will be described. Here, the case where the interleaver 104 uses the procedure of FIG. 9A will be described, but the same effect can be obtained when the interleaver 104 uses FIGS. 9B and 9C.

FIG. 20 shows an example in which the interleaver 104 interleaves the OFDM symbol 0 (q = 0) when the N _SD is 728, the L _CW is 624, and the _{NC BPS} is 4. The interleaver 104 writes line by line in the same manner as in FIG. 5A, but in FIG. 20, the arrow indicating the writing order is omitted. Further, the interleaver 104 writes in each column in the same manner as in FIGS. 5B, 10A, and 12. In FIG. 20, the arrow indicating the reading order describes the first two columns in order to specify the reading position, but omits the remaining column numbers.

In step S1001, the interleaver 104 calculates the values of N _x and N _y using equations 13B and 13C. As an example, N _y is 20 and N _x is 5.

In FIG. 20, the number of data symbol groups per codeword (L _CW / N _CBPS / N _S ) is 19.5, which is different from the value of N _y (= 20) calculated by the interleaver 104. According to Equation 13B, the value of N _y is a value obtained by rounding up (ceiling) the number of data symbol groups (L _CW / N _CBPS / N _S ) per codeword. Therefore, the last four symbols of codeword 1 and the first four symbols of codeword 2 are mixed in the symbol (d (19)) in the last column of row number 0. That is, there is a discrepancy in the correspondence between the rows of the two-dimensional array and the codeword. Line number 0 contains 4 symbols different from codeword 1, so the amount of deviation is 4 symbols.

In addition, the amount of deviation is accumulated for each row, and the amount of deviation of row number 1 corresponds to 8 symbols, that is, 1 data symbol group. Therefore, the columns (d (20) to d (38)) except the last column (d (39)) of row number 1 include the data symbol group of codeword 2, but the last column of row number 1 (d (39)). )) Includes the codeword 3 data symbol group.

The deviation amount of line number 2 corresponds to 12 symbols, that is, 1.5 data symbol groups. Therefore, the columns (d (40) to d (57)) excluding the last two columns of row number 1 (d (58), d (59)) include the data symbol group of codeword 3 and are in d (58). Is a mixture of codeword 3 and codeword 4 data symbols, and the last column (d (59) ) contains the codeword 4 data symbol group.

FIG. 21 shows an example in which the interleaver 104 interleaves OFDM symbol 1 (q = 1) when the same parameters as in FIG. 20 (for example, N _SD = 728, L _CW = 624, N _CBPS = 4) are used. show. In FIG. 21, as in FIG. 20, an arrow indicating the reading order of the two columns including the reading start position is described, and the description of the arrow regarding writing and reading of the remaining columns is omitted.

In each row number of FIG. 21, when the data symbol group of the code word of the column including the read start position (d (7)) is included in the column before the column including the read start position, the number of data symbols is deviated. Consider it as.

For example, in FIG. 21, in line number 0, since the read start position is d (7), the code word 6 is read from the first data symbol group, but the code word 7 is the second data symbol group. Read from a certain d (27).

Therefore, in codeword 6, the column before the read start position (d (7)) (the column including d (6)) contains the four symbols of CW6 (the first four symbols), so the amount of deviation Is 4 symbols. In the code word 7, since the column including the read start position (d (27)) and the column (column including d (26)) include 8 symbols of CW7, the deviation amount is 8 symbols. In codeword 8, the column (d (45), d (46)) before the column containing the read start position (column containing d (47)) contains 4 symbols and 8 symbols of CW8, so that the deviation occurs. The quantity is 12 symbols. In codeword 9, the column (d (65), d (66)) before the column containing the read start position (column containing d (67)) contains 8 symbols of CW9 and 8 symbols, so that the deviation occurs. The quantity is 16 symbols. In codeword 10, the CW10 symbol is 4 symbols, 8 in the column (d (84), d (85), d (86)) before the column containing the read start position (column including d (87)). Since 8 symbols and 8 symbols are included, the deviation amount is 20 symbols.

22 and 23 are diagrams showing the distribution of codeword data symbols in the frequency domain when the interleaver 104 interleaves the OFDM symbols 0 and 1 of FIGS. 20 and 21.

In step S1001 of FIGS. 9A and 9B, the interleaver 104 determines the number of columns N _y based on the number of symbols per codeword. Therefore, the codewords 1,2,3,4,6,7,8,9 are widely distributed from the low frequency subcarriers of the OFDM symbol to the high frequency subcarriers.

Further, in step S2003 of FIG. 9A and step S2103 of FIG. 9B, the interleaver 104 sets the read start position to the number of data subcarriers (N _SD ) of the OFDM symbol and the number of symbols per codeword (L _CW / N _CBPS ). Determined accordingly. Therefore, when the codeword is divided into a plurality of OFDM symbols, the frequency overlap in the codeword should be reduced, and the codeword should be widely distributed from the low frequency subcarriers to the high frequency subcarriers. Can be done.

In addition, in FIGS. 22 and 23, in the code word 5, duplication of the distribution of the data symbols occurs in the subcarriers having a high frequency according to the amount of deviation. However, the interleaver 104 determines the read initial value so that the deviation amount does not accumulate for each OFDM symbol (see, for example, Equation 14, Equation 19, Equation 20A). Therefore, the deviation amount can be set to a smaller value than the number of subcarriers of the OFDM symbol, and the performance deterioration due to the duplication of the distribution of the data symbols can be reduced.

Further, in FIGS. 22 and 23, the interleaver 104 arranges the data symbols of each codeword in the subcarriers of the OFDM symbols in the order of the data symbols in the codeword except for the head portion corresponding to the deviation amount. do.

As a result, when the communication device 100 receives FIGS. 22 and 23, the deinterleaver 116 can easily output data while maintaining the order of the data symbols of each code word. Therefore, the demodulation circuit 117 in the subsequent stage. And the circuit configuration of the FEC decoding circuit 118 can be simplified. Further, since the communication device 100 can easily perform parallel processing for each code word, the data throughput can be increased.

<Operation example 5>
24 and 25 are diagrams showing another example in which the interleaver 104 performs interleaving. In FIGS. 24 and 25, as in FIGS. 20 and 21, the data symbol group because the number of symbols per codeword ( _{L CW} / N _CBPS ) is not a multiple of the number of symbols per data symbol group (NS). A case where data symbols of a plurality of code words are mixed will be described. The case where the interleaver 104 uses the procedure of FIG. 9A will be described, but the same effect can be obtained when the interleaver 104 uses FIGS. 9B and 9C.

FIG. 24 shows, as an example, an example in which the interleaver 104 interleaves OFDM symbol 0 (q = 0) when N _SD = 728, L _CW = 624, and N _CBPS = 4. The interleaver 104 writes line by line in the same manner as in FIG. 5A, but the arrow indicating the writing order is omitted in FIG. 20. Further, the interleaver 104 writes line by line in the same manner as in FIGS. 5B, 10A, and 12. In FIG. 20, the arrow indicating the reading order describes the first two columns in order to specify the reading position, but omits the remaining columns.

In step S1001, the interleaver 104 calculates the values of N _x and N _y according to equations 29 and 30.

Unlike the formula 13B, the formula 29 uses the floor function instead of the ceiling function. Equation 30 is the same as Equation 13C, but the value of N _y calculated by Equation 29 is used. As an example, N _y is 19 and N _x is 5.

In FIG. 24, the number of data symbol groups per codeword (L _CW / N _CBPS / N _S ) is 19.5, which is different from the value of N _y (= 19) calculated by the interleaver 104. According to Equation 29, the value of N _y is the value obtained by rounding down the number of data symbol groups (L _CW / N _CBPS / N _S ) per codeword. Therefore, the last four symbols of the code word 1 and the first four symbols of the code word 2 are mixed in the symbol (d (19)) of the row number 1 and the column number 0. That is, a deviation in the correspondence between the row and the codeword occurs in the column at the read start position.

FIG. 25 shows an example in which the interleaver 104 interleaves OFDM symbol 1 (q = 1) when the same parameters as in FIG. 24 (eg, N _SD = 728, L _CW = 624, N _CBPS = 4) are used. show. Similar to FIG. 24, an arrow indicating the reading order of the two columns including the reading start position is described, and the description of the arrow regarding writing and reading of the remaining columns is omitted.

In FIG. 25, unlike FIG. 21, the interleaver 104 defines the position of the data symbol group including one or more data symbols of CW6 as the read start position (for example, the position of d (10)). That is, the interleaver 104 is not selected as the read start position in FIG. 21 if it contains a data symbol of another CW (eg CW5) (eg d (6) in FIG. 21), but in FIG. 25 it is another CW. Even if the data symbol of (for example, CW5) is included, if the data symbol of CW6 is included, it is selected as the read start position.

When the interleaver 104 performs the reading shown in FIG. 25, the interleaver 104 uses the equation 31 instead of the equation 14 in step S2103 of FIG. 9B.

The interleaver 104 uses the floor function in equation 31 as opposed to using the ceiling function in equation 14.

26 and 27 are diagrams showing the distribution of codeword data symbols in the frequency domain when the interleaver 104 interleaves the OFDM symbols 0 and 1 of FIGS. 24 and 25.

In step S1001 of FIGS. 9A and 9B, the interleaver 104 determines the number of columns N _y based on the number of symbols per codeword. Therefore, the codewords 1,2,3,4,6,7,8 are widely distributed from the low frequency subcarriers of the OFDM symbol to the high frequency subcarriers.

Further, in step S2003 of FIG. 9A and step S2103 of FIG. 9B, the interleaver 104 sets the read start position to the number of data subcarriers (N _SD ) of the OFDM symbol and the number of symbols per codeword (L _CW / N _CBPS ). Determined accordingly. Therefore, when the codeword is divided into a plurality of OFDM symbols, the frequency overlap in the codeword should be reduced, and the codeword should be widely distributed from the low frequency subcarriers to the high frequency subcarriers. Can be done.

In addition, in FIGS. 26 and 27, in the code word 5, duplication of the distribution of the data symbols occurs in the subcarriers of some frequencies according to the amount of deviation. However, the interleaver 104 determines the read initial value so that the deviation amount does not accumulate for each OFDM symbol (see, for example, Equation 31, Equation 19, Equation 20A). Therefore, the deviation amount can be set to a smaller value than the number of subcarriers of the OFDM symbol, and the performance deterioration due to the duplication of the distribution of the data symbols can be reduced.

Further, in FIGS. 26 and 27, the interleaver 104 arranges the data symbol group of each codeword in the subcarrier of the OFDM symbol in the order of the data symbol group in the codeword except for the final part of the codeword. do.

For example, in FIG. 25, in codeword 6, the last part (d (29)) of codeword 6 is read before d (11) to d (28), and in codeword 7, codeword 7 The last part d (48) of is read out before d (30) to d (47). Therefore, in FIG. 27, the code word 6 keeps the order of the data symbol groups corresponding to d (11) to d (28), and the code word 7 corresponds to d (30) to d (47). The order of the data symbol groups is maintained.

As a result, when the communication device 100 receives FIGS. 26 and 27, the deinterleaver 116 can easily output data while maintaining the order of the data symbols of each code word. Therefore, the demodulation circuit 117 in the subsequent stage. And the circuit configuration of the FEC decoding circuit 118 can be simplified. Further, since the communication device 100 can easily perform parallel processing for each code word, the data throughput can be increased.

<Operation example 6>
28 and 29 are diagrams showing another example in which the interleaver 104 performs interleaving. In FIGS. 28 and 29, similarly to FIGS. 20 and 21, a case where the number of symbols per codeword ( _{L CW} / N _CBPS ) is not a multiple of the number of symbols per data symbol group (NS) will be described. The case where the interleaver 104 uses the procedure of FIG. 9A will be described, but the same effect can be obtained when the interleaver 104 uses FIGS. 9B and 9C.

FIG. 28 shows, as an example, an example in which the interleaver 104 interleaves OFDM symbol 0 (q = 0) when N _SD = 728, L _CW = 624, and N _CBPS = 4. In FIG. 28, as in FIG. 21, the arrow indicating the writing order is omitted, and the arrow indicating the reading order describes the first two columns in order to specify the reading position, but omits the remaining columns.

In step S1001, the interleaver 104 calculates the number of columns N _y using the equation 13B. Further, the number of padding symbols N _yd is calculated using the equation 32.

In step S1002, the interleaver 104 writes the data symbol group in the row direction. The interleaver 104 adds a padding symbol and writes in the row direction in the last column. For example, if N _S is 8 and N _yd is 4, the interleaver 104 will be placed in the last column of data symbol groups (eg d (19), d (39), d (59), d (79)). The remaining 4 symbols may include, for example, empty, dummy symbols, padding symbols, including N _S -N _yd data symbols (eg 4 data symbols).

As a result, the first data symbol group of each codeword is placed in column number 0.

FIG. 29 shows an example in which the interleaver 104 interleaves OFDM symbol 1 (q = 1) when the same parameters as in FIG. 24 (eg, N _SD = 728, L _CW = 624, N _CBPS = 4) are used. show. Similar to FIG. 28, an arrow indicating the read order of the two columns including the read start position is described, and the description of the arrow regarding the write and the read of the remaining columns is omitted.

In step S1002, the interleaver 104 writes the data symbol group in the row direction. The interleaver 104 is a data symbol group (eg, d (6), d (26), d (46) of the column before the column containing the read start position (or the last column if the read start position is the first column). , D (66), d (86)), add a padding symbol and write in the row direction. As a result, the first data symbol group of each codeword is arranged in the column including the read start position.

In FIGS. 28 and 29, the interleaver 104 calculates the read start position using the formula 33 instead of the formula 14.

In addition, in FIGS. 28 and 29, the interleaver 104 may use the formula 34 which is a modification of the formula 18 instead of the formula 33.

Equation 34 is an equation in which L _CW / N _CBPS (corresponding to the number of symbols per codeword) in Equation 18 is replaced with L _CW / N _CBPS + N _yd (corresponding to the number of symbols per codeword including dummy symbols). Is.

Since the total number of dummy symbols included in the OFDM symbol is (N _x -1) × N _yd , Equation 33 is an equation in which N _SD in Equation 14 is replaced with N _SD + (N _x -1) × N _yd . be.

In the method of FIGS. 28 and 29, the interleaver 104 widely distributes the data symbol of each codeword from the low frequency subcarriers of the OFDM symbol to the high frequency subcarriers, similar to the methods of FIGS. 10A and 11A. It can be arranged and the communication quality can be improved.

Further, in the method of FIGS. 28 and 29, the interleaver 104 arranges the data symbols of each codeword in the subcarrier while maintaining the order in the codeword, as in the method of FIGS. 10A and 11A. Therefore, when the communication device 100 receives a packet, the circuit scale is reduced in order to simplify the configuration of the processing after the deinterleaver 116 (for example, the demodulation circuit 117 and the FEC decoding circuit 118) and facilitate the parallel processing. It can be reduced and the data throughput can be improved.

(Modified Example of Embodiment 1)
FIG. 30 is a flowchart showing a method different from FIGS. 9A, 9B, and 9C in which the interleaver 104 of the communication device 100 performs the interleave processing. The interleaver 104 calculated the read address by adding the offset (n _offset ^(q) ) to the interleaved address (idx1 (n)) in the procedure of FIG. 9B, whereas in the procedure of FIG. 30, it is different from that of FIG. 4B. Similarly, interleaving without adding offset is performed, and the data after interleaving is cyclically shifted according to the value of offset (n _offset ^(q) ).

Adding an offset at the time of address calculation as shown in FIG. 9B corresponds to cyclically shifting the data according to the offset value. Therefore, the interleaver 104 of the communication device 100 has the same output data symbol order regardless of which method of FIG. 9A, FIG. 9B, FIG. 9C, and FIG. 30 is used.

In step S1001 of FIG. 30, the interleaver 104 calculates the number of columns (N _y ) and the number of rows (N _x ) of the interleaver using equations 9 and 12 in the same manner as in step S1001 of FIG. 9B. When the size (Ns) of the data symbol group is 1, the interleaver 104 may use the formulas 35 and 36 instead of the formulas 9 and 12.

In step S1101 of FIG. 30, the interleaver 104 calculates the block interleave address idx0 using the formula 13A in the same manner as in step S1101 of FIG. 4B.

The interleaver 104 may use the formula 37 instead of the formula 13A.

In step S1102 of FIG. 30, the interleaver 104 removes a value equal to or larger than the number of input data symbols (N _SD ) from the block interleaved address idx0, as in step S1102 of FIG. 4B, and interleaves the address idx1 (0), idx1. (1), ..., idx1 (N _SD -1) is calculated.

In step S1103 of FIG. 30, the interleaver 104 writes the input data d (k) to the memory using the ascending order address in the same manner as in step S1103 of FIG. 4B.

In step S1104 of FIG. 30, the interleaver 104 reads the input data d (k) from the memory using idx1 (n), similarly to step S1104 of FIG. 4B.

In step S3101 of FIG. 30, the interleaver 104 calculates the value of k _offset ^(q) using equation 14 and the value of N _L using equation 19 in the same manner as in step S2103 of FIG. 9B. The value of n _offset ^(q) is calculated as the shift amount (n_shift) using the equation 20A.

When the size (Ns) of the data symbol group is 1, the interleaver 104 may calculate the value of N _L by using the formula 38 instead of the formula 19.

Further, when the size (Ns) of the data symbol group is 1, the interleaver 104 may calculate the value of n _offset ^(q) by using the formula 39 instead of the formula 20A.

Further, the interleaver 104 may calculate the value of n _offset ^(q) by using the formula 40 instead of the formula 20A.

In equation 40, idx ^-1 (k) represents the inverse function of idx (k) and satisfies equation 41.

Further, when the size (Ns) of the data symbol group is 1, the interleaver 104 may calculate the value of n _offset ^(q) by using the equation 42 instead of the equation 40.

The meanings of the formulas 40 and 42 will be described with reference to FIG. 10A. floor (k _offset ^(q) / N _S ) represents the column number of the read start position (eg 14). The data symbol group with row number 0 and column number (floor (k _offset ^(q) / N _S ) ) is written in the floor (k _offset ^(q) / N _S ) th data symbol group d (floor) in step S1103. (k _offset ^(q) / N _S )). The interleaver 104 reads the data symbol d (k) at the idx ^-1 (k) th, so the data symbol group d (floor (k _offset ^(q) / N _S )) is idx ^-1 (floor (k _offset ⁽ k offset)). ^q) / N _S )) Read th. That is, the formula 40 and the formula 42 are obtained.

In step S3102 of FIG. 30, the interleaver 104 cyclically shifts the array of data symbol groups read in step S1104 to the left (direction in which the index is 0) by n_shift (= n _offset ^(q) ) data symbol groups. ..

FIG. 31 is a diagram showing an example of a cyclic shift in step S3102. In the data symbol sequence before the cyclic shift, d (0) (that is, d (idx (0))) is the first symbol, as in the reading result in FIG. 5B, for example. When the interleaver 104 performs a cyclic shift, the symbol corresponding to the read start position (for example, d (14), that is, d (idx (n _offset ^(q) ))) moves to the beginning of the data symbol series.

The value of n _offset ^(q) corresponds to the read start position in FIGS. 10A and 11A. In steps S1001 to S1104 of FIG. 30, the read start position is not adjusted (corresponding to step 2104 of FIG. 9B) as in the procedure of FIG. 4B. In this case, the data symbol group corresponding to the read start position in FIGS. 10A and 11A is read at the n _offset ^(q) + 1th position in step S1104.

The interleaver 104 can perform a cyclic shift of the n _offset ^(q) symbol in step S3102 so that the data symbol group corresponding to the read start position is located at the beginning of the output of the interleaver, and the procedure of FIG. 9B. You can get the same interleaving result as.

Hereinafter, the procedure of FIG. 30 will be described by a mathematical formula. The input data symbol sequence (d _in ^(q) ) to the interleaver 104 at OFDM symbol number q (q is a non-negative integer) is represented by Equation 43.

The output data symbol sequence (d _interleave ^(q) ) in step S1104 is obtained by Equation 44.

In equation 43, idx (n) is obtained by equation 45.

The output data symbol sequence (d _out ^(q) ) in step S3102 is obtained by the equation 46.

In Equation 46, mod (x) represents x mod N _SD .

In Equation 46, the first line corresponds to the case where the output data symbol sequence (d _interleave ^(q) ) in step S1104 is n _offset ^(q) symbol-shifted, as described in step S3102 of FIG. In the formula 46, the second line is obtained by substituting the formula 42 and the formula 44 in the first line. Further, in the formula 46, the third line corresponds to the case where the procedure of FIG. 9B is used, that is, the case where the offset is added when the address (idx) is calculated.

The interleaver 104 may generate an output data sequence using any of the first line, the second line, and the third line of the formula 46.

Note that the interleaver 104 may reverse the order of the data symbol sequence in step S3102 of FIG. 30 instead of cyclically shifting the data symbol sequence. Equation 47 shows an example of the calculation equation of the output data symbol series (d _out ^(q) ).

FIG. 32 is a diagram showing the distribution of data symbols in the frequency domain for each codeword when the interleaver 104 performs interleaving using the equation 47. By using the formula 47, the distribution of the data symbols is reversed left and right as compared with FIG. 7B, and the distribution of the data symbols of the code word 5 is arranged on the high frequency side. Therefore, the overlap with the distribution of the data symbol of the code word 5 (FIG. 6B) in the previous OFDM symbol (OFDM symbol 0) is reduced, and the communication quality in the multipath environment can be improved.

As described above, in the modification of the first embodiment, the interleaver 104 performs a cyclic shift to the data read from the memory, and arranges the data symbol group at the head of the code word in the head subcarrier. Therefore, the duplication of the frequency distribution of the data symbols of the codewords arranged over the plurality of OFDM symbols is reduced, and the communication quality in the multipath environment can be improved.

(Embodiment 2)
FIG. 33 is a block diagram showing the configuration of the communication device 100a according to the second embodiment. The order of the demodulation circuit 117a and the deinterleaver 116a is different from that of the communication device 100 of the first embodiment. That is, in the communication device 100a, the output of the equalization circuit 115 is connected to the demodulation circuit 117a, the output of the demodulation circuit 117a is connected to the deinterleaver 116a, and the output of the deinterleaver 116a is output to the FEC decoding circuit 118. ..

The deinterleaver 116a of FIG. 33 is a circuit that deinterleaves the data interleaved by the procedures of FIGS. 4A, 4B, 4C, 9A, 9B, 9C, and 30, for example.

The demodulation circuit 117a outputs N _CBPS likelihood information (for example, LLR, Log Likelihood Ratio) for each input data symbol. For example, the demodulation circuit 117a has N _CBPS LLR series e (n × N _CBPS ), e (n × N _CBPS +1), ..., e (n × N _CBPS ) from the data symbol d (n). + N _{Generate CBPS} -1).

The deinterleaver 116a treats N _{CBP S} LLRs as one data symbol and performs deinterleave. For example, the series e (idx (0 + n _offset ^(q) )), e (idx (0 + n _offset ^(q) ) +1), ..., e (idx (idx (idx (0 + n offset (q))) of N _SD × N _{CBP S} LLRs. 0 + n _offset ^(q) ) + N _CBPS -1), e (idx (1 + n _offset ^(q) )), e (idx (1 + n _offset ^(q) ) +1), ..., e (idx (1 + n _offset ^(q) ) + N _CBPS -1), ..., e (idx (N _SD -1 + n _offset ^(q) )), e (idx (N _SD -1 + n _offset ) ^(q) ) +1), ..., e (idx (N _SD -1 + n _offset ^(q) ) + N _CBPS -1) are rearranged, e (0), e (1), ... , e (N _SD × N _CBPS -1) is output. Here, the description of mod is omitted, and idx ((x + k) mod N _SD ) is simply described as "idx (x + k)".

Moreover, when described using the inverse function idx ^-1 (k) of idx (k), the deinterleaver 116a is the series e (0), e (1), ..., e (i × N _CBPS ) of LLR. + j), ..., e (N _SD × N _CBPS -1) is rearranged, and i × N _CBPS + jth LLR (e (i × N _CBPS + j)) is changed to idx ^-1 (mod (mod (mod) i + k _offset ^(q) , N _SD )) × N _CBPS + Move to the jth position and output.

FIG. 34 is a diagram showing an example showing the circuit configuration of the deinterleaver 116a. The deinterleaver 116a includes an N _x , N _y calculation circuit 1161, an OFDM symbol number counter 1162, a shift amount calculation circuit 1163, a row counter 1164, a column counter 1165, and a demultiplexer 1166.

The N _x , N _y calculation circuit 1161 calculates the number of rows N _x and the number of columns N _y of the two-dimensional array using the equations 9 and 12, the equation 13B and the equation 13C, the equation 35 and the equation 36, and the shift amount. Input to the calculation circuit 1163 (corresponding to step S1001 in FIG. 30).

The OFDM symbol number counter 1162 determines the value of the OFDM symbol number (q) according to the number of LLRs input from the demodulation circuit 117a, and inputs the value to the shift amount calculation circuit 1163.

The shift amount calculation circuit 1163 calculates the value of N _L using the formulas 19 and 38, and calculates the value of the shift amount (n_shift = n _offset ^(q) ) using the formulas 20A, 40, and 42. (Corresponding to step S3101 in FIG. 30).

The row counter 1164 and the column counter 1165 calculate the row number and the column number on the interleaver matrix corresponding to the LLR input from the demodulation circuit 117a. For example, FIG. 10A shows the output order of the interleaver and the input order of the deinterleaver. For example, if d (14) is input to the deinterleaver 116a at time 0, the row number at time 0 is 0 and the column number is 14. Further, for example, when d (35) is input to the deinterleaver 116a at time 1, the row number at time 1 is 1 and the column number is 14.

FIG. 35 is a timing chart showing an example of the operation of the row counter 1164 and the column counter 1165. As an example, the case where the value (q) of the OFDM symbol counter is 1 will be described.

When the data symbol groups input from the demodulation circuit 117a are d (14), d (35), d (56), and d (77) at times 0, 1, 2, and 3, see FIG. 10A. , The column number is 14. The line numbers are 0,1,2,3 at time 0,1,2,3, respectively.

The row counter 1164 outputs a codeword number (CW number) corresponding to the data symbol group input from the demodulation circuit 117a. For example, when q is 1, the OFDM symbol contains codewords 5,6,7,8,9, so CW numbers 0,1,2,3,4 may be associated with each. For example, as described with reference to FIG. 7A, since the data symbol group d (14) is the data of the code word 6, at time 0, the row counter 1164 outputs the CW number 1.

If the value of the column counter exceeds floor (k _offset ^(q) / _NS ), the CW number is the value of the row counter plus one. Also, if the value of the column counter is less than or equal to floor (k _offset ^(q) / _NS ), the CW number is equal to the value of the row counter.

In this way, the row counter 1164 of the deinterleaver 116a can easily identify the CW number from the value of the row counter, the value of the column counter, and the value of k _offset ^(q) . This is because the interleaver 104 of the communication device 100 determines the number of columns (N _y ) based on the codeword size (L _CW ) and adds an offset (n _offset ^(q) ) to the interleaved address to perform interleaving. , This is an effect obtained by placing the head data symbol group of the codeword 6 at the head of the subcarrier.

Further, the column counter 1165 calculates the rank in the codeword (rank in CW) corresponding to the data symbol group input from the demodulation circuit 117a. For example, the data symbol group d (14) is the first data in the code word 6, so the rank in CW is 0. Further, for example, since the data symbol group d (15) is the next data group of d (14) in the code word 6, the rank in CW is 1.

The column counter 1165 may calculate the CW internal rank (n _CW ) by the equation 48.

In this way, the column counter 1165 of the deinterleaver 116a can easily identify the rank in CW from the value of the column counter and the value of k _offset ^(q) . This is because the interleaver 104 of the communication device 100 determines the number of columns (N _y ) based on the codeword size (L _CW ) and adds an offset (n _offset ^(q) ) to the interleaved address to perform interleaving. , This is an effect obtained by placing the head data symbol group of the codeword 6 at the head of the subcarrier.

The demultiplexer 1166 selects one of the output ports 0 to 5 based on the CW number calculated by the row counter 1164, and outputs the LLR input from the demodulation circuit 117a to the selected output port. For example, since the CW number of the data symbol group d (14) is 1 (corresponding to codeword 6), it is output to the output port 1.

The FEC decoding circuit 118 outputs the LLR output from the deinterleaver 116a based on which port of the output port 0 to the output port 5 is the data output from, and the order in the CW output by the column counter 1165. Stored in LDPC decoding buffer memory (not shown).

In this way, the deinterleaver 116a can perform deinterleave without providing a deinterleave memory.

The deinterleaver 116a may output the CW number to the FEC decoding circuit 118 instead of including the demultiplexer 1166. The FEC decoding circuit 118 may store the LLR input from the deinterleaver 116a or the demodulation circuit 117a in the LDPC decoding buffer memory (not shown) using the CW number and the CW internal order information.

As described above, the deinterleaver 116a determines the CW number and the CW internal ranking corresponding to the data interleaved by the procedures of FIGS. 4A, 4B, 4C, 9A, 9B, 9C, and 30, for example. Calculate and output to the FEC decoding circuit. Therefore, the communication device 100a can perform deinterleaving with a simple configuration, can reduce the processing delay, and can reduce the circuit scale and the power consumption.

Summary of Embodiments The transmitter according to one aspect of the present disclosure converts an interleaver circuit that interleaves the first to Nth codewords and the interleaved first to Nth codewords into an OFDM signal. The OFDM modulation circuit and the transmission circuit for transmitting the OFDM signal are provided, and the number of data symbols included in the first code word is smaller than the number of data symbols included in the second code word. The interleaver circuit writes from the first codeword to the Nth codeword in ascending order, and starts reading from the second codeword.

In the transmitter according to one aspect of the present disclosure, the interleaver circuit has a memory size of N _x × N _y , where N _y is equal to the number of data symbols contained in the second code word.

In the transmitting device according to one aspect of the present disclosure, the interleaver circuit uses an address obtained by shifting the interleaved address generated according to the interleave size according to the number of data symbols included in the first code word. Read the second codeword.

The receiving device according to one aspect of the present disclosure includes a receiving circuit that receives an OFDM signal including the first to N codewords interleaved in the transmitting device, and the interleaved first to Nth from the OFDM signal. A DFT circuit that extracts the codeword of the above and a deinterleaver circuit that deinterleaves the interleaved first to Nth codewords, and the number of data symbols included in the first codeword is The interleaved first to Nth codewords, which are less than the number of data symbols contained in the second codeword, are the first to Nth codewords in the interleaver circuit of the transmitter. The code words are written in ascending order, and reading is started from the second code word to generate the code word.

In the receiving device according to one aspect of the present disclosure, the deinterleaver has a memory size of N _x × N _y , where N _y is equal to the number of data symbols contained in the second code word.

In the receiving device according to one aspect of the present disclosure, the interleaver circuit uses an address obtained by shifting the interleaved address generated according to the interleave size according to the number of data symbols included in the first code word. Read the second codeword.

In the transmission method according to one aspect of the present disclosure, the first to Nth codewords are interleaved, the interleaved first to Nth codewords are converted into an OFDM signal, and the OFDM signal is transmitted. The number of data symbols included in the first codeword is smaller than the number of data symbols included in the second codeword, and the first codeword is written in ascending order from the first codeword to the Nth codeword, and the second codeword is written. Reading is started from the code word of.

The receiving method according to one aspect of the present disclosure receives an OFDM signal including the first to N codewords interleaved in the transmitting device, and receives the interleaved first to N codewords from the OFDM signal. Is extracted, the interleaved first to Nth codewords are deinterleaved, and the number of data symbols contained in the first codeword is less than the number of data symbols contained in the second codeword. , The interleaved first to Nth codewords are written in ascending order from the first codeword to the Nth codeword in the interleaver circuit of the transmitter, and from the second codeword. Read is started and generated.

It should be noted that this disclosure can be realized by software, hardware, or software linked with hardware. Each functional block used in the description of the above embodiment is partially or wholly realized as an LSI which is an integrated circuit, and each process described in the above embodiment is partially or wholly. It may be controlled by one LSI or a combination of LSIs. The LSI may be composed of individual chips, or may be composed of one chip so as to include a part or all of functional blocks. The LSI may include data input and output. LSIs may be referred to as ICs, system LSIs, super LSIs, and ultra LSIs depending on the degree of integration. The method of making an integrated circuit is not limited to LSI, and may be realized by a dedicated circuit, a general-purpose processor, or a dedicated processor. Further, an FPGA (Field Programmable Gate Array) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure the connection and settings of the circuit cells inside the LSI may be used. The present disclosure may be realized as digital processing or analog processing. Furthermore, if an integrated circuit technology that replaces an LSI appears due to advances in semiconductor technology or another technology derived from it, it is naturally possible to integrate functional blocks using that technology. The application of biotechnology may be possible.

One aspect of the present disclosure is useful for communication systems.

100, 100a Communication device 101 MAC control circuit 102 FEC coding circuit 103 Modulation circuit 104, 104a, 104b, 104c Interleaver 105, 105a OFDM modulation circuit 106 Transmission RF circuit 107 Transmission antenna array 111 Receiving antenna array 112 Receiving RF circuit 113 Synchronization Circuit 114 DFT circuit 115 Equalization circuit 116, 116a Deinterleaver 117, 117a Demodulation circuit 118 FEC Decoding circuit 119 Channel estimation circuit 1040, 1052 Memory 1041, 1041a Address counter 1042, 1161 N _x , N _y Calculation circuit 1043, 1162 OFDM Number of symbols Counter 1044 , 1 163 Shift amount calculation circuit 1045 Block interleaved address idx0 generation circuit 1046 Interleaved address idx1 generation circuit 1047, 1047a Address shift circuit 1048 Demodulated address table Memory 1051 Data subcarrier Address calculation circuit 1053 Pilot and guard subcarrier insertion Circuit 1054 Address generation circuit 1055 IDFT circuit 1056 CP addition and window function circuit
1164 line counter
1165 column counter 1166 demultiplexer

Claims (8)

An interleaver circuit that interleaves the first to Nth codewords,
An OFDM modulation circuit that converts the interleaved first to Nth codewords into an OFDM signal, and
The transmission circuit that transmits the OFDM signal and
Equipped with
The number of data symbols contained in the first code word is less than the number of data symbols contained in the second code word.
The interleaver circuit writes from the first codeword to the Nth codeword in ascending order and starts reading from the second codeword.
Transmitter. The interleaver circuit has a memory size of N _x × N _y and has a memory size of N x × N y.
_Ny is equal to the number of data symbols contained in the second codeword,
The transmitter according to claim 1. The interleaver circuit reads out the second codeword by using an address obtained by shifting the interleaved address generated according to the interleave size according to the number of data symbols included in the first codeword.
The transmitter according to claim 1. A receiver circuit that receives an OFDM signal containing interleaved first to N codewords in the transmitter,
A DFT circuit that extracts the interleaved first to Nth codewords from the OFDM signal, and
A deinterleaver circuit that deinterleaves the interleaved first to Nth codewords,
Equipped with
The number of data symbols contained in the first code word is less than the number of data symbols contained in the second code word.
The interleaved first to Nth codewords are written in ascending order from the first codeword to the Nth codeword in the interleaver circuit of the transmitter, and read from the second codeword. Is started and generated,
Receiver. The deinterleaver circuit has a memory size of N _x × N _y and has a memory size of N x × N y.
_Ny is equal to the number of data symbols contained in the second codeword,
The receiving device according to claim 4. The interleaver circuit reads out the second codeword by using an address obtained by shifting the interleaved address generated according to the interleave size according to the number of data symbols included in the first codeword.
The receiving device according to claim 4. Interleave the 1st to Nth codewords,
The interleaved first to Nth codewords are converted into OFDM signals by converting them into OFDM signals.
The OFDM signal is transmitted,
The number of data symbols contained in the first code word is less than the number of data symbols contained in the second code word.
Writing from the first codeword to the Nth codeword in ascending order, and reading from the second codeword is started.
Sending method. Receives an OFDM signal containing interleaved first to N codewords in the transmitter and receives
The interleaved first to Nth codewords are extracted from the OFDM signal.
Deinterleave the interleaved 1st to Nth codewords
The number of data symbols contained in the first code word is less than the number of data symbols contained in the second code word.
The interleaved first to Nth codewords are written in ascending order from the first codeword to the Nth codeword in the interleaver circuit of the transmitter, and read from the second codeword. Is started and generated,
Receiving method.

Images