JP7027857B2 - Control device - Google Patents

Description

The present disclosure relates to a control device mounted on a vehicle and capable of performing floating point arithmetic.

As the above-mentioned control device, Patent Document 1 below proposes a technique of initializing data in units of control blocks in order to suppress propagation of non-numbers when non-numbers are generated by floating-point arithmetic. There is.

Japanese Patent No. 5379712

However, as a result of detailed examination by the inventor, in a configuration in which data is initialized in units of control blocks, data that does not need to be initialized is also initialized and recalculated, resulting in processing performance such as a delay in processing. It was found that there is a risk of deterioration of the product.

One aspect of the present disclosure is to provide a technique for suppressing deterioration of processing performance when a non-number occurs in a control device mounted on a vehicle and capable of performing floating-point arithmetic.

The control device (20A, 20B) according to one aspect of the present disclosure includes a calculation determination unit (S120, S220) and an instruction execution unit (S130, S150, S200, S250, S260, S310). The operation determination unit is configured to determine the presence / absence of a division instruction representing an operation instruction for performing an operation of dividing 0 by 0 by a floating-point operation.

When there is a division instruction, the instruction execution unit generates a multiplication instruction that adds the sign of each value included in the division instruction and multiplies 0 to 0 by multiplying the division, and multiplies it in place of the division instruction. It is configured to execute an instruction.

According to such a configuration, the multiplication instruction considering the sign is executed instead of the division instruction which is an operation instruction of dividing 0 by 0, so that the non-number is predetermined while suppressing the propagation of the non-number. It is possible to suppress the deterioration of processing performance that may occur when performing an operation that is used by replacing it with a value.

In addition, the reference numerals in parentheses described in this column and the scope of claims indicate the correspondence with the specific means described in the embodiment described later as one embodiment, and the technical scope of the present disclosure is defined. It is not limited.

It is a block diagram which shows the structure of an electronic control system. It is a schematic diagram which shows the configuration example of a register group and RAM. It is a flowchart of the instruction execution process executed by the arithmetic unit. It is a flowchart which shows exception handling in instruction execution processing. It is a schematic diagram which shows an example of the instruction acquired in the instruction execution process. It is explanatory drawing which shows an example of the generated subroutine. It is a map showing an input / output example by an invalid operation.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
[1. First Embodiment]
[1-1. Constitution]
FIG. 1 is a block diagram showing a configuration of an electronic control system 1 to which the present invention is applied. The electronic control system 1 includes an electronic control device 5. The electronic control system 1 may include a crank angle sensor 31 and an injector 32.

The electronic control device 5 includes a microcomputer 10 and an input / output circuit 7, and the microcomputer 10 includes a plurality of arithmetic units 20A and 20B, a ROM 12, a RAM 13, and an interface unit 15. The ROM 12 and the RAM 13 are well-known memories, and are configured as, for example, semiconductor memories. The input / output circuit 7 is a well-known interface circuit for exchanging data between the electronic control device 5 and an external device, and is referred to as an I / F in the drawings via a well-known interface unit 15. Data is exchanged inside and outside the microcomputer 10. Further, in the present embodiment, a configuration including two arithmetic units 20A and 20B is illustrated, but the number of arithmetic units may be 1 or 3 or more.

The plurality of calculation units 20A and 20B include a calculation unit [A] 20A and a calculation unit [B] 20B. Each of the arithmetic units 20A and 20B has the same hardware configuration, and has CPUs 21A and 21B, FPU22A and 22B, and register groups 23A and 23B, respectively. Each function of the arithmetic units 20A and 20B is realized by the CPUs 21A and 21B and the FPU 22A and 22B executing a program stored in the non-volatile memory. In this example, the ROM 12 and the RAM 13 correspond to the non-volatile memory in which the program is stored. In addition, when this program is executed, the method corresponding to the program is executed. Further, the electronic control device 5 may include one microcomputer or a plurality of microcomputers.

The CPUs 21A and 21B have a well-known configuration for executing a predetermined program according to a predetermined calculation order, and can respond to interrupts. The CPUs 21A and 21B have, for example, a function of executing an instruction execution process described later as a part of the function of executing the program.

The method for realizing the functions of each part included in the CPUs 21A and 21B is not limited to software, and some or all of the functions may be realized by using one or a plurality of hardware. For example, when the above function is realized by an electronic circuit which is hardware, the electronic circuit may be realized by a digital circuit, an analog circuit, or a combination thereof.

The operation results and the like by the CPUs 21A and 21B are temporarily recorded in the register groups 23A and 23B. As shown in FIG. 2 as an example, the register groups 23A and 23B include a data recording area from R0 to R31 for recording the calculation result of a predetermined variable. A storage area for floating-point data is secured in the data recording area.

The crank angle sensor 31 is a well-known sensor that detects the angle of the crank in the internal combustion engine of a vehicle. Further, the injector 32 is a well-known fuel injection device in an internal combustion engine of a vehicle. The injector 32 is mainly controlled by the CPUs 21A and 21B.

The FPUs 22A and 22B execute floating-point arithmetic among the operations based on the program. Floating-point arithmetic is an operation using floating-point data. By providing FPU22A and 22B, it is possible to perform an operation using floating-point type data, and an operation result can be obtained with finer accuracy than fixed-point type data. The floating-point type data of the calculation result is recorded in the register groups 23A and 23B. FPU22A and 22B are, for example, data formats according to the IEEE754 standard and represent floating point type data.

That is, the single-precision floating-point data according to the IEEE754 standard is composed of a 1-bit sign part, an 8-bit exponent part, and a 23-bit mantissa part. In the floating-point data of this standard, for example, an operation result that cannot be expressed as a numerical value can be expressed as a "non-number".

In an operation using floating-point data, if a non-number occurs, all the operation results using this non-number will be non-number. Therefore, when a non-number occurs, it is necessary to rewrite the non-number to a normal value that is not a non-number. An operation result such as an operation divided by 0 or an operation using ∞ (infinity) can be given as an example of an operation result that cannot be expressed as a numerical value.

For example, in this standard, if all 8 bits of the exponent part are "1", that is, the exponent part is "255" in decimal notation and the mantissa part is other than "0", this floating point type data is "non-number". Represents. Further, in the above-mentioned standard, when all 8 bits of the exponent part are "1" and the mantissa part is "0", this floating point type data represents "infinity". In the following, operations that result in operations that cannot be expressed as numerical values, such as operations that divide by 0 and operations that use infinity, are referred to as invalid operations, or are included in invalid operations. The command is called an invalid command.

The CPUs 21A and 21B execute fixed-point arithmetic among the operations based on the program, and cause the FPUs 22A and 22B to execute the floating-point arithmetic. The CPUs 21A and 21B can handle interrupts as described above. The interrupts include hardware interrupts based on requests from well-known interrupt controllers and the like, and software interrupts based on the execution of instructions by the CPUs 21A and 21B themselves. In this embodiment, the CPUs 21A and 21B correspond to hardware interrupts. However, the CPUs 21A and 21B may correspond to software interrupts or may correspond to both of them.

The CPUs 21A and 21B carry out the processes described later based on the program. Further, the CPUs 21A and 21B also carry out a well-known vehicle control process for controlling the operation and the like of the injector 32 based on the detection result and the like by the crank angle sensor 31.

When an interrupt occurs, the CPUs 21A and 21B perform CPU processing at the time of interruption. Specifically, when the CPU interrupt request signal is input, the CPUs 21A and 21B interrupt the currently executing process and save the process information necessary for restarting the process to the register groups 23A and 23B. That is, they are stacked. In particular, in the present embodiment, as shown in FIG. 2, the processing information is saved in the area including the reference register 23D in the register groups 23A and 23B.

The reference register 23D indicates a register in which the reference address 13D at the time of relative address access is described. Further, the relative address access represents a method of specifying a recording area in the RAM 13 by a relative path from the reference address 13D set in the RAM 13.

That is, when accessing the RAM 13, the CPUs 21A and 21B recognize the reference address 13D by referring to the reference address 13D described in the reference register 23D, and use an area in the RAM 13 with a relative path from the reference address 13D. It is configured to be specific.

Further, the processing information is information indicating a processing state such as a flag, for example. In this embodiment, the processing information also includes information representing the contents of so-called local variables used in the interrupted program. The CPUs 21A and 21B specify interrupt processing to be executed, for example, exception handling described later, based on the interrupt information acquired when the CPU interrupt request signal is input.

The CPUs 21A and 21B execute, for example, an exception handling described later as the interrupt processing specified in this way, and after the interrupt processing is completed, read the saved information from the area including the reference register 23D. Based on that information, the previously interrupted process is restarted. In the following, the process of saving the processed information to the area including the reference register 23D is referred to as a save process, and the process of reading the saved information from the area including the reference register 23D is referred to as a return process.

[1-2. process]
Next, the instruction execution processing executed by the arithmetic units 20A and 20B will be described with reference to the flowchart of FIG. The instruction execution process is a process that is started when the arithmetic units 20A and 20B execute a floating-point arithmetic, and is a process that is repeatedly executed until the floating-point arithmetic is completed. Although the configuration in which the arithmetic unit 20A executes the instruction execution process is illustrated below, the arithmetic unit 20B may execute the instruction execution process, or the arithmetic units 20A and 20B cooperate to execute the instruction execution process. You may.

In the instruction execution process, first, in S110, the arithmetic unit 20A selects an arithmetic including the instruction. The form of the operation is arbitrary, but for example, one line of the program may be selected as the operation.
Subsequently, in S120, the calculation unit 20A determines whether or not the selected operation includes an invalid instruction. When it is determined in S120 that the invalid instruction is included, the arithmetic unit 20A shifts to S130 and determines whether or not the exception setting is valid. The exception setting is a setting for determining whether or not to execute interrupt processing such as exception processing, and is managed by, for example, the registers of FPU22A and 22B. In particular, the exception setting is set for each control unit. The control unit represents each control target such as an air conditioner and fuel injection, or each calculation when controlling the control target.

When the calculation unit 20A determines in S130 that the exception setting is valid, the calculation unit 20A shifts to S140, executes the exception processing described later, and then ends the instruction execution process of FIG.
On the other hand, when the calculation unit 20A determines in S130 that the exception setting is not valid, the operation unit 20A shifts to S150, outputs a default value in place of an invalid instruction, and then ends the instruction execution process of FIG. That is, when the exception setting is invalid, if there is a preset invalid instruction including a division instruction, the arithmetic unit 20A replaces the operation result of the invalid instruction with a default value which is a default value and outputs the output.

Further, when the calculation unit 20A determines that the operation selected in S120 does not include an invalid instruction, the operation unit 20A shifts to S160, executes an operation including a valid instruction which is an instruction that is not an invalid instruction, and then shows FIG. Ends the instruction execution process of.

Next, the exception handling executed by the arithmetic unit 20A will be described with reference to the flowchart of FIG.
First, the evacuation process is executed in S200. In the save process, as described above, the process information is saved in the area including the reference register 23D. At this time, the processing information may be saved by using only the reference register 23D. When the arithmetic unit 20A saves the processing information using only the reference register 23D, only the reference register 23D, which is not used in the normal processing, is rewritten by the save processing, so that the data written to the registers 23A and 23B by the exception processing. However, it is possible to prevent the saved processing information from being affected.

Subsequently, in S210, the arithmetic unit 20A acquires an invalid instruction and a return address. The return address indicates a position on the ROM 12 in which the operation including the invalid instruction was written, and is a position that becomes a mark when reading the program on the ROM 12 again after the exception handling is completed.

Subsequently, in S220, the arithmetic unit 20A determines whether or not the invalid instruction includes division. When the calculation unit 20A determines in S220 that the invalid instruction includes division, the calculation unit 20A shifts to S230 and acquires the register numbers of the numerator RA and the denominator RB used for the calculation in this instruction from the register groups 23A and 23B. As shown in FIG. 5, the instruction here is represented by, for example, 32 bits, and includes a code “1011” indicating division. In this process, a code indicating whether the numerator RA and the denominator RB are positive or negative numbers is also acquired.

Subsequently, in S240, the arithmetic unit 20A determines whether or not RA = 0 and RB = 0. Here, 0 represents +0 or −0. In this process, the arithmetic unit 20A determines whether or not there is a division instruction. The division instruction represents an operation instruction for dividing 0 by 0 by a floating-point operation.

When the calculation unit 20A determines in S240 that RA = 0 and RB = 0, the calculation unit 20A shifts to S250 and generates a multiplication instruction in which the division included in the division instruction is changed to multiplication. At this time, the calculation unit 20A adopts the register numbers of the numerator RA and the denominator RB used for the calculation in this instruction as they are, and, for example, as shown in FIG. 5, a code indicating multiplication by the code "1011" indicating division. Replace with "1010". That is, a multiplication instruction is generated, which is an operation of multiplying 0 by 0 while adding the signs of the numerator RA and the denominator RB. The multiplication instruction is executed in S280, which will be described later, instead of the division instruction.

Subsequently, in S260, the arithmetic unit 20A generates a subroutine including a multiplication instruction on the RAM 13. The subroutine generated by this process has, for example, the data shown in FIG. That is, the subroutine includes an instruction executed by the FPU and an instruction returned from the subroutine.

In particular, the contents of the process include an instruction executed by the FPU and an instruction returned from the subroutine. The instruction returned from the subroutine is an instruction for returning the process to the main routine after the subroutine is completed. In the subroutine, the content of the processing is described for each arithmetic unit to be processed in preparation for the case where the parallel processing is performed by the plurality of arithmetic units 20A and 20B.

By the way, the process of S260 for generating a subroutine is also executed when the arithmetic unit 20A determines in S220 that the invalid instruction does not include division, and also in S240 when it determines that RA = 0 and RB = 0. .. In this case, a subroutine is generated to output the solution RD by the invalid instruction included in the operation as the default value determined according to the map shown in FIG.

For example, in the upper two rows of the map shown in FIG. 7, when the numerator RA is a non-numerical value, that is, ± norm, and the denominator RB is 0, the signs of the values of the numerator RA and the denominator RB are signed. An example of determining the solution RD according to the combination is shown. That is, in this process, the exclusive OR of the signs of the numerator RA and the denominator RB becomes the sign of the solution RD, and the absolute value of the solution RD is set to be the maximum value max. The maximum value max here may be the same value as the above-mentioned “infinity”, but is preferably a value predetermined as a maximum value excluding “infinity”.

The lower two rows of the map shown in FIG. 7 also show the calculation results when both the numerator RA and the denominator RB are 0. By executing the process of replacing the division instruction with the multiplication instruction as shown above, the solution RD with the sign added can be obtained.

Subsequently, in S270, the arithmetic unit 20A sets the exception setting to invalid. If the exception setting is invalidated, the occurrence of an exception due to an invalid instruction is suppressed while the exception setting is invalid, so that it is possible to prevent the subroutine or the like generated by other processing from being overwritten.

Subsequently, in S280, the arithmetic unit 20A executes the subroutine by the FPU 22A and 22B.
Subsequently, when the execution of the subroutine is completed, the arithmetic unit 20A effectively sets the exception setting in S290. By re-enabling the exception setting, exception handling can be executed when the next selected instruction contains an invalid instruction.

Subsequently, in S300, the arithmetic unit 20A increments the return address. This process is to prevent the same operation from being executed again.
Subsequently, in S310, the arithmetic unit 20A executes the above-mentioned return process. At this time, the reference address 13D is described in the reference register 23D. The reference address 13D is described in advance in a specific area in the ROM 12, and is set so that the reference address 13D can be specified by referring to this area.

After this processing, the exception processing shown in FIG. 4 is terminated.
[1-3. effect]
According to the first embodiment described in detail above, the following effects are obtained.

(1a) In the electronic control system 1 described above, the calculation units 20A and 20B are configured to determine the presence / absence of a division instruction representing an operation instruction for performing an operation of dividing 0 by 0 by a floating-point operation. When there is a division instruction, the arithmetic units 20A and 20B generate a multiplication instruction that is an operation of multiplying 0 by 0 with the division as a multiplication by adding the sign of each value included in the division instruction, and replace it with the division instruction. Is configured to execute the multiplication instruction.

According to such a configuration, the multiplication instruction considering the sign is executed instead of the division instruction which is an operation instruction of dividing 0 by 0, so that the non-number is predetermined while suppressing the propagation of the non-number. It is possible to suppress the deterioration of processing performance that may occur when performing an operation that is used by replacing it with a value.

For example, in a configuration in which 0 is divided by 0 and the calculation result is simply replaced with 0, case classification for determining the sign of the denominator numerator is required. That is, a process for adding an exclusive OR by a combination of + and-signs of the denominator numerator is required for 0, and there is a possibility that the process performance may be deteriorated, such as a delay in the process. In the configuration of the present disclosure, since the multiplication instruction considering the sign is executed instead of the division instruction in which 0 is divided by 0, the deterioration of the processing performance when a non-number occurs can be suppressed.

(1b) In the electronic control system 1 described above, the arithmetic units 20A and 20B are configured to generate a subroutine including a multiplication instruction on a preset RAM and execute the subroutine.

According to such a configuration, since the subroutine including the multiplication instruction is generated on the RAM, the ROM area can be saved as compared with the configuration in which the subroutine including the multiplication instruction is prepared in advance on the ROM.

(1c) In the electronic control system 1 described above, the arithmetic units 20A and 20B are configured to generate a multiplication instruction when the exception setting prepared in advance is valid and there is a division instruction. Further, when the exception setting is invalid, if there is a preset invalid instruction including a division instruction, the default value is output instead of the invalid instruction. Further, the arithmetic units 20A and 20B are configured to invalidate the exception setting when executing the multiplication instruction based on the subroutine, and to enable the exception setting after executing the multiplication instruction.

According to such a configuration, the exception setting is temporarily invalidated until the subroutine is executed, so that the generated subroutine can be prevented from being overwritten by another process.

(1d) The electronic control system 1 described above further includes register groups 23A and 23B having a plurality of registers configured to hold data obtained by calculation. Of the register groups 23A and 23B, the register in which the reference address 13D for relative address access is described is used as the reference register 23D, and the arithmetic units 20A and 20B generate a multiplication instruction and execute the multiplication instruction. The register including the reference register 23D is configured to be used as a data save area.

According to such a configuration, since the data is saved by using the reference register 23D which is not used during normal control, it is possible to suppress adverse effects such as data being rewritten by other control.

(1e) In the above electronic control system 1, it is possible to set whether to enable or disable the exception setting prepared in advance for each control unit for the processing executed by the arithmetic units 20A and 20B. The arithmetic units 20A and 20B generate a multiplication instruction when the exception setting for the processing to be executed is valid and there is a division instruction, and the division is performed when the exception setting for the processing to be executed is invalid. If there is a preset invalid instruction including an instruction, the default value is output instead of the invalid instruction.

According to such a configuration, it is possible to set whether to execute the division instruction as a multiplication instruction or output the default value for each control unit.
[2. Other embodiments]
Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and can be variously modified and implemented.

(2a) In the above embodiment, an example in which the crank angle sensor 31 and the injector 32 are connected to the electronic control system 1 and the arithmetic units 20A and 20B execute control of the internal combustion engine has been described, but the present invention is limited thereto. is not it. For example, instead of the crank angle sensor 31 and the injector 32, an arbitrary sensor and an actuator may be provided, and the actuator may be controlled according to the detection result by the sensor and the calculation result by the calculation unit.

(2b) A plurality of functions possessed by one component in the above embodiment may be realized by a plurality of components, or one function possessed by one component may be realized by a plurality of components. .. Further, a plurality of functions possessed by the plurality of components may be realized by one component, or one function realized by the plurality of components may be realized by one component. Further, a part of the configuration of the above embodiment may be omitted. Further, at least a part of the configuration of the above embodiment may be added or replaced with the configuration of the other above embodiment. It should be noted that all aspects included in the technical idea specified from the wording described in the claims are embodiments of the present disclosure.

(2c) In addition to the electronic control system 1 described above, a control device that is a component of the electronic control system 1, a program for operating a computer as the electronic control system 1, a non-transition such as a semiconductor memory in which this program is recorded, etc. The present disclosure can also be realized in various forms such as a realistic recording medium and a control method involving floating point arithmetic.

[3. Relationship between the configuration of the embodiment and the configuration of the present disclosure]
In the above embodiment, the arithmetic units 20A and 20B correspond to the control device referred to in the present disclosure. Further, among the processes executed by the arithmetic units 20A and 20B, the processes of S120 and S220 correspond to the arithmetic determination unit referred to in the present disclosure, and the processes of S130, S150, S200, S250, S260 and S310 are in the instruction execution unit. Equivalent to. Further, the processing of S270 and S290 corresponds to the setting change unit referred to in the present disclosure.

1 ... Electronic control system, 5 ... Electronic control device, 7 ... Input / output circuit, 10 ... Microcomputer, 12 ... ROM, 13 ... RAM, 13D ... Reference address, 20A, 20B ... Calculation unit, 21A, 21B ... CPU, 22A , 22B ... FPU, 23A, 23B ... register group, 23D ... reference register, 31 ... crank angle sensor, 32 ... injector.

Claims (5)

It is a control device (20A, 20B) that is mounted on a vehicle and can execute floating-point arithmetic.
Whether or not there is a division instruction that represents an operation command that divides the numerator value to 0 and the denominator value to 0 by floating-point operation, taking into account the sign of the numerator value and the sign of the denominator value. An arithmetic determination unit (S120, S220) configured to make a determination,
When there is the division instruction , a multiplication instruction for multiplying the value of the numerator by the value of the denominator is generated by using the code of the value of the numerator and the code of the value of the denominator included in the division instruction. , An instruction execution unit (S130, S150, S200, S250, S260, S310) configured to execute the multiplication instruction in place of the division instruction.
A control device equipped with. The control device according to claim 1.
The instruction execution unit is a control device configured to generate a subroutine including the multiplication instruction on a preset RAM and execute the subroutine. The control device according to claim 2.
The instruction execution unit is configured to generate the multiplication instruction when the exception setting prepared in advance is valid and the division instruction is present, and when the exception setting is invalid, the division is performed. If there is a preset invalid instruction including an instruction, it is configured to output a default value in place of the invalid instruction.
Setting change units (S270, S290) configured to invalidate the exception setting when executing the multiplication instruction based on the subroutine and to enable the exception setting after executing the multiplication instruction.
Further equipped with a control device. The control device according to any one of claims 1 to 3.
It further comprises a register group (23A, 23B) having a plurality of registers configured to hold the data obtained by the operation.
The register in which the reference address (13D) at the time of relative address access in the register group is described is used as the reference register (23D).
The instruction execution unit is a control device configured to use a register including the reference register as a data save area when generating the multiplication instruction and executing the multiplication instruction. The control device according to any one of claims 1 to 4.
The control device is configured to enable or disable the exception setting prepared in advance for each control unit for the process executed by the instruction execution unit.
The instruction execution unit generates the multiplication instruction when the exception setting for the process to be executed is valid and the division instruction is present, and when the exception setting for the process to be executed is invalid, the division instruction is given. A control device configured to output a default value in place of the invalid instruction when there is a preset invalid instruction including.

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