JP7022071B2 - Ground reference scheme for memory cells - Google Patents

Description

(There is no description corresponding to the technical field in the text)

<Cross reference>
This patent application is US Patent Application No. 15 / 057,914 filed on March 1, 2016 by Vimercati et al. Named "Ground Reference Picture for a Memory Cell" and is transferred to the transferee of this application. Claim the priority of the filed application Claim the priority of the PCT application number PCT / US2017 / 020251 filed on March 1, 2017 . These applications are incorporated herein by reference in their entirety.

The following relates generally to memory devices, and more specifically to ground reference schemes for ferroelectric memory cells.

Memory devices are widely used for storing information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming into different states of the memory device. For example, a binary device often has two states, often represented by logic "1" or logic "0". In other systems, more than one state can be stored. To access the stored information, the electronic device may read or sense the stored state in the memory device. To store the information, the electronic device may write or program the state of the memory device.

Random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), strong dielectric RAM (FeRAM), magnetic RAM (MRAM), resistance change type RAM (RRAM) There are various types of memory devices including, flash memory, and others. The memory device can be volatile or non-volatile. For example, a non-volatile memory such as a flash memory can store data for a long period of time even in the absence of an external power supply. Volatile memories such as DRAMs can lose their stored state over time unless they are periodically refreshed by an external power source. The binary memory device is an example of a volatile memory device, and can store a logical state by charging or discharging a capacitor. However, the charged capacitor can be discharged by the leak current over time, resulting in the loss of stored information. Mechanisms with volatile memory can provide advantageous performance such as high read or write speeds, while non-volatile memory mechanisms have the advantage of being able to store data without periodic refreshes. ..

The FeRAM may use the same device structure as the volatile memory, but may have non-volatile properties due to the use of the ferroelectric capacitor as the storage device. Therefore, the FeRAM device may have superior performance as compared with other non-volatile memory devices and volatile memory devices. The FeRAM detection scheme can rely on a non-zero reference voltage for comparison with the digit line voltage to determine the state stored in the memory cell. However, using a non-zero reference voltage may not be able to adapt to fluctuations in the digit line voltage and may lead to further errors in read operations.

Disclosures herein refer to and include the following drawings.
It is a diagram illustrating an example of a memory array that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. It is a diagram illustrating an example of a memory cell circuit that supports a ground reference scheme according to various embodiments of the present disclosure. It is a diagram illustrating an example of a hysteresis plot for the operation of a ferroelectric memory cell that supports a ground reference scheme according to various embodiments of the present disclosure. It is a diagram illustrating an example of a circuit that supports a ground reference scheme for a memory cell according to various embodiments of the present disclosure. It is a figure explaining the example of the timing diagram of the ground reference scheme for a memory cell according to various embodiments of this disclosure. It is a diagram illustrating an example of a circuit that supports a ground reference scheme for a memory cell according to various embodiments of the present disclosure. It is a figure explaining the example of the timing diagram of the ground reference scheme for the memory cell which operates according to various embodiments of this disclosure. It is a diagram illustrating an example of a ferroelectric memory array that supports a ground reference scheme according to various embodiments of the present disclosure. It is a diagram illustrating an example of an apparatus including a memory array that supports a ground reference scheme according to various embodiments of the present disclosure. It is a flowchart illustrating one or more methods of a ground reference scheme for a memory cell according to various embodiments of the present disclosure. It is a flowchart illustrating one or more methods of a ground reference scheme for a memory cell according to various embodiments of the present disclosure.

The memory device can use a ground reference scheme to increase the reliability of the digit line voltage sensing operation. The ground reference scheme described herein centers the possible read voltage of the digit line (ie, the voltage representing logic "1" and logic "0" of the memory cell) to ground (ie, two reads ). The technique of positioning the ground in the center of the voltage) can be used. The digit line voltage detected during the read operation can therefore be input to the sense amplifier and compared to the ground reference. Without the ground reference scheme, the digit line voltage during read operation may have to be compared to a non-zero value that may differ from different cells or arrays or both. Therefore, comparison with a non-zero value makes the read operation more sensitive to fluctuations in the digit line, which makes it more likely to generate an error.

As an example, a positive voltage can be applied to the plate of a ferroelectric capacitor in a memory cell, and the cell can be selected to discharge from the ferroelectric capacitor to the digit line. As soon as a certain amount of time has passed, or once the digit line voltage reaches a certain threshold, a negative voltage can be applied to the plate of the ferroelectric capacitor. The application of a negative voltage causes the digit line voltage to be centered at 0 volt in the center of two possible values of the digit line representing the logical state of the memory cell (ie, logic "1" or logic "0"). Can be lowered . The voltage of the digit line can then be read out and compared to a reference voltage equal to 0 volt. For example, a positive digit line voltage can represent logic "1" and a negative digit line voltage can represent logic "0".

The advantage of the ground reference scheme is also that it is realized without the need for a negative voltage source. For example, a reference circuit containing a reference capacitor can be used with a memory cell. The memory cell can be selected and the reverse voltage of the applied voltage can be applied to the reference capacitor at the same time (or almost simultaneously) the voltage is applied to the plate of the capacitor of the memory cell. The charge stored in the cell can be transferred to the digit line while the reference capacitor sends the stored charge to the digit line. Therefore, as described below, the reference capacitor can remove the charge from the digit line, and there are two possibilities of the digit line representing the logical state of the memory cell (ie, logic "1" or logic "0"). The 0 volt can be located in the center of the value. Therefore, the advantages of the ground reference scheme described above can be realized.

The mechanisms of the present disclosure previously introduced are further described below in the context of memory arrays. Specific examples are then described with reference to the circuits that can be used for the ground reference scheme. These and other mechanisms of the present disclosure are further described and described with reference to device diagrams, system diagrams, and flowcharts associated with the ground reference scheme for memory cells.

FIG. 1 illustrates an example of a memory array 100 that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. The memory array 100 may also be described as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 may be programmed to store two states, represented as logic "0" and logic "1". In some cases, memory cell 105 is configured to store three or more logical states. The memory cell 105 may include a capacitor for storing charges that represent a programmable state. For example, a charged capacitor and an uncharged capacitor can each represent two logical states. DRAM structures can generally use such designs, and the capacitors used may include dielectric materials with linear electrical polarization properties. In contrast, a ferroelectric memory cell may include a capacitor having a ferroelectric material as the dielectric material. Different charge levels of ferroelectric capacitors can represent different logic states. Ferroelectric materials have non-linear electrical polarization properties. Some details and advantages of the ferroelectric memory cell 105 will be described later.

Operations such as reading and writing may be performed by activating or selecting appropriate word lines 110 or digit lines 115 (which may also be referred to as access lines) on the memory cell 105. Activating or selecting the word line 110 or the digit line 115 may include applying a voltage to the individual lines. In some cases, the digit wire 115 may also be described as a bit wire. The word wire 110 and the digit wire 115 are made of a conductive material. For example, the word wire 110 and the digit wire 115 are made from a metal such as copper, aluminum, gold, or tungsten. According to FIG. 1, the individual rows of memory cell 105 are connected to one word line 110 and the individual columns of memory cell 105 are connected to one digit line 115. By activating (ie, applying a voltage) one of the word lines 110 and one of the digit lines 115, one memory cell 105 at their intersection can be accessed. The intersection of the word line 110 and the digit line 115 may be referred to as the address of the memory cell.

In some structures, cell logic storage devices, such as capacitors, may be electrically separated from the digit line by a selection component. The word line 110 can be connected to the selected component and can control the selected component. For example, the selection component may be a transistor and the word line 110 may be connected to the gate of the transistor. Activation of the word line 110 results in an electrical connection between the capacitor in the memory cell 105 and the corresponding digit line 115 in the memory cell 105. The digit line can then be accessed for reading or writing in memory cell 105.

Access to memory cells 105 can be controlled through the row decoder 120 and the column decoder 130. In some examples, the row decoder 120 receives a row address from the memory controller 140 and activates the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives the column address from the memory controller 140 and activates the appropriate digit line 115. Therefore, the memory cell 105 can be accessed by activating the word line 110 and the digit line 115. For example, the memory array 100 can access the memory cell 105 by activating DL_1 and WL_3.

Upon access, the memory cell 105 may be read or detected by the sense component 125 to determine the state of the stored memory cell 105. For example, after accessing the memory cell 105, the ferroelectric capacitor of the memory cell 105 may be discharged to the corresponding digit wire 115, inducing a voltage on the digit wire 115. The voltage of the digit wire 115 may be input to the sense component 125, where the voltage of the digit wire 115 may be compared to the reference voltage. For a memory cell 105 containing a ferroelectric capacitor, reading the memory cell may include biasing the plate of the ferroelectric capacitor (eg, applying a voltage).

The sense component 125 may include various transistors or amplifiers for detecting and amplifying (also referred to as latching) signal differences. The sense component 125 may include a sense amplifier that receives and compares the voltage of the digit line 115 and the reference voltage. The output of the sense amplifier can be driven to a higher (eg, positive) or lower (eg, negative or ground) supply voltage , at least in part, based on comparison. As an example, if the digit wire 115 has a voltage higher than the reference voltage, the output of the sense amplifier can be driven to a positive supply voltage. In some cases, the sense amplifier may additionally drive the output of the digit line 115 to the supply voltage. The sense component 125 then latches the output of the sense amplifier and / or the voltage of the digit line 115, which can be used to determine that the state stored in the memory cell 105 is logic "1". Alternatively, if the digit wire 115 has a voltage lower than the reference voltage, the output of the sense amplifier can be driven to a negative or ground voltage. The sense component 125 latches the output of a sense amplifier that can be used to determine that the state stored in the memory cell 105 is logic "0". The detected logical state of the memory cell 105 can then be output as input 135 through the column decoder 130.

The memory array 100 can use any or almost any voltage as the reference voltage, and the sense component 125 compares the voltage of the digit line 115 with the reference voltage to determine the logical state of the memory cell 105. be able to. However, the magnitude of the voltage on the digit line 115 due to the selection of the memory cell 105 is the stored state (ie, logic "1" or logic "0"), the characteristics of the ferroelectric capacitor, and the applied readout. It can fluctuate based on various factors including voltage and the like. Due to these fluctuations, the detected voltage can be relatively close in magnitude to the reference voltage, and the detection margin (ie, the "margin" between the digit line voltage representing logic "1" or logic "0" and the reference voltage. ") Can be reduced. This makes the read circuit more sensitive and complex in order to accurately read the state of the memory cell 105, otherwise a narrow detection margin can increase read errors. In addition, there can be an error in the reference voltage itself. For example, fluctuations in supply voltage, temperature, characteristics of the digit line 115 used as a reference line (eg, length, line thickness, etc.), characteristics of the memory cell 105 (eg, parasitic element), etc., are reference lines. Can affect (eg, increase or decrease) the magnitude of the voltage of. If the reference voltage is generated using another memory cell 105, the properties of the ferroelectric capacitor in the memory cell 105 may further affect the resulting voltage generated on the reference line.

Additional problems associated with using a non-zero reference are the charging of the digit line 115 itself (eg, parasitic circuit elements can affect the resulting reference voltage), and the readout applied to the plate of memory cell 105. Voltage errors (eg, higher plate voltages can be associated with increased voltages obtained from different logic states) can be included. That is, in some cases, more to increase the amount of charge extracted from the ferroelectric capacitor and to increase the sensing window (eg, the difference in voltage obtained from logic "1" and logic "0"). A high plate voltage may be applied to the memory cell 105. However, applying a higher plate voltage can increase the voltage obtained for both logic states compared to the reference voltage. Therefore, the resulting voltage may not have the generated reference voltage located in the center thereof, which may reduce the detection margin.

Using zero volt (0V) as a reference (eg, a detection scheme where the reference voltage is ground or de facto ground) can simplify the detection operation. As described herein, a detection scheme that uses 0V as a reference is referred to as a ground reference scheme. The ground reference uses a similar sensing window (eg, the voltage difference between logic "1" and logic "0") and / or a detection margin as compared to using a non-zero reference voltage. It can produce accurate results. For example, in a ground reference scheme, a positive digit line voltage can correspond to one logic state and a negative digit line voltage can correspond to a different logic state. Whether the digit line voltage is positive or negative can be determined more easily than whether the digit line voltage is above or below a certain non-zero voltage. The ground reference scheme can also reduce the errors associated with the generation of non-zero reference voltages, eliminating the need for additional circuitry to generate the reference voltage. In addition, the use of ground references can reduce the tests associated with selecting the initial preferred reference voltage that can vary from memory array to memory array.

To use the ground reference scheme, the possible read voltage of the digit line 115 from different logic states is such that the voltage associated with logic "1" and logic "0" is centered on the ground. Can be adjusted. Circuits and related methods that can achieve voltage adjustment of the digit wire 115 are described in more detail below. As described with reference to FIGS. 4 and 5, in some embodiments a negative voltage may be applied to the plate of the ferroelectric cell to adjust the voltage of the digit wire 115. In other embodiments, including those described with reference to FIGS. 6 and 7, a reference circuit may be used to adjust the voltage of the digit wire 115. For example, conversely or complementaryly , the voltage can be applied to the plate of the ferroelectric cell and the plate of the reference capacitor.

The memory cell 105 can be set or written by activating the associated word line 110 and digit line 115. As mentioned above, activation of the word line 110 electrically connects the memory cells 105 in the corresponding row to their individual digit lines 115. The memory cell 105 can be written by controlling the associated digit line 115 while the word line 110 is activated. That is, the logic value may be stored in the memory cell 105. The column decoder 130 may accept data written to memory cells 105, such as input 135. In the case of a ferroelectric capacitor, the memory cell 105 is written by applying a voltage across the ferroelectric capacitor. This process is discussed in detail below.

In some memory structures, access to the memory cell 105 can degrade or destroy the stored logical state, and a rewrite or refresh operation can be performed to return the original logical state to the memory cell 105. For example, in a DRAM, the capacitor can be partially or completely discharged during the detection operation, breaking the stored logic state. Therefore, the logical state can be rewritten after the detection operation. Further, activating one word line 110 may result in the discharge of all memory cells in that row, and some or all memory cells 105 in that row may need to be rewritten.

Some memory structures, including DRAMs, can lose their stored state over time unless they are regularly refreshed by an external power source. For example, a charged capacitor can be discharged by a leak current over time, resulting in the loss of stored information. The refresh rate of these so-called volatile memory devices can be relatively high. For example, in a DRAM, the refresh operation may be performed 10 times per second. It results in significant power consumption. Greater power consumption, as memory arrays grow larger, can curb the deployment or operation of memory arrays, especially for mobile devices that rely on finite power sources such as batteries (eg, power supply, heat generation, materials). Limits etc.). However, ferroelectric memory cells can have the advantage of being able to provide improved performance compared to other memory structures. For example, a ferroelectric memory cell tends to be less susceptible to degradation of stored charge, so a memory array 100 with a ferroelectric memory cell 105 may or may require a smaller number of refreshes. However, for this reason, less power may be required for operation.

The memory controller 140 may control the operation of the memory cell 105 (eg, read, write, rewrite, refresh, etc.) through various components such as the row decoder 120, the column decoder 130, and the sense component 125. The memory controller 140 may generate row address signals and column address signals to activate the desired word line 110 and digit line 115. The memory controller 140 may further generate and control various potentials used during the operation of the memory array 100. In general, the amplitude, shape, or duration of the applied voltage discussed herein can be adjusted or varied and can vary with various operations on the memory array 100. Further, one, a plurality, or all the memory cells 105 in the memory array 100 can be accessed at the same time. For example, a plurality or all cells of the memory array 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to one logical state.

In some cases, the memory controller 140 may be used to implement the mechanism of the ground reference scheme. As an example, the memory controller 140 may provide an input to the amplification device used to apply a read voltage to the plate of the ferroelectric capacitor in the memory cell 105. In some embodiments, the memory controller 140 can provide a negative voltage to the amplification device, which in turn can apply a negative voltage to the plate of the ferroelectric capacitor. In another embodiment, the memory controller 140 can provide a selective voltage to one or more amplification devices for selecting memory cells and reference capacitors, followed by a ferroelectric associated with the complementary voltage. It can be applied to the plate of the body cell and the plate of the reference capacitor.

FIG. 2 illustrates an example of a memory cell circuit 200 that supports a ground reference scheme according to various embodiments of the present disclosure. The circuit 200 includes the memory cell 105, the word line 110, the digit line 115, and the ferroelectric memory cell 105-a, which is an example of the sense component 125, and the word line 110-a (access line 110) described with reference to FIG. -A), digit wire 115-a, and sense component 125-a. Memory cells 105-a may include logic storage components such as capacitors 205. The capacitor 205 has a capacitively coupled first plate and a second plate, the first plate is sometimes referred to as the cell plate 230 and the second plate is referred to as the cell bottom 215. Sometimes. In some embodiments, the position of the capacitor may be reversed without changing the operation of memory cells 105-a. That is, the first plate may correspond to the cell bottom 215 and the second plate may correspond to the cell plate 230. In the example of FIG. 2, the cell plate 230 can be accessed via the plate wire 210 and the cell bottom 215 can be accessed via the digit wire 115-a. Further, in the example of FIG. 2, the terminals of the capacitor 205 are separated by an insulating ferroelectric material. As mentioned above, various states can be stored by charging or discharging the capacitor 205 (ie, polarization of the ferroelectric material of the capacitor 205). The total amount of charge required to polarize the capacitor 205 is sometimes referred to as the residual polarization (PR) value, and the voltage charged by only half of the entire capacitor 205 is called the coercive voltage (VC). May be described.

The state of the stored capacitor 205 can be read out or detected by the operation of various elements represented in the circuit 200. The capacitor 205 may electronically communicate with the digit line 115-a. For example, when the selection component 220 is deactivated, the capacitor 205 can be separated from the digit lines 115-a and the selection component 220 is active to select the ferroelectric memory cell 105-a. When the capacitor 205 is used, the capacitor 205 can be connected to the digit line 115-a. In other words, memory cells 105-a may be selected using a selection component 220 that electronically communicates with the capacitor 205. Here, the ferroelectric memory cell 105-a includes a selection component 220 and a ferroelectric capacitor 205. In some cases, the selection component 220 is a transistor whose operation is controlled by applying a voltage to the transistor gate that is greater than the magnitude of the transistor's threshold. The word line 110-a may activate the selection component 220. For example, the voltage applied to the word line 110-a is applied to the transistor gate to connect the capacitor 205 to the digit line 115-a. In an alternative embodiment, the selection component 220 and the selection component 220 are such that the selection component 220 is between the plate wire 210 and the cell plate 230 and the capacitor 205 is between the digit wire 115-a and the other terminals of the selection component 220. The positions of the capacitors 205 can be swapped. In this embodiment, the selection component 220 may remain in electronic communication with the digit lines 115-a through the capacitor 205. This configuration may relate to alternative timing and bias of read and write operations.

Due to the ferroelectric material between the plates of the capacitor 205, the capacitor 205 may not discharge when connected to the digit wire 115-a, as discussed in more detail below. In some schemes, the plate wire 210 and the word wire 110-a may be biased by an external voltage to detect the state stored in the ferroelectric capacitor 205 during readout. In some cases, the digit wire 115-a is separated from the de facto ground before applying an external voltage to the plate wire 210 and the word wire 110-a. The selection of the ferroelectric memory cell 105-a can result in a voltage difference across the capacitor 205 (eg, the plate wire 210 voltage minus the digit wire 115-a voltage). The difference in applied voltage was stored in the capacitor 205, which may depend on the initial state of the capacitor 205 (eg, whether the initial state contained logic "1" or logic "0"). A charge change can occur, inducing the voltage of the digit lines 115-a based on the resulting charge stored in the capacitor 205. Then, in order to determine the logical state stored in the memory cell 105-a, the voltage induced in the digit line 115-a is compared with the reference (for example, the voltage of the reference line 225) by the sense component 125-a. obtain.

The specific detection scheme or process can take many forms. In one example, the digit wire 115-a can have an intrinsic capacitance and can develop a non-zero voltage when the capacitor 205 is charging or discharging in response to a voltage applied to the plate 210. The intrinsic capacitance can be determined by the physical properties (including magnitude) of the digit wire 115-a. Since the digit wire 115-a can be connected to many memory cells 105, the digit wire 115-a can have a length of non-negligible capacitance (eg, on the order of picofarad (pF)). Subsequent voltage of digit line 115-a may depend on the initial logic state of capacitor 205, and the sense component 125-a may compare this voltage with the reference voltage 225 generated by the reference component. Circuit 200 may operate such that 0V is centered on a possible digit line 115 voltage during read operation. That is, either a negative voltage is applied to the plate wire 210, or a reference circuit (not shown) is used to effectively lower the voltage of the digit wire 115 so that the digit wire 115 is in read operation. Allows the voltage of to be compared to ground.

In some embodiments, the reference line 225 is an unused digit line that may be grounded. For example, a voltage may be applied to the plate wire 210 and the voltage at the bottom of the capacitor 215 may change in relation to the stored charge. The voltage at the bottom of the capacitor 215 can be compared to the reference voltage of the sense component 125-a, and the comparison with the reference voltage can indicate the change in charge of the capacitor 205 resulting from the applied voltage and is therefore stored in memory cells 105-a. Can indicate the logical state being done. The reference voltage can be 0V (ie ground or de facto ground). The relationship between charge and voltage in the capacitor 205 will be described in more detail with reference to FIG.

A voltage may be applied across the capacitor 205 to write to memory cells 105-a. Various methods can be used. In one example, the selection component 220 may be activated through the word wire 110-a to electrically connect the capacitor 205 to the digit wire 115-a. By controlling the voltage of the cell plate 230 with the plate wire 210 and controlling the voltage of the cell bottom 215 with the digit wire 115-a, the voltage can be applied over the capacitor 205. To write the logic "0", the plate 210 can be high (ie, a positive voltage can be applied) and the cell bottom 215 can be low (eg, using digit lines 115-a). Be on the ground above). The reverse process is performed to write the logic "1". That is, the cell plate 230 can be low and the cell bottom 215 can be high. The read and write operations of the capacitor 205 may consist of non-linear properties associated with the ferroelectric device.

FIG. 3 illustrates examples of such non-linear characteristics for memory cells that support ground reference schemes according to the various embodiments of the present disclosure, along with hysteresis curves 300-a and 300-b. Hysteresis curves 300-a and 300-b describe examples of write processing and read processing to the ferroelectric memory cell, respectively. The hysteresis curve 300 describes the charge Q stored in the ferroelectric capacitor (for example, the capacitor 205 in FIG. 2) as a function of the voltage V.

Ferroelectric materials are characterized by naturally occurring electrical polarization (ie, maintaining non-zero electrical polarization in the absence of an electric field). Examples of ferroelectric materials include barium titanate (BaTIO ₃ ), lead titanate (PbTiO ₃ ), lead zirconate titanate (PZT), and strontium bismuth tantanate (SBT). The ferroelectric capacitors described herein may include these ferroelectric materials or other ferroelectric materials. Electrical polarization in a ferroelectric capacitor results in a net charge on the surface of the ferroelectric material, attracting the opposite charge through the terminals of the capacitor. Therefore, the charge is stored at the interface between the ferroelectric material and the terminals of the capacitor. Since electrical polarization can be maintained for a relatively long period of time (even indefinitely) without an externally applied electric field, charge leakage is significantly reduced compared to capacitors used in DRAM arrays, for example. To. This reduces the need to perform the refresh operation as described above for some DRAM structures.

The hysteresis curve 300 can be understood from the point of view of one terminal of the capacitor. As an example, if the ferroelectric has a negative polarization, a positive charge will accumulate at the terminal. Similarly, if the ferroelectric has a positive polarization, a negative charge will accumulate at the terminal. It should also be understood that the voltage in the hysteresis curve 300 represents the difference and direction of the voltage across the capacitor. For example, a positive voltage can be applied by applying a positive voltage to the terminal in question and keeping the second terminal ground. By keeping the terminal in question ground and applying a positive voltage to the second terminal (ie, a positive voltage can be applied to negatively polarize the terminal in question). Negative voltage can be applied. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages is applied to the appropriate capacitor terminals to generate the voltage difference shown in the hysteresis curve 300. Can be done.

As depicted in the hysteresis curve 300-a, the ferroelectric material can maintain positive or negative polarization with a voltage difference of 0, so there are two possible charged states (charged state 305 and charged state 310). ) Brings. According to the example of FIG. 3, the charge state 305 represents the logic "0" and the charge state 310 represents the logic "1". In some embodiments, the logic values of the individual charge states may be reversed in order to apply other schemes for memory cell operation.

The logic "0" or logic "1" can be written to a memory cell by applying a voltage to control the electrical polarization of the ferroelectric material (as a result, the charge on the terminals of the capacitor). For example, when a net positive voltage 315 is applied over a capacitor, charge buildup occurs until the charged state 305-a is reached. When the voltage 315 is removed, the charged state 305-a follows the path 320 until it reaches the charged state 305 at zero potential. Similarly, the charged state 310 is written by applying a net negative voltage 325 that results in the charged state 310-a. After removing the negative voltage 325, the charged state 310-a follows the path 330 until it reaches the charged state 310 at zero potential.

A voltage is applied across the capacitor to read or detect the stored state of the ferroelectric capacitor. The stored charge changes accordingly, and the degree of change depends on the initial charge state. That is, the degree of change in the stored charge of the capacitor changes depending on whether the charged state 305-b was stored first or the charged state 310-b was stored first. For example, the hysteresis curve 300-b illustrates two possible stored charged states (charged state 305-b and charged state 310-b). A net voltage 335 may be applied to the cell plate of the capacitor (eg, cell plate 230 with reference to FIG. 2). Although depicted as a positive charge, the voltage 335 may be negative. In response to voltage 335, charge state 305-b can follow path 340. Similarly, if the charge state 310-b was initially stored, then path 345 is followed. The final position of the charged states 305-c and 310-c is determined by a number of factors, including the particular detection operation and circuit.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line of the memory cell. For example, if a capacitor is electrically connected to the digit wire and a voltage of 335 is applied, the voltage of the digit wire can rise due to its inherent capacitance, and the voltage measured by the sense component is of the digit wire. It can depend on the resulting voltage. The final positions of the final charge states 305-c and 310-c on the hysteresis curve 300-b can therefore depend on the capacitance of the digit line and can be determined by load line analysis. That is, the charge states 305-c and 310-c can be defined with respect to the capacitance of the digit line. As a result, the voltage of the capacitor (voltage 350 or voltage 355) can vary and can depend on the initial state of the capacitor.

The initial state of the capacitor can be determined by comparing the difference between the voltage applied to the cell plate (eg, voltage 355) and the voltage across the capacitor (eg, voltage 350 and voltage 355) with the reference voltage. As understood by reference to FIG. 2, the voltage of the digit wire can be expressed as the difference between the voltage applied to the plate wire 210 and the resulting voltage across the capacitor 205. As discussed above, the voltage of the digit line is at least partially based on the change in charge stored in the capacitor, and the change in charge is related to the magnitude of the voltage applied across the capacitor. In some embodiments, the reference voltage is the average of the digit line voltages obtained from the voltage 350 and the voltage 355, and by comparison, the detected digit line voltage can be determined to be higher or lower than the reference voltage. .. Then, based on the comparison, the value of the ferroelectric cell (ie, logic "0" or logic "1") can be determined.

However, as discussed earlier, the digit line and reference voltage can vary, at least in part, based on cell characteristics (eg, age), environmental factors (eg, temperature), applied voltage, and the like. In some situations, using the average digit line voltage as the reference voltage can reduce the detection margin. As an example, fluctuations in the digit line voltage resulting from two logical states can increase the average of the digit line voltage, and the reference voltage can be biased towards one digit line voltage. Using a ground reference instead of a non-zero reference voltage (eg, the average of the digit line voltages) can reduce errors associated with the reference voltage, simplify the generation of the reference voltage, and even relate to the detection operation. You can reduce the complexity.

As discussed above, reading a memory cell without a ferroelectric capacitor can degrade or destroy the stored logic state. However, the ferroelectric memory cell 105 may retain its initial logical state after the read operation. For example, if the charge state 305-b is stored and a read operation is performed, the charge state follows the path 340 to the charge state 305-c and, for example, the path 340 in the reverse direction after the voltage 335 is removed. Allows the charged state to return to the original charged state 305-b.

FIG. 4 illustrates an example of circuit 400 that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. The circuit 400 is a memory cell 105-b, a word line 110-b (access) which is an example of each of the memory cell 105, the word line 110, the digit line 115, and the sense component 125 described with reference to FIGS. 1 and 2. Also referred to as wire 110-b), digit wire 115-b, and sense component 125-b. Circuit 400 also includes plate wire 210-a and reference wire 225-a, which are examples of plate wire 210 and reference wire 225, respectively, described with reference to FIG. Circuit 400 also includes a voltage source 405, a voltage source 410, and a switching component 420.

The digit lines 115-b and the reference lines 225-a may have intrinsic capacitances 415-a and 415-b, respectively. The intrinsic capacitances 415-a and 415-b do not have to be electrical devices. That is, it does not have to be a two-terminal capacitor. Instead, the intrinsic capacitances 415-a and 415-b may depend on the physical characteristics of the digit lines 115-b and the reference lines 225-a, including their magnitude. In some cases, the reference line 225-a is an unused or unactivated digit line. Although not drawn, in some embodiments the digit lines 115-b are connected to the de facto ground via a switching component. The de facto ground can float to a voltage different (eg, greater than or less than) 0 volt when compared to earth ground, but the de facto ground can act as a common reference for circuit 400, ground or 0V. Can behave as.

The reference line 225-a can be used by the sense component 125-b as a reference for comparison with the digit line 115-b. In some examples, the reference line 225-a is connected to the de facto ground to provide a ground reference for comparison with the voltage of the digit line 115-b. The reference line 225-a can be separated from the de facto ground through a switching component 420 which can be mounted as a transistor (eg, a p-type field effect transistor (FET)). In other cases, the reference line 225-a is directly connected to the de facto ground.

As drawn, the memory cells 105-b are in electronic communication with the digit lines 115-b. As described with reference to FIG. 2, memory cells 105-b can be selected using a selection component that electronically communicates with the ferroelectric capacitor via the word line 110-b. Activation of the selected component may connect a ferroelectric capacitor to the digit wire 115-b.

The plate wire 210-a can electronically communicate with a ferroelectric capacitor (eg, a plate of a ferroelectric capacitor). A voltage may be applied to the plate wire 210-a of the ferroelectric capacitor of the memory cell 105-b to read out the memory cell 105-b. The application of a positive voltage to the plate wire 210-a in combination with the application of a voltage to the ward wire 110-b results in the ferroelectric capacitor charging the digit wire 115-b. After applying a positive voltage, a negative voltage may be applied to the plate wire 210-a to adjust the voltage of the digit wire 115-b. In some cases, a negative voltage is applied after it is determined that the voltage of the digit lines 115-b has reached a threshold in response to the application of a positive voltage. This negative voltage is such that the voltage derived from the logical state "0" and the voltage derived from the logical state "1" stored in the ferroelectric capacitor are substantially grounded at the center thereof . Can be selected to adjust. As an example, a ferroelectric memory cell from a ferroelectric memory array can be applied to determine an average logic "1" voltage and an average logic "0" voltage (eg, by applying various plate voltages, temperatures, etc.). ) Tested and negative voltage can be properly selected. In other cases, negative voltages may be selected based on mathematical models developed for ferroelectric memory arrays or based on established test results. In some cases, voltage may be applied to the plate wire 210-a and the word wire 110-a via an external voltage source, amplifier, line driver, and the like.

The sense component 125-b may be used to determine the state stored in memory cells 105-b. In some cases, the sense component 125-b can be a sense amplifier or can include a sense amplifier. The sense component 125-b can be operated by a voltage source 405 and a voltage source 410. In some examples, the voltage source 405 is a positive supply voltage, while the voltage source 410 is a negative supply voltage or de facto ground. The sense component 125-b can be used to determine the logic value of the ferroelectric memory cell 105-b, at least partially based on the voltage of the digit line 115-b and the voltage of the reference line 225-a. The sense component 125-b can be activated or deactivated by the controller. In some cases, the sense component 125-b is activated or "fired" to make a comparison between the voltage of the digit line 115-b and the voltage of the reference line 225-a. To. The sense component 125-b can latch the output of the sense amplifier to the voltage supplied by the voltage source 405 or the voltage source 410. For example, if the voltage of the digit line 115-b is greater than the voltage of the reference line 225-a, the sense component 125-b can latch the output of the sense amplifier to the positive voltage supplied by the voltage source 405.

FIG. 5 illustrates an example of timing diagram 500 of a ground reference scheme for memory cells according to various embodiments of the present disclosure. The timing diagram 500 shows the voltage on the axis 505 and the time on the axis 510. Therefore, the voltages of the various components can be represented on the timing diagram 500 as a function of time. For example, the timing diagram 500 includes a word line voltage 515, a plate voltage 520, and digit line voltages 530-a and 530-b. The timing diagram 500 also includes a read voltage 535, a voltage threshold 540, a reference voltage 545, and a timing threshold 550. The timing diagram 500 describes an example of the operation of the circuit 400 described with reference to FIG. FIG. 5 is described below with reference to the components of the preceding figure. Voltages approaching zero can be offset from the axis 510 for simplification of representation , and in some cases these voltages can be the same as or substantially the same as 0 volts.

As discussed in FIG. 4, a voltage can be applied to the plate wire 210-a. In some examples, a read voltage (ie, the voltage used to read the state of the ferroelectric capacitor) may be applied to the plate wire 210-a, which biases the ferroelectric capacitor. The plate voltage 520 measured on the plate of a ferroelectric capacitor can rise with the application of a readout voltage. After applying the read voltage, the memory cells 105-b can be accessed by applying another voltage to the word line 110-b. The word line voltage 515, which can be measured at the gate of the selected component of memory cells 105-a, can rise with the application of voltage to the word line 110-b. As the word line voltage 515 rises, the selection component may provide a conductive path between the biased ferroelectric capacitor of memory cells 105-b and the digit line 115-b. Therefore, as the ferroelectric capacitor discharges to the digit wire 115-b, the digit wire voltage 530 may increase. The digit line voltage 530 may be virtually grounded before the read operation begins. In one example, a switching component such as a transistor may be used to connect the digit lines 115-c to ground.

When the word line 110-b is selected, the voltage of the cell bottom of the strong dielectric capacitor of the memory cell 105-b (for example, the cell bottom 215 described with reference to FIG. 2) and the voltage over the natural capacitance 415-a are set. Until equal, the strong dielectric capacitor in memory cells 105-b shares the charge with the intrinsic capacitance 415-a. The digit line voltage 530 can rise to one of the two voltages based on the stowed state. However, as discussed above, these two voltages can fluctuate depending on the characteristics, temperature, etc. of the memory cells 105-b. If the logic "1" is stored in the ferroelectric capacitor, a digit line voltage 530-a can be obtained, and if the logic "0" is stored in the ferroelectric capacitor, the digit line voltage 530-a. b can be brought. The digit line voltage 530-a may be associated with a smaller voltage drop across the ferroelectric cell and therefore, as described with reference to FIG. 3, a higher digit line voltage when compared to the digit line voltage 530-b. Can be related to.

Following the example shown in FIG. 5, after the digit line voltage 530 reaches the voltage threshold 540 and / or timing threshold 550, a negative voltage is applied to the plate line 210-a to drive the plate voltage 520 negatively. .. In some cases, the negative voltage may be applied after determining that a positive voltage has been applied over a predetermined duration (eg, a duration exceeding the timing threshold 550). A predetermined duration can be determined at least in part based on the characteristics of the ferroelectric capacitor, the characteristics of the digit wire, the timing of reading or writing the ferroelectric memory cell, or any combination thereof. In other cases, a negative voltage may be applied based on the determination that the digit line has reached the threshold. Alternatively, in some cases, the negative voltage is applied based on the determination that the digit line voltage 530 has stabilized (eg, the rate of change in the digit line voltage has reached a threshold). For example, it can be determined that the rate of change is lower than the threshold (eg, 10 mV / ns). In another embodiment, it is negative based on the determination that the digit line voltage 530 is within the predicted regulated voltage percent range (eg, within 5%) of either the digit line voltage 530-a or 530-b. A voltage is applied. In some cases, the predicted regulated voltage can be determined using experimental data, predictive models, and so on.

Since the plate voltage 520 transitions to a negative voltage, the digit line voltage 530 can return the charge to the ferroelectric capacitor and the digit line voltage 530 can also decrease. The decrease in the digit line voltage 530 may depend on the negative magnitude applied. In some cases, the magnitude of the negative voltage is selected based at least in part on the reduction caused by the digit line voltage 530-a or 530-b. In some examples, in the center of the digit line voltages 530-a and 530-b (ie, the possible digit line voltages brought about by memory cell selection), a de facto ground (eg, as shown in timing diagram 500). A negative voltage is selected so that the reference voltage 545, which is 0V), is located . In some cases, the reference voltage 545 may be generated by connecting the reference line 225-a to the de facto ground via the switching component 420. The sense component 125 is fired at time 555 after the digit line voltage 530 resulting from the application of the negative voltage has stabilized.

The sense component 125-b may compare the digit line voltage 530 with the reference voltage 545 and therefore the output of the sense component 125-b may be properly latched. For example, if the ferroelectric capacitor stores the logic value "1", the sense component 125-b can compare the digit line voltage 530-a with the reference voltage 545, and the digit line voltage 530-a is higher than the reference voltage 545. It can be judged to be high. Therefore, the output of the sense component 125-b can be positive supply voltage and can be latched. In this example, when the sense component 125-b outputs a positive supply voltage, the digit lines 115-b are also driven by the supply voltage.

FIG. 6 illustrates an example of a circuit 600 that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. The circuit 600 may be an example of each of the memory cell 105, the word line 110, the digit line 115, and the sense component 125 described with reference to FIGS. 1, 2, 4, and 5, memory cell 105-c. , Word line 110-c (also referred to as access line 110-c), digit line 115-c, and sense component 125-c. Circuit 600 may also include plate wire 210-b and reference wire 225-b, which may be examples of plate wire 210 and reference wire 225, respectively, described with reference to FIGS. 2 and 4. Further, the circuit 600 may be an example of a voltage source 405, a voltage source 410, and an intrinsic capacitance 415, and a switching component 420 described with reference to FIG. 4, a voltage source 405-a, a voltage source 410-a. , Intrinsic capacitances 415-c and 415-d, as well as switching components 420-a and 420-b. Circuit 600 may also include reference circuit 605, which is electronically communicable with the digit line 115-c and may include a reference capacitor 615, a selection component 610, a selection line 620, and a reference plate line 625.

The selection component 610 can be used to connect the digit wire 115-c and the reference capacitor 615. The reference capacitor 615 can be mounted as a dielectric capacitor, a ceramic capacitor, an electrolytic capacitor, or a ferroelectric capacitor. In some cases, the selection component 610 can be a transistor such as a p-type FET. The selection line 620 is electronically communicable with the selection component 610 and is used to activate the selection component 610. For example, the reference capacitor 615 can be accessed by applying a voltage to the selection line 620 (which can be mounted as a word line in the case of a ferroelectric capacitor). The size of the reference capacitor 615 may be selected so that the voltage of the digit lines 115-c resulting from logic "0" and logic "1" is centered on the ground reference. In one example, the size of the capacitor is chosen to be approximately 80 femtofarads (fF). In some cases, the size of the reference capacitor 615 relates to the capacitance associated with the ferroelectric capacitor containing the logic "0", and to the ferroelectric capacitor containing the logic "1". It can be selected to be the average of the capacitance. In another embodiment, when a ferroelectric capacitor is used, the size of the ferroelectric capacitor may be selected to be larger than the size of the ferroelectric capacitor in memory cells 105-c. In some examples, a reference capacitor may be implemented with a first ferroelectric capacitor containing the logic "0" and a second ferroelectric capacitor containing the logic "0".

The reference plate wire 625 can electronically communicate with the reference capacitor 615 and the digit wire 115-c. First, a positive voltage can be applied to the reference plate wire 625, and then 0 voltage to bias the ferroelectric capacitor of memory cells 105-c and to bias the reference capacitor 615. Can be applied to the plate wire 210-b. In some cases, another side of the reference capacitor 615 may be maintained at the ground reference via the switching component 420-b to allow charging of the reference capacitor 615. Subsequently, a selective voltage may be applied to the word line 110-c and the selection line 620 to access the memory cells 105-c and the reference circuit 605. The application of the selection voltage to the word line 110-c and the selection line 620 can connect the ferroelectric capacitor and the reference capacitor 615 of the memory cell 105-c to the digit line 115-c, respectively. In some cases, the digit line 115-c may remain connected to the de facto ground for the duration after the selective voltage is applied and may then be separated from the ground. At a later point in time, a zero voltage may be applied to the reference plate wire 625 or a positive voltage may be applied to the plate wire 210-b. In some cases, the magnitude of the positive voltage applied to the plate wire 210-b may differ from the magnitude of the positive voltage previously applied to the reference capacitor 615.

Applying the opposite or complementary (complementary) voltage (ie, applying a zero voltage to the reference plate wire 625 and applying a positive voltage to the plate wire 210-b) causes the reference capacitor 615 to charge. The ferroelectric capacitor can be discharged to the digit wire 115-c while being drawn from the digit wire 115-c. As the charge increases on the digit wire 115-c, the voltage on the digit wire 115-c can increase. Then, when the electric charge is drawn from the digit wire 115-c, the voltage of the digit wire 115-c may decrease. These complementary functions center the voltage of logic "1" and logic "0" (ie, the possible voltage of the digit lines 115-c brought about by the selection of memory cells 105-c). It can be used so that 0 volt is located . In order to determine the logic value stored in the memory cells 105-c, the voltage of the digit line 115-c can be compared with the voltage of the reference line 225-b. In some cases, as discussed above, the voltage on the reference line 225-b can be virtually ground. In some cases, voltage may be applied to the plate wire 210-b, the word wire 110-b, the selection wire 620, and the reference plate wire 625 via an external voltage source, amplifier, or line driver or the like.

FIG. 7 illustrates an example of timing diagram 700 that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. The timing diagram 700 shows the voltage on the axis 505-a and the time on the axis 510-a. The voltages of the various components can be represented on the timing diagram 700 as a function of time. For example, the timing diagram 700 may be an example of each of the word line voltage 515, the plate voltage 520, and the digit line voltage 530 described with reference to FIG. 5, the word line voltage 515-a, the plate voltage 520-a, and Includes digit line voltages 530-c and 530-d. The timing diagram 700 may also include a read voltage 535-a and a reference voltage 545-a, which may be examples of the read voltage 535 and the reference voltage 545 described with reference to FIG. The timing diagram 700 can be derived from the operation of the circuit 600 described with reference to FIG. FIG. 7 is described below with reference to the components of the preceding figure. Voltages approaching zero may be offset from axis 510 for simplification of representation. In some cases, these voltages are the same as or substantially the same as 0 volts.

As discussed in FIG. 6, to charge the reference capacitor 615 while a plate voltage 520-a is applied to the plate wire 210-b and the other side of the reference capacitor can be kept in effect ground. , A reference plate voltage 710 can be applied to the reference plate wire 625. In some cases, the magnitude of the applied voltage can be the voltage associated with the read operation. A selection voltage 705 may then be applied to the selection line 620 to generate a conductive path through the selection component 610 between the reference capacitor 615 and the digit line 115-c. Substantially at the same time as the application of the selective voltage 705, the word line voltage 515-a is changed to the word line 110- in order to generate a conductive path between the ferroelectric capacitor of the memory cell 105-c and the digit line 115-c. Can be applied to c. In some cases the same voltage is used to access both the ferroelectric and reference capacitors in memory cells 105-c and the reference circuit 605, but in other cases different voltages are used. In some cases, the digit line voltage 530 may be maintained ground via the switching component 420- a before and after the selection voltage 705 and the word line voltage 515-a are applied.

The reference plate voltage 710 and the plate voltage 520-a can then be applied to the reference plate wire 625 and the plate wire 210-b in the opposite direction (eg, the voltage can move in complementary directions). Therefore, the reference plate voltage 710 can decrease and the plate voltage 520-a can increase. That is, the voltage applied to the reference plate wire 625 is removed to 0 volt, and at substantially the same time a voltage (eg, read voltage) can be applied to the plate wire 210-b. Applying voltages at substantially the same time means applying voltages at the same time or almost simultaneously. Applying voltages at substantially the same time also means applying one voltage and applying a second voltage during a period of time (eg, 0.5 nanoseconds from the application of the first voltage). A second voltage is applied within seconds (ns)). As an example, a decrease in reference plate voltage 710 can overlap with an increase in plate voltage 520-a. In some cases, the period between the application of voltage to the word line 110-c and the reference plate line 625 is increased due to the characteristics of the memory array (eg, propagation delay). In some cases, the increase and decrease of the reference plate voltage 710 and the plate voltage 520-a do not overlap, and the period between the application of multiple voltages can be on the order of 3ns. As drawn, the increase in plate voltage 520-a discharges the ferroelectric capacitor in memory cell 105-c to the digit wire 115-c. On the other hand, a decrease in the reference plate voltage 710 can extract charge from the digit lines 115-c.

Providing charge to the digit lines 115-c can increase the digit line voltage 530, and removing the charge can decrease the digit line voltage 530. The amount of charge removed from the digit wire 115-c is the rate of change of the reference plate voltage 710, the size of the reference capacitor 615, the charge currently stored in the reference capacitor 615, the magnitude of the reference plate voltage 710, or these. Can be related to any combination of. In some cases, the size of the resulting reference plate voltage 710 and reference capacitor 615 is chosen so that the digit line voltages 530-c and 530-d are centered on a de facto ground. The sense component 125-c may be fired at time 555-a to compare the digit line voltage 530 with the reference voltage 545-a. If the detected digit line voltage 530 is high (eg, digit line voltage 530-c) and is compared to the reference voltage 545-a, then the output of the sense component 125-c and the digit line voltage 530-c are It can rise to the voltage supplied by the voltage source 405-a. Otherwise, if the detected digit line voltage 530 is low (eg, digit line voltage 530-d) and compared to the reference, then the output and digit line voltage of the sense component 125-c is the voltage source 410. Can rise to the voltage supplied by -a. The output of the sense component 125-c can be latched and used to determine the stored state associated with memory cells 105-c.

FIG. 8 shows block diagram 800 of a memory array 100-a that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. The memory array 100-a may include a memory controller 140-a and a memory cell 105-a which may be examples of the memory controller 140 and the memory cell 105 described with reference to FIGS. 1 and 2. The memory controller 140-a may include a bias component 810, a timing component 815, and a digit line (DL) voltage conditioning component 830 to operate the memory array 100-a as described in FIGS. 1-7. can.

The memory controller 140-a includes a word line 110-d (also referred to as an access line 110-d), a digit line 115-d, a sense component 125-d, a plate line 210-c, and a reference circuit 605-a. An example of a memory cell 105-d (a word line 110, a digit line 115, a sense component 125, a plate line 210, a reference circuit 605, and a memory cell described with reference to FIGS. 1, 2, 4, or 6). Can communicate electronically with (obtain). The memory array 100-a may also include a reference component 820, a latch 825, and a control line 835. The components of the memory array 100-a can communicate electronically with each other and perform the functions described in FIGS. 1-7. In some cases, the reference component 820, the sense component 125-a, and the latch 825 can be components of the memory controller 140-a.

The memory controller 140-a may be configured to activate the word line 110-d, the plate line 210-a, or the digit line 115-d by applying a voltage to these various nodes. In some cases, the memory controller 140-a can operate with the bias component 810. For example, the bias component 810 may be configured to apply a voltage for manipulating the memory cells 105-d to read or write to the memory cells 105-d as described above. In some cases, the memory controller 140-a may include the row decoder, column decoder, or both described with reference to FIG. This allows the memory controller 140-a to access one or more memory cells 105. The bias component 810 can also provide a voltage to the reference component 820 to generate a reference signal for the sense component 125-a. Further, the bias component 810 can also provide a voltage for the operation of the sense component 125-a.

In some cases, the memory controller 140-a may operate with the timing component 815. For example, the timing component 815 may control the timing of various wordline selections or plate biases, including the timing of switching and voltage application to perform memory functions such as reads and writes discussed herein. .. In some cases, the timing component 815 may control the operation of the bias component 810. In some cases, the timing component 815 may be used to select memory cells 105-d for read operation and to operate the reference circuit 605-a.

The reference component 820 may include various components that generate a reference signal for the sense component 125-a. Reference component 820 may include circuits specifically configured to generate a reference signal. In some examples, the reference component 820 may be another memory cell 105. In some examples, the reference component 820 may be configured to output a voltage between the two sense voltages, as described with reference to FIG. Alternatively, the reference component 820 may be designed to output a de facto ground. The sense component 125-a can compare the signal from the memory cells 105-d (via the digit line 115-d) with the reference signal from the reference component 820. Upon determining the logical state, the sense component 125-a can then store the output in the latch 825, which can be used according to the operation of the electronic device with the memory device of which the memory array 100-a is a component.

In some cases, the memory controller 140-a may adjust the voltage of the digit lines 115-d via the control line 835. For example, the DL voltage adjustment component 830 may be used to adjust the voltage on the digit lines 115-d so that a ground reference is used. In some cases, the DL voltage adjustment component 830 may be used with the digit line voltage derived from the initial logical state "1" or "0" so that the ground reference is located in the center thereof . For example, the DL voltage adjustment component 830, in collaboration with the bias component 810 and the timing component 815, applies a positive voltage to the plate wire 210-c to determine if the voltage on the digit wire 115-d has reached the threshold. And can be used to apply a negative voltage to the plate wire 210-c after the voltage of the digit wire 115-d has reached the threshold. In one example, the memory controller 140-a can use the control wire 835 to bias the plate wire 210-c.

For example, the bias component 810 may connect the ferroelectric capacitor of memory cells 105-d to a first voltage source (eg, a positive voltage source), a second voltage source (eg, a negative voltage source), or both. .. The timing component 815 and / or the DL voltage adjustment component 830 may be used to determine that the voltage on the digit lines 115-d has reached a threshold in response to the application of a positive voltage. In some cases, determining that the voltage on the digit line 115-d has reached the threshold means determining that a positive voltage has been applied over a predetermined duration, and determining that the voltage on the digit line has reached the threshold voltage. It can be determined at least in part to determine that it has been reached, that the rate of change in voltage on the digit line has reached a threshold, or any combination thereof. The memory controller 140-a can be used to force the sense component 125-a to compare the voltage of the digit line 115-d with the ground reference after a negative voltage has been applied. In some cases, the memory controller 140-a of the sense component 125-a is used to determine the logic value of the ferroelectric memory cell, at least in part, based on a comparison with the ground reference of the digit line voltage. Output is available.

In another embodiment, the DL voltage adjustment component 830 is a bias component in order to apply a first voltage to the plate wire 210-c and a second voltage opposite to the first voltage to the reference circuit 605-a. It can be used in combination with the 810, timing component 815, and reference circuit 605-a. In one embodiment, the memory controller 140-a uses a bias component 810 and a control line 835 to initiate the reference circuit 605-a to bias the plate wires 210-c.

For example, the bias component 810 can be used to connect a first voltage source to a ferroelectric capacitor in a ferroelectric memory cell 105-d. Here, the ferroelectric capacitor is electronically communicating with the digit lines 115-d via the first selection component. The bias component 810 can be used to connect a second voltage source to the reference capacitor of the reference circuit 605-a. Here, the reference capacitor is electronically communicating with the digit line via the second selection component, where the second voltage is the opposite of the first voltage and is at least partially based on the application of the first voltage. Applied. In some cases, the timing component 815 operates the bias component 810 to apply a first voltage and a second voltage at substantially the same time. The bias component 810 is first to activate the first selection component to perform the ferroelectric memory cell read operation and to transfer the charge of the reference capacitor to the digit lines 115-d during the read operation. It can also be used to activate the selection component of 2. The bias component 810 can also be used to bring the digit wire to the de facto ground before connecting the first voltage source to the ferroelectric capacitor or before connecting the second voltage source to the reference capacitor. .. As mentioned above, the sense component 125-a can compare the signal from the memory cells 105-d (through the digit lines 115-d) with the reference signal from the reference component 820. In some cases, the memory controller 140-a is a sense component used to determine the logic value of a ferroelectric memory cell, at least in part, based on a comparison of the voltage of the digit line with a ground reference. An output of 125-a can be used.

FIG. 9 illustrates a system 900 that supports a ground reference scheme for memory cells according to various embodiments of the present disclosure. The system 900 includes a device 905 that may be a printed circuit board or may include a printed circuit board for connecting to or physically supporting various components. The device 905 includes a memory array 100-b which may be an example of the memory array 100 described with reference to FIGS. 1 and 6. The memory array 100-b may be an example of the memory controller 140 described with reference to FIGS. 1 and 6, and the memory cells described with reference to FIGS. 1, 2, 4, 6, and 8. It may include a memory controller 140-b and a memory cell 105-e, which may be examples of 105. The device 905 may also include a processor 910, a BIOS component 915, a peripheral component 920, an input / output control component 925, and a DL voltage conditioning component 940. The DL voltage adjustment component 940 may be an example of the DL voltage adjustment component 830 as described with reference to FIG. The components of the device 905 may electronically communicate with each other via the bus 930.

Processor 910 may be configured to operate through the memory controller 140-b. In some cases, the processor 910 may perform the functions of the memory controller 140 described with reference to FIGS. 1 and 6. In other cases, the memory controller 140-b may be integrated into the processor 910. Processor 910 is a general purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware. It may be a component, or the processor 910 may be a combination of these types of components, the processor 910 being the variety described herein, including support for a ground reference scheme for memory cells. Can perform various kinds of functions. Processor 910 may be configured to execute stored computer readable instructions, for example, to cause device 905 to perform various functions and tasks.

The BIOS component 915 can be a software component that includes a basic input / output system (BIOS) that acts as firmware, which can initialize and operate various hardware components of the system 900. The BIOS component 915 can also manage the flow of data between the processor 910 and various components (eg, peripheral components 920, I / O control components 925, etc.). The BIOS component 915 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component 920 can be any input or output device, or an interface for these devices integrated into device 905. Examples are disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, USB controllers, serial or parallel ports, or peripheral cards such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots. May include slots.

The input / output control component 925 can manage data communication between the processor 910 and the input or output device received via the peripheral component 920, input 935 or output 945. The input / output control component 925 can also manage peripheral devices that are not integrated into the device 905. In some cases, the I / O control component 925 represents a physical coupling or port to an external peripheral.

The input 935 may represent an external signal to the device or device 905 that provides the input to the device 905 or a component of the device 905. It may include a user interface or an interface between other devices. In some cases, the input 935 may be a peripheral device interlocking with the device 905 via the peripheral component 920, or may be managed by the input / output control component 925.

The output 945 may be implemented as an external signal to a device or device 905 configured to receive output from device 905 or any component of device 905. Examples of output devices may include displays, audio speakers, printing devices, other processors, printed circuit boards, and the like. In some cases, the output 945 may be a peripheral device interlocking with the device 905 via the peripheral component 920, or may be managed by the input / output control component 925.

The components of the memory controller 140-b, the device 905, and the memory array 100-b may be built up by circuits designed to perform those functions. This may include various circuit elements configured to perform the functions described herein (eg, conductive wires, transistors, capacitors, coils, resistors, amplifiers, or other active or passive elements). Can include.

FIG. 10 shows a flow chart illustrating method 1000 using a ground reference scheme for memory cells according to various embodiments of the present disclosure. The operation of the method 1000 can be performed by the memory array 100 as described with reference to FIGS. 1-9. For example, the operation of method 1000 may be performed by the memory controller 140 as described with reference to FIGS. 1, 8 and 9. In some examples, the memory controller 140 can execute a set of codes to control the functional elements of the memory array 100 in order to perform the functions described below. Additional or alternative, the memory controller 140 can perform the functions of the mechanisms described below using special purpose hardware.

At block 1005, the method may include applying a positive voltage to the ferroelectric capacitor of the ferroelectric memory cell. Here, the ferroelectric capacitor is in electronic communication with the digit wire. In one example, the operation of block 1005 may be performed or facilitated by the bias component 810, as described with reference to FIG.

At block 1010, the method may include determining that the voltage of the digit line has reached a threshold in response to the application of a positive voltage. In one example, the operation of block 1010 may be performed or facilitated by the timing component 815, as described with reference to FIG. In some cases, determining that the voltage of the digit line has reached the threshold includes determining that the voltage of the digit line has reached the threshold voltage. Additional or alternative, determining that the voltage of the digit line has reached the threshold may include determining that the rate of change in voltage of the digit line has reached the threshold.

At block 1015, the method may include applying a negative voltage to the ferroelectric capacitor after the voltage of the digit line has reached a threshold. In one example, the operation of block 1015 may be performed or facilitated by the bias component 810, as described with reference to FIG. In some cases, the magnitude of the negative voltage applied to the ferroelectric capacitor is at least partially based on the threshold. Determining that the voltage of the digit line has reached the threshold may include determining that a positive voltage has been applied for a predetermined duration. The predetermined duration may be at least partially based on the characteristics of the ferroelectric capacitor, the characteristics of the digit line, the timing associated with reading or writing the ferroelectric memory cell, or at least one of any combination thereof. .. In some cases, the method involves comparing the voltage of the digit line with a ground reference after applying a negative voltage. In some cases, the logic value of a ferroelectric memory cell is determined at least partially based on a comparison with a ground reference of the voltage of the digit line.

FIG. 11 shows a flow chart illustrating method 1100 using a ground reference scheme for memory cells according to various embodiments of the present disclosure. The operation of method 1100 may be performed by the memory array 100 as described with reference to FIGS. 1-9. For example, the operation of method 1100 may be performed by the memory controller 140 as described with reference to FIGS. 1, 8 and 9. In some examples, the memory controller 140 can execute a set of codes to control the functional elements of the memory array 100 in order to perform the functions described below. Additional or alternative, the memory controller 140 can perform the functions of the mechanisms described below using special purpose hardware.

At block 1105, the method may include applying a first voltage to the ferroelectric capacitor of the ferroelectric memory cell. Here, the ferroelectric capacitor is in electronic communication with the digit wire. In one embodiment, as described with reference to FIG. 8, the operation of block 1105 may be performed or facilitated by the bias component 810. In some examples, the method selects a ferroelectric memory cell for readout operation by activating a ferroelectric capacitor and a first selection component that electronically communicates with the digit wire, as well as. It may include activating a second selection component that electronically communicates with the reference capacitor and the digit wire. In some cases, the first selection component and the second selection component are activated before applying the first voltage.

At block 1110, the method may include applying a second voltage to a reference capacitor that electronically communicates with the digit line. Here, the second voltage is the reverse of the first voltage and is applied at least partially based on the application of the first voltage. In one example, the operation of block 1110 may be performed or facilitated by the bias component 810, as described with reference to FIG. In some embodiments, the first voltage and the second voltage are applied substantially simultaneously. In some cases, the first selection component and the second selection component are activated before applying the first voltage and / or the second voltage. In some examples, the method may include putting the digit wire in effect ground before applying a first or second voltage. In some examples, the method involves comparing the voltage of the digit line with the ground reference after a second voltage has been applied to the reference capacitor. Determining the logic value of a ferroelectric memory cell can be at least partially based on a comparison with a ground reference of the voltage of the digit line.

Therefore, methods 1000 and 1100 may be provided for use with the ground reference scheme. It should be noted that Method 1000 and Method 1100 describe possible implementations, and the actions and steps may be rearranged or modified to allow other implementations. In some embodiments, mechanisms from two or more methods 1000 and 1100 may be combined.

The device is described. In some examples, the device is a means for applying a positive voltage to a ferroelectric capacitor in a ferroelectric memory cell, wherein the ferroelectric capacitor is electronically communicating with a digit wire. , A means for determining that the voltage of the digit line has reached the threshold in response to the application of the positive voltage, and the strong after the voltage of the digit line has reached the threshold. It may include means for applying a negative voltage to a dielectric capacitor.

In some embodiments, the device may include means for comparing the voltage of the digit line with a ground reference after the negative voltage has been applied. In some embodiments, the device is a means for determining the logic value of the ferroelectric memory cell, at least partially based on the means for comparing the voltage of the digit line with the ground reference. May include. In some examples, the magnitude of the negative voltage applied to the ferroelectric capacitor is at least partially based on the threshold. In some examples, the means for determining that the voltage of the digit line has reached the threshold includes means for determining that the positive voltage has been applied for a predetermined duration. ..

In some embodiments, the predetermined duration is the characteristic of the ferroelectric capacitor, the characteristic of the digit line, the timing associated with reading or writing to the ferroelectric memory cell, or any combination thereof. At least partially based on at least one of. In some examples, the means for determining that the voltage of the digit line has reached the threshold includes means for determining that the voltage of the digit line has reached the threshold voltage. In some embodiments, the means for determining that the voltage of the digit line has reached the threshold is a means for determining that the rate of change of the voltage of the digit line has reached the threshold. include.

The device is described. In some examples, the device is a means for applying a first voltage to a ferroelectric capacitor in a ferroelectric memory cell, the ferroelectric capacitor electronically communicating with a digit wire. Means may include means and means for applying a second voltage to the reference capacitor that is electronically communicating with the digit wire. The second voltage is the reverse of the first voltage and is applied at least partially based on the means for applying the first voltage.

In some examples, the device may include means for selecting said ferroelectric memory cells for read operation. The means for selecting are means for activating the ferroelectric capacitor and the first selection component electronically communicating with the digit wire, as well as electronically with the reference capacitor and the digit wire. Includes means for activating a second selection component communicating with. In some examples, the device includes means for comparing the voltage of the digit line with the ground reference after the second voltage has been applied to the reference capacitor.

In some examples, the device provides means for determining the logic value of the ferroelectric memory cell, at least partially based on the means for comparing the voltage of the digit line with the ground reference. Can include. In some embodiments, the first voltage and the second voltage are applied at substantially the same time. In some embodiments, the device may include means for effectively grounding the digit line prior to applying the first or second voltage.

The device is described. In some examples, the device is a ferroelectric memory cell containing a ferroelectric capacitor that is electronically communicating with a digit wire, a means for connecting a positive voltage source to the ferroelectric capacitor, and. It may include means for connecting a negative voltage source to the ferroelectric capacitor after the voltage of the digit line has reached a threshold.

In some examples, the device may include means for comparing the voltage of the digit line with a ground reference after a negative voltage has been applied to the ferroelectric capacitor. In some examples, the device may include means for determining the logic value of the ferroelectric memory cell, at least in part, based on a comparison of the voltage of the digit line with the ground reference. In some embodiments, the device may include means for determining that the voltage of the digit line has reached the threshold in response to a positive voltage applied to the ferroelectric capacitor.

In some examples, the device is a means for determining that the voltage of the positive voltage source is applied to the ferroelectric capacitor for a predetermined duration, and for the predetermined duration. , The means for determining that the voltage of the digit line has reached the threshold may be included, at least in part, based on the means for determining that the voltage of the positive voltage source is applied. In some examples, the device may include means for determining that the rate of change in the voltage of the digit line has reached the threshold.

The device is described. In some examples, the device is an electron with the digit wire through a second selection component, a hard dielectric memory cell containing a dielectric capacitor that is electronically communicating with the digit wire and the first selection component. Can include a reference capacitor that is communicating with the user, a means for connecting a first voltage source to the strong dielectric capacitor, and a means for connecting a second voltage source to the reference capacitor. The output of the second voltage source is the reverse of the output of the first voltage source.

In some examples, the device is a means for activating the first selection component to perform a readout operation of the ferroelectric memory cell, and a charge of the reference capacitor during the readout operation. In order to move to the digit line, the means for activating the second selection component may be included. In some examples, the device may include means for comparing the voltage of the digit line with the ground reference after the voltage of the second voltage source has been applied to the reference capacitor. In some examples, the device may include means for determining the logic value of the ferroelectric memory cell, at least in part, based on a comparison of the voltage of the digit line with the ground reference. In some examples, the device effectively connects the digit wire before connecting the first voltage source to the ferroelectric capacitor or connecting the second voltage source to the reference capacitor. It may include means to make it a ground.

The statements made herein provide examples and are not intended to limit the scope, applicability, or examples described in the claims. The functions and arrangement of the above-mentioned components may be changed without departing from the scope of the present disclosure. The various examples may omit, replace, or add various procedures or components as appropriate. In addition, the features described for one example may be combined in another example.

What has been described herein in association with the accompanying drawings is an exemplary configuration and does not represent all examples that are feasible or within the scope of the claims. The terms "example" and "exemplary" used herein mean "to serve as an example, an example, an embodiment, or an explanation" and are more advantageous than "preferable" and "other examples". It doesn't mean "na". The detailed description includes detailed specific details to provide an understanding of the techniques described herein. However, the techniques of the present disclosure may be practiced without those detailed specific details. In one example, a well-known structure and device is shown in the form of a block diagram to avoid obscuring the concept of the described example.

In the accompanying drawings, similar components or structures may have the same reference numerals. Further, various components of the same type can be distinguished by a reference sign followed by a dash and a second sign that distinguishes between similar components. Where the first reference code is used herein, this description may apply to any of the similar components having the same first reference code, regardless of the second reference code.

The information and signals described herein may be represented using any of a variety of different techniques and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the description so far may be voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or them. Can be represented by any combination of. One figure may represent multiple signals as one signal, but those skilled in the art may represent a bus of signals, where the buses have various bit widths. Will understand.

As described herein, the term "virtual ground" refers to a node in an electronic circuit that holds a voltage of approximately 0 volts (0V) but is not directly connected to ground. .. Therefore, the virtual ground voltage can fluctuate temporarily and can return to almost 0V in a stable state. The de facto ground can be implemented using various electronic circuit elements such as a voltage divider consisting of an operable amplifier and a resistor. "Virtual grounding" or "virtually grounded" means connected to near 0V.

The term "electronic communication" refers to the relationships between components that support the flow of electrons between them. It may include direct connections between components, or it may include components in between. Components that are communicating electronically can dynamically exchange electrons or signals (eg, in a voltage-applied circuit) or electrons (eg, in a non-voltage-applied circuit). Alternatively, the signals may not be dynamically exchanged, but may be configured or be capable of exchanging electrons or signals in response to a voltage applied to the circuit. As an example, two components physically connected via a switch (eg, a transistor) communicate electronically regardless of the state of the switch (ie, open or closed). The term "isolated" refers to the relationship between components that currently do not allow electrons to flow. For example, two components physically connected by a switch can be separated from each other when the switch is open.

The devices discussed herein, including the memory array 100, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon on insulator (SOI) substrate such as silicon on glass (SOG) or silicon on sapphire (SOP), or a semiconductor on another substrate. It may be an epixial layer of material. The conductivity of the substrate or its subregions can be controlled by doping with a variety of chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be done by ion implantation or any other doping means during the initial formation or growth of the substrate.

The transistors discussed herein can represent field effect transistors (FETs) and include a three-terminal device that includes a source, drain and gate. The terminals may be connected to other electronic devices through a conductive material (eg, metal). Sources and drains may be conductive and may include highly concentrated (eg, modified) semiconductor regions. Sources and drains can be separated from low concentration doped semiconductor regions or channels. If the channel is n-type (ie, the main carrier is an electron), the FET may be referred to as an n-type FET. If the channel is p-type (ie, the main carrier is a hole), the FET may be referred to as a p-type FET. The channel can be covered with an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to each of the n-type and p-type FETs can make the channel conductive. The transistor is "started (on)" or "activated" when a voltage equal to or greater than the threshold voltage of the transistor is applied to the transistor gate. The transistor is "off" or "inactivated" when a voltage below the transistor threshold voltage is applied to the transistor gate.

The various exemplary blocks, components, and modules described in connection with the disclosure herein are general purpose processors, DSPs, ASICs, designed to perform the functions described herein. It can be implemented or implemented using FPGAs or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, or any combination thereof. The general purpose processor may be a microprocessor, but instead, the processor may be any conventional processor, controller, microcontroller, or state machine. Processors are also implemented as a combination of computing devices (eg, a combination of DSP and microprocessor, multiple microprocessors, one or more microprocessors working together with a DSP core, or any other similar configuration). May be done.

The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. When implemented in software executed by a processor, the function may be stored or transmitted as one or more instructions or codes on a computer readable medium. Other examples and implementations are also within the scope of this disclosure and the accompanying claims. For example, due to the nature of the software, the functions described above can be performed using software, hardware, firmware, hard wiring, or any combination thereof performed by the processor. Mechanisms that implement the function may also be physically located at various locations, including the distribution of parts of the function so that they are performed at different physical locations. Also, as used herein, including the claims, a list of items (eg, "at least one of ..." or "one or more of ...". The "or" used in a list of items that begins with such a phrase) indicates a comprehensive list. For example, the list of at least one of A, B, or C means A, or B, or C, or AB, or AC, or BC, or ABC (ie, A and B and C).

Computer-readable media include both non-temporary computer storage media and communication media, including some media that facilitates the transfer of computer programs from one location to another. The non-temporary storage medium may be any available medium accessible by a general purpose or purpose-built computer. As an example, non-temporary computer readable media include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other. A magnetic storage device, or a general-purpose or specific-purpose computer, or a general-purpose or specific-purpose computer that can be used to carry or store a desired program code means in the form of instructions or data structures. It may include, but is not limited to, other non-temporary media accessible by the processor.

Also, any connection is properly referred to as a computer readable medium. For example, software can use coaxial cables, fiber optic cables, twist pairs, digital subscriber lines (DSL), or wireless technologies such as infrared, high frequency, and microwave from websites, servers, or other remote sources. When transmitted, coaxial cables, fiber optic cables, twisted pairs, digital subscriber lines (DSL), or wireless technologies such as infrared, high frequency, microwave, etc. are included in the definition of the medium. The discs (disks and discs) used herein include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy discs, and Blu-ray discs. A disc usually reproduces data magnetically, whereas a disc reproduces data optically by a laser. Their combination may also be included within the scope of computer readable media.

What is stated herein is provided to allow one of ordinary skill in the art to carry out or use the present disclosure. Various modifications to the present disclosure may be readily made to those of skill in the art, and the general principles defined herein may also be applied to other variations without departing from the scope of the present disclosure. .. Accordingly, this disclosure is not limited to the examples and designs described herein, and the broadest scope should be acknowledged in this disclosure that is consistent with the principles and novel features described herein.

Claims (14)

A method of operating a ferroelectric memory cell by a memory controller during a read operation.
By applying a positive voltage to the plate wire, the positive voltage is applied to the ferroelectric capacitor of the ferroelectric memory cell, and the ferroelectric capacitor electronically communicates with the digit wire. That and that
It is determined that the rate of change in the voltage of the digit line caused by the positive voltage applied to the ferroelectric capacitor has reached the threshold value.
Applying the negative voltage to the ferroelectric capacitor by applying a negative voltage to the plate wire after the rate of change of the voltage of the digit wire reaches the threshold value.
After the negative voltage is applied to the ferroelectric capacitor, the voltage of the digit line is compared to the ground reference.
How to include. The method of claim 1, further comprising determining the logic value of the ferroelectric memory cell based on the comparison of the voltage of the digit line with the ground reference. The method according to claim 1, wherein the magnitude of the negative voltage applied to the ferroelectric capacitor is based on the threshold value. The first aspect of the present invention further comprises determining that the voltage of the digit line has reached a second threshold based on the determination that the positive voltage has been applied for a predetermined duration. the method of. The predetermined duration may be at least one of the characteristics of the ferroelectric capacitor, the characteristics of the digit line, the timing associated with reading or writing to the ferroelectric memory cell, or any combination thereof. The method according to claim 4. The method according to claim 1, further comprising determining that the voltage of the digit line has reached a second threshold based on determining that the voltage of the digit line has reached the threshold voltage. A ferroelectric memory cell containing a ferroelectric capacitor that electronically communicates with the digit wire and is connected to the plate wire.
A controller that electronically communicates with the ferroelectric memory cell,
An electronic memory device that includes
The controller
A positive voltage source is connected to the ferroelectric capacitor via the plate wire.
It is determined that the rate of change in the voltage of the digit line caused by the connection of the positive voltage source to the ferroelectric capacitor has reached the threshold value.
Based on the determination that the rate of change in the voltage of the digit wire has reached the threshold, a negative voltage source is connected to the ferroelectric capacitor via the plate wire and
After the negative voltage of the negative voltage source is applied to the ferroelectric capacitor, the voltage of the digit line is compared to the ground reference.
An electronic memory device that can operate like this. 7. The electronic memory of claim 7 , wherein the controller is capable of operating to determine the logic value of the ferroelectric memory cell based on the comparison of the voltage of the digit line with the ground reference. Device. The controller can operate to determine that the voltage of the digit line has reached a second threshold in response to the positive voltage of the positive voltage source being applied to the ferroelectric capacitor. The electronic memory device according to claim 7 . The controller
It is determined that the voltage of the positive voltage source is applied to the ferroelectric capacitor for a predetermined duration.
Based on the determination that the voltage of the positive voltage source is applied during the predetermined duration, it is determined that the voltage of the digit line has reached the second threshold value.
The electronic memory device according to claim 9 , which is capable of operating as described above. A ferroelectric memory cell containing a ferroelectric capacitor that electronically communicates with the digit wire and is connected to the plate wire.
A means of connecting a positive voltage source to the ferroelectric capacitor via the plate wire, and
A means for determining that the rate of change in the voltage of the digit line generated in response to the positive voltage of the positive voltage source being applied to the ferroelectric capacitor has reached a threshold value.
A means of connecting a negative voltage source to the ferroelectric capacitor via the plate wire after the rate of change in the voltage of the digit wire reaches the threshold.
A means of comparing the voltage of the digit line with a ground reference after the negative voltage of the negative voltage source has been applied to the ferroelectric capacitor.
Equipment including. 11. The apparatus of claim 11 , further comprising means for determining the logic value of the ferroelectric memory cell based on the comparison of the voltage of the digit line with the ground reference. 11. The claim 11 further comprises means for determining that the voltage of the digit line has reached a second threshold in response to the positive voltage of the positive voltage source being applied to the ferroelectric capacitor. The device described in. A means for determining that the voltage of the positive voltage source has been applied to the ferroelectric capacitor for a predetermined duration, and
A means for determining that the voltage of the digit line has reached the second threshold value based on the means for determining that the voltage of the positive voltage source has been applied for the predetermined duration.
13. The apparatus of claim 13 .

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