JP6989632B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

There is a semiconductor package having a metal-plated wiring on the surface of a semiconductor chip or a via contact provided in a sealing resin of the semiconductor chip as a fan-out wiring. In such a fan-out type semiconductor package, a metal layer may be provided as a back electrode of the semiconductor chip. Conventionally, via contacts and wiring have been provided on both the front surface and the back surface of a semiconductor package in order to connect the wiring to the pad on the front surface of the semiconductor chip and the metal layer on the back surface thereof.

However, in order to provide via contacts and wiring on both the front surface and the back surface of the semiconductor package, the manufacturing process becomes long and the materials required for the via contacts and wiring are also required.

Japanese Unexamined Patent Publication No. 2016-025144

Provided is a semiconductor device capable of providing via contacts and wiring on the electrodes on the front surface and the back surface of a semiconductor chip provided in a resin easily and at low cost.

The semiconductor device according to the present embodiment includes a first metal layer having a first surface and a second surface opposite to the first surface. The first semiconductor chip is provided on the first surface of the first metal layer. The first via contact is provided on the first surface of the first metal layer. The second via contact is provided on the first semiconductor chip. The resin layer seals the first metal layer, the first semiconductor chip, the first via contact and the second via contact. The resin layer has a third surface, and the first end portion of the first via contact and the second end portion of the second via contact are exposed on the third surface. The first wiring is provided on the third surface of the resin layer and electrically connects the first end portion of the first via contact and the second end portion of the second via contact. The second wiring is provided on the third surface of the resin layer.

The cross-sectional view which shows the structural example of the semiconductor device 1 by 1st Embodiment. The cross-sectional view which shows an example of the manufacturing method of the semiconductor device 1 by 1st Embodiment. FIG. 2 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 3 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 4 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 5 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 6 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 7 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. 7. FIG. 8 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 9 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 10 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. The cross-sectional view which shows the structural example of the semiconductor device 2 by 2nd Embodiment. FIG. 3 is a cross-sectional view showing a configuration example of the semiconductor device 3 according to the third embodiment. The cross-sectional view which shows an example of the manufacturing method of the semiconductor device by 4th Embodiment. FIG. 14 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 15 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 16 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1. FIG. 17 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1 following FIG. FIG. 18 is a cross-sectional view showing an example of a manufacturing method of the semiconductor device 1.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. The present embodiment is not limited to the present invention.

(First Embodiment)
FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a semiconductor chip 10, a metal layer 20, a resin layer 30, pads 31, 32, package wirings 41, 42, via contacts 51 to 53, solder resists 61, 62, and terminals 71. It is equipped with 72.

The semiconductor chip 10 as the first semiconductor chip has a first surface F1 provided with the semiconductor element 11 and a second surface F2 on the opposite side of the first surface F1. As a semiconductor element, the semiconductor chip 10 is a power semiconductor such as an IGBT (Insulated Gate Bipolar Transistor) or a HEMT (High Electron Mobility Transistor) capable of passing a large current between the first surface F1 and the second surface F2. It may be an element.

The metal layer 20 as the first metal layer has a third surface F3 on which the semiconductor chip 10 is mounted and a fourth surface F4 on the opposite side of the third surface F3. The third surface F3 faces the second surface F2 of the semiconductor chip 10, and is adhered to the semiconductor chip 10 by the conductive material 13. The third surface F3 has a larger outer edge than the outer edge of the second surface F2 of the semiconductor chip 10. Therefore, the metal layer 20 is provided so as to cover the entire surface of the second surface F2 of the semiconductor chip 10. The metal layer 20 may be a metal material containing, for example, copper, iron, nickel, stainless steel, or the like. Further, a semiconductor such as silicon, glass, or an organic substrate may be used. In that case, it is necessary to provide a metal film or metal wiring on the surface in order to make it conductive. The conductive material 13 may be, for example, a conductive material such as solder, silver paste, or silver sintered paste. The resin layer 30 is provided around the semiconductor chip 10, the metal layer 20, and the via contacts 51 to 53, and has a fifth surface F5 on the semiconductor chip 10 side and a sixth surface F6 on the metal layer 20 side. .. The resin layer 30 seals the semiconductor chip 10, the metal layer 20, and the via contacts 51 to 53, and protects them from the outside of the resin layer 30.

The pads 31 and 32 are provided on the first surface F1 of the semiconductor chip 10 via the interlayer insulating film ILD, and are electrically connected to the semiconductor element 11 at the opening of the interlayer insulating film ILD. The pads 31 and 32 function as drawer wiring (fan-out wiring) drawn from the semiconductor element 11. The pads 31 and 32 are electrically connected to the semiconductor element, and may be plated low resistance metals such as copper, aluminum, and nickel, for example.

The via contact 51 as the first via contact is provided in the resin layer 30 and is provided on the third surface F3 of the metal layer 20. The via contacts 52 and 53 as the second via contacts are provided in the resin layer 30 and are provided on the pads 31 and 32, respectively. The via contact 51 is drawn out from the third surface F3 of the metal layer 20 to the fifth surface F5 side of the resin layer 30, and electrically connects the metal layer 20 to the wiring 41 provided on the fifth surface F5. .. The via contact 52 is drawn out from the pad 31 to the fifth surface F5 side of the resin layer 30, and electrically connects the pad 31 to the wiring 41. The via contact 53 is drawn out from the pad 32 to the fifth surface F5 side of the resin layer 30, and electrically connects the pad 32 to the wiring 42.

The wiring 41 as the first wiring is provided on the fifth surface F5 of the resin layer 30, and is electrically connected to the pad 31 and the metal layer 20 via the via contacts 51 and 52. The wiring 42 as the second wiring is provided on the fifth surface F5 of the resin layer 30, and is electrically connected to the pad 32 via the via contact 53. For the wirings 41 and 42, for example, low resistance metals such as copper and aluminum are used. As described above, the wirings 41 and 42 are provided on one surface of the resin layer 30 (for example, the fifth surface F5).

The via contact 51 as the first via contact is provided in the resin layer 30 and electrically connects between the third surface F3 of the metal layer 20 and the wiring 41. The via contact 52 is provided in the resin layer 30 and electrically connects between the pad 31 connected to the semiconductor element and the wiring 41. The via contact 53 as the second via contact is provided in the resin layer 30 and electrically connects between the pad 32 connected to the semiconductor element and the wiring 42.

The solder resist 61 is provided on the upper surface of the resin layer 30, and partially covers the wirings 41 and 42. The solder resist 62 is provided on the bottom surface of the resin layer 30 and covers the back surface of the metal layer 20. The solder resist 62 is used to suppress the adhesion of the material (for example, solder) of the terminals 71 and 72.

The terminals 71 and 72 are provided on the fifth surface F5 side of the resin layer 30, and are provided on the wirings 41 and 42 on which the solder resist 61 is not provided. Terminals 71 and 72 are, for example, solder bumps. The terminal 71 is electrically connected to the back surface of the semiconductor chip 10 via the wiring 41, the via contact 51, and the metal layer 20, and is electrically connected to the semiconductor element 11 via the wiring 41, the via contact 52, and the pad 31. It is connected to the. The wiring 41 electrically connected to the via contact 51 and the wiring 41 electrically connected to the via contact 52 may be electrically independent and connected to an external terminal.

The semiconductor device 1 according to the present embodiment includes a metal layer 20 larger than the semiconductor chip 10 on the second surface F2 of the semiconductor chip 10. As a result, the semiconductor device 1 can provide the via contact 51 on the third surface F3 of the metal layer 20, and the metal layer 20 on the second surface F2 side of the semiconductor chip 10 can be provided on the first surface F1 of the semiconductor chip 10. It can be electrically connected to the wiring 41 on the side. Therefore, the semiconductor device 1 is not only the wiring 42 electrically connected to the semiconductor element on the first surface F1 side of the semiconductor chip 10, but also the wiring electrically connected to the metal layer 20 on the second surface F2 side. 41 can also be provided on the first surface F1. That is, the wirings 41 and 42 are drawn out to one side (F5) side of the resin layer 30 and not to the other side (F6). As described above, by using the one-sided wiring, the via contacts 51 to 53 and the wirings 41 and 42 can be formed by processing from the fifth surface F5 side of the resin layer 30. That is, in the semiconductor device 1 according to the present embodiment, it is not necessary to process both surfaces of the resin layer 30 in order to form via contacts and wiring.

Double-sided processing prolongs the manufacturing process if it is processed one side at a time. Alternatively, if both sides are to be processed at the same time, a special device is required. Therefore, double-sided processing complicates the manufacturing process and increases the manufacturing cost.

On the other hand, according to the present embodiment, it is sufficient to process the via contacts 51 to 53 and the wirings 41 and 42 from one side of the resin layer 30. Therefore, in the present embodiment, via contacts 51 to 53 and wirings 41 and 42 are easily and inexpensively formed on the electrodes of the first surface F1 and the second surface F2 of the semiconductor chip 10 provided in the resin layer 30. be able to.

Further, in the present embodiment, the solder resist 62 is provided on the fourth surface F4 of the metal layer 20, but the metal layer 20 is not provided. As a result, the metal layer 20 can function not only as a back electrode of the semiconductor chip 10 but also as a heat sink of the semiconductor chip 10. When the metal layer 20 is used as a heat sink, the solder resist 62 may not be provided on at least a part of the fourth surface F4 of the metal layer 20.

Next, a method of manufacturing the semiconductor device 1 according to the present embodiment will be described.

2A to 11 are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment. First, as shown in FIG. 2A, the semiconductor element 11 and the pads 31 and 32 are formed on the semiconductor wafer 15 in the wafer process process. The semiconductor wafer 15 is, for example, a semiconductor substrate such as a silicon substrate.

The pads 31 and 32 are formed by using copper plating or the like on the electrodes (not shown) of the semiconductor element 11 or the like. As a result, the pads 31 and 32 are plated on the electrodes of the semiconductor element 11 and / or on the interlayer insulating film ILD of the semiconductor element 11.

Next, as shown in FIG. 2B, the back surface of the semiconductor wafer 15 is polished using a CMP (Chemical Mechanical Polishing) or a grinding method. As a result, the semiconductor wafer 15 is thinned to, for example, about 20 μm to about 200 μm.

Next, as shown in FIG. 2C, a metal thin film 17 is formed on the back surface of the semiconductor wafer 15 by using a sputtering method or a vapor deposition method. The metal thin film 17 improves the wettability of the die attach material and enables the semiconductor chip 10 to be satisfactorily adhered to the lead frame (metal layer 20) 25 with the die attach material. The metal thin film 17 may be, for example, a laminated film of Ti, Ni and Ag, a laminated film of Cr, Ni and Ag, a laminated film of Ti, Ni and Au, or the like. The film thickness of the metal thin film 17 is considerably thinner than the film thickness of the metal film 20 (for example, 80 μm or more), and is, for example, about 2 μm or less. Therefore, the metal thin film 17 is thin enough not to adversely affect the next dicing step. If the wettability of the fitting material is good on the back surface of the semiconductor chip 10, it is not necessary to form the metal thin film 17 on the back surface of the semiconductor chip 10. As a result, burrs and peeling of the metal thin film 17 do not occur in the dicing step, and the productivity is further improved.

Next, as shown in FIG. 3, the semiconductor wafer 15 is mounted on the dicing tape, and the semiconductor wafer 15 is diced by the dicing blade 102. By this dicing step, the semiconductor wafer 15 is separated into a plurality of semiconductor chips 10. At this stage, the semiconductor chip 10 has a semiconductor element 11, an interlayer insulating film ILD, and pads 31 and 32 on the first surface F1.

Next, as shown in FIGS. 4 (A) and 4 (B), the semiconductor chip 10 is mounted on the lead frame 25 by using the fitting material 26. FIG. 4A shows a plane of the lead frame 25 and the semiconductor chip 10, and FIG. 4B shows a cross section of the lead frame 25 and the semiconductor chip 10. The lead frame 25 is a low resistance metal such as copper, and its thickness is, for example, about 80 μm. The die-touch material 26 may be, for example, solder, silver paste, silver sintered paste, conductive DAF (Die Attachment Film), or the like, and may be in the form of a liquid or a film.

Next, as shown in FIG. 5, the lead frame 25 on which the semiconductor chip 10 is mounted is mounted on the dicing tape 103, and the lead frame 25 is diced by the dicing blade 104. As a result, the lead frame 25 is cut for each semiconductor chip 10 and functions as a metal layer 20. The metal layer 20 has a third surface F3 on which the semiconductor chip 10 is mounted and a fourth surface F4 on the opposite side thereof. Further, the third surface F3 of the metal layer 20 has a larger outer edge than the outer edge of the second surface F2 of the semiconductor chip 10.

Hereinafter, the structure composed of the semiconductor chip 10 and the metal layer 20 will be referred to as a structure 130 for convenience.

Next, as shown in FIG. 6, the structure 130 of the semiconductor chip 10 and the metal layer 20 is bonded onto the support portion 110 by using the adhesive layer 120. In the present embodiment, the plurality of structures 130 are bonded onto the support portion 110 so that the fourth surface F4 of the metal layer 20 faces the support portion 110. That is, the semiconductor chip 10 is mounted with the element forming surface (F1) facing upward (face-up mounting method). The support portion 110 may be, for example, a silicon plate, a metal plate (for example, copper, iron, stainless steel, etc.), a glass (SiO ₂ ) plate, or the like. The thickness of the support portion 110 may be, for example, about 0.1 mm to about 2 mm. The adhesive layer 120 may be, for example, an organic adhesive, a metal adhesive, a mixture thereof, or the like. In the face-up type mounting method, the resin layer 30 can be formed at one time as compared with the face-down type mounting method described later. Therefore, the face-up mounting method can manufacture the semiconductor device 1 at a relatively low cost.

Next, as shown in FIG. 7, a resin layer 30 is formed around the plurality of structures 130 on the support portion 110, and the resin layers 30 of the plurality of structures 130 are sealed. As a result, the resin layer 30 having the fifth surface F5 on the semiconductor chip 10 side and the sixth surface F6 on the metal layer 20 side is formed. The resin layer 30 may seal a plurality of structures 130, for example, by laminating or vacuum pressing an organic film. At this time, an organic film excluding only the portion of the structure 130 may be used. In this case, after the formation of the organic film, another thin organic film is coated on the structure 130. The resin layer 30 may be formed by applying a liquid resin material instead of the organic film.

Next, as shown in FIG. 8, the support portion 110 is peeled off from the structure 130 and the resin layer 30. The peeling of the support portion 110 is performed by, for example, heating, light irradiation, immersion in a solvent, mechanical peeling, or the like. The peeling of the support portion 110 may be performed after forming the wirings 41 and 42 described later.

Next, as shown in FIG. 9, via contacts 51 to 53 are formed in the resin layer 30. The via contact 51 is formed on the third surface F3 of the metal layer 20, and the via contacts 52 and 53 are formed on the first surface F1 of the semiconductor chip 10. At this time, all the via contacts 51 to 53 are formed from the fifth surface F5 side of the resin layer 30. For example, via holes are formed from the fifth surface F5 of the resin layer 30 to the metal layer 20 and the pads 31 and 32. Via holes are formed, for example, using laser via processing. Alternatively, via holes may be formed using, for example, lithography and etching techniques. After cleaning the via hole, metal is embedded in the via hole from the fifth surface F5 of the resin layer 30. For example, the metal is formed in the via hole using electroless copper plating. As a result, the via contacts 51 to 53 can all be formed from one side of the resin layer 30. Since the metal layer 20 is larger than the semiconductor chip 10, the via contact 51 can come into contact with the third surface F3 of the metal layer 20 from the fifth surface F5 side of the resin layer 30.

Next, the wirings 41 and 42 are formed on the fifth surface F5 of the resin layer 30. At this time, the wiring 41 is formed on the fifth surface F5 of the resin layer 30 and the via contacts 51 and 52. The wiring 42 is formed on the fifth surface F5 of the resin layer 30 and the via contact 53.

Next, as shown in FIG. 10, solder resists 61 and 62 are formed on the fifth surface F5 and the sixth surface F6 of the resin layer 30. Next, the solder resist 61 on the fifth surface F5 is patterned using the lithography technique. As a result, a part of the wirings 41 and 42 is exposed.

Next, as shown in FIG. 11, dicing is performed for each structure 130. As a result, the semiconductor package containing each semiconductor chip 10 is separated.

After that, the terminals 71 and 72 are formed on the wirings 41 and 42, respectively. For the terminals 71 and 72, for example, solder or the like is used. As a result, the semiconductor device 1 shown in FIG. 1 is completed. When the metal layer 20 is used as a heat sink, the solder resist 62 on the fourth surface F4 of the metal layer 20 may be removed after the terminals 71 and 72 are formed.

According to the present embodiment, the via contacts 51 to 53, the wirings 41 and 42, and the terminals 71 and 72 are formed on one side of the resin layer 30. Therefore, the semiconductor device 1 according to the present embodiment can be easily and inexpensively formed.

(Second Embodiment)
FIG. 12 is a cross-sectional view showing a configuration example of the semiconductor device 2 according to the second embodiment. The second embodiment is different from the first embodiment in that the terminals 71 to 73 are provided on the sixth surface F6 side of the resin layer 30.

The configurations of the metal layers 20 and 21, the arrangement of the via contacts 51 to 54, the layout of the wirings 41 and 42, the arrangement of the terminals 71 to 73, and the like can be arbitrarily changed. For example, in the second embodiment, the metal layers 20 and 21 are separated into two. A semiconductor chip 10 is mounted on the third surface F3 of the metal layer 20, and a via contact 51 is provided on the surface F13 of the metal layer 21. The via contact 51 is connected to the wiring 41. The wiring 41 may be connected to another pad (not shown) of the semiconductor chip 10.

The third surface F3 of the metal layer 20 has a larger outer edge than the outer edge of the second surface F2 of the semiconductor chip 10, similar to that of the first embodiment. Therefore, the via contact 54 can be provided on the third surface F3 of the metal layer 20 and connected to the wiring 42. The wiring 42 is electrically connected to the pads 31 and 32 via the via contacts 52 and 53.

The terminal 71 is provided on the surface F14 of the metal layer 21. The terminals 71 and 73 are provided on the fourth surface F4 of the metal layer 20. That is, the terminals 71 to 73 are provided on the sixth surface F6 side of the resin layer 30. Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment.

According to the second embodiment, the terminals 71 to 73 are provided on the sixth surface F6 of the resin layer 30, but the via contacts 51 to 54 and the wirings 41 and 42 are provided on the fifth surface F5 of the resin layer 30. Has been done. Therefore, the wirings 41 and 42 are drawn out to one side (F5) side of the resin layer 30 and not to the other side (F6). As described above, by using one-sided wiring, the via contacts 51 to 54 and the wirings 41 and 42 can be formed by processing from the fifth surface F5 side of the resin layer 30. Thereby, the second embodiment can obtain the same effect as the first embodiment. Since the electrodes 71 and 72 are formed after the semiconductor packages are separated as described with reference to FIG. 11, there is no problem even if the electrodes 71 and 72 are provided on the sixth surface F6 of the resin layer 30.

In the second embodiment, a part of the wirings 41 and 42 may be exposed. As a result, another semiconductor device (not shown) may be laminated on the semiconductor device 2 and the electrodes of the other semiconductor device may be connected to the wirings 41 and 42. As described above, the semiconductor device 2 may have a three-dimensional laminated structure.

The manufacturing method of the second embodiment can be easily understood by referring to the manufacturing method of the first embodiment, and detailed description thereof will be omitted here.

(Third Embodiment)
FIG. 13 is a cross-sectional view showing a configuration example of the semiconductor device 3 according to the third embodiment. The semiconductor device 3 is a semiconductor module in which a plurality of semiconductor chips 10 and 310 are incorporated in one semiconductor package.

The configuration of the semiconductor device on the semiconductor chip 10 side as the first semiconductor chip may be the same as the configuration of the semiconductor device 1 shown in FIG. Therefore, the configuration of the semiconductor device on the semiconductor chip 310 side as the second semiconductor chip will be described.

The semiconductor chip 310 as the second semiconductor chip has a seventh surface F7 provided with the semiconductor element 311 and an eighth surface F8 on the opposite side of the seventh surface F7. The thickness of the semiconductor chip 310 is different from the thickness of the semiconductor chip 10. The semiconductor element 311 provided on the seventh surface F7 of the semiconductor chip 310 may be the same as or different from the semiconductor element 11 on the semiconductor chip 10.

The metal layer 320 as the second metal layer has a ninth surface F9 on which the semiconductor chip 310 is mounted and a tenth surface F10 on the opposite side of the ninth surface F9. The ninth surface F9 faces the eighth surface F8 of the semiconductor chip 310 and is adhered to by the conductive material 313. The ninth surface F9 has a larger outer edge than the outer edge of the eighth surface F8 of the semiconductor chip 310. Therefore, the metal layer 320 is provided so as to cover the entire surface of the eighth surface F8 of the semiconductor chip 310. The material of the metal layer 320 may be the same as the material of the metal layer 20. The material of the conductive material 313 may be the same as the material of the conductive material 13.

Further, the metal layer 320 is thinner than the thickness of the metal layer 20. The sum of the thickness of the semiconductor chip 10 and the thickness of the metal layer 20 is substantially equal to the sum of the thickness of the semiconductor chip 310 and the thickness of the metal layer 320. As a result, the heights of the pads 31, 32, 331, and 332 can be made substantially equal, and the depths of the via contacts 52, 53, 352, and 353 can be made substantially equal.

The metal layer 320 can function not only as a back electrode of the semiconductor chip 310 but also as a heat sink of the semiconductor chip 310. When the metal layer 320 is used as a heat sink, the solder resist 62 may not be provided on at least a part of the tenth surface F10 of the metal layer 320.

The pads 331 and 332 are provided on the seventh surface F7 of the semiconductor chip 310 via the interlayer insulating film ILD, and are electrically connected to the semiconductor element 311. The pads 331 and 332 function as drawer wiring (fan-out wiring) drawn from the semiconductor element 311. The material of the pads 331 and 332 may be the same as the material of the pads 31 and 32.

The via contacts 352 and 353 as the third via contacts are provided in the resin layer 30, and are provided on the pads 331 and 332, respectively. The via contacts 352 and 353 are drawn out from the pads 331 and 332 to the fifth surface F5 side of the resin layer 30, respectively, and electrically connect the pad 331 to the wiring 341. The via contact 353 is drawn out from the pad 332 to the fifth surface F5 side of the resin layer 30, and electrically connects the pad 332 to the wiring 342.

The wirings 341 and 342 as the third wiring are provided on the fifth surface F5 of the resin layer 30, and are electrically connected to the pads 331 and 332 via the via contacts 352 and 353. The material of the wirings 341 and 342 may be the same as the material of the wirings 41 and 42. The material of the pads 331 and 332 may be the same as the material of the pads 31 and 32. As described above, the wirings 341 and 342 are provided on one surface (for example, the fifth surface F5) of the resin layer 30.

The terminals 371 and 372 are provided on the fifth surface F5 side of the resin layer 30, and are provided on the wirings 341 and 342 without the solder resist 61. Terminals 371 and 372 are, for example, solder bumps. The terminal 371 is electrically connected to the semiconductor element 311 via the wiring 341, the via contact 351 and the pad 331. The terminal 372 is electrically connected to another semiconductor element 311 via the wiring 342, the via contact 352, and the pad 332.

Although the semiconductor device 3 according to the third embodiment includes a plurality of semiconductor chips 10, 310, the wirings 41, 42, 341, and 342 are drawn out to one side (F5) side of the resin layer 30 and the other. It is not pulled out to the surface (F6). By making the wiring on one side in this way, the via contacts 51 to 53, 352, 353 and the wirings 41, 42 can be formed by processing from the fifth surface F5 side of the resin layer 30. As a result, the same effect as that of the first embodiment can be obtained in the third embodiment.

The semiconductor chip 310 side is not provided with a via contact for connecting the metal layer 320 and the wiring 341. However, since the ninth surface F9 of the metal layer 320 has a larger outer edge than the semiconductor chip 310, a via contact (not shown) connecting the metal layer 320 and the wiring 341 may be provided.

Next, a method for manufacturing the semiconductor device 3 will be described.

For each of the semiconductor chips 10 and 310, a structure in which the semiconductor chips 10 and 310 are mounted is formed on the metal layers 20 and 320 through the steps described with reference to FIGS. 2 to 5.

Next, in the step shown in FIG. 6, the structure of the semiconductor chip 10 and the metal layer 20 and the structure of the semiconductor chip 310 and the metal layer 320 are arranged side by side on the support portion 110.

Next, via contacts 51-353, wiring 41-342, and the like are formed through the steps described with reference to FIGS. 7 to 10. The thickness of the semiconductor chip 310 is thicker than that of the semiconductor chip 10, but the metal layer 320 is thinner than the thickness of the metal layer 20. The sum of the thickness of the semiconductor chip 10 and the thickness of the metal layer 20 is substantially equal to the sum of the thickness of the semiconductor chip 310 and the thickness of the metal layer 320. As a result, the depths of the via contacts 52, 53, 352, and 353 can be made substantially equal, so that the via contacts 52, 53, 352, and 353 can be easily formed.

Next, dicing is performed for each semiconductor package including the structure of the semiconductor chip 10 and the metal layer 20 and the structure of the semiconductor chip 310 and the metal layer 320. As a result, each semiconductor package is separated as a module including the structure of the semiconductor chip 10 and the metal layer 20 and the structure of the semiconductor chip 310 and the metal layer 320.

According to the third embodiment, the via contacts 51-353, the wirings 41-342, and the terminals 71-372 are formed on one side of the resin layer 30. Therefore, the third embodiment can obtain the same effect as the first embodiment. The third embodiment may be combined with the second embodiment.

(Fourth Embodiment)
In the manufacturing method according to the first embodiment, the semiconductor device 1 is manufactured by a so-called face-up mounting method. On the other hand, in the manufacturing method according to the fourth embodiment, the semiconductor device 1 is manufactured by a so-called face-down mounting method.

14 to 19 are sectional views showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment. After going through the steps shown in FIGS. 2A to 5, as shown in FIG. 14, the structure 130 is placed on the support portion 110 so that the element forming surface (F1) of the semiconductor chip 10 faces the support portion 110. Is glued to.

Next, as shown in FIG. 15, a resin layer 30 is formed around the plurality of structures 130 on the support portion 110, and is sealed with the resin layers 30 of the plurality of structures 130.

Next, as shown in FIG. 16, the support portion 110 is peeled off from the structure 130 and the resin layer 30. The peeling of the support portion 110 may be performed after forming the wirings 41 and 42 described later.

Next, as shown in FIG. 17, after the resin layer 31 is further formed on the resin layer 30, via contacts 51 to 53 and wirings 41 and 42 are formed as described with reference to FIG.

Next, as shown in FIG. 18, solder resists 61 and 62 are formed on the fifth surface F5 and the sixth surface F6 of the resin layer 30. Next, the solder resist 61 on the wirings 41 and 42 is patterned using the lithography technique. As a result, a part of the wirings 41 and 42 is exposed.

Next, as shown in FIG. 19, dicing is performed for each structure 130. As a result, the semiconductor package containing each semiconductor chip 10 is separated.

After that, the terminals 71 and 72 are formed on the wirings 41 and 42, respectively. As a result, the semiconductor device 1 shown in FIG. 1 is completed. When the metal layer 20 is used as a heat sink, the solder resist 62 and the resin layer 30 on the fourth surface F4 of the metal layer 20 may be removed after the terminals 71 and 72 are formed.

As described above, even in the face-down mounting method according to the fourth embodiment, the semiconductor device 1 can be manufactured, and the same effect as that of the first embodiment can be obtained.

Further, in the face-down type mounting method, the resin layer 31 provided on the pads 31 and 32 is formed separately from the resin layer 30, so that the thickness of the resin layer 31 is stable. Therefore, via contacts and the like can be arranged at a narrow pitch, and the semiconductor device 1 can be further miniaturized.

Further, for example, a frame made of a prepreg or a metal may be provided around the semiconductor chip 10. As a result, the rigidity of the semiconductor device 1 is improved and the thermal resistance is lowered. Further, by using the metal frame as a shield, the resistance of the semiconductor device 1 to noise is improved.

The fourth embodiment may be combined with the second or third embodiment.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope of the invention described in the claims and the equivalent scope thereof, as are included in the scope and gist of the invention.

1 ... Semiconductor device, 10 ... Semiconductor chip, 20 ... Metal layer, 30 ... Resin layer, 31, 32 ... Pad, 41, 42 ... Package wiring, 50 to 53 ...・ Via contact, 61, 62 ... Solder resist, 71, 72 ... Terminal

Claims (12)

A first metal layer having a first surface and a second surface opposite to the first surface,
A first semiconductor chip provided on the first surface of the first metal layer, and
With the first via contact provided on the first surface of the first metal layer,
The second via contact provided on the first semiconductor chip and
A resin layer for sealing the first metal layer, the first semiconductor chip, the first via contact, and the second via contact, which has a third surface and is the first end portion of the first via contact. And a resin layer that exposes the second end of the second via contact on the third surface,
A first wiring provided on the third surface of the resin layer and electrically connecting the first end portion of the first via contact and the second end portion of the second via contact,
A second wiring provided on the third surface of the resin layer,
A second metal layer having a ninth surface and a tenth surface opposite to the ninth surface,
A second semiconductor chip provided on the ninth surface of the second metal layer, and
With the third via contact provided on the second semiconductor chip,
The second surface of the first metal layer and the insulating layer covering the tenth surface side of the second metal layer are provided.
The resin layer surrounds the second metal layer, the second semiconductor chip, and the third via contact, and exposes the third end of the third via contact on the third surface.
The thickness of the second metal layer is different from the thickness of the first metal layer.
The sum of the thickness of the first semiconductor chip and the thickness of the first metal layer is substantially equal to the sum of the thickness of the second semiconductor chip and the thickness of the second metal layer.
A semiconductor device in which wiring is not provided on the second surface of the first metal layer and the tenth surface side of the second metal layer. The semiconductor device according to claim 1, wherein the first surface of the first metal layer is larger than the chip area of the first semiconductor chip. The semiconductor device according to claim 1, wherein the first metal layer has an outer circumference larger than the outer circumference of the first semiconductor chip. The semiconductor device according to claim 1, wherein the first metal layer has an outer edge protruding outside the outer edge of the first semiconductor chip. The semiconductor device according to claim 1, wherein the second surface of the first metal layer is exposed from the resin layer. The second metal layer separated from the first metal layer and
Further provided with a third via contact provided on the second metal layer,
The semiconductor device according to claim 1, wherein the third end portion of the third via contact is exposed from the resin layer on the third surface. The semiconductor device according to claim 1, further comprising a terminal connected to the first wiring, the second wiring, or the first metal layer. A first metal layer having a first surface and a second surface opposite to the first surface,
A first semiconductor chip disposed on the first surface of the first metal layer, the chip area of the first semiconductor chip, the less than the first surface of the first metal layer first semiconductor chip When,
With the first via contact provided on the first surface of the first metal layer,
The second via contact provided on the first semiconductor chip and
A resin layer that seals the first metal layer, the first semiconductor chip, the first via contact, and the second via contact and has a third surface, the first end portion of the first via contact, and the resin layer. A resin layer that exposes the second end of the second via contact on the third surface, and
A first wiring provided on the third surface of the resin layer and electrically connecting the first end portion of the first via contact and the second end portion of the second via contact.
A second wiring provided on the third surface of the resin layer and electrically connected to the second via contact is provided.
A second metal layer having a ninth surface and a tenth surface opposite to the ninth surface,
A second semiconductor chip provided on the ninth surface of the second metal layer, and
With the third via contact provided on the second semiconductor chip,
An insulating layer that covers the second surface of the first metal layer and the tenth surface side of the second metal layer,
A semiconductor device in which wiring is not provided on the second surface of the first metal layer and the tenth surface side of the second metal layer. The semiconductor device according to claim 8 , wherein the first metal layer has an outer edge protruding outside the outer edge of the first semiconductor chip. The semiconductor device according to claim 8 , wherein the second surface of the first metal layer is exposed from the resin layer. The second metal layer separated from the first metal layer and
The semiconductor device according to claim 8 , further comprising a third via contact provided on the second metal layer and extending to the third surface of the resin layer. The semiconductor device according to claim 8 , further comprising a terminal connected to the first wiring, the second wiring, or the first metal layer.

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