JP6977074B2 - Display device and sensor device - Google Patents

Description

Embodiments of the present invention relate to display devices and sensor devices.

In recent years, a display device with a touch detection function including a drive electrode and a detection electrode has been developed. The drive electrode of the touch detection device also functions as a common electrode of the display device, and as an example, a technique is known in which the drive electrode is arranged so as to extend in the same direction as the signal line. In such a display device, it is required to suppress deterioration of display quality.

Japanese Unexamined Patent Publication No. 2012-47007 Japanese Unexamined Patent Publication No. 2011-23018

An object of the present embodiment is to provide a display device and a sensor device capable of suppressing deterioration of display quality.

According to the present embodiment, a display area for displaying an image, a non-display area surrounding the display area, a first signal line, and a second signal line arranged at intervals from the first signal line are provided. A first interlayer insulating film covering the first signal line and the second signal line, a first metal wiring arranged on the first interlayer insulating film and overlapped with the first signal line, and a metal wiring. A second metal wiring arranged so as to overlap the second signal line, and a pixel electrode arranged on the first interlayer insulating film and arranged between the first metal wiring and the second metal wiring. , The first metal wiring, the second metal wiring, the pixel electrode, the second interlayer insulating film, and the first common electrode and the second common electrode arranged on the second interlayer insulating film. The gap between the first common electrode and the second common electrode overlaps with the first signal line and the first metal wiring, and the second signal line and the second metal wiring are the same. Overlapping with the second common electrode, the second metal wiring is connected to the second common electrode via a contact hole formed in the second interlayer insulating film in the display region, and the contact hole is connected to the second common electrode. A display device that overlaps with the signal line and is connected to the first common electrode in the non-display region is provided for the first metal wiring.

According to the present embodiment, the detection region for detecting the position of the object to be detected, the non-detection region outside the detection region, the first metal wiring, and the first metal wiring are arranged at intervals. The first metal wiring is provided with an interlayer insulating film covering the first metal wiring and the second metal wiring, and a first detection electrode and a second detection electrode arranged on the interlayer insulating film. The gap between the detection electrode and the second detection electrode overlaps with the first metal wiring, the second metal wiring overlaps with the second detection electrode, and the second metal wiring overlaps with the detection region. A sensor device is provided in which the first metal wiring is connected to the second detection electrode via a contact hole formed in the interlayer insulating film, and the first metal wiring is connected to the first detection electrode in the non-detection region. ..
According to the present embodiment, the display area for displaying an image, the first signal line, the inorganic insulating film, and the first signal line overlap and extend in parallel with the first signal line, and the inorganic insulation is provided. A first metal wiring in contact with the first surface of the film, a first common electrode and a second common electrode in contact with a second surface opposite to the first surface of the inorganic insulating film, and the first common electrode. A display device is provided in which the gap between the second common electrode overlaps with the first signal line and the first metal wiring, and the first metal wiring is connected to the first common electrode. ..

FIG. 1 is a perspective view showing the configuration of a display device. FIG. 2 is a schematic view showing a cross section of a display panel. FIG. 3 is a plan view showing a configuration in the display area of the display panel shown in FIG. FIG. 4 is a cross-sectional view showing the configuration of the display panel taken along the line AB of FIG. FIG. 5 is a cross-sectional view showing the configuration of the display panel on the CD line of FIG. FIG. 6 is a plan view showing a configuration example of the switching element. FIG. 7 is a cross-sectional view showing the configuration of the first substrate SUB1 including the switching element TR1 in the EF line of FIG. FIG. 8 is a plan view showing the relationship between the width of the metal wiring and the contact hole. FIG. 9 is a plan view showing the positional relationship of the light-shielding layer, the metal wiring, the spacer, the contact hole, and the like. FIG. 10 is a plan view showing a partial configuration of the display device. FIG. 11 is a diagram for explaining the principle of the sensing method. FIG. 12 is a plan view schematically showing an equivalent circuit connected to the drive electrode. FIG. 13 is a plan view showing the connection relationship between the drive electrode and the metal wiring. FIG. 14 is a plan view showing another embodiment of the connection relationship between the drive electrode and the metal wiring.

Hereinafter, this embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is merely an example, and the present invention is used. It does not limit the interpretation. Further, in the present specification and each figure, components exhibiting the same or similar functions as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and duplicate detailed description may be omitted as appropriate. ..

First, the display device according to the present embodiment will be described in detail.
In this embodiment, a liquid crystal display device is disclosed as an example of the display device. This liquid crystal display device can be used in various devices such as smartphones, tablet terminals, mobile phone terminals, personal computers, television image receiving devices, in-vehicle devices, and game devices. The main configuration disclosed in this embodiment is a self-luminous display device having an organic electrochromism display element or the like, an electronic paper type display device having an electrophoresis element or the like, and a MEMS (Micro Electro Mechanical Systems). It can also be applied to an applied display device or a display device to which electrochromism is applied.

FIG. 1 is a perspective view schematically showing the configuration of the display device DSP.
The display device DSP includes an active matrix type display panel PNL, a drive IC chip 2 for driving the display panel PNL, a backlight unit BL for illuminating the display panel PNL, a control module CM, a flexible wiring board FPC1, FPC2, and the like. ..

The display panel PNL includes a first substrate SUB1 and a second substrate SUB2 arranged to face the first substrate SUB1. Further, the display panel PNL includes a display area DA for displaying an image and a frame-shaped non-display area NDA surrounding the display area DA. The plurality of pixels PX are arranged in a matrix in the display area DA.

The backlight unit BL is arranged on the back side of the first substrate SUB1. Various forms can be applied to such a backlight unit BL, but the detailed structure will be omitted. The drive IC chip 2 is mounted on the first substrate SUB1. The flexible wiring board FPC1 connects the display panel PNL and the control module CM. The flexible wiring board FPC2 connects the backlight unit BL and the control module CM.

The display device DSP having such a configuration is a transmissive liquid crystal display device having a transmissive display function of displaying an image by selectively transmitting light incident on the display panel PNL from the backlight unit BL by each pixel PX. Corresponds to. However, the display device DSP may be a reflective liquid crystal display device having a reflection display function for displaying an image by selectively reflecting external light or auxiliary light, and may have a transmission display function and a reflection display function. It may be a semi-transmissive type liquid crystal display device provided with.

FIG. 2 is a schematic view showing a cross section of the display panel PNL.
The display panel PNL includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LQ, a sealing material SE, a spacer SP, an optical element OD1, an optical element OD2, and the like. Details of the first substrate SUB1 and the second substrate SUB2 will be described later.

The sealing material SE is arranged in the non-display area NDA, and the first substrate SUB1 and the second substrate SUB2 are bonded together. The spacer SP is arranged between the first substrate SUB1 and the second substrate SUB2. In the illustrated example, the spacer SP2 is formed on the second substrate SUB2. The liquid crystal layer LQ is held between the first substrate SUB1 and the second substrate SUB2. The optical element OD1 is arranged on a surface of the first substrate SUB1 opposite to the side facing the second substrate SUB2. The optical element OD2 is arranged on a surface of the second substrate SUB2 opposite to the side facing the first substrate SUB1. The optical elements OD1 and OD2 each include a polarizing plate. The optical elements OD1 and OD2 may include other optical elements such as a retardation plate.

FIG. 3 is a plan view showing the configuration of the display panel PNL shown in FIG. 1 in the display area DA. In the present embodiment, the display panel PNL is applied to a mode using a transverse electric field along the main surface of the substrate, such as an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode, which is one of the IPS modes. Will be done. In the figure, only the main parts necessary for explanation are shown.

Here, FIG. 3 shows a plan view of the display panel PNL in the XY planes defined by the first direction X and the second direction Y intersecting each other. In the illustrated example, the first direction X and the second direction Y are orthogonal to each other, but may intersect at an angle other than 90 °. Further, in the figure, the direction that intersects the second direction Y at an acute angle counterclockwise is defined as the direction D1, and the direction that intersects the second direction Y at an acute angle clockwise is defined as the direction D2. .. The angle θ1 formed by the second direction Y and the direction D1 is substantially the same as the angle θ2 formed by the second direction Y and the direction D2.

As shown in FIG. 3, the display panel PNL includes scanning lines G, signal lines S1 to S4, switching elements TR1 to TR3, metal wirings M1 to M4, pixel electrodes PE1 to PE6, common electrodes CE1 and CE2, a light-shielding layer BM, and the like. It is equipped with.

The scanning line G extends along the first direction X. The signal lines S1 to S4 extend substantially along the second direction Y, and are arranged at intervals along the first direction X. In the illustrated example, the signal lines S1 to S4 extend along the direction D1 above the scanning line G (the rear end side of the arrow indicating the second direction Y) and below the scanning line G (second direction). On the tip side of the arrow indicating the direction Y), it extends along the direction D2. These scanning lines G and the signal lines S1 to S4 intersect each other in the XY plane.

The switching element TR1 is located near the intersection of the scanning line G and the signal line S2, and is electrically connected to the scanning line G and the signal line S2. The switching element TR2 is located near the intersection of the scanning line G and the signal line S3, and is electrically connected to the scanning line G and the signal line S3. The switching element TR3 is located near the intersection of the scanning line G and the signal line S4, and is electrically connected to the scanning line G and the signal line S4. Here, the switching elements TR1 to SW3 are shown in a simplified manner, but will be described in detail later.

The metal wirings M1 to M4 extend substantially along the second direction Y, and are arranged at intervals along the first direction X. The metal wirings M1 to M4 overlap with the signal lines S1 to S4, respectively, and extend in parallel with the signal lines S1 to S4, respectively. Further, the metal wirings M1 to M4 intersect with each other in the scanning line G and the XY plane. The metal wirings M1 to M4 are each formed with the same width along the first direction X. It is desirable that each of the metal wirings M1 to M4 has a width equal to or larger than that of the signal lines S1 to S4.

The pixel electrodes PE1 to PE3 are arranged at intervals in the first direction X. Further, the pixel electrodes PE4 to PE6 are arranged at intervals in the first direction X. The pixel electrodes PE1 and PE4 are located between the signal lines S1 and S2, and are arranged at intervals in the second direction Y with the scanning lines G in between. The pixel electrodes PE2 and PE5 are located between the signal lines S2 and S3, and are arranged at intervals in the second direction Y with the scanning lines G in between. The pixel electrodes PE3 and PE6 are located between the signal lines S3 and S4, and are arranged at intervals in the second direction Y with the scanning lines G in between.

The common electrode CE1 is arranged so as to overlap with the signal line S1, the metal wiring M1, the pixel electrodes PE1 and PE4. The common electrode CE2 is arranged so as to overlap with the signal lines S3 and S4, the metal wirings M3 and M4, and the pixel electrodes PE2, PE3, PE5, and PE6. As will be described later, the common electrodes CE1 and CE2 are formed in a band shape, and a gap GP is formed between the common electrodes CE1 and CE2. The gap GP overlaps with the signal line S2 and the metal wiring M2, and is formed along the signal line S2 and the metal wiring M2. The common electrodes CE1 and CE2 have slits SL at positions overlapping each of the pixel electrodes PE1 to PE6. The slit SL formed at a position overlapping the pixel electrodes PE1 to PE3 is formed along the direction D1. The slit SL formed at a position overlapping the pixel electrodes PE4 to PE6 is formed along the direction D2. The number of slits SL formed at positions overlapping with one pixel electrode is, but is not limited to, three in the illustrated example.

The contact holes CHa, CHb, and CHc are formed in an insulating film between the metal wirings M1 to M4 and the common electrodes CE1 and CE2, which will be described later. The contact hole CHa is formed at a position where it overlaps with the signal line S1 and the metal wiring M1. The metal wiring M1 is connected to the common electrode CE1 via the contact hole CHa. The contact hole CHb is formed at a position where it overlaps with the signal line S3 and the metal wiring M3. The metal wiring M3 is connected to the common electrode CE2 via the contact hole CHb. The contact hole CHc is formed at a position where it overlaps with the signal line S4 and the metal wiring M4. The metal wiring M4 is connected to the common electrode CE2 via the contact hole CHc.

The light-shielding layer BM is arranged in a region overlapping with wiring portions such as scanning lines G, signal lines S1 to S4, and metal wirings M1 to M4. The light-shielding layer BM is shown by a two-dot chain line in FIG. The light-shielding layer BM defines openings OP1 to OP6. The openings OP1 to OP6 include a region where the pixel electrodes PE1 to PE6 overlap with the slits SL of the common electrodes CE1 and CE2, respectively.

Although the example in which the signal lines S1 to S4 are bent with respect to the second direction Y has been described here, the signal lines S1 to S4 may extend linearly along the second direction Y.

FIG. 4 is a cross-sectional view showing the configuration of the display panel PNL in line AB of FIG.
In the present embodiment, the direction from the first substrate SUB1 to the second substrate SUB2 is defined as upward or upward, and the direction from the second substrate SUB2 to the first substrate SUB1 is defined as downward or downward. Further, in the case of "the second member above the first member" and "the second member below the first member", the second member may be in contact with the first member or may be separated from the first member. May be located. In the latter case, a third member may be interposed between the first member and the second member. On the other hand, in the case of "the second member above the first member" and "the second member below the first member", the second member is in contact with the first member.

The first substrate SUB 1 is configured by using the first insulating substrate 10, which is a substrate having light transmittance such as a glass substrate or a resin substrate. The first substrate SUB1 has a first insulating film 11, a second insulating film 12, a third insulating film 13, signal lines S1 to S4, and a fourth on the surface 10A side of the first insulating substrate 10 facing the second substrate SUB2. It includes an insulating film 14, metal wirings M1 to M4, pixel electrodes PE1 to PE3, a fifth insulating film 15, a common electrode CE, a first alignment film AL1, and the like.

The first insulating film 11 is arranged on the first insulating substrate 10. The second insulating film 12 is arranged on the first insulating film 11. The third insulating film 13 is arranged on the second insulating film 12. The signal lines S1 to S4 are arranged on the third insulating film 13. The signal lines S1 to S4 are arranged at intervals in the first direction X from each other. The fourth insulating film 14 covers the signal lines S1 to S4. The fourth insulating film 14 is also arranged on the third insulating film 13. The fourth insulating film 14 corresponds to the first interlayer insulating film.

The metal wirings M1 to M4 are arranged on the fourth insulating film 14. The metal wirings M1 to M4 are located directly above the signal lines S1 to S4, respectively. The metal wirings M1 to M4 are composed of, for example, a single layer or a laminated body of molybdenum, aluminum, or molybdenum. The pixel electrodes PE1 to PE3 are arranged on the fourth insulating film 14. The pixel electrode PE1 is arranged between the metal wiring M1 and the metal wiring M2. The pixel electrode PE2 is arranged between the metal wiring M2 and the metal wiring M3. The pixel electrode PE3 is arranged between the metal wiring M3 and the metal wiring M4. The pixel electrodes PE1 to PE3 and the metal wirings M1 to M4 are separated from each other. The pixel electrode PE is formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The fifth insulating film 15 covers the metal wirings M1 to M4 and the pixel electrodes PE1 to PE3. The fifth insulating film 15 corresponds to the second interlayer insulating film.

The common electrodes CE1 and CE2 are arranged on the fifth insulating film 15. The common electrode CE1 faces the pixel electrode PE1, and the common electrode CE2 faces the pixel electrodes PE2 and PE3. The gap GP between the common electrode CE1 and the common electrode CE2 is located directly above the signal line S2 and the metal wiring M2. The common electrode CE is formed of, for example, a transparent conductive material such as ITO or IZO. The common electrodes CE1 and CE2 are covered with the first alignment film AL1. The first alignment film AL1 also covers the fifth insulating film 15.

Here, attention is paid to the positional relationship between the signal line S3 and the metal wiring M3 and the common electrode CE2. The common electrode CE2 includes an electrode portion EL located directly above the signal line S3 and the metal wiring M3. The electrode portion EL has a width W1 in the first direction X. Further, the gap GPa between the pixel electrode PE2 and the metal wiring M3 has a width W2 in the first direction X, and the gap GPb between the pixel electrode PE3 and the metal wiring M3 is in the first direction X. It has a width W4. In one example, the width W2 and the width W4 are approximately equal. The metal wiring M3 has a width W3 in the first direction X. The width W1 of the electrode portion EL is, for example, equal to or greater than the sum of the width W2 of the gap GPa, the width W3 of the metal wiring M3, and the width W4 of the gap GPb. Further, the metal wiring M3, the gap GPa, and the gap GPb are arranged in a region overlapping the electrode portion EL in the third direction Z. In the present embodiment, for example, the width W1 is 10 μm, the width W2 and the width W4 are both 2 μm, the width W3 is 5 μm, one end of the electrode portion EL is located directly above the pixel electrode PE2, and the electrode portion. The other end of the EL is located directly above the pixel electrode PE3.

The first insulating film 11, the second insulating film 12, the third insulating film 13, and the fifth insulating film 15 as described above are formed by using an inorganic material such as silicon oxide or silicon nitride, for example. ing. Further, the fourth insulating film 14 is formed by using an organic material such as a transparent resin.

The second substrate SUB2 is configured by using a second insulating substrate 20 which is a substrate having light transmittance such as a glass substrate or a resin substrate. The second substrate SUB2 is provided with a light-shielding layer BM, color filters CF1 to CF3, an overcoat layer OC, a second alignment film AL2, and the like on the surface 20A side of the second insulating substrate 20 facing the first substrate SUB1.

The light-shielding layer BM is arranged on the surface 20A of the second insulating substrate 20 facing the first substrate SUB1. The light-shielding layer BM is formed of, for example, a black resin material.

The color filters CF1 to CF3 are arranged on the surface 20A of the second insulating substrate 20, and their respective ends overlap with the light-shielding layer BM. The color filters CF1 to CF3 are formed of resin materials colored in a plurality of different colors, for example, red, blue, and green. The color filters CF1 to CF3 are located in the openings OP1 to OP3, respectively, and face the pixel electrodes PE1 to PE3, respectively.

The overcoat layer OC covers the color filters CF1 to CF3. The overcoat layer OC is formed of a transparent resin material. The second alignment film AL2 covers the overcoat layer OC. The first alignment film AL1 and the second alignment film AL2 are formed of, for example, a material exhibiting horizontal orientation.

The first substrate SUB1 and the second substrate SUB2 as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the first substrate SUB1 and the second substrate SUB2 by a spacer (not shown). The first substrate SUB1 and the second substrate SUB2 are bonded to each other with a sealing material in a state where a cell gap is formed. The liquid crystal layer LQ is composed of the liquid crystal composition enclosed in the cell gap.

FIG. 5 is a cross-sectional view showing the configuration of the display panel PNL on the CD line of FIG.
The contact holes CHa, CHb, and CHc are formed in the fifth insulating film 15. The metal wiring M1 is connected to the common electrode CE1 via the contact hole CHa. The metal wiring M3 is connected to the common electrode CE2 via the contact hole CHb. The metal wiring M4 is connected to the common electrode CE2 via the contact hole CHc. That is, the common electrodes CE1 and CE2 and the metal wirings M1, M3, and M4 have the same potential. In this way, the metal wirings M1, M3, and M4 are connected to the common electrodes CE1 and CE2, so that the resistance of the common electrodes CE1 and CE2 is reduced.

According to this embodiment, the common electrodes CE1 and CE2 are arranged above the pixel electrodes PE1 to PE3. Further, the gap GP between the common electrode CE1 and the common electrode CE2 is formed at a position overlapping the signal line S2 and the metal wiring M2. Therefore, the metal wiring M2 shields the electric field formed between the signal line S2 and the common electrode CE1 and the common electrode CE2. Therefore, it is possible to suppress the electric field leakage from the signal line S2 to the liquid crystal layer LQ via the gap GP, the misalignment of the liquid crystal molecules due to the electric field leakage is suppressed in the gap GP, and the display in the vicinity of the gap GP is suppressed. It is possible to suppress unevenness. This makes it possible to suppress deterioration of display quality.

Further, by suppressing the display unevenness in the vicinity of the gap GP, the degree of freedom in the position where the gap GP is provided can be improved. That is, when display unevenness occurs in the vicinity of the gap GP, the position of the gap GP needs to be arranged between the color pixels in which the display unevenness is hard to be visually recognized. For example, when the display panel PNL is provided with a three-color red-blue-green color filter, the position where the gap GP is formed is limited between the red pixel and the blue pixel. On the other hand, according to the present embodiment, the position of the gap GP is not limited and may be between any color pixels.

Further, the width W2 of the gap GPa between the pixel electrode PE2 and the metal wiring M3 and the width W4 of the gap GPb between the pixel electrode PE3 and the metal wiring M3 are substantially equal to each other. In other words, the metal wiring M3 is arranged at equidistant positions from the opening OP2 and the opening OP3. Therefore, when the display panel PNL is observed from an oblique direction inclined from its normal line, the colors of adjacent color filters are mixed and visually recognized, and the color shift is caused by the change in the ratio of the opening area for each color pixel. Can be suppressed from being visually recognized. Similarly, the metal wiring M2 that overlaps with the gap GP is also arranged at equal intervals from the opening OP1 and the opening OP2, and suppresses display unevenness due to color mixing and color shift even in the vicinity of the gap GP. be able to.

Further, the metal wiring M2 is arranged between the pixel electrode PE1 and the pixel electrode PE2 and overlaps with the signal line S2. Therefore, while the signal line S2 is capacitively coupled to the metal wiring M2, the parasitic capacitance between the signal line S2 and the pixel electrodes PE1 and PE2 can be reduced.

Next, the configuration of the switching element shown in FIG. 3 will be described in detail.
FIG. 6 is a plan view showing a configuration example of the switching element TR1. Here, only the main part necessary for the explanation in the first substrate SUB1 is illustrated, and the illustration of the common electrode and the like is omitted. Further, since the switching elements TR2 and TR3 shown in FIG. 3 have the same configuration as the switching element TR1, the configuration will be described here focusing on the switching element TR1.

The switching element TR1 includes a semiconductor layer SC and a relay electrode RE. The semiconductor layer SC is formed in a substantially U shape and intersects the scanning line G at two points. The semiconductor layer SC has an end E11 and an end E12. The end portion E11 is electrically connected to the signal line S2 via the contact hole CH11. The end portion E12 is electrically connected to the relay electrode RE via the contact hole CH12. The relay electrode RE is arranged between the signal line S1 and the signal line S2. In the scanning line G, the two portions intersecting the semiconductor layer SC function as gate electrodes G11 and G12, respectively. The light-shielding body SI is arranged at a position where the semiconductor layer SC and the gate electrode G12 overlap. The relay electrode RE is electrically connected to the pixel electrode PE1 via the contact hole CH1.

FIG. 7 is a cross-sectional view showing the configuration of the first substrate SUB1 including the switching element TR1 in the EF line of FIG. In the illustrated example, the switching element TR1 is a top gate type thin film transistor, but may be a bottom gate type.

The light-shielding body SI is arranged on the first insulating substrate 10 and is covered with the first insulating film 11. The semiconductor layer SC is arranged on the first insulating film 11 and is covered with the second insulating film 12. The semiconductor layer SC is formed of, for example, polycrystalline silicon, but may be formed of amorphous silicon, an oxide semiconductor, or the like.

The gate electrodes G11 and G12 are arranged on the second insulating film 12 and covered with the third insulating film 13. The gate electrodes G11 and G12 face the semiconductor layer SC via the second insulating film 12. The gate electrode G12 is located above the light-shielding body SI. The signal line S2 and the relay electrode RE are arranged on the third insulating film 13 and covered with the fourth insulating film 14. The signal line S2 is connected to the semiconductor layer SC via a contact hole CH 11 penetrating the second insulating film 12 and the third insulating film 13. The relay electrode RE is connected to the semiconductor layer SC via a contact hole CH 12 penetrating the second insulating film 12 and the third insulating film 13.

The metal wiring M2, the pixel electrodes PE1 and PE4 are arranged on the fourth insulating film 14 and covered with the fifth insulating film 15. The pixel electrode PE1 is connected to the relay electrode RE via the contact hole CH1 penetrating the fourth insulating film 14. The common electrode CE1 is arranged on the fifth insulating film 15 and is covered with the first alignment film AL1. Further, in FIG. 3, the gap GP is formed at a position where it overlaps with the metal wiring M2 in a plan view, and also in FIG. 7, the gap is defined as a region where the common electrode is not arranged at the position where it overlaps with the metal wiring M2. GP is formed.

FIG. 8 is a plan view showing the relationship between the widths of the metal wiring M3 and the contact hole CHb.
As shown in FIG. 4, the metal wiring M3 has a width W3 along the first direction X. Further, as shown in FIG. 5, the metal wiring M3 is connected to the common electrode CE2 via the contact hole CHb. In the example shown in FIG. 8, the contact hole CHb has a width W11 along the first direction X.
FIG. 8A is a plan view showing the relationship between the widths of the metal wiring M3 and the contact hole CHb shown in FIG. In the example shown in FIG. 8A, the metal wiring M3 is formed in a band shape having a substantially constant width W3. Here, the width W11 is formed smaller than the width W3.

8 (b) and 8 (c) are diagrams showing other embodiments of the relationship between the widths of the metal wiring M3 and the contact hole CHb.
In the example shown in FIG. 8B, the metal wiring M3 is formed in a band shape having a substantially constant width W3. Here, the width W11 is formed larger than the width W3. From the viewpoint of equalizing the contact area between the common electrode and the metal wiring, the position corresponding to the center of the contact hole CHb, that is, 1/2 of the width W11, and the position corresponding to the center of the metal wiring M3, that is, 1/2 of the width W3. It is desirable that and overlap. The relationship between the width W11 and the width W3 is not limited to the illustrated example, and the width W11 and the width W3 may be the same.

In the example shown in FIG. 8 (c), the metal wiring M3 has an expansion portion M31 at a position overlapping the contact hole CHb. The expansion portion M31 has a width W31 along the first direction X. The width W31 is formed larger than the width W3. Further, the width W11 is formed smaller than the width W31. In FIG. 8C, the position corresponding to 1/2 of the width W3 and the position corresponding to 1/2 of the width W31 are located, for example, on a straight line. Here, it is desirable that the center of the contact hole CHb, that is, the position corresponding to 1/2 of the width W11, and the center of the metal wiring M31, that is, the position corresponding to 1/2 of the width W31 overlap. The relationship between the width W11 and the width W31 is not limited to the illustrated example, and the width W11 and the width W31 may be the same.
If the contact hole CHb and the metal wiring M3 are arranged at overlapping positions, the center of the contact hole CHb and the center of the metal wiring M3 may be deviated from each other. Further, the relationship between the widths of the metal wiring M3 and the contact hole CHb is similarly applied to the metal wiring M1 and the contact hole CHa, and the metal wiring M4 and the contact hole CHc.

FIG. 9 is a plan view showing the positional relationship between the light-shielding layer BM, the metal wirings M11 to M17, the spacers SP1 to SP3, and the like. Here, for example, a case where one pixel PX is composed of three sub-pixels SPX is shown. The scanning line and the signal line are indicated by a alternate long and short dash line in the figure.

The metal wirings M11 to M17 overlap the signal lines S11 to S17, respectively. The gap GP between the common electrodes CE1 and CE2 overlaps the signal line S14 and the metal wiring M14. The light-shielding layer BM is arranged at a position where it overlaps with the scanning lines G11 to G15 and the signal lines S11 to S17, respectively, and is formed in a grid pattern. The contact hole CHA for connecting the common electrode CE1 and the metal wirings M11 to M13, respectively, is located near the intersection of the scanning lines G11 to G15 and the signal lines S11 to S13. The contact hole CHB for connecting the common electrode CE2 and the metal wirings M15 to M17, respectively, is located near the intersection of the scanning lines G11 to G15 and the signal lines S15 to S17. However, neither the contact hole CHA nor the CHB is arranged at the position where the signal line S14 and the metal wiring M14 overlap. Further, the spacer SP is arranged at the intersection of the scanning line and the signal line, but is not arranged so as to overlap the signal line S14 that overlaps with the gap GP. Neither the contact hole CHA nor the CHB is arranged at the position where it overlaps with the spacer. Further, the metal wiring is interrupted at a position where it overlaps with the spacer SP.

These points will be described in more detail by focusing on the metal wiring M17, the spacers SP1 to SP3, and the like, but the description thereof will be omitted assuming that the positional relationship of the other metal wirings and spacers has the same configuration.

Similar to the spacer SP shown in FIG. 2, the spacers SP1 to SP3 are arranged between the first substrate SUB1 and the second substrate SUB2. The spacers SP1 to SP3 are arranged at positions overlapping with the signal line S17. In the illustrated example, the spacer SP1 is located at the intersection of the scanning line G11 and the signal line S17, the spacer SP2 is located at the intersection of the scanning line G13 and the signal line S17, and the spacer SP3 is located at the intersection of the scanning line G15 and the signal line S17. It is located at the intersection with S17. The metal wiring M17 is interrupted at a position where it overlaps with the spacers SP1 to SP3, and has a first portion M17a and a second portion M17b. The second portion M17b is arranged at a distance from the first portion M17a. The first portion M17a is located between the spacer SP1 and the spacer SP2, and the second portion M17b is located between the spacer SP2 and the spacer SP3. That is, the spacer SP2 is arranged between the first portion M17a and the second portion M17b. The contact hole CHBa is located between the spacer SP1 and the spacer SP2, and the contact hole CHBb is located between the spacer SP2 and the spacer SP3. The first portion M17a is connected to the common electrode CE2 via the contact hole CHBa in the vicinity of the position where the scanning line G12 intersects. The second portion M17b is connected to the common electrode CE2 via the contact hole CHBb in the vicinity of the position where the scanning line G14 intersects. Therefore, it is suppressed that the first portion M17a and the second portion M17b are in a floating state. Further, in order to make the resistance values of the first portion M17a and the second portion M17b uniform, the contact holes CHBa and CHBb are located at the center of the width of the first portion M17a and the second portion M17b along the second direction Y, respectively. It is desirable to be formed.

Neither metal wiring nor contact holes are formed at the positions where the spacers SP1 to SP3 are arranged, and they overlap with the region where the unevenness is relaxed. Therefore, when a pressing force is applied from the outside while the spacers SP1 to SP3 are in contact with the first substrate SUB1, the spacers SP1 to SP3 suppress the occurrence of display defects due to damage to the first alignment film AL1. be able to. Further, since the spacers SP1 to SP3 come into contact with a flat region of the first substrate SUB1 that is not affected by unevenness such as metal wiring, the pressure resistance due to the decrease in the installation area of the spacers SP1 to SP3 in contact with the first substrate is reduced. Can be suppressed.

In the display region, a contact hole for connecting the metal wiring M14 and the common electrode is not formed at a position overlapping the gap GP in order to avoid the risk of short-circuiting the common electrode. The metal wiring M14 is connected to the common electrode CE1 in a non-display area. Further, in order to prevent the metal wiring M14 from being in a floating state, the spacer is not arranged at a position where it overlaps with the signal line S14 and the gap GP.

The light-shielding layer BM has an expansion portion EP at a position overlapping each of the spacers SP. Further, the light-shielding layer BM also has an expansion portion EP at a position overlapping the gap GP. The expansion portion EP is formed in four sub-pixels around the spacer SP. The expansion unit EP is formed for each pixel PX along the first direction X, and is formed for each two pixel PX along the second direction Y. Therefore, it is possible to suppress variations in the opening area of each pixel PX.

The metal wirings M12, M13, M15, and M16 are connected to the common electrode by contact holes formed for each pixel PX along the second direction Y, but depending on the resistance value of the common electrode, these may be connected. Contact holes may be thinned out.

FIG. 10 is a plan view showing a configuration example of the sensor device SS provided in the display device DSP. The sensor device SS includes drive electrodes TX1 to TXn, detection electrodes RX1 to RXm, a flexible wiring board FPC3, a touch detection IC chip 4, and the like. Note that n and m are, for example, integers of 2 or more. The drive electrodes TX1 to TXn are arranged on the first substrate SUB1 and correspond to the above-mentioned common electrodes. The detection electrodes RX1 to RXm are arranged, for example, on a surface of the second substrate SUB2 opposite to the surface facing the first substrate SUB1. The flexible wiring board FPC3 is connected to the second board SUB2. The touch detection IC chip 4 is mounted on the flexible wiring board FPC3.

The sensor device SS has a detection region DR for detecting an object to be detected and a non-detection region NDR outside the detection region DR. The detection area DR overlaps with the display area DA of the display device DSP, and the non-detection area NDR overlaps with the non-display area NDA. The display area DA and the detection area DR, the non-display area NDA, and the non-detection area NDR do not have to be the same area. The display area DA or the detection area DR includes a first end portion E1 and a second end portion E2 along the first direction X, and a third end portion E3 and a fourth end portion E4 along the second direction Y. It has a substantially rectangular shape.

As shown in FIG. 10, the plurality of drive electrodes TX1 to TXn are each formed in a band shape, extend from the first end portion E1 to the second end portion E2 in the second direction Y, and are spaced apart from each other in the first direction X. They are lined up. That is, the gap between the adjacent drive electrodes corresponds to the gap GP between the common electrodes. That is, the gap GP extends from the first end portion E1 to the second end portion E2 in a plan view. In the present embodiment, the drive electrodes TX1 to TXn are formed so as to extend to the non-display region NDA.

The plurality of detection electrodes RX1 to RXm are each formed in a band shape, extend from the third end portion E3 to the fourth end portion E4 in the first direction X, and are arranged at intervals in the second direction Y. The plurality of detection electrodes RX1 to RXm intersect with the plurality of drive electrodes TX1 to TXn in the display region DA or the detection region DR. The detection electrodes RX1 to RXm are electrically connected to the flexible wiring board FPC3 by a lead wire LD located in the non-display region NDA or the non-detection region NDR. Here, the lead wire LD is electrically connected to the detection electrodes RX1 to RXm on a one-to-one basis. The detection electrodes RX1 to RXm are formed of, for example, a transparent conductive material such as ITO or IZO, but may be formed of a mesh-like or fine wire-shaped metal wire, and may be a laminate of the metal wire and the transparent conductive layer. It may be formed by such as. The lead wire LD is preferably formed of a thin metal wire from the viewpoint of reducing resistance.

Next, the operation at the time of sensing drive, which performs sensing for detecting the approach or contact of the object to be detected with the above-mentioned display device DSP, will be described. The sensing mode described here may be referred to as a mutual capacitive sensing method. The mutual capacitance method detects an object to be detected based on the change in the capacitance between the electrodes between the drive electrode TX and the detection electrode RX.

FIG. 11 is a diagram for explaining the principle of the mutual capacitance method sensing method. Here, a case where a finger Fg as a conductive object to be detected is input to the display device DSP will be described.

The drive electrode TX and the detection electrode RX are capacitively coupled, and an interelectrode capacitance Cc is formed between the drive electrode TX and the detection electrode RX. The finger Fg approaches the detection electrode RX from the side opposite to the side facing the drive electrode TX of the detection electrode RX. Here, the position of the finger Fg on the XY plane is defined as the position LC. In the position LC, a coupling capacitance Cx is formed between the finger Fg and the detection electrode RX.

When sensing is performed, first, a pulsed sensor drive signal Vw is written in the drive electrode Tx, and the inter-electrode capacitance Cc between the drive electrode Tx and the detection electrode Rx as shown above is changed. A sensor signal is generated. Next, the touch detection IC chip 4 reads a pulse-shaped detection signal Vr indicating a change in the sensor signal from the detection electrode Rx. The position of the finger Fg can be detected based on the timing at which the sensor drive signal Vw is supplied to the drive electrode Tx and the detection signal Vr from the detection electrode Rx.

The display drive and the sensing drive of the display device DSP are performed, for example, within one frame period. In one example, the one-frame period is divided into a first period for displaying an image and a second period for detecting an object to be detected. In the first period, the display drive for writing the video signal to all the pixels PX of the display area DA is performed in a time-division manner (display period). Further, in the second period following the first period, the sensing drive for detecting the object to be detected is time-divisioned in the entire display area DA (detection period or sensing period). A common drive signal is supplied to the drive electrode Tx in the first period, and a sensor drive signal is supplied in the second period.

Although the sensing by the mutual capacitance method has been described here, the sensor device may have a configuration capable of sensing by the self-capacity method.

FIG. 12 is a plan view schematically showing an equivalent circuit connected to the drive electrodes TX1 to TXn.
In the illustrated example, the display device DSP is the first switch group SWG1, the second switch group SWG2, the third switch group SWG3 formed in the selector SD, the fourth switch group SWG4, the fifth switch group SWG5, and the first supply. It includes a wire 30, a second supply line 40, and the like.

In the illustrated example, the first to fifth switch groups SWG1 to SWG5 are all formed in a region overlapping with the second substrate SUB2 in a plan view. The first switch group SWG1, the selector SD (third switch group SWG3), and the fourth switch group SWG4 are arranged on the drive IC chip 2 side with respect to the display area DA. The third switch group SWG3 is arranged between the first switch group SWG1 and the fourth switch group SWG4. Further, the second switch group SWG2 and the fifth switch group SWG5 are arranged on the side opposite to the drive IC chip 2 side of the display area DA. The fifth switch group SWG5 is arranged between the second switch group SWG2 and the display area DA.

The selector SD is connected to the drive IC chip 2 via a plurality of video lines VL. The selector SD is controlled by the drive IC chip 2 and selectively supplies a video signal to each signal line S. The third switch group SWG3 is included in the selector SD and is sometimes called a multiplexer.

_{A common voltage VCOM} for displaying an image is applied to the first supply line 30. The first supply line 30 branches from both sides of the drive IC chip 2 through both sides of the first switch group SWG1, one passes between the first switch group SWG1 and the third switch group SWG3, and the other. , Extends toward the second switch group SWG2, passes between the second switch group SWG2 and the fifth switch group SWG5, and is connected to the second switch group SWG2.

A drive signal for touch detection is supplied to the second supply line 40. In this embodiment, the second supply line 40 includes a low-voltage line 41 to the first voltage _{V TPL} is applied, a high voltage line 42 which is higher than the first voltage _{V TPL} second voltage _{V TPH} is applied, Includes. The low voltage line 41 passes through both sides of the drive IC chip 2 and is arranged between the first switch group SWG1 and the third switch group SWG3. Further, the high voltage line 42 passes through both sides of the drive IC chip 2 and is arranged between the first switch group SWG1 and the drive IC chip 2.

For example, the first supply line 30, the low voltage line 41, and the high voltage line 42 are connected to the touch detection IC chip 4 via the flexible wiring board FPC3. The first supply line 30, the low voltage line 41 and the high voltage line 42 may be connected to the drive IC chip 2.

The first switch group SWG1 includes a plurality of switches SW1 provided for each of the drive electrodes TX1 to TXn. The switch SW1 switches the connection destination of the drive electrodes TX1 to TXn between the first supply line 30 and the second supply line 40 (low voltage line 41 or high voltage line 42). Specifically, the switch SW1 is between the common voltage switch SWC that turns on or off the connection between the drive electrodes TX1 to TXn and the first supply line 30, and the drive electrodes TX1 to TXn and the low voltage line 41. It includes a low voltage switch SWL that turns the connection on or off, and a high voltage switch SWH that turns the connection between the drive electrodes TX1 to TXn and the high voltage line 42 on or off. For example, the common voltage switch SWC, the low voltage switch SWL, and the high voltage switch SWH are all turned on or off by the control of the drive IC chip 2.

The second switch group SWG2 includes a plurality of switches SW2 provided for each of the drive electrodes TX1 to TXn. The switch SW2 turns on or off the connection between the drive electrodes TX1 to TXn and the first supply line 30. For example, the switch SW2 is turned on or off by the control of the drive IC chip 2.

The third switch group SWG3 includes a plurality of switches SW3 provided for each signal line S provided in the display area DA. The switch SW3 is connected to the drive IC chip 2 via the video line VL, and turns on or off the connection between each signal line S and the drive IC chip 2. For example, the third switch SW3 is turned on or off so as to sequentially supply the video signals to be supplied to the pixel electrodes in a time-division manner to each signal line S under the control of the drive IC chip 2.

The fourth switch group SWG4 includes a plurality of switches SW4 provided for each signal line S. The switch SW4 turns on or off the connection between the signal line S and the drive electrodes TX1 to TXn. For example, the switch SW4 is turned on or off by the control of the drive IC chip 2.

The fifth switch group SWG5 includes a plurality of switches SW5 provided for each signal line S. The switch SW5 turns on or off the connection between the signal line S and the drive electrodes TX1 to TXn. For example, the switch SW5 is turned on or off by the control of the drive IC chip 2.

In the illustrated example, the metal wirings MA1 to Mann are connected to the drive electrodes TX1 to TXn adjacent to each other on the left side of the metal wirings MA1 to Mann. The metal wirings MA1 to Mann are connected to the drive electrodes TX1 to TXn in the non-detection region NDR. Further, the metal wirings MA1 to Mann are connected to the drive electrodes TX1 to TXn in the non-display region NDA. Of the metal wiring MA1 to Man, the metal wiring excluding the metal wiring MAn is arranged so as to overlap the gap GP between the drive electrodes TX1 to TXn. The metal wiring Man is arranged along the fourth end E4 of the display area DA.

The metal wirings MA1 to MAn overlap with a signal line (not shown). The signal lines arranged so as to overlap the metal wirings MA1 to Man are also connected to the drive electrodes TX1 to TXn adjacent to each other on the left side. For example, in the configurations shown in FIGS. 4 and 6, the signal line S2 is connected to the pixel electrode PE1 on the left side, and the metal wiring M2 is electrically connected to the common electrode CE1 on the left side in the non-display region. Will be done.

The metal wiring MB is arranged along the third end E3 of the display area DA. The metal wiring MB is connected to the first supply line 30 to which the _{common voltage VCOM is applied.}

As described above, the metal wiring MB is arranged along the third end E3, and the metal wiring Man is arranged along the fourth end E4. Therefore, when the first substrate SUB1 and the second substrate SUB2 are attached so as to be displaced in the first direction X, the area contributing to the display by the pixels on the third end E3 side and the pixels on the fourth end E4 side. Can be equivalent. Further, since the common voltage _VCOM is applied to the metal wiring MB, it is possible to avoid the coupling that occurs between the metal wiring MB and the drive electrode TX1 adjacent to the right side of the metal wiring MB.

Here, the operation of each switch group SWG1 to SWG5 in the first period and the second period will be described.
In the first period, which is the display period for displaying an image, the common voltage switch SWC of each switch SW1, each switch SW2 and each switch SW3 are turned on, and each switch SW4 and each switch SW5 are turned off. Thus, each drive electrodes TX1 to TXn common voltage _{V COM} is applied. Further, a video signal is supplied from the drive IC chip 2 to each signal line S.

In the second period of sensing for detecting the approach or contact of the object to be detected with the display device DSP, for example, the sensor drive signal Vw is sequentially supplied to the drive electrodes TX1 to TXn. The connection mode of the switch SW1 is different between the drive electrode TX of the sensor drive signal Vw supply target (hereinafter referred to as the drive target) and the remaining drive electrode TX. FIG. 12 shows a case where the drive electrode TX2 is a drive target. The common voltage switch SWC of the drive electrode TX2 to be driven is turned off, and the common voltage switch SWCs of the remaining drive electrodes TX are all turned on. The switch SW2 and the switch SW3 are all turned off, and the switch SW4 and the switch SW5 are all turned on.

The connection destination of the drive electrode TX2 to be driven is swung between the low voltage line 41 and the high voltage line 42. That is, the low voltage switch SWL and the high voltage switch SWH provided for the drive electrode TX2 are alternately turned on or off. As a result _{, a sensor drive signal Vw that toggles between the first voltage VTPL} and the second voltage _VTPH is generated, and this sensor drive signal Vw is supplied to the drive electrode TX2. Based on the detection signal obtained from the detection electrode with respect to this sensor drive signal Vw, the touch detection IC chip 4 detects the position of the object to be detected approaching or in contact with the display device DSP.

Since the switch SW4 and the switch SW5 are turned on, each signal line S has the same potential as the connected drive electrodes TX1 to TXn. As a result, it is possible to prevent the formation of a capacitance between each signal line S and each drive electrode TX1 to TXn, and improve the accuracy of touch detection. In the illustrated example, since each signal line S is connected to the drive electrode TX at both ends when viewed on the second direction Y side of each drive electrode TX, the drive electrode TX and the signal line S are covered as a whole. The same potential can be stably obtained.

In the second period of sensing, each video line VL between the drive IC chip 2 and the third switch group SWG3 becomes floating, reducing the occurrence of unnecessary capacitance formation due to the potential of each video line VL. be able to. In the second period, all or part of the switch SW4 and the switch SW5 may be turned off, whereby all or part of the signal line S may be floated.

The drive electrode TX to be driven may be selected in order from the drive electrode TX1 toward the drive electrode TXn, or may be selected in another order. Further, a plurality of drive electrodes TX may be selected as drive targets at the same time. Further, the drive electrodes TX1 to TXn may be selected as one drive target in one second period, or the drive electrodes TX1 to TXn may be dispersed in two or more second periods and the drive electrodes TX1 to TXn may be selected as drive targets. It may be selected.

FIG. 13 is a plan view showing the connection relationship between the drive electrode TX1 and the metal wiring MA1.
In the illustrated example, the drive electrode TX1 has protrusions T1 and T2 protruding in the first direction X. The protrusions T1 and T2 are arranged in the non-display region NDA, and are arranged at intervals from the drive electrode TX2 shown in FIG. As shown in FIG. 12, the metal wiring MA1 is arranged at a position overlapping the gap GP between the drive electrode TX1 and the drive electrode TX2. The metal wiring MA1 is connected to the protrusion T1 on one end side via a contact hole CHDa formed so as to overlap the protrusion T1. Further, the metal wiring MA1 is connected to the protruding portion T2 on the other end side via a contact hole CHDb formed so as to overlap the protruding portion T2. The contact holes CHDa and CHDb are formed in the fifth insulating film 15 in the same manner as the contact holes CHb shown in FIG.

The metal wiring MC is arranged so as to overlap the drive electrode TX1 at a position different from the position where the metal wiring MC overlaps the gap GP. The metal wiring MC is connected to the drive electrode TX1 via the contact hole CHC in the display area DA. The contact hole CHC is formed on the fifth insulating film 15 in the same manner as the contact hole CHb shown in FIG.
As described above, the metal wiring MA1 is connected to the detection electrode TX1 in the non-display region NDA.

FIG. 14 is a plan view showing another embodiment of the connection relationship between the drive electrode TX1 and the metal wiring MA1. FIG. 14 is different from the configuration shown in FIG. 13 in that the metal wiring MA1 is connected to the connection electrode MD.
The metal wiring MA1 and MC are arranged so as to extend to the non-display area NDA. The connection electrode MD is connected to the metal wiring MA1 and MC in the non-display region NDA. That is, the metal wiring MA1, the metal wiring MC, and the connection electrode MD have the same potential. Further, the metal wiring MA1, the metal wiring MC, and the connection electrode MD are connected to the drive electrode TX1 via the contact hole CHC. The connection electrode MD, the metal wiring MA1, and the metal wiring MC are arranged on the fourth insulating film 14 in the same manner as the metal wirings M1 to M4 shown in FIG. Further, the connection electrode MD, the metal wiring MA1, and the metal wiring MC are made of, for example, the same material.
As described above, the metal wiring MA1 is connected to the detection electrode TX1 in the non-display region NDA.

As described above, according to the present embodiment, it is possible to obtain a display device and a sensor device capable of suppressing deterioration of display quality.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

DSP ... Display device S1 to S4 ... Signal line M1 to M4 ... Metal wiring
14 ... 4th insulating film 15 ... 5th insulating film CE1, CE2 ... Common electrode GP ... Gap
PE1 to PE6 ... Pixel electrodes CHa, CHb, CHc, CHd ... Contact holes.

Claims (4)

The display area for displaying images and
The first signal line and
A scanning line that intersects the first signal line and extends in the first direction,
Inorganic insulating film and
A first metal wiring that overlaps with the first signal line, extends in parallel with the first signal line, and is in contact with the first surface of the inorganic insulating film.
A first common electrode and a second common electrode in contact with a second surface opposite to the first surface of the inorganic insulating film are provided.
The gap between the first common electrode and the second common electrode overlaps with the first signal line and the first metal wiring.
The first metal wiring is connected to the first common electrode and is connected to the first metal wiring .
The first common electrode has a first protruding portion and a second protruding portion protruding in the first direction.
The gap is located between the first protrusion and the second protrusion.
The first metal wiring is connected to the first common electrode via a first contact hole formed in the inorganic insulating film at a position where the first protrusion is provided.
The first metal wiring is a display device connected to the first common electrode via a second contact hole formed in the inorganic insulating film at a position where the second protrusion is provided. The display area for displaying images and
A non-display area surrounding the display area and
The first signal line and
A scanning line that intersects the first signal line and extends in the first direction,
Inorganic insulating film and
A first metal wiring that overlaps with the first signal line, extends in parallel with the first signal line, and is in contact with the first surface of the inorganic insulating film.
The first common electrode and the second common electrode in contact with the second surface opposite to the first surface of the inorganic insulating film,
A second metal wiring and a connection electrode in contact with the first surface of the inorganic insulating film,
Equipped with
The gap between the first common electrode and the second common electrode overlaps with the first signal line and the first metal wiring.
The first metal wiring is connected to the first common electrode and is connected to the first metal wiring.
The second metal wiring extends in parallel with the first metal wiring and is connected to the first common electrode via a third contact hole formed in the inorganic insulating film.
The first metal wiring and the second metal wiring are connected to each other by the connection electrode extending in the first direction.
The third contact hole is located in the display area and is located in the display area.
A display device in which the connection electrode is located in the non-display area. A pixel electrode in contact with the first surface of the inorganic insulating film is provided.
The display device according to claim 1 or 2 , wherein the pixel electrode faces the first common electrode. A non-display area surrounding the display area is provided.
The display device according to claim 1 , wherein the first protruding portion and the second protruding portion are located in the non-display area.

Images