JP2017129615A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of suppressing deterioration in display quality.SOLUTION: A display device comprises a display panel in which a liquid crystal layer is held between a first substrate and a second substrate. The first substrate includes: an insulation substrate; a gate wire; a frist source wire and a second source wire intersecting with the gate wire; a switching element electrically connected to the gate wire and the first source wire; a first light shielding layer that individually covers the switching element, the first source wire, and the second source wire and is formed with an opening between the first source wire and the second source wire; and a pixel electrode electrically connected to the switching element.SELECTED DRAWING: Figure 6

Description

  Embodiments described herein relate generally to a display device.

2. Description of the Related Art Active matrix drive display devices widely employ a configuration using thin film transistors (hereinafter sometimes referred to as TFTs) as pixel electrode switching elements.
When the TFT is in an OFF state, light leaks when light enters the TFT semiconductor layer, and the pixel potential held in the pixel capacitor fluctuates. Therefore, there is a possibility that display quality is deteriorated due to flicker or the like.
As a means for suppressing light leakage, a method is known in which a light shielding layer is provided on the lower layer side of a TFT to suppress light that is directly incident on the TFT from a backlight unit (Patent Document 1).

JP-A-11-84359

  When the display device is driven at a low frequency or intermittently, the holding time of the pixel potential becomes long, and thus a display device that can further suppress light leakage is demanded. Further, the light incident on the TFT includes not only light directly incident from the backlight unit, but also light incident on the substrate layer by being subjected to multiple reflections. For this reason, further measures are required.

  An object of the present embodiment is to provide a display device capable of suppressing deterioration in display quality.

  According to this embodiment, the display panel having the liquid crystal layer held between the first substrate and the second substrate is provided, and the first substrate is an insulating substrate, a gate wiring, and a first source wiring intersecting the gate wiring. And the second source wiring, the switching element electrically connected to the gate wiring and the first source wiring, and the switching element, the first source wiring, and the second source wiring, respectively, and the first source wiring and the second source wiring There is provided a display device including a first light-shielding layer having an opening between and a pixel electrode electrically connected to a switching element.

FIG. 1 is a perspective view schematically showing the configuration of the liquid crystal display device DSP. FIG. 2 is a schematic view showing a cross section of the liquid crystal display panel PNL. FIG. 3 is a plan view showing a schematic configuration of the array substrate AR. FIG. 4 is a plan view of the array substrate AR showing a schematic configuration of the unit pixels PX1 and PX2. FIG. 5 is a schematic plan view showing a part of the sub-pixel PXR1 shown in FIG. FIG. 6 is a schematic cross-sectional view of the array substrate AR shown along the line AB in FIG. FIG. 7 is a schematic cross-sectional view of the liquid crystal display panel PNL shown along line CD in FIG.

  Hereinafter, an embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the sake of clarity, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part as compared to actual aspects, but are merely examples, and The interpretation is not limited. In each drawing, the reference numerals may be omitted for the same or similar elements arranged in succession. In addition, in the present specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are denoted by the same reference numerals, and redundant detailed description may be omitted.

  In the present embodiment, a liquid crystal display device is disclosed as an example of a display device. The liquid crystal display device can be used for various devices such as a smartphone, a tablet terminal, a mobile phone terminal, a personal computer, a television receiver, an in-vehicle device, and a game machine. Note that the main configuration disclosed in this embodiment includes a self-luminous display device having an organic electroluminescence display element, an electronic paper display device having an electrophoretic element, and a micro electro mechanical systems (MEMS). The present invention can also be applied to a display device to which application is applied or a display device to which electrochromism is applied.

FIG. 1 is a perspective view schematically showing the configuration of the liquid crystal display device DSP. Here, the first direction X and the second direction Y are orthogonal to each other. The third direction Z is orthogonal to each of the first direction X and the second direction Y.
The liquid crystal display device DSP includes an active matrix type liquid crystal display panel PNL, a drive IC chip IC that drives the liquid crystal display panel PNL, a backlight unit BL that illuminates the liquid crystal display panel PNL, a control module CM, flexible wiring boards FPC1, FPC2, etc. It has.

  The liquid crystal display panel PNL includes an array substrate AR and a counter substrate CT disposed to face the array substrate AR. In the present embodiment, the array substrate AR functions as a first substrate, and the counter substrate CT functions as a second substrate. The liquid crystal display panel PNL includes a display area DA for displaying an image and a frame-shaped non-display area NDA surrounding the display area DA. The liquid crystal display panel PNL includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y in the display area DA.

  The backlight unit BL is disposed on the back surface of the array substrate AR. As such a backlight unit BL, various forms can be applied, but a detailed description of the structure is omitted. The driving IC chip IC is mounted on the array substrate AR. The flexible wiring board FPC1 connects the liquid crystal display panel PNL and the control module CM. The flexible wiring board FPC2 connects the backlight unit BL and the control module CM.

  The liquid crystal display device DSP having such a configuration corresponds to a so-called transmissive liquid crystal display device that displays an image by selectively transmitting light incident on the liquid crystal display panel PNL from the backlight unit BL through each pixel PX. To do. However, the liquid crystal display device DSP may be a reflective liquid crystal display device that displays an image by selectively reflecting external light incident on the liquid crystal display panel PNL from the outside by each pixel PX. It may be a transflective liquid crystal display device having both transmissive and reflective functions.

FIG. 2 is a schematic view showing a cross section of the liquid crystal display panel PNL.
The liquid crystal display panel PNL includes an array substrate AR, a counter substrate CT, a liquid crystal layer LQ, a sealing material SE, a first optical element OD1, a second optical element OD2, and the like. Details of the array substrate AR and the counter substrate CT will be described later.

  The sealing material SE is disposed in the non-display area NDA and bonds the array substrate AR and the counter substrate CT together. The liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT. The first optical element OD1 is disposed on the opposite side of the surface in contact with the liquid crystal layer LQ of the array substrate AR. The second optical element OD2 is disposed on the opposite side of the surface in contact with the liquid crystal layer LQ of the counter substrate CT. Each of the first optical element OD1 and the second optical element OD2 includes a polarizing plate. Note that the first optical element OD1 and the second optical element OD2 may include other optical elements such as a phase difference plate.

FIG. 3 is a plan view showing a schematic configuration of the array substrate AR.
The array substrate AR includes a gate line G, a source line S, a pixel electrode PE, a counter electrode CE, a switching element SW, a first drive circuit DR1, a second drive circuit DR2, a third drive circuit DR3, and the like.

  The plurality of gate lines G extend in the first direction X and are arranged at intervals in the second direction Y in the display area DA. In this embodiment, the gate line G extends linearly in the first direction X. The plurality of source lines S extend in the second direction Y in the display area DA, intersect the plurality of gate lines G, and are arranged at intervals in the first direction X. Note that the source wiring S does not necessarily extend linearly, and a part thereof may be bent or may extend in a direction intersecting the first direction X and the second direction Y. The pixel electrode PE and the switching element SW are disposed in each pixel PX. The switching element SW is electrically connected to the gate line G and the source line S. The pixel electrode PE is electrically connected to the switching element SW. The common electrode CE is disposed over the plurality of pixels PX, and forms a pixel capacitor CS with the pixel electrode PE.

  The first drive circuit DR1, the second drive circuit DR2, and the third drive circuit DR3 are arranged in the non-display area NDA. The first drive circuit DR1 is electrically connected to the gate line G drawn to the non-display area NDA. The second drive circuit DR2 is electrically connected to the source line S drawn to the non-display area NDA. The third drive circuit DR3 is electrically connected to the common electrode CE. The first drive circuit DR1 outputs a control signal for controlling on / off of the switching element SW to each gate line G. The second drive circuit DR2 outputs an image signal to each source line S. The third drive circuit DR3 controls the voltage applied to the common electrode CE.

FIG. 4 is a plan view of the array substrate AR showing a schematic configuration of the unit pixels PX1 and PX2.
In the illustrated example, the unit pixels PX1 and PX2 have a configuration corresponding to an FFS (Fringe Field Switching) mode as a display mode, but the illustration of the common electrode is omitted. The array substrate AR includes gate wirings G1 to G2, source wirings S1 to S4, a light shielding layer SH1, and a light shielding layer SH2. The light shielding layer SH1 is indicated by hatching in the drawing. The light shielding layer SH2 is indicated by a one-dot chain line in the drawing. In the present embodiment, the light shielding layer SH2 functions as a first light shielding layer, and the light shielding layer SH1 functions as a second light shielding layer.

  The unit pixels PX1 and PX2 are formed between the source line S1 and the source line S4. The unit pixels PX1 and PX2 are adjacent to each other in the second direction Y across the gate line G2. Each of the unit pixels PX1 and PX2 corresponds to a minimum unit for displaying a color image. The unit pixel PX1 includes a sub-pixel PXR1, a sub-pixel PXG1, and a sub-pixel PXB1. The unit pixel PX2 includes a sub-pixel PXR2, a sub-pixel PXG2, and a sub-pixel PXB2. The subpixel PXR1 and the subpixel PXR2 are pixels that display the first color. The subpixel PXG1 and the subpixel PXG2 are pixels that display a second color different from the first color. The subpixel PXB1 and the subpixel PXB2 are pixels that display a third color different from the first color and the second color. In one example, the first color is red, the second color is green, and the third color is blue.

  However, the unit pixels PX1 and PX2 may include sub-pixels that display colors other than red, blue, and green. Further, the shape of the sub-pixel is not limited to the rectangular example as illustrated, but may be a square or a substantially parallelogram. The areas of the sub-pixels may have different areas. The layout of the sub-pixels is not limited to the illustrated example.

  The subpixel PXR1 includes a switching element SWR1 electrically connected to the source line S1 and the gate line G1, and a pixel electrode PER1 electrically connected to the switching element SWR1. The subpixel PXG1 includes a switching element SWG1 electrically connected to the source line S2 and the gate line G1, and a pixel electrode PEG1 electrically connected to the switching element SWG1. The subpixel PXB1 includes a switching element SWB1 electrically connected to the source line S3 and the gate line G1, and a pixel electrode PEB1 electrically connected to the switching element SWB1. The subpixel PXR2 includes a switching element SWR2 electrically connected to the source line S1 and the gate line G2, and a pixel electrode PER2 electrically connected to the switching element SWR2. The subpixel PXG2 includes a switching element SWG2 electrically connected to the source line S2 and the gate line G2, and a pixel electrode PEG2 electrically connected to the switching element SWG2. The subpixel PXB2 includes a switching element SWB2 electrically connected to the source line S3 and the gate line G2, and a pixel electrode PEB2 electrically connected to the switching element SWB2. In the present embodiment, the source line S1 functions as a first source line, and the source line S2 functions as a second source line.

  The pixel electrode PER1 and the pixel electrode PER2 are formed between the source line S1 and the source line S2. The pixel electrode PER1 and the pixel electrode PER2 are adjacent to each other in the second direction Y across the gate line G2. The pixel electrode PEG1 and the pixel electrode PEG2 are formed between the source line S2 and the source line S3. The pixel electrode PEG1 and the pixel electrode PEG2 are adjacent to each other in the second direction Y across the gate wiring G2. The pixel electrode PEB1 and the pixel electrode PEB2 are formed between the source line S3 and the source line S4. The pixel electrode PEB1 and the pixel electrode PEB2 are adjacent to each other in the second direction Y across the gate wiring G2.

As will be described later, the light shielding layer SH1 is disposed on the lower layer side than the switching element. The light shielding layer SH <b> 1 is arranged at a position overlapping the switching elements illustrated in a simplified manner in plan view of the array substrate AR.
As will be described later, the light shielding layer SH2 is disposed on the upper layer side of the switching element. The light shielding layer SH2 is arranged at a position that covers each of the switching elements and the source wirings S1 to S4 shown in a simplified manner in plan view of the array substrate AR. The light shielding layers SH1 and SH2 are not disposed in the upper layer or the lower layer of each pixel electrode. In other words, the light shielding layer SH1 is formed in an island shape, and is individually arranged at a position overlapping each switching element. In the light shielding layer SH2, an opening is formed between adjacent source lines. A region surrounded by the light shielding layers SH1 and SH2 is a region contributing to display. The light shielding layer SH2 is preferably arranged at a position that covers the gate wirings G1 and G2 in plan view of the array substrate AR. However, in the illustrated example, the opening of the light shielding layer SH2 intersects the gate wirings G1 and G2.

  The above-described light shielding layer SH2 will be described more specifically. The light shielding layer SH2 covers the source lines S1 to S4, respectively. The light shielding layer SH2 has openings OP1 to OP3 between the source wiring S1 and the source wiring S2, between the source wiring S2 and the source wiring S3, and between the source wiring S3 and the source wiring S4, respectively. Is formed. The openings OP1 to OP3 intersect with the gate lines G1 and G2, respectively, and are connected in the second direction Y. The pixel electrodes PER1 and PER2 are arranged in the opening OP1, the pixel electrodes PEG1 and PEG2 are arranged in the opening OP2, and the pixel electrodes PEB1 and PEB2 are arranged in the opening OP3. The common electrode CE is disposed in each of the openings OP1 to OP3, and faces the six pixel electrodes shown in the figure. Further, the common electrode CE extends in the first direction X beyond the light shielding layer SH2. The common electrode CE extends in the second direction Y beyond the gate lines G1 and G2.

FIG. 5 is a schematic plan view showing a part of the sub-pixel PXR1 shown in FIG.
The switching element SWR1 includes a semiconductor layer SC1. The semiconductor layer SC1 is formed in an L shape, for example. The gate line G1 has a main part GA extending in the first direction X and a branch part GB branched from the main part GA and extending in the second direction Y. The semiconductor layer SC1 intersects with the main part GA and the branch part GB of the gate wiring G1 at two points. That is, in the illustrated example, the switching element SWR1 is configured by a double-gate thin film transistor. Note that the semiconductor layer SC1 may be formed in a U-shape, and in this case, a double-gate thin film transistor in which the semiconductor layer SC1 intersects with the gate wiring G1 having no branch portion at two locations may be configured. it can. Further, the semiconductor layer SC1 may be formed in an I-shape, and in this case, a single-gate thin film transistor in which the semiconductor layer SC1 intersects at only one point of the branch portion GB of the gate wiring G1 can be configured.

One end of the semiconductor layer SC1 is electrically connected to the source line S1 through the contact hole CH11, extends in the second direction Y at a position overlapping the source line S1, and bends in the middle thereof to be bent in the first direction X The other end is electrically connected to the relay electrode RE1 through the contact hole CH12.
The relay electrode RE1 is located between the source line S1 and the source line S2. The pixel electrode PER1 is electrically connected to the relay electrode RE1. The pixel electrode PER1 has a comb electrode T1. The comb electrodes T1 extend in parallel to each other, and extend in the second direction Y in the illustrated example.

FIG. 6 is a schematic cross-sectional view of the array substrate AR shown along the line AB in FIG.
The array substrate AR is formed using a first insulating substrate 10 having optical transparency such as a glass substrate or a resin substrate. The array substrate AR includes a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a light shielding layer SH1, a light shielding layer SH2, a switching element SWR1, a pixel electrode PER1, a common electrode CE, a first electrode One alignment film AL1 is provided. In the illustrated example, the switching element SWR1 has a top gate structure, but may have a bottom gate structure.

  The light shielding layer SH1 is formed on the first insulating substrate 10 at a position corresponding to the switching element SWR1. The first insulating film 11 is formed on the first insulating substrate 10 and the light shielding layer SH1. The semiconductor layer SC1 of the switching element SWR1 is formed on the first insulating film 11. The semiconductor layer SC1 is formed of, for example, polycrystalline silicon, but may be formed of amorphous silicon, an oxide semiconductor, or the like.

  The second insulating film 12 is formed on the first insulating film 11 and the semiconductor layer SC1. The gate wiring G1 is formed on the second insulating film 12, and faces the semiconductor layer SC1 at two places. The third insulating film 13 is formed on the gate wiring G1 and the second insulating film 12. The source line S1 and the relay electrode RE1 are formed on the third insulating film 13. The source line S1 is in contact with the semiconductor layer SC1 through a contact hole CH11 that penetrates the second insulating film 12 and the third insulating film 13.

  The relay electrode RE1 is in contact with the semiconductor layer SC1 through a contact hole CH12 that penetrates the second insulating film 12 and the third insulating film 13. Focusing on the positional relationship between the light shielding layer SH1 and the switching element SWR1, the light shielding layer SH1 is located between the first insulating substrate 10 and the semiconductor layer SC1, and in particular, the position where the gate wiring G1 and the semiconductor layer SC1 face each other. Located in the lower layer.

  The light shielding layer SH2 is formed on the third insulating film 13 and the source line S1. In the opening OP1 of the light shielding layer SH2, the relay electrode RE1 and the surrounding third insulating film 13 are exposed. Focusing on the positional relationship between the light shielding layer SH2 and the switching element SWR1, the light shielding layer SH2 is located in an upper layer where the gate wiring G1 and the semiconductor layer SC1 face each other.

  The common electrode CE is formed on the light shielding layer SH2. A part of the common electrode CE is located in the opening OP <b> 1 and is formed on the third insulating film 13. The fourth insulating film 14 is formed on the light shielding layer SH2 and the common electrode CE. The fourth insulating film 14 is formed on the third insulating film 13, the relay electrode RE1, and the common electrode CE in the opening OP1. The first insulating film 11, the second insulating film 12, the third insulating film 13, and the fourth insulating film 14 are formed of an inorganic material such as silicon nitride (SiN) or silicon oxide (SiO), for example. . The light shielding layer SH2 is a black resin layer having a light shielding property, and is formed of an organic material such as an acrylic resin in which a black pigment is dispersed.

  The pixel electrode PER1 is formed on the fourth insulating film 14 and the relay electrode RE1. The pixel electrode PER1 is electrically connected to the relay electrode RE1 through a contact hole that penetrates the fourth insulating film 14. The pixel electrode PER1 is opposed to the common electrode CE with the fourth insulating film 14 interposed therebetween. The common electrode CE and the pixel electrode PER1 are formed of a transparent conductive material such as indium zinc oxide (IZO) or indium tin oxide (ITO). The first alignment film AL1 is formed on the fourth insulating film 14 and the pixel electrode PER1. The first alignment film AL1 is made of, for example, a material that exhibits horizontal alignment.

FIG. 7 is a schematic cross-sectional view of the liquid crystal display panel PNL shown along line CD in FIG.
In the array substrate AR, the source wirings S1 and S2 are formed on the third insulating film 13 and covered with the light shielding layer SH2. The light shielding layer SH2 has a tapered cross section that tapers toward the counter substrate CT. That is, the light shielding layer SH2 has a substantially flat upper surface SHT and an inclined surface SHS. The common electrode CE is formed on the third insulating film 13 in the opening OP1, is further formed on the upper surface SHT and the inclined surface SHS of the light shielding layer SH2, and is covered with the fourth insulating film 14. The pixel electrode PER1 is formed on the fourth insulating film 14 and is covered with the first alignment film AL1. The pixel electrode PER1 is opposed to the common electrode CE in the opening OP1 between the source line S1 and the source line S2.

  The counter substrate CT is formed using a second insulating substrate 20 having optical transparency such as a glass substrate or a resin substrate. The counter substrate CT includes a light shielding layer SH3, color filters CF1 and CF2, an overcoat layer OC, a second alignment film AL2, and the like.

  The light shielding layer SH3 is formed on the side of the second insulating substrate 20 facing the array substrate AR. The light shielding layer SH3 is formed at a position facing the gate wiring (not shown) and the source wirings S1 and S2. The color filter CF1 is opposed to the pixel electrode PER1. The color filter CF2 is opposed to the pixel electrode PEG1. The end portions of the color filters CF1 and CF2 overlap the light shielding layer SH3. The color filters CF1 and CF2 are each formed of a colored resin material. The overcoat layer OC is formed of a transparent resin material and covers the color filters CF1 and CF2. The second alignment film AL2 is formed on the side of the overcoat layer OC that faces the array substrate AR. The second alignment film AL2 is formed of a material exhibiting horizontal alignment.

  According to the present embodiment, the switching element has a structure sandwiched between the light shielding layer SH1 disposed in the lower layer and the light shielding layer SH2 disposed in the upper layer. The light shielding layer SH1 suppresses direct incidence of light from the backlight unit to the switching element. The light-shielding layer SH2 can suppress reflection on the side surface and the upper surface of the source wiring, and can suppress the incidence of light that is multiple-reflected at the interface of the layer of the array substrate with respect to the switching element. Thereby, generation | occurrence | production of light leak can be suppressed more effectively and the fluctuation | variation of the pixel electric potential hold | maintained at pixel capacity | capacitance can be suppressed. For this reason, it is possible to suppress deterioration in display quality due to flicker or the like due to light leakage even when driven at a low frequency or intermittently. In addition, the power consumption of the display device can be reduced by driving the display device at a low frequency or intermittently.

  Further, when comparing the array substrate described in the present embodiment and the array substrate of the comparative example provided with the transparent resin layer on the source wiring, the light shielding layer SH2 of the present embodiment is the same as the transparent resin layer of the comparative example. Can be replaced. For this reason, the light shielding layer SH2 can be manufactured without substantially increasing the number of manufacturing steps.

  In addition, there are almost no steps in the lower layer of the opening OP formed in the light shielding layer SH2 because no wiring or circuits are arranged. That is, a substantially flat surface is formed in the opening OP. Since the pixel electrode PE is disposed in the flat opening OP, it hardly affects the alignment of the liquid crystal molecules.

Further, the common electrode CE extends in the first direction X over the light shielding layer SH2 as well as the opening OP. Since the light shielding layer SH2 has a tapered cross section, disconnection of the common electrode CE over the light shielding layer SH2 can be suppressed.
Further, the position where the light shielding layer SH2 is arranged corresponds to the boundary between the different color sub-pixels. For this reason, it is possible to suppress color mixture between sub-pixels of different colors adjacent to each other in the first direction X. That is, color mixing occurs when light incident on the display panel PNL from an oblique direction inclined with respect to the normal line of the display panel PNL passes through color filters that do not match each other. In this way, mismatched light that passes through the color filters of adjacent subpixels and causes color mixing occurs at the boundary between adjacent subpixels. According to the present embodiment, among the light incident in the oblique direction, the light incident near the boundary is shielded by the light shielding layer SH2 and does not pass through the adjacent color filter. For this reason, it is difficult for the color mixture to be visually recognized, and display quality deterioration can be suppressed.

The light shielding layer SH2 covers the source wiring and is preferably disposed on the gate wiring. For this reason, in the array substrate AR, reflection of light incident from the counter substrate CT side on the source wiring and the gate wiring can be suppressed. For this reason, it is possible to suppress a decrease in contrast ratio due to reflection on the source wiring and the gate wiring. In that case, the light shielding layer SH3 of the counter substrate CT may be omitted. When the light shielding layer SH3 is omitted, it is possible to suppress a decrease in the aperture ratio due to misalignment between the array substrate AR and the counter substrate CT. Further, when the light shielding layer SH3 is not provided, the manufacturing process of the display device can be reduced.
As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing deterioration in display quality.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DSP ... Liquid crystal display device PNL ... Display panel G ... Gate wiring
S ... Source wiring SW ... Switching element PE ... Pixel electrode CE ... Common electrode PX ... Unit pixel CF ... Color filter SH ... Light shielding layer

Claims (6)

A display panel holding a liquid crystal layer between the first substrate and the second substrate;
The first substrate is
An insulating substrate;
Gate wiring,
A first source line and a second source line intersecting the gate line;
A switching element electrically connected to the gate line and the first source line;
A first light shielding layer that covers the switching element, the first source wiring, and the second source wiring, respectively, and an opening is formed between the first source wiring and the second source wiring;
A pixel electrode electrically connected to the switching element;
A display device comprising:   The display device according to claim 1, wherein the pixel electrode is disposed in the opening. The switching element includes a semiconductor layer between the insulating substrate and the gate wiring,
The display device according to claim 1, wherein the first substrate further includes a second light shielding layer between the insulating substrate and the semiconductor layer.   The display device according to claim 3, wherein the first light shielding layer is disposed at a position where the semiconductor layer and the gate wiring overlap.   5. The display device according to claim 1, wherein the first substrate further includes a common electrode facing the pixel electrode and extending in the first direction beyond the first light shielding layer. 6.   The display device according to claim 1, wherein the first light shielding layer is a black resin layer.

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