JP6973586B2 - Drive circuit - Google Patents

Description

The present invention relates to a drive circuit.

An inkjet printer that ejects ink to print an image or a document is known to use a piezoelectric element (for example, a piezo element). Piezoelectric elements are provided in the head unit corresponding to each of a plurality of nozzles, and when each is driven according to a drive signal, a predetermined amount of ink (liquid) is ejected from the nozzles at a predetermined timing, and dots are formed. Is formed. Since the piezoelectric element is a capacitive load like a capacitor when viewed electrically, it is necessary to supply a sufficient current in order to operate the piezoelectric element of each nozzle.

Therefore, the drive signal amplified by the amplifier circuit is supplied to the head unit to drive the piezoelectric element. As an amplifier circuit, a method of current-amplifying the source signal before amplification by class AB or the like can be mentioned, but since energy efficiency is poor, class D amplification has been proposed in recent years (see Patent Document 1).
In such class D amplification, in order to stabilize the frequency of self-oscillation, a PLL (Phase Locked Loop) is incorporated in the feedback path for self-oscillation, and the self-oscillation signal is used as the reference signal. A technique for following a frequency has been proposed (see Patent Document 2).

Japanese Unexamined Patent Publication No. 2010-114711 Japanese Unexamined Patent Publication No. 2013-118628

By the way, in the configuration in which the PLL is incorporated in the feedback path (loop) of the self-excited oscillation, an oscillation circuit for generating the reference signal is separately required, which causes the circuit to become complicated.
It has also been pointed out that in the above configuration, the reproducibility of the output signal after amplification is poor with respect to the source signal. One of the reasons for this is that the modulated signal in the middle stage is fed back instead of the output signal (final output) demodulated by the low-pass filter. If the reproducibility of the output signal with respect to the source signal is poor, ink ejection failure or the like is caused, and the print quality is deteriorated.
Therefore, one of the objects of some aspects of the present invention is to improve the reproducibility of the output signal with respect to the source signal with a relatively simple configuration in the liquid discharge device that amplifies the drive signal applied to the piezoelectric element in class D. The purpose of the present invention is to provide a technique capable of preventing deterioration of print quality.

In order to achieve one of the above objects, the liquid discharge device according to one aspect of the present invention includes a modulation circuit that generates a modulation signal in which a source signal is pulse-modulated by self-excited oscillation, and a modulation circuit that amplifies and amplifies the modulation signal. A low-pass filter that includes a transistor that generates a modulation signal, an oscillator, and a capacitor to smooth the amplification modulation signal to generate a drive signal, a feedback circuit that feeds back the drive signal to the modulation circuit, and a drive signal are applied. A piezoelectric element that is displaced by being oscillated, a cavity that is filled with droplets and whose internal volume changes due to the displacement of the piezoelectric element, and a cavity that discharges liquid in the cavity according to a change in the internal volume of the cavity. A nozzle provided for this purpose is provided, and the self-resonance frequency of the condenser is higher than the frequency of the self-excited oscillation.

According to the liquid discharge device according to this aspect, a separate oscillation circuit is not required, and the drive signal, which is the final output, is fed back. Therefore, a comparatively simple configuration prevents deterioration of print quality. be able to.
Further, when the self-resonant frequency of the condenser is made higher than the frequency of self-oscillation as in the liquid discharge device according to this aspect, abnormal oscillation (for example, oscillation at twice the frequency) or self-oscillation frequency is increased. It is possible to suppress the occurrence of variations and the like. Therefore, according to the liquid discharge device according to this aspect, the reproducibility of the waveform is improved, for example, the ripple of the drive signal filtered by the low-pass filter is reduced.
The frequency of self-oscillation means the frequency of the self-oscillation signal.
In the relatively low frequency region, the impedance of the capacitor decreases as the frequency increases, but in the high frequency region, it has a minimum value with respect to frequency changes due to losses such as parasitic inductance components and electrode specific resistance. Will be. The frequency with this minimum value is defined as the self-resonant frequency.
The source signal is a signal that is a source of a drive signal that defines the displacement of the piezoelectric element, that is, a signal before modulation, and is a signal that is a reference of the waveform of the drive signal (including a specified signal, analog, digital). It doesn't matter). The modulated signal is a digital signal obtained by pulse-modulating the source signal (for example, pulse width modulation, pulse density modulation, etc.).

By the way, in the liquid discharge device according to the above aspect, the amplification modulation signal is smoothed to generate a drive signal, and the piezoelectric element is displaced by the application of the drive signal to discharge the liquid from the nozzle. Here, when the waveform of the drive signal for the liquid discharge device to discharge small dots is analyzed by frequency spectrum, it is found that the frequency component of 50 kHz or more is contained. In order to generate a drive signal including such a frequency component of 50 kHz or more, it is necessary to set the frequency of self-oscillation (frequency of the modulated signal) to 1 MHz or more.
If the frequency is lower than 1 MHz, the edge of the waveform of the reproduced drive signal becomes dull and rounded. In other words, the corners are removed and the waveform becomes dull. When the waveform of the drive signal becomes dull, the displacement of the piezoelectric element that operates according to the rising and falling edges of the waveform becomes slow, causing tailing during ejection and ejection failure, and the print quality deteriorates. It ends up.
On the other hand, if the frequency of self-oscillation is higher than 8 MHz, the resolution of the waveform of the drive signal is improved. However, as the switching frequency of the transistor increases, the switching loss increases, and the power saving and heat saving properties, which are superior to the linear amplification of a class AB amplifier or the like, are impaired.
Therefore, in the liquid discharge device according to the above aspect, the frequency of the modulated signal is preferably 1 MHz or more and 8 MHz or less.

In the liquid discharge device according to the above aspect, the self-resonant frequency of the condenser is preferably 1.5 times or more the frequency of the self-excited oscillation. By setting the self-resonant frequency of the capacitor to 1.5 times or more the frequency of self-oscillation in this way, it is possible to further suppress the occurrence of abnormal oscillation and frequency variation of self-oscillation.

In the liquid crystal display device according to the above aspect, at least one of the modulation circuit, the transistor, the low-pass filter, and the feedback circuit may have a delay element. With such a delay element, the frequency of self-oscillation can be lowered.
The delay element is preferably a frequency cut filter. The frequency cut filter is, for example, a low-pass filter, a high-pass filter, or a band-pass filter.

Further, in the liquid crystal discharge device according to the above aspect, the condenser may be configured such that a plurality of elements are connected in parallel. That is, the capacitor of the low-pass filter may be configured by the combined capacitance of the elements connected in parallel. With this configuration, the self-resonant frequency of the capacitor can be increased.
The present invention can be realized in various aspects, such as a single head unit.

It is a figure which shows the schematic structure of the printing apparatus. It is a block diagram which shows the structure of a printing apparatus. It is a figure which shows the structure of the discharge part in a head unit. It is a figure which shows the nozzle arrangement in a head unit. It is a figure for demonstrating operation of a selection control part in a head unit. It is a figure which shows the structure of the selection control part in a head unit. It is a figure which shows the decoding content of the decoder in the head unit. It is a figure which shows the structure of the selection part in a head unit. It is a figure which shows the drive signal selected by a selection part. It is a figure which shows the structure of the drive circuit in a printing apparatus. It is a figure for demonstrating the operation of a drive circuit. It is a figure which shows the frequency characteristic of self-oscillation in a drive circuit. It is a figure which shows the phase difference characteristic in a drive circuit. It is a figure which shows the equivalent circuit of LPF in a drive circuit. It is a figure which shows the impedance characteristic of the inductor of LPF. It is a figure which shows the impedance characteristic of the capacitor of LPF. It is a figure which shows the impedance characteristic of the capacitor of LPF. It is a figure which shows the connection example of the capacitor in LPF. It is a top view which shows the wiring pattern of the circuit board on which a drive circuit is mounted. It is a figure which shows the arrangement of the element mounted on a circuit board. It is a figure which shows the positional relationship of the element mounted on a circuit board. It is a figure which shows the self-resonant frequency of a capacitor mounted on a circuit board. It is a figure which shows the parasitic inductance and the wiring inductance. It is a figure which shows the impedance characteristic of a capacitor in relation to the said inductance.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

The printing apparatus according to this embodiment forms an ink dot group on a printing medium such as paper by ejecting ink according to image data supplied from an external host computer, thereby responding to the image data. It is an ink jet printer that prints images (including characters, figures, etc.), that is, a liquid ejection device.

FIG. 1 is a perspective view showing a schematic configuration inside a printing apparatus.
As shown in this figure, the printing device 1 includes a moving mechanism 3 that moves (reciprocating) the moving body 2 in the main scanning direction.
The moving mechanism 3 extends substantially parallel to the carriage motor 31 that is the drive source of the moving body 2, the carriage guide shaft 32 having both ends fixed, and the carriage guide shaft 32, and is driven by the carriage motor 31. 33 and.
The carriage 24 of the moving body 2 is reciprocally supported by the carriage guide shaft 32 and is fixed to a part of the timing belt 33. Therefore, when the timing belt 33 is driven forward and reverse by the carriage motor 31, the moving body 2 is guided by the carriage guide shaft 32 and reciprocates.
Further, a head unit 20 is provided in a portion of the moving body 2 facing the print medium P. As will be described later, the head unit 20 is for ejecting ink droplets (droplets) from a large number of nozzles, and is configured to supply various control signals and the like via a flexible cable 190. ..

The printing apparatus 1 includes a transport mechanism 4 for transporting the print medium P on the platen 40 in the sub-scanning direction. The transport mechanism 4 includes a transport motor 41 that is a drive source, and a transport roller 42 that is rotated by the transport motor 41 to transport the print medium P in the sub-scanning direction.
When the print medium P is conveyed by the transfer mechanism 4, the head unit 20 ejects ink droplets onto the print medium P to form an image on the surface of the print medium P.

FIG. 2 is a block diagram showing an electrical configuration of a printing apparatus.
As shown in this figure, in the printing apparatus 1, the control unit 10 and the head unit 20 are connected via a flexible cable 190.
The control unit 10 includes a control unit 100, a carriage motor 31, a carriage motor driver 35, a transfer motor 41, a transfer motor driver 45, and two drive circuits 50-a and 50-b. Of these, the control unit 100 outputs various control signals and the like for controlling each unit when image data is supplied from the host computer.
Specifically, first, the control unit 100 supplies the control signal Ctr1 to the carriage motor driver 35, and the carriage motor driver 35 drives the carriage motor 31 according to the control signal Ctr1. This controls the movement of the carriage 24 in the main scanning direction.
Second, the control unit 100 supplies the control signal Ctr2 to the transfer motor driver 45, and the transfer motor driver 45 drives the transfer motor 41 according to the control signal Ctr2. As a result, the movement in the sub-scanning direction by the transport mechanism 4 is controlled.
Third, the control unit 100 supplies digital data dA to one of the two drive circuits 50-a and 50-b to the drive circuit 50-a, and digital data to the other drive circuit 50-b. Supply dB. Here, the data dA defines the waveform of the drive signal COM-A among the drive signals supplied to the head unit 20, and the data dB defines the waveform of the drive signal COM-B.
Although the details will be described later, the drive circuit 50-a supplies the class D amplified drive signal COM-A to the head unit 20 after analog conversion of the data dA. Similarly, the drive circuit 50-b supplies the class D amplified drive signal COM-B to the head unit 20 after analog conversion of the data dB. Further, regarding the drive circuits 50-a and 50-b, only the input data and the output drive signal are different, and the circuit configuration is the same as described later. Therefore, when it is not necessary to distinguish the drive circuits 50-a and 50-b (for example, when FIG. 10 described later is described), the "-(hyphen)" and below are omitted, and the reference numeral is simply "50". ".
Fourth, the control unit 100 supplies the clock signal Sck, the data signal Data, the control signal LAT, and CH to the head unit 20.

The head unit 20 is provided with a selection control unit 210, and a plurality of sets of the selection unit 230 and the piezoelectric element (piezo element) 60.
The selection control unit 210 is supplied by the control unit 100 as to whether the drive signals COM-A and COM-B should be selected (or neither should be selected) for each of the selection units 230. Instructed by a control signal or the like, the selection unit 230 selects the drive signals COM-A and COM-B according to the instruction of the selection control unit 210, and supplies them to one end of the piezoelectric element 60 as a drive signal. In the figure, the voltage of this drive signal is referred to as Vout.
_{In this example, the voltage VBS} is commonly applied to the other end of each of the piezoelectric elements 60.

The piezoelectric element 60 is provided corresponding to each of the plurality of nozzles in the head unit 20. The piezoelectric element 60 is displaced to eject ink in accordance with the difference between the voltage Vout and the voltage V _BS of the drive signal selected by the selection unit 230. Therefore, next, a configuration for ejecting ink by driving the piezoelectric element 60 will be briefly described.

FIG. 3 is a diagram showing a schematic configuration corresponding to one nozzle in the head unit 20.
As shown in the figure, the head unit 20 includes a piezoelectric element 60, a diaphragm 621, a cavity (pressure chamber) 631, a reservoir 641, and a nozzle 651. Of these, the diaphragm 621 functions as a diaphragm that is displaced (bending vibration) by the piezoelectric element 60 provided on the upper surface in the drawing to expand / reduce the internal volume of the cavity 631 filled with ink. The nozzle 651 is provided in the nozzle plate 632 and is an opening portion communicating with the cavity 631.

The piezoelectric element 60 shown in this figure has a structure in which the piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In the piezoelectric body 601 having this structure, the central portion of the piezoelectric body 601 together with the electrodes 611 and 612 and the diaphragm 621 bends in the vertical direction with respect to both end portions in the figure according to the voltage applied by the electrodes 611 and 612. Specifically, the piezoelectric element 60 is configured to bend upward when the voltage Vout of the drive signal is high, and to bend downward when the voltage Vout is low. In this configuration, bending upward increases the internal volume of the cavity 631 so that ink is drawn from the reservoir 641, while bending downward reduces the internal volume of the cavity 631 and thus the degree of shrinkage. In some cases, ink is ejected from the nozzle 651.

The piezoelectric element 60 is not limited to the structure shown in the figure, and may be any type as long as the piezoelectric element 60 can be deformed to discharge a liquid such as ink. Further, the piezoelectric element 60 is not limited to bending vibration, and may be configured to use so-called longitudinal vibration.
Further, the piezoelectric element 60 is provided in the head unit 20 corresponding to the cavity 631 and the nozzle 651, and the piezoelectric element 60 is also provided corresponding to the selection unit 230 in FIG. Therefore, a set of the piezoelectric element 60, the cavity 631, the nozzle 651, and the selection unit 230 will be provided for each nozzle 651.

FIG. 4A is a diagram showing an example of an arrangement of nozzles 651.
As shown in this figure, the nozzles 651 are arranged in two rows, for example, as follows. Specifically, when viewed in one row, a plurality of nozzles 651 are arranged at a pitch Pv along the sub-scanning direction, while in the two rows, the two rows are separated by the pitch Ph in the main scanning direction and the sub-scanning is performed. The relationship is such that the pitch Pv is shifted in the direction by half.
In the case of color printing, the nozzle 651 is provided with a pattern corresponding to each color such as C (cyan), M (magenta), Y (yellow), K (black), for example, along the main scanning direction. , In the following description, for the sake of simplification, a case where gradation is expressed by a single color will be described.

FIG. 4B is a diagram for explaining the basic resolution of image formation by the nozzle arrangement shown in FIG. 4A. In addition, this figure is an example of a method (first method) in which ink droplets are ejected once from a nozzle 651 to form one dot for simplification of explanation, and black circles are ink. It shows the dots formed by the impact of the drops.

When the head unit 20 moves at a velocity v in the main scanning direction, as shown in the figure, the spacing D (in the main scanning direction) of dots formed by the impact of ink droplets and the velocity v are The relationship is as follows.
That is, when one dot is formed by ejecting one ink droplet, the dot interval D is a value obtained by dividing the velocity v by the ink ejection frequency f (= v / f), in other words, the ink droplet is formed. It is indicated by the distance that the head unit 20 moves in the cycle of repeated ejection (1 / f).
In the example of FIG. 4, the pitch Ph is proportional to the dot spacing D by a coefficient n, and the ink droplets ejected from the two rows of nozzles 651 land on the print medium P so as to be aligned in the same row. I'm letting you. Therefore, as shown in (b), the dot spacing in the sub-scanning direction is half the dot spacing in the main scanning direction. Needless to say, the arrangement of dots is not limited to the illustrated example.

By the way, in order to realize high-speed printing, it is sufficient to simply increase the speed v at which the head unit 20 moves in the main scanning direction. However, simply increasing the speed v will increase the dot spacing D. Therefore, in order to realize high-speed printing while ensuring a certain resolution, it is necessary to increase the ink ejection frequency f and increase the number of dots formed per unit time.
In addition to the printing speed, in order to increase the resolution, the number of dots formed per unit area may be increased. However, when the number of dots is increased, if the amount of ink is not reduced, not only the adjacent dots are bonded to each other, but also the printing speed is lowered unless the ink ejection frequency f is increased.
As described above, in order to realize high-speed printing and high-resolution printing, it is necessary to increase the ink ejection frequency f.

On the other hand, as a method of forming dots on the print medium P, in addition to the method of ejecting ink droplets once to form one dot, the ink droplets can be ejected twice or more in a unit period, and the ink droplets can be ejected twice or more in a unit period. A method of forming one dot by landing one or more ejected ink droplets and combining the landed one or more ink droplets (second method), or combining these two or more ink droplets. There is a method of forming two or more dots (third method). In the following description, a case where dots are formed by the above-mentioned second method will be described.

In the present embodiment, the second method will be described assuming the following example. That is, in the present embodiment, for one dot, the ink is ejected at most twice to express four gradations of large dot, medium dot, small dot, and non-recording. In order to express these four gradations, in the present embodiment, two types of drive signals COM-A and COM-B are prepared, and each of them has a first half pattern and a second half pattern in one cycle. In one cycle, the drive signals COM-A and COM-B are selected (or not selected) according to the gradation to be expressed in the first half and the second half, and are supplied to the piezoelectric element 60.
Therefore, the drive signals COM-A and COM-B will be described, and then the configuration for selecting the drive signals COM-A and COM-B will be described. The drive signals COM-A and COM-B are generated by the drive circuit 50, respectively, but the drive circuit 50 is configured to select the drive signals COM-A and COM-B for convenience. It will be explained later.

FIG. 5 is a diagram showing waveforms and the like of drive signals COM-A and COM-B.
As shown in the figure, the drive signal COM-A is a trapezoidal waveform Adp1 arranged in the period T1 of the print cycle Ta from the time when the control signal LAT is output (starts up) to the time when the control signal CH is output. And the trapezoidal waveform Adp2 arranged in the period T2 from the output of the control signal CH to the output of the next control signal LAT in the print cycle Ta is a continuous waveform.

In the present embodiment, the trapezoidal waveforms Adp1 and Adp2 have substantially the same waveforms, and if each of them is supplied to one end of the piezoelectric element 60, a predetermined amount is specified from the nozzle 651 corresponding to the piezoelectric element 60. It is a waveform that ejects a medium amount of ink.

The drive signal COM-B is a waveform in which the trapezoidal waveform Bdp1 arranged in the period T1 and the trapezoidal waveform Bdp2 arranged in the period T2 are continuous. In the present embodiment, the trapezoidal waveforms Bdp1 and Bdp2 are different waveforms from each other. Of these, the trapezoidal waveform Bdp1 is a waveform for slightly vibrating the ink in the vicinity of the opening portion of the nozzle 651 to prevent an increase in the viscosity of the ink. Therefore, even if the trapezoidal waveform Bdp1 is supplied to one end of the piezoelectric element 60, ink droplets are not ejected from the nozzle 651 corresponding to the piezoelectric element 60. Further, the trapezoidal waveform Bdp2 has a waveform different from that of the trapezoidal waveform Adp1 (Adp2). If the trapezoidal waveform Bdp2 is supplied to one end of the piezoelectric element 60, it is a waveform that ejects an amount of ink smaller than the predetermined amount from the nozzle 651 corresponding to the piezoelectric element 60.

The voltage at the start timing of the trapezoidal waveforms Adp1, Adp2, Bdp1 and Bdp2 and the voltage at the end timing are all common to the voltage Vc. That is, the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are waveforms that start at the voltage Vc and end at the voltage Vc, respectively.

FIG. 6 is a diagram showing the configuration of the selection control unit 210 in FIG. 2.
As shown in this figure, the clock signal Sck, the data signal Data, the control signal LAT, and the CH are supplied to the selection control unit 210 from the control unit 10. In the selection control unit 210, a pair of a shift register (S / R) 212, a latch circuit 214, and a decoder 216 is provided corresponding to each of the piezoelectric elements 60 (nozzle 651).

The data signal Data defines the size of the dots in forming one dot in the image. In the present embodiment, the data signal Data is composed of two bits, a high-order bit (MSB) and a low-order bit (LSB), in order to represent four gradations of non-recording, small dots, medium dots, and large dots.
The data signal Data is serially supplied from the control unit 100 for each nozzle in synchronization with the clock signal Sck in accordance with the main scan of the head unit 20. The shift register 212 is configured to temporarily hold the serially supplied data signal Data for 2 bits corresponding to the nozzle.
Specifically, the shift registers 212 having the number of stages corresponding to the piezoelectric element 60 (nozzle) are connected in series with each other, and the serially supplied data signal Data is sequentially transferred to the subsequent stage according to the clock signal Sck. ing.
When the number of piezoelectric elements 60 is m (m is plural), in order to distinguish the shift register 212, one step, two steps, ..., M step in order from the upstream side to which the data signal Data is supplied. It is written as.

The latch circuit 214 latches the data signal Data held by the shift register 212 at the rising edge of the control signal LAT.
The decoder 216 decodes the 2-bit data signal Data latched by the latch circuit 214, and outputs the selection signals Sa and Sb for each period T1 and T2 defined by the control signal LAT and the control signal CH. , The selection in the selection unit 230 is specified.

FIG. 7 is a diagram showing the contents of decoding in the decoder 216.
In this figure, the latched 2-bit print data Data is referred to as (MSB, LSB). For example, if the latched print data Data is (0, 1), the decoder 216 sets the logic levels of the selection signals Sa and Sb to H and L levels in the period T1 and L and H levels in the period T2, respectively. , Means to output.
The logic levels of the selection signals Sa and Sb are level-shifted to higher amplitude logic by a level shifter (not shown) rather than the logic levels of the clock signal Sck, print data Data, control signal LAT, and CH.

FIG. 8 is a diagram showing a configuration of a selection unit 230 corresponding to one piezoelectric element 60 (nozzle 651) in FIG. 2.
As shown in this figure, the selection unit 230 has an inverter (NOT circuit) 232a, 232b and a transfer gate 234a, 234b.
The selection signal Sa from the decoder 216 is supplied to the positive control end not marked with a circle in the transfer gate 234a, while being logically inverted by the inverter 232a and the negative control marked with a circle in the transfer gate 234a. Supplied to the edge. Similarly, the selection signal Sb is supplied to the positive control end of the transfer gate 234b, while it is logically inverted by the inverter 232b and supplied to the negative control end of the transfer gate 234b.
The drive signal COM-A is supplied to the input end of the transfer gate 234a, and the drive signal COM-B is supplied to the input end of the transfer gate 234b. The output ends of the transfer gates 234a and 234b are commonly connected and connected to one end of the corresponding piezoelectric element 60.
The transfer gate 234a conducts (on) between the input end and the output end when the selection signal Sa is H level, and does not conduct between the input end and the output end when the selection signal Sa is L level. Turn it off. Similarly, the transfer gate 234b is turned on and off between the input end and the output end according to the selection signal Sb.

Next, the operation of the selection control unit 210 and the selection unit 230 will be described with reference to FIG.

The data signal Data is serially supplied from the control unit 100 to each nozzle in synchronization with the clock signal Sck, and is sequentially transferred in the shift register 212 corresponding to the nozzle. Then, when the control unit 100 stops the supply of the clock signal Sck, the data signal Data corresponding to the nozzle is held in each of the shift registers 212. The data signal Data is supplied in the order corresponding to the final m-stage, ..., 2-stage, and 1-stage nozzles in the shift register 222.
Here, when the control signal LAT rises, each of the latch circuits 214 latches the data signal Data held in the shift register 212 all at once. In FIG. 5, L1, L2, ..., Lm indicate the data signal Data in which the data signal Data is latched by the latch circuit 214 corresponding to the shift register 212 of the first stage, the second stage, ..., M stage.

The decoder 216 outputs the logic levels of the selection signals Sa and Sa as shown in FIG. 7 in each of the periods T1 and T2 according to the size of the dots defined by the latched data signal Data.
That is, first, when the data signal Data is (1, 1) and the size of the large dot is specified, the decoder 216 sets the selection signals Sa and Sb to H and L levels in the period T1 and sets the period. The H and L levels are also used for T2. Second, when the data signal Data is (0, 1) and the size of the middle dot is specified, the decoder 216 sets the selection signals Sa and Sb to H and L levels in the period T1 and sets them to the H and L levels in the period T2. L and H levels. Third, when the data signal Data is (1, 0) and the size of the small dot is specified, the decoder 216 sets the selection signals Sa and Sb to L and L levels in the period T1 and sets them to the L and L levels in the period T2. L and H levels. Fourth, when the data signal Data is (0, 0) and the non-recording is specified, the decoder 216 sets the selection signals Sa and Sb to L and H levels in the period T1 and L in the period T2. Let it be L level.

FIG. 9 is a diagram showing a voltage waveform of a drive signal selected according to the data signal Data and supplied to one end of the piezoelectric element 60.
When the data signal Data is (1, 1), the selection signals Sa and Sb are at the H and L levels in the period T1, so that the transfer gate 234a is turned on and the transfer gate 234b is turned off. Therefore, the trapezoidal waveform Adp1 of the drive signal COM-A is selected in the period T1. Since the selection signals Sa and Sb are at the H and L levels even in the period T2, the selection unit 230 selects the trapezoidal waveform Adp2 of the drive signal COM-A.
In this way, when the trapezoidal waveform Adp1 is selected in the period T1 and the trapezoidal waveform Adp2 is selected in the period T2 and supplied to one end of the piezoelectric element 60 as a drive signal, the nozzle 651 corresponding to the piezoelectric element 60 is used. A certain amount of ink is ejected in two steps. Therefore, the respective inks land on the print medium P and coalesce, and as a result, large dots as defined by the data signal Data are formed.

When the data signal Data is (0, 1), the selection signals Sa and Sb are at the H and L levels in the period T1, so that the transfer gate 234a is turned on and the transfer gate 234b is turned off. Therefore, the trapezoidal waveform Adp1 of the drive signal COM-A is selected in the period T1. Next, since the selection signals Sa and Sb become L and H levels in the period T2, the trapezoidal waveform Bdp2 of the drive signal COM-B is selected.
Therefore, medium and small amounts of ink are ejected from the nozzle in two batches. Therefore, the respective inks land on the print medium P and coalesce, and as a result, middle dots as defined by the data signal Data are formed.

When the data signal Data is (1, 0), the selection signals Sa and Sb both reach the L level in the period T1, so that the transfer gates 234a and 234b are turned off. Therefore, neither the trapezoidal waveforms Adp1 nor Bdp1 is selected in the period T1. When both the transfer gates 234a and 234b are turned off, the path from the connection point between the output ends of the transfer gates 234a and 234b to one end of the piezoelectric element 60 becomes a high impedance state that is not electrically connected to any part. .. However, the piezoelectric element 60 holds the voltage (Vc-V _BS ) immediately before the transfer gate is turned off due to its own capacitance.

Next, since the selection signals Sa and Sb become L and H levels in the period T2, the trapezoidal waveform Bdp2 of the drive signal COM-B is selected. Therefore, since a small amount of ink is ejected from the nozzle 651 only during the period T2, small dots as defined by the data signal Data are formed on the print medium P.

When the data signal Data is (0,0), the selection signals Sa and Sb are at the L and H levels in the period T1, so that the transfer gate 234a is turned off and the transfer gate 234b is turned on. Therefore, the trapezoidal waveform Bdp1 of the drive signal COM-B is selected in the period T1. Next, since the selection signals Sa and Sb both reach the L level during the period T2, neither the trapezoidal waveforms Adp2 nor Bdp2 is selected.
Therefore, in the period T1, the ink in the vicinity of the opening of the nozzle 651 only slightly vibrates, and the ink is not ejected. As a result, dots are not formed, that is, the non-dots as defined by the data signal Data are not formed. It will be a record.

In this way, the selection unit 230 selects (or does not select) the drive signals COM-A and COM-B according to the instruction from the selection control unit 210, and supplies them to one end of the piezoelectric element 60. Therefore, each piezoelectric element 60 is driven according to the size of the dots defined by the data signal Data.
The drive signals COM-A and COM-B shown in FIG. 5 are merely examples. Actually, various combinations of waveforms prepared in advance are used according to the moving speed of the head unit 20 and the properties of the print medium P.
Further, here, an example in which the piezoelectric element 60 bends upward with an increase in voltage has been described, but when the voltage supplied to the electrodes 611 and 612 is reversed, the piezoelectric element 60 causes the piezoelectric element 60 with an increase in voltage. Will bend downward. Therefore, in the configuration in which the piezoelectric element 60 bends downward as the voltage rises, the drive signals COM-A and COM-B illustrated in the figure have waveforms inverted with respect to the voltage Vc.

As described above, in the present embodiment, one dot is formed with respect to the print medium P in units of period Ta, which is a unit period. Therefore, in the present embodiment in which one dot is formed by ejecting ink droplets twice (at most) in the cycle Ta, the ink ejection frequency f is 2 / Ta, and the dot interval D is the moving speed v of the head unit. Is divided by the ink ejection frequency f (= 2 / Ta).
Generally, when an ink droplet can be ejected Q (Q is an integer of 2 or more) times in a unit period T and one dot is formed by ejecting the ink droplet Q times, the ink ejection frequency f is Q /. It can be expressed as T.
The case where dots of different sizes are formed on the print medium P as in the present embodiment is required to form one dot as compared with the case where one dot is formed by ejecting one ink droplet. Even if the time (cycle) is the same, it is necessary to shorten the time because one ink droplet is ejected once.
No particular explanation is required for the third method of forming two or more dots without binding two or more ink droplets.

Subsequently, the drive circuits 50-a and 50-b will be described. Of these, to outline one of the drive circuits 50-a, the drive signal COM-A is generated as follows. That is, the drive circuit 50-a first converts the data dA supplied from the control unit 100 into analog, and secondly feeds back the output drive signal COM-A to the drive signal COM-A. The deviation between the based signal (attenuated signal) and the target signal is corrected by the high frequency component of the drive signal COM-A, a modulated signal is generated according to the corrected signal, and third, a transistor is generated according to the modulated signal. Amplification-modulated signal is generated by switching the above, and fourth, the amplified-modulated signal is smoothed (demoderated) by a low-pass filter, and the smoothed signal is output as a drive signal COM-A.
The other drive circuit 50-b has the same configuration, and differs only in that the drive signal COM-B is output from the data dB. Therefore, in FIG. 10 below, the drive circuits 50-a and 50-b will be described as the drive circuit 50 without distinction.
However, the input data and the output drive signal are expressed as dA (dB), COM-A (COM-B), etc., and in the case of the drive circuit 50-a, the data dA is input. It means that the drive signal COM-A is output, and in the case of the drive circuit 50-b, the data dB is input and the drive signal COM-B is output.

FIG. 10 is a diagram showing a circuit configuration of the drive circuit 50.
As shown in this figure, the drive circuit 50 is composed of an LSI 500, N-channel transistors M1 and M2, and various elements such as a resistor and a capacitor.

The LSI (Large Scale Integration) 500 is, for example, N-channel FET (Field Effect Transistor) transistors M1 and M2 based on 10-bit data dA (dB) input from the control unit 100 via pins D0 to D9. A gate signal is output to each of the above. In order to output such a gate signal, the LSI 500 includes a DAC (Digital to Analog Converter) 502, an adder 504, 510, an attenuator 508, a delayer 512, a comparator 520, and a gate driver 530. include.

The DAC 502 converts the data dA (dB) defining the waveform of the drive signal COM-A (COM-B) into an analog signal Aa and supplies it to the input end (+) of the adder 504. The voltage amplitude of this analog signal Aa is, for example, about 0 to 2 volts, and the drive signal COM-A (COM-B) is obtained by amplifying this voltage about 20 times. That is, the analog signal Aa is a target signal before amplification of the drive signal COM-A.
The voltage of the terminal Out input via the pin Vfb, that is, the drive signal COM-A (COM-B) is supplied to the input end (-) of the adder 504.
The adder 504 integrates and attenuates the voltage at the input end (−), and then calculates the voltage at the input end (+). Specifically, the adder 504 obtains a deviation obtained by subtracting the integration / attenuation voltage of the input end (-) from the voltage of the input end (+), and outputs a signal Ab indicating the deviation to one of the input ends of the adder 510. Supply to.
The power supply voltage of the circuit from the DAC 502 to the comparator 520 is 3.3 volts with a low amplitude. While the voltage of the analog signal Aa is about 2 volts at the maximum, the voltage of the drive signal COM-A may exceed 40 volts at the maximum. The voltage of the signal COM-A (COM-B) is attenuated.

The attenuator 508 attenuates the high frequency component of the drive signal COM-A (COM-B) input via the pin Ifb and supplies it to the other end of the input end of the adder 510. The attenuation by the attenuator 508 is for adjusting the voltage amplitude when feeding back the drive signal COM-A (COM-B), similarly to the input end (−) in the adder 504. The adder 510 supplies the signal As of the voltage obtained by adding the voltage at one of the input ends and the voltage at the other end to the delay device 512.
For the voltage of the signal As output from the adder 510, the attenuation voltage of the signal supplied to the pin Ifb is added to the deviation obtained by subtracting the attenuation voltage of the signal supplied to the pin Vfb from the voltage of the analog signal Aa indicating the target. It is the voltage that was applied. Therefore, the voltage of the signal As by the adder 510 is the deviation obtained by subtracting the attenuation voltage of the drive signal COM-A (COM-B) which is the output from the voltage of the target analog signal Aa, which is the drive signal COM. It can be said that the signal is corrected by the high frequency component of −A (COM—B).
The delay device 512 supplies the signal Ad, which is the signal As delayed by the time described later, to the comparator 520.

The comparator 520 outputs a modulated signal Ms pulse-modulated as follows based on the signal Ad delayed by the delay device 512. Specifically, when the signal Ad rises in voltage, the comparator 520 becomes H level when the voltage threshold Vth1 or higher is reached, and when the signal Ad falls below the voltage threshold Vth2, the comparator 520 becomes H level. The modulation signal Ms which becomes L level is output. As will be described later, the voltage threshold value is
Vth1> Vth2
It is set in the relationship.

The modulated signal Ms by the comparator 520 is supplied to the gate driver 530. The gate driver 530 converts the modulated signal Ms into a high logic amplitude and supplies it to the gate electrode of the transistor M1 via the pin Hdr and the resistor R1, while the signal in which the logic level of the modulated signal Ms is inverted has a high logic amplitude. It is converted and supplied to the gate electrode of the transistor M2 via the pin Ldr and the resistor R2.

Therefore, the logic levels of the gate signals supplied to the gate electrodes of the transistors M1 and M2 have an exclusive relationship with each other.
The logic level of the two gate signals output by the gate driver 530 is actually timing controlled so as not to be H level at the same time (that is, so that the N-channel transistors M1 and M2 are not turned on at the same time). You may. Therefore, strictly speaking, the exclusive meaning here means that the H level is not reached at the same time (in the case of the transistors M1 and M2, they are not turned on at the same time).

By the way, the modulated signal referred to here is a modulated signal Ms in a narrow sense, but if it is considered that it is a signal that drives the transistors M1 and M2 by pulse-modulating according to the signal Aa, it is a gate signal to the transistor M1. Also, the gate signal to the transistor M2 is included in the modulation signal. That is, the modulated signal pulse-modulated according to the signal Aa includes not only the modulated signal Ms but also the one in which the logic level of the modulated signal Ms is inverted and the one whose timing is controlled.

Since the comparator 520 outputs the modulation signal Ms, the circuit up to the comparator 520, that is, the DAC 502, the adder 504, 510, the attenuator 508, the delayer 512, and the comparator 520. Can be said to be a modulation circuit that generates a modulation signal Ms.
Further, in the configuration shown in FIG. 10, the digital data dA (dB) is converted into an analog signal Aa by the DAC 502, but the signal Aa is supplied from the external circuit according to the instruction by the control unit 100, for example, without going through the DAC 502. You may receive it. Whether it is digital data dA (dB) or analog signal Aa, it is a source signal because it defines the target value for generating the waveform of the drive signal COM-A (COM-B). Is no different.

Of the transistors M1 and M2, in the higher-side transistor M1 (high-side transistor), a voltage Vh (for example, 42 volts) is applied to the drain electrode. For the low-order transistor M2 (low-side transistor), the source electrode is grounded to the ground.
Since each of the transistors M1 and M2 is an N-channel type in this example, it is turned on if the gate signal is H level. Therefore, a modulation amplification signal obtained by amplifying the modulation signal Ms appears at the connection point Sd between the source electrode of the transistor M1 and the drain electrode of the transistor M2, that is, at one end of the inductor L1. Therefore, the transistors M1 and M2 as a pair of transistors output a modulation amplification signal obtained by amplifying the modulation signal Ms.

The other end of the inductor L1 is a terminal Out which is an output in the drive circuit 50, and a drive signal COM-A (COM-B) is transmitted from the terminal Out to the head unit 20 and a flexible cable 190 (FIGS. 1 and 2). See).

Further, the terminal Out is connected to one end of the capacitor C1, one end of the capacitor C7, and one end of the resistor R4, respectively. Of these, the other end of the capacitor C1 is grounded to the ground. Therefore, the inductor L1 and the capacitor C1 function as an LPF (Low Pass Filter) 550 that smoothes the amplification modulation signal appearing at the connection point of the transistors M1 and M2.

The other end of the resistor R4 is connected to one end of the pin Vfb and the resistor R23, and a voltage Vh is applied to the other end of the resistor R23. As a result, the drive signal COM-A (COM-B) from the terminal Out is pulled up and returned to the pin Vfb.
Although the resistors R4 and R23 are external to the LSI 500, they may have a configuration built in the LSI 500.

The other end of the capacitor C7 is connected to one end of the resistor R18 and one end of the resistor R10. Of these, the other end of the resistor R18 is grounded to the ground. Therefore, the capacitor C7 and the resistor R18 function as an HPF (High Pass Filter) for passing a high frequency component having a cutoff frequency or higher in the drive signal COM-A (COM-B) from the terminal Out. The cutoff frequency of the HPF is set to, for example, about 9 MHz.

Further, the other end of the resistor R10 is connected to one end of the capacitor C5 and one end of the capacitor C8. Of these, the other end of the capacitor C8 is grounded to the ground. Therefore, the resistor R10 and the capacitor C8 function as LPFs that pass low frequency components below the cutoff frequency among the signal components that have passed through the HPF. The cutoff frequency of the LPF is set to, for example, about 160 MHz.
Since the cutoff frequency of the HPF is set lower than the cutoff frequency of the LPF, the HPF and the LPF pass through a frequency component in a predetermined frequency range of the drive signal COM-A (COM-B). It functions as a BPF (Band Pass Filter) 560.

The other end of the capacitor C5 is connected to the pin Ifb of the LSI 500. As a result, the DC component of the high frequency components of the drive signal COM-A (COM-B) that has passed through the BPF is cut and returned to the pin Ifb.

The drive circuit 50 has two feedback paths, a path via the pin Vfb and a path via the pin Ifb. Of these, the dominant path that defines the frequency of self-oscillation is the path via the pin Ifb. Therefore, the term feedback circuit means a circuit involved in the path via the pin Ifb, and specifically, LPF550 and BPF560.

The drive signal COM-A (COM-B) output from the terminal Out is a signal obtained by smoothing the amplification modulation signal at the connection point Sd of the transistors M1 and M2 by LPF550. This drive signal COM-A (COM-B) is returned to the adder 504 via the pin Vfb, and is output as a signal Ab which is a deviation from the target signal Aa.
Here, for convenience of explanation, the drive signal COM-A (COM-B) is integrated and attenuated via the pin Vfb, assuming a configuration excluding the feedback via the pin Ifb and the delay due to the delay device 512. Then, since it is fed back to the adder 504, the modulated signal Ms self-excited and oscillates at a frequency determined by the transfer function of the feedback path, that is, the path passing through the LPF 550 and the adder 504.
However, since the delay amount of the feedback path via the pin Vfb is large, the frequency of self-oscillation and the waveform accuracy of the drive signal COM-A (COM-B) can be determined only by the feedback via the pin Vfb. It cannot be high enough to be secured.

Therefore, in the present embodiment, by providing a path for feeding back the high frequency component of the drive signal COM-A (COM-B) via the pin Ifb, in addition to the path via the pin Vfb, when viewed as a whole circuit. The delay of is reduced. Therefore, the frequency of the signal As, which is the sum of the signal Ab and the high frequency component of the drive signal COM-A (COM-B), is higher than that in the case where the path via the pin Ifb does not exist (that is, self-oscillation). The oscillation frequency becomes higher), and the ripple component is reduced in the drive signal COM-A (COM-B) to improve the accuracy of the waveform.
The amount of delay in the delay device 512 will be described later.

FIG. 11 is a diagram showing an ideal relationship between the signal As and the modulated signal Ms with respect to the waveform of the analog signal Aa.
As shown in this figure, the signal As is a triangular wave, and its oscillation frequency fluctuates according to the voltage (input voltage) of the analog signal Aa. Specifically, it becomes the highest when the input voltage is an intermediate value, and decreases as the input voltage increases from the intermediate value or decreases. The signal As (Ad) is a self-oscillation signal.

Further, in the signal As, the slope of the triangular wave is almost equal between the ascending (voltage rise) and the descent (voltage descent) when the input voltage is near the intermediate value. Therefore, the duty ratio of the modulated signal Ms, which is the result of comparing the signal As with the voltage thresholds Vth1 and Vth2 by the comparator 520, is approximately 50%. When the input voltage increases from the intermediate value, the downward slope of the signal As becomes gentle. Therefore, the period during which the modulated signal Ms becomes the H level becomes relatively long, and the duty ratio becomes large. On the other hand, as the input voltage becomes lower than the intermediate value, the upward slope of the signal As becomes gentler. Therefore, the period during which the modulation signal Ms becomes the L level becomes relatively short, and the duty ratio becomes small.
Therefore, the modulated signal Ms becomes the following pulse density modulated signal. That is, the duty ratio of the modulated signal Ms is approximately 50% at the intermediate value of the input voltage, increases as the input voltage becomes higher than the intermediate value, and decreases as the input voltage becomes lower than the intermediate value.

The gate driver 530 turns the transistors M1 and M2 on / off based on the modulation signal Ms as described above. That is, the gate driver 530 turns on the transistor M1 and turns off the transistor M2 when the modulation signal Ms is H level, while turns off the transistor M1 and turns off the transistor M2 when the modulation signal Ms is L level. Turn on.
Therefore, the voltage of the drive signal COM-A (COM-B) obtained by smoothing the amplified modulation signal at the connection point Sd of the transistors M1 and M2 with the inductor L1 and the condenser C1 increases as the duty ratio of the modulated signal Ms increases. As the duty ratio becomes smaller, the duty ratio becomes lower. As a result, the drive signal COM-A (COM-B) is controlled and output so as to be a signal obtained by expanding the voltage of the analog signal Aa. Become.

Since this drive circuit 50 uses pulse density modulation, there is an advantage that a large change width of the duty ratio can be obtained as compared with pulse width modulation in which the modulation frequency is fixed.
That is, since the minimum positive pulse width and negative pulse width that can be handled by the entire circuit are restricted by the circuit characteristics, in the pulse width modulation with a fixed frequency, the duty ratio change width is within a predetermined range (for example, from 10%). Only up to 90%) can be secured. On the other hand, in pulse density modulation, the oscillation frequency decreases as the input voltage deviates from the intermediate value, so that the duty ratio can be made larger in the region where the input voltage is high, and the region where the input voltage is low. In, the duty ratio can be made smaller. Therefore, in the self-oscillation type pulse density modulation, a wider range (for example, a range from 5% to 95%) can be secured as the change width of the duty ratio.

Further, the drive circuit 50 is a self-excited oscillation, and does not require a circuit that generates a carrier wave having a high frequency as in the separately excited oscillation. Therefore, there is an advantage that it is easy to integrate the functions other than the circuit that handles high voltage, that is, the functions carried out by the LSI 500.

However, in the actual drive circuit 50, it has been pointed out that the stability of self-excited oscillation is poor.

FIG. 12 is a diagram for explaining the frequency stability of self-oscillation. Here, (a) is a diagram showing an example of the frequency characteristic of self-oscillation with respect to the input value of DAC502, and (b) shows an example of the frequency dispersion (variation) characteristic of self-oscillation with respect to the input value. It is a figure. In the figure, the input value of the DAC 502 is a 10-bit data dA (dB) expressed as a decimal value.

As described with reference to FIG. 11, as for the frequency of self-excited oscillation, the voltage of the signal Aa is the intermediate value, that is, the input value of the data dA (dB) is the highest near "500" in decimal notation, and the input voltage is intermediate. Ideally, it goes down as you move away from the value. However, in reality, as shown in FIG. 12A, there is a phenomenon that the frequency of self-oscillation drops in the range including the intermediate value.
Further, in the vicinity of the boundary where the frequency drops, the frequency dispersion also peaks as shown in (b) of the figure. That is, the frequency of self-oscillation fluctuates in the vicinity of this area, resulting in lack of stability.
Therefore, next, we will consider the reason why the frequency of self-oscillation is not stable.

FIG. 13 shows the difference (position) between the phase of the modulation signal Ms and the phase of the signal Ad in which the modulation amplification signal generated by driving the transistors M1 and M2 based on the modulation signal Ms is fed back via the LPF550 and BPF560. It is a figure which shows the characteristic of phase difference). Here, for the sake of explanation, the delay amount in the delay device 512 is set to zero.
As shown by the broken line circles in this figure, the frequency of self-oscillation is around 6 to 8 MHz, and the phase difference is the minimum point. Further, the phase difference at this minimum point is a value near -360 degrees, which is delayed by one cycle.
What can be said from this characteristic is that two frequencies with a phase difference of around -360 degrees are close to each other. Specifically, when the frequency of self-oscillation is around 6 to 8 MHz, the phase difference is the minimum point. On the other hand, it falls to either the low frequency side (a) side or the high frequency side (b) side, and it is difficult to determine either of the two states.

Therefore, in order to stabilize the frequency of self-excited oscillation, it is sufficient to prevent two frequencies having a phase difference of around -360 degrees from being close to the frequency domain used for self-excited oscillation.

FIG. 14 is a diagram showing an equivalent circuit of LPF550.
In the inductor L1 constituting the LPF550, not only the original inductance Lr but also the resistance R51 in the electrodes and windings and the capacitance C51 formed between the windings are parasitic. Also in the capacitor C1 constituting the LPF550, not only the original capacitance Cr but also the resistance R52 and the inductance L52 in the electrodes and the like are parasitic.

FIG. 15 is a diagram showing the impedance characteristics of the actual inductor L1.
The impedance Z of the inductor L1 increases as the frequency increases, but at a certain frequency find, the original inductance Lr and the capacitance C51 cause a resonance phenomenon. Further, as the frequency becomes higher, the capacitance C51 becomes dominant and the impedance Z becomes lower.
In such a characteristic of impedance Z, the frequency find which is the variable pole (maximum) point is called the inductor self-resonance frequency. At frequencies higher than the self-resonant frequency find, the inductor does not function as an inductor.

FIG. 16 is a diagram showing the impedance characteristics of the actual capacitor C1.
The impedance Z of the capacitor C1 decreases as the frequency increases, but at a certain frequency fcap, the original capacitance Cr and the inductance L52 cause a resonance phenomenon. Further, as the frequency becomes higher, the inductance L52 becomes dominant and the impedance Z becomes higher.
In such a characteristic of impedance Z, the frequency fcap that becomes a variable (minimum) point is called the self-resonant frequency of the capacitor. At a frequency higher than the self-resonant frequency fcap, the capacitor does not function as a capacitor.

The following points should be noted here. That is, the frequency of the minimum point in FIG. 13 is hardly affected by the self-resonant frequency find of the inductor L1 in FIG. 15, and is substantially the same as the self-resonant frequency fcap of the capacitor C1 in FIG. That is, in FIG. 13, one of the factors that determines the frequency of the minimum point of the phase difference characteristic, that is, the frequency at which self-oscillation tends to be unstable is the self-resonant frequency fcap of the condenser C1 and the self of the inductor L1. The resonance frequency fla has almost no effect on the frequency fm of self-oscillation. Therefore, the self-resonant frequency fcap of the capacitor C1 should be higher than (the highest value) of the self-oscillation frequency fm, that is,
fcap> fm ... (1),
When set to, the frequency of self-oscillation tends to be stabilized.

If the frequency fm of self-oscillation is close to the self-resonant frequency fcap, self-oscillation may become uneasy.
fcap ≧ 1.5fm… (2),
That is, it is desirable to raise the self-resonant frequency fcap of the capacitor C1 by 1.5 times or more the frequency fm of self-oscillation.

When the capacitance Cr of the capacitor C1 is increased, the impedance characteristic of the capacitor C1 becomes as shown in FIG. 17, and the self-resonant frequency fcap decreases. Conversely, it can be said that it is effective to lower the capacitance Cr in order to raise the self-resonant frequency fcap of the capacitor C1.

Further, in general, when the capacitance of the capacitor is reduced, the entire element including the electrodes and the like becomes smaller, so that it can be expected that the parasitic inductance becomes smaller. However, the predetermined capacitance cannot be secured as it is. Therefore, for example, as shown in FIG. 18, it is preferable to connect two capacitor elements having a predetermined capacitance in parallel and use this combined capacitance as the capacitor C1.
According to such a parallel connection configuration, the self-resonant frequency when viewed from the capacitor C1 can be increased by reducing the parasitic inductance. The number of elements of the capacitors connected in parallel is not limited to "2" and may be "3" or more.

By the way, in the present embodiment, as described above, the entire circuit is viewed by a path for feeding back the high frequency component of the drive signal COM-A (COM-B) via the pin Ifb, in addition to the path via the pin Vfb. The time delay is reduced and the frequency of self-oscillation is increased. Conversely, by appropriately setting the delay amount at this time, the condition of the above inequality (1) or (2) can be satisfied and the stability of self-excited oscillation can be improved.

Here, in FIG. 10, the path for feeding back the high frequency component of the drive signal COM-A (COM-B) is the connection point Sd → LPF550 → BPF560 → attenuator 508 → adder 510 → delayer 512 → comparator 520. → Gate driver 530 → Resistors R1, R2 → Transistors M1, M2 → (connection point Sd). Of these, in the LPF550, BPF560 and the delay device 512, the delay amount can be set relatively easily.

That is, for the LPF550, the delay amount can be set according to the cutoff frequency. Since the BPF 560 is a combination of the HPF and the LPF as described above, the delay amount can be similarly set by the cutoff frequency. Although the detailed configuration of the delay device 512 is not mentioned, the delay amount can be similarly set by the cutoff frequency as an LPF of a digital filter, for example. Further, with respect to the delay device 512, the delay amount may be set by simply switching the number of connections in which the logic circuit (NOT circuit) is vertically connected.

Further, the attenuator 508 can have a delay element by adding an integrator circuit, for example, and the comparator 520 can have a delay element by, for example, voltage thresholds Vth1 and Vth2. The gate driver 530 may have a delay element when converting the logic amplitude. The transistors M1 and M2 have a delay element during on / off switching. Further, the resistance R1 (R2) of the gate of the transistor M1 (M2) and the capacitive component parasitic on the gate can also be delay factors.
As described above, at least one of the circuits existing in the feedback path may have a delay element, and the delay amount may be appropriately set to reduce the self-oscillation frequency fm. That is, as the delay amount due to the feedback path becomes longer, the frequency fm of the self-excited oscillation becomes lower. Therefore, the self-oscillation is caused by making the frequency fm lower than the self-resonant frequency fcap of the condenser C1. It can be stabilized.

By the way, the drive circuit 50 has a configuration in which various elements such as an LSI, a capacitor, and a resistor are mounted on a circuit board. Therefore, next, how the elements constituting the drive circuit 50 are arranged and mounted on what kind of circuit board will be described.

FIG. 19 is a diagram showing a wiring pattern of the circuit board when the circuit board is viewed in a plan view, and FIG. 20 shows the arrangement of elements mounted on the circuit board with the wiring pattern shown in FIG. It is a figure which shows the relationship.
As shown in FIG. 20, LSI500, transistors M1, M2, inductor L1, capacitors C1, C5, C7, C8, resistors R4, R10, R18, and R23 constituting the drive circuit 50 are mounted on the circuit board. ..

In FIGS. 19 and 20, the gate signal output from the pin Hdr of the LSI 500 is supplied to the gate electrode of the transistor M1 via the resistor R1 (omitted in FIGS. 19 and 20). The same applies to the gate signal output from the pin Ldr, which is supplied to the gate electrode of the transistor M2 via the resistor R2 (omitted in FIGS. 19 and 20).
The terminal X1 connected to the other end of the capacitor C1, the terminal X2 connected to the source electrode of the transistor M2, the terminal X3 connected to the other end of the resistor R18, and the terminal X4 connected to the other end of the capacitor C8 , Each is configured to be connected to the ground pattern.

Further, a through hole N1 is provided in a pattern (output, terminal Out) including the terminal X5 connected to the other end of the inductor L1 and the terminal X6 connected to one end of the capacitor C1. On the other hand, a through hole N2 is provided in the pattern including the terminal X7 connected to one end of the capacitor C7 and the terminal X8 connected to one end of the resistor R4.
In the circuit diagram of FIG. 10, the terminal Out is divided into two systems and fed back to the pins Vfb and Ifb of the LSI 500, but in reality, as shown in FIG. 19, the terminals are provided in a pattern including the terminal Out. The through hole N1 is branched into one end of the resistor R4 and one end of the capacitor C7 via the insertion wiring pattern (not shown) and the through hole N2 in sequence. Of these, the path on the resistor R4 side is fed back to the pin Vfb, and the path on the capacitor C7 side is fed back to the pin Ifb.
The interpolated wiring pattern referred to here means a wiring pattern other than the first layer when the wiring pattern shown in FIG. 19 is the first layer.

A through hole N3 is provided in the pattern including the terminal X10 connected to the drain electrode of the transistor M1. Further, a through hole N4 is provided in the pattern including the terminal X11 connected to the other end of the resistor R23. A voltage Vh is applied to each of these through holes N3 and N4 by being connected to an interpolation pattern (not shown).
A through hole N6 is provided in a pattern (connection point Sd in FIG. 10) including a terminal X12 connected to the source electrode of the transistor M1 and a terminal X13 connected to the drain electrode of the transistor M2. A through hole N7 is provided in the pattern including the terminal X14 connected to one end of the inductor L1. The through-hole N6 and the through-hole N7 are electrically connected to each other via an interpolated wiring pattern (not shown).

As described above, in the present embodiment, the drive circuit 50 is configured by mounting various elements on the circuit board. Here, the LPF550 is arranged close to the output terminal Out.

FIG. 21 is a diagram for explaining such an arrangement.
As shown in this figure, the capacitors C1 constituting the LPF550 are arranged so as to be closer to the transistor M2 than the transistor M1. Specifically, the shortest distance Q2 from the capacitor C1 to the transistor M2 is arranged to be shorter than the shortest distance Q1 from the capacitor C1 to the transistor M1.
The shortest distance between the elements is, for example, the distance from the (diagonal) center point when the element is viewed in a plane to the center point when the other element is viewed in a plane.

Explaining the reason for such an arrangement, the wiring inductance of the pattern connected to the terminal of the capacitor C1 is added to the inductance L52 (parasitic component) in FIG. 14, so that the influence of the sum of the inductances is suppressed. be. Therefore, this effect will be described next.

FIG. 22 is a diagram showing the self-resonant frequency fcap of the capacitor C1 in consideration of the inductance between the following two points.
In addition, in FIG. 22, after the improvement (that is, the configuration in which the transistors M1, M2 and the capacitor C1 are mounted as shown in FIGS. 20 and 21 with respect to the ground pattern shown in FIG. 19) and before the improvement (ground pattern). And the configuration that does not consider the component arrangement) is shown in comparison.
Also, what is meant by the two points here?
(1) Single element of capacitor C1 (almost the same as between terminals X1-X6 in the mounted state),
(2) Between the test pins Tp-terminal X6 with the capacitor C1 mounted on the circuit board, and
(3) Between terminals X2-X6 with the capacitor C1 mounted on the circuit board
Is.

The terminal X2 is the terminal closest to the terminal X1 among the terminals grounded to the ground in the various elements of the drive circuit 50, and the two points between the terminal X1 and the terminal X1 are compared with the influence between the other terminals. Is considered to be dominant.

As can be seen from FIG. 22, even if the performance of the single element of the capacitor C1 is good (even if the parasitic inductance is small), the wiring inductance is added when it is actually mounted on the circuit board, so the shape of the ground pattern, etc. If the arrangement of the elements and the elements is inappropriate, the self-resonant frequency fcap of the capacitor C1 is deteriorated.
Therefore, in order to increase the self-resonant frequency fcap of the capacitor C1, it is necessary to reduce not only the parasitic inductance of a single capacitor but also the wiring inductance of the circuit board.
After the improvement as in the embodiment, the self-resonant frequency fcap of the capacitor C1 in the state of the element alone does not have to be deteriorated as compared with the state before the improvement even in the state of being mounted on the circuit board.

FIG. 23 is a diagram showing the results of measuring the inductance between the same two points as in FIG. 22. It can be seen from FIG. 23 that the inductance should be set as follows in order not to deteriorate the self-resonant frequency fcap of the capacitor C1 as in the improvement of FIG. 22. That is, the inductance from the terminal X6 to which one end of the capacitor C1 is connected to the terminal X2 to which the source electrode of the transistor M2 is connected is, in other words, the parasitic inductance of the capacitor C1 and the other end of the capacitor C1. It can be seen that the inductance including the wiring inductance from the terminal X1 to the terminal X2 may be 1 nH or less.

FIG. 24 is a diagram showing phase difference characteristics as in FIG. 13.
Here, the simulation result when the inductance including the parasitic inductance of the capacitor C1 and the wiring inductance from the terminal X1 to the terminal X2 is changed to 0.6 nH, 0.8 nH, 1.0 nH, and 1.2 nH is shown. Shows.
As shown in this figure, when the inductance is higher than 1.0 nH, it can be seen that the two frequencies having a phase difference of around -360 degrees are close to each other and the stability of self-oscillation is lacking. Conversely, if the inductance is 1.0 nH or less, the two frequencies having a phase difference of around -360 degrees are sufficiently separated, and as a result, self-oscillation is stabilized.

The present invention is not limited to the above-described embodiment, and various modifications and applications as described below are possible, for example. It should be noted that the following modifications and application modes may be appropriately combined with one or more arbitrarily selected.

Further, in the embodiment shown in FIG. 2, for convenience of explanation, the number of nozzles is set to a relatively small number, and the drive signals COM-A and COM-B are used in the two drive circuits 50-a and 50-b, respectively. However, a drive circuit for outputting the drive signals COM-C, COM-D, ... May be further provided. That is, the number of drive circuits is not limited to "2".
Regarding the printing device 1, the head units having a plurality of nozzles 651 are arranged in a direction orthogonal to or oblique to the sub-scanning direction, instead of ejecting ink while reciprocating in the main scanning direction. It may be a so-called line printer in which a plurality of head units are provided and the head units are fixed to the housing.

In the embodiment, the piezoelectric element 60 that ejects ink has been described as an example of the driving target of the drive circuit 50, but the driving target is not limited to the piezoelectric element 60, for example, an ultrasonic motor, a touch panel, a flat speaker, and a liquid crystal. It may be a capacitive load such as a display such as. That is, the drive circuit 50 may be any capacitive load drive circuit that drives such a capacitive load.

1 ... Printing device (liquid ejection device), 10 ... Control unit, 20 ... Head unit, 50 ... Drive circuit, 60 ... Piezoelectric element, 520 ... Comparator, L1 ... Inductor, C1 ... Condenser, M1, M2 ... Transistor, 600 ... Discharge part, 631 ... Cavity, 651 ... Nozzle.

Claims (8)

A drive circuit that outputs a drive signal that drives a capacitive load.
A modulation circuit that generates a modulation signal in which the source signal is pulse-modulated by self-oscillation,
A transistor that amplifies the modulated signal to generate an amplified modulated signal,
A low-pass filter that includes an inductor and a capacitor to smooth the amplified modulation signal to generate the drive signal.
A feedback circuit that pulls up the drive signal and feeds it back to the modulation circuit,
Equipped with
A drive circuit characterized in that the self-resonant frequency of the capacitor is higher than the frequency of the self-excited oscillation. The feedback circuit feeds back the frequency component of the drive signal to the modulation circuit.
The drive circuit according to claim 1. The drive circuit according to claim 1 or 2 , wherein the frequency of the self-excited oscillation is 1 MHz or more. The drive circuit according to any one of claims 1 to 3 , wherein the frequency of the self-excited oscillation is 8 MHz or less. The drive circuit according to any one of claims 1 to 4 , wherein the self-resonant frequency of the capacitor is 1.5 times or more the frequency of the self-excited oscillation. The drive circuit according to any one of claims 1 to 5 , wherein at least one of the modulation circuit, the transistor, the low-pass filter, and the feedback circuit has a delay element. The drive circuit according to claim 6 , wherein the delay element is a frequency cut filter. The drive circuit according to any one of claims 1 to 7 , wherein the capacitor is connected in parallel with a plurality of elements.

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