JP6583508B2 - Drive circuit for driving capacitive load and liquid ejection device - Google Patents

Description

The present invention relates to a drive circuit that drives a capacitive load and a liquid ejection apparatus.

  2. Related Art An ink jet printer that prints an image or a document by ejecting ink is known that uses a piezoelectric element (for example, a piezo element). The piezoelectric element is provided corresponding to each of the plurality of nozzles in the head unit, and each is driven according to a drive signal, whereby a predetermined amount of ink (liquid) is ejected from the nozzle at a predetermined timing. Is formed. Since the piezoelectric element is a capacitive load such as a capacitor when viewed electrically, it is necessary to supply a sufficient current to operate the piezoelectric element of each nozzle.

  For this reason, the drive signal amplified by the amplifier circuit is supplied to the head unit to drive the piezoelectric element. Examples of the amplifier circuit include a method of linearly amplifying a source signal before amplification using a class AB or the like (linear amplification, see Patent Document 1). However, since linear amplification consumes a large amount of power and has low energy efficiency, in recent years, class D amplification has also been proposed (see Patent Document 2).

On the other hand, in recent years, there is a strong demand for high-speed printing and multi-gradation in inkjet printers. In order to realize high-speed printing, the number of dots that can be formed per unit time may be increased. However, since the number of piezoelectric elements (nozzles) that can be driven by a single amplifier circuit is limited, a large number of amplifier circuits are required.
In order to realize multi-gradation, it is only necessary to increase variations in the amount of ink ejected from the nozzles.To that end, the amount of ink to be ejected is selected from a plurality of types of drive signals prepared in advance. Accordingly, any one of the drive signals is selected. Even in this configuration, a large number of amplifier circuits are still required.
In order to reduce the size of the entire inkjet printer, it is necessary to reduce the space for accommodating many amplifier circuits. Therefore, in order to increase the mounting density of the amplifier circuit, it has been considered to adopt a configuration (double-sided substrate mounting) in which the components of the amplifier circuit are mounted on both sides of the circuit board.
For example, Patent Document 3 describes how to arrange the components of the class D amplifier circuit in double-sided board mounting.

JP 2009-190287 A JP 2010-114711 A JP 2006-50431 A

Incidentally, as described above, in order to realize high-speed printing, it is only necessary to increase the number of dots that can be formed per unit time. To that end, it is necessary to increase the ink ejection frequency. For this purpose, it is necessary to increase the switching frequency of the class D amplification to increase the frequency of the drive signal supplied to the piezoelectric element.
However, it has been pointed out that various problems such as generation of noise occur when the components of the class D amplifier circuit are mounted on both sides of the circuit board when the frequency of the drive signal is high.
Accordingly, one of the objects of some aspects of the present invention is to solve the problem in the case where the constituent elements of the class D amplifier circuit are mounted on both sides of the substrate.

  In order to achieve one of the above objects, a liquid ejection apparatus according to an aspect of the present invention includes a modulation circuit that generates a modulation signal obtained by pulse-modulating a source signal, and generates an amplified modulation signal by amplifying the modulation signal. A low-pass filter that smoothes the amplified modulated signal and generates a drive signal, a feedback circuit that feeds back the drive signal to the modulation circuit, the modulation circuit, the transistor, and the low-pass filter A circuit board on which a filter and the feedback circuit are mounted; a piezoelectric element that is displaced when the drive signal is applied; a cavity that is filled with droplets and whose internal volume changes due to the displacement of the piezoelectric element; A nozzle provided for discharging the liquid in the cavity according to a change in the internal volume of the cavity. The circuit board includes a first mounting surface and a second mounting surface, the capacitor and the feedback circuit are mounted on the first mounting surface, and a first ground wiring connected to the capacitor, And a second ground line connected to the feedback circuit, and at least one of the modulation circuit, the transistor, and the inductor is mounted on the second mounting surface.

According to the liquid ejecting apparatus according to the above aspect, the drive signal faithfully reproducing the source signal can be output by returning the drive signal to the modulation circuit. Here, since circuit components are mounted on the circuit board on both the first mounting surface and the second mounting surface, the mounting density can be improved.
In addition, the capacitor constituting the low-pass filter and the feedback circuit are mounted on the same first mounting surface on the circuit board, the first ground wiring connected to the capacitor, and the second ground connected to the feedback circuit Since the wiring is provided, the ground potential is stabilized, and noise superimposed on the signal fed back to the modulation circuit is reduced. As a result, the waveform accuracy of the drive signal can be improved and the ejection of droplets can be stabilized.
The source signal is a signal that is a source of a drive signal that defines the displacement of the piezoelectric element, that is, a signal before modulation and a signal that serves as a reference for the waveform of the drive signal (including a signal that is defined, analog, Regardless of digital). The modulation signal is a digital signal obtained by subjecting the source signal to pulse modulation (for example, pulse width modulation, pulse density modulation, etc.).

By the way, in the liquid ejection device according to the above aspect, the amplification modulation signal is smoothed to generate a drive signal, and the drive signal is applied to displace the piezoelectric element to eject the liquid from the nozzle. Here, when the frequency spectrum analysis is performed on the waveform of a drive signal for the liquid ejection device to eject small dots, for example, it is known that a frequency component of 50 kHz or more is included. In order to generate a drive signal including such a frequency component of 50 kHz or higher, the frequency of the modulation signal (amplified modulation signal) needs to be 1 MHz or higher.
If the frequency of the modulation signal is made lower than 1 MHz, the edge of the waveform of the reproduced drive signal becomes dull and rounded. In other words, the corners are removed and the waveform becomes dull. When the waveform of the drive signal is dull, the displacement of the piezoelectric element that operates in response to the rising and falling edges of the waveform becomes slow, causing tailing during ejection and defective ejection, thereby reducing print quality. End up.
On the other hand, if the frequency of the modulation signal is higher than 8 MHz, the resolution of the waveform of the drive signal is increased. However, when the switching frequency in the transistor is increased, the switching loss is increased, and the power-saving and heat-saving properties that are superior to linear amplification such as a class AB amplifier are impaired.
For this reason, in the liquid ejection device according to the above aspect, the frequency of the modulation signal is preferably 1 MHz or more and 8 MHz or less.

  In the liquid ejection apparatus according to the above aspect, the first ground wiring and the second ground wiring may be configured as an integrated pattern. That is, there may be a configuration in which no other wiring pattern exists between the first ground wiring and the second ground wiring, or a configuration in which the first ground wiring and the second ground wiring are not divided by a through hole. . With this configuration, since the potential of the ground wiring is stabilized as compared with the case where other wiring patterns exist, malfunctions can be reduced.

  By the way, the transistor and the inductor generate heat when a current flows. Therefore, in the liquid ejection device according to the above aspect, the transistor and the inductor may be mounted on the same mounting surface. According to this configuration, since the transistor and the inductor that generate heat are mounted on the same mounting surface, a configuration in which a heat dissipation member is provided on the mounting surface is sufficient.

  In the liquid ejection device according to the above aspect, the drive circuit mounted on the circuit board may include a plurality of sets. When a plurality of sets of drive circuits are mounted in this manner, variations in drive signals applied to the piezoelectric elements can be increased, and multi-gradation by liquid ejection is facilitated. Further, the present invention can be realized in various modes, and can be realized in various modes such as a single head unit.

1 is a diagram illustrating a schematic configuration of a printing apparatus. 1 is a block diagram illustrating a configuration of a printing apparatus. It is a figure which shows the structure of the discharge part in a head unit. It is a figure which shows the nozzle arrangement | sequence in a head unit. It is a figure for demonstrating operation | movement of the selection control part in a head unit. It is a figure which shows the structure of the selection control part in a head unit. It is a figure which shows the decoding content of the decoder in a head unit. It is a figure which shows the structure of the selection part in a head unit. It is a figure which shows the drive signal selected by the selection part. It is a figure which shows the structure of the drive circuit in a printing apparatus. It is a figure for demonstrating operation | movement of a drive circuit. It is a figure which shows arrangement | positioning of the element mounted in the surface of a circuit board. It is a figure which shows arrangement | positioning of the element mounted in the back surface of a circuit board. It is a figure which shows the wiring pattern in the back surface of a circuit board. It is a figure which shows the relationship between the pattern and element in the back surface of a circuit board.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  The printing apparatus according to this embodiment forms an ink dot group on a print medium such as paper by ejecting ink in accordance with image data supplied from an external host computer, and thus according to the image data. Inkjet printers that print images (including characters, graphics, etc.), that is, liquid ejection devices.

FIG. 1 is a perspective view illustrating a schematic configuration inside the printing apparatus.
As shown in this figure, the printing apparatus 1 includes a moving mechanism 3 that moves (reciprocates) the moving body 2 in the main scanning direction.
The moving mechanism 3 includes a carriage motor 31 that is a driving source of the moving body 2, a carriage guide shaft 32 that is fixed at both ends, a timing belt that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31. 33.
The carriage 24 of the moving body 2 is supported by the carriage guide shaft 32 so as to be able to reciprocate and is fixed to a part of the timing belt 33. Therefore, when the timing belt 33 is moved forward and backward by the carriage motor 31, the moving body 2 is guided by the carriage guide shaft 32 and reciprocates.
Further, a head unit 20 is provided in a portion of the moving body 2 that faces the print medium P. As will be described later, the head unit 20 is for ejecting ink droplets (droplets) from a large number of nozzles, and is configured to be supplied with various control signals and the like via a flexible cable 190. .

The printing apparatus 1 includes a transport mechanism 4 that transports the print medium P on the platen 40 in the sub-scanning direction. The transport mechanism 4 includes a transport motor 41 that is a driving source, and a transport roller 42 that is rotated by the transport motor 41 and transports the print medium P in the sub-scanning direction.
When the print medium P is conveyed by the conveyance mechanism 4, the head unit 20 ejects ink droplets onto the print medium P, whereby an image is formed on the surface of the print medium P.

FIG. 2 is a block diagram illustrating an electrical configuration of the printing apparatus.
As shown in this figure, in the printing apparatus 1, the control unit 10 and the head unit 20 are connected via a flexible cable 190.
The control unit 10 includes a control unit 100, a carriage motor 31, a carriage motor driver 35, a transport motor 41, a transport motor driver 45, and two drive circuits 50-a and 50-b. Among these, the control unit 100 outputs various control signals and the like for controlling each unit when image data is supplied from the host computer.
Specifically, first, the control unit 100 supplies a control signal Ctr1 to the carriage motor driver 35, and the carriage motor driver 35 drives the carriage motor 31 according to the control signal Ctr1. Thereby, the movement of the carriage 24 in the main scanning direction is controlled.
Second, the control unit 100 supplies a control signal Ctr2 to the transport motor driver 45, and the transport motor driver 45 drives the transport motor 41 according to the control signal Ctr2. Thereby, the movement in the sub-scanning direction by the transport mechanism 4 is controlled.
Third, the control unit 100 supplies the digital data dA to one of the two drive circuits 50-a and 50-b, and the digital data to the other drive circuit 50-b. Supply dB. Here, the data dA defines the waveform of the drive signal COM-A among the drive signals supplied to the head unit 20, and the data dB defines the waveform of the drive signal COM-B.
Although details will be described later, the drive circuit 50-a supplies the head unit 20 with a drive signal COM-A obtained by performing D-class amplification after analog conversion of the data dA. Similarly, the drive circuit 50-b supplies the head unit 20 with a drive signal COM-B obtained by performing analog conversion on the data dB and then amplifying the class D. The drive circuits 50-a and 50-b are different only in input data and output drive signals, and have the same circuit configuration as described later. For this reason, when it is not necessary to distinguish between the drive circuits 50-a and 50-b (for example, in the case of FIG. 10 described later), “-(hyphen)” and the following are omitted, and the symbol is simply “50”. ".
Fourthly, the control unit 100 supplies the head unit 20 with the clock signal Sck, the data signal Data, and the control signals LAT and CH.

The head unit 20 is provided with a selection control unit 210 and a plurality of sets of selection units 230 and piezoelectric elements (piezo elements) 60.
The selection control unit 210 is supplied from the control unit 100 as to whether one of the drive signals COM-A and COM-B should be selected for each of the selection units 230 (or both should be unselected). Instructed by a control signal or the like, the selection unit 230 selects the drive signals COM-A and COM-B according to the instruction of the selection control unit 210 and supplies them to one end of the piezoelectric element 60 as a drive signal. In the figure, the voltage of this drive signal is expressed as Vout.
In this example, the voltage _VBS is commonly applied to the other end of each of the piezoelectric elements 60.

The piezoelectric element 60 is provided corresponding to each of the plurality of nozzles in the head unit 20. The piezoelectric element 60 is displaced to eject ink in accordance with the difference between the voltage Vout and the voltage V _BS of the drive signal selected by the selection unit 230. Next, a configuration for ejecting ink by driving the piezoelectric element 60 will be briefly described.

FIG. 3 is a diagram illustrating a schematic configuration corresponding to one nozzle in the head unit 20.
As shown in the figure, the head unit 20 includes a piezoelectric element 60, a diaphragm 621, a cavity (pressure chamber) 631, a reservoir 641, and a nozzle 651. Among these, the vibration plate 621 functions as a diaphragm that is displaced (bending vibration) by the piezoelectric element 60 provided on the upper surface in the drawing and expands / reduces the internal volume of the cavity 631 filled with ink. The nozzle 651 is an opening provided in the nozzle plate 632 and communicating with the cavity 631.

  The piezoelectric element 60 shown in this figure has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In the piezoelectric body 601 having this structure, the central portion in the figure along with the electrodes 611 and 612 and the diaphragm 621 bends in the vertical direction with respect to both end portions in accordance with the voltage applied by the electrodes 611 and 612. Specifically, the piezoelectric element 60 is configured to bend upward when the voltage Vout of the drive signal increases, and to bend downward when the voltage Vout decreases. In this configuration, if the ink is bent upward, the internal volume of the cavity 631 is expanded. Therefore, if the ink is drawn from the reservoir 641, if the ink is bent downward, the internal volume of the cavity 631 is reduced. In some cases, ink is ejected from the nozzle 651.

The piezoelectric element 60 is not limited to the illustrated structure, and may be any type that can deform the piezoelectric element 60 and discharge a liquid such as ink. In addition, the piezoelectric element 60 is not limited to bending vibration, and may be configured to use so-called longitudinal vibration.
Further, the piezoelectric element 60 is provided corresponding to the cavity 631 and the nozzle 651 in the head unit 20, and the piezoelectric element 60 is also provided corresponding to the selection unit 230 in FIG. 1. For this reason, the set of the piezoelectric element 60, the cavity 631, the nozzle 651, and the selection unit 230 is provided for each nozzle 651.

FIG. 4A shows an example of the arrangement of the nozzles 651.
As shown in this figure, the nozzles 651 are arranged in, for example, two rows as follows. Specifically, when viewed in one row, the plurality of nozzles 651 are arranged at a pitch Pv along the sub-scanning direction, while the two rows are separated from each other by the pitch Ph in the main scanning direction and are sub-scanned. The relationship is shifted in the direction by half the pitch Pv.
In the case of color printing, the nozzle 651 is provided with a pattern corresponding to each color such as C (cyan), M (magenta), Y (yellow), and K (black) along the main scanning direction, for example. In the following description, for the sake of simplification, a case where gradation is expressed in a single color will be described.

  FIG. 4B is a diagram for explaining the basic resolution of image formation by the nozzle arrangement shown in FIG. This drawing is an example of a method (first method) in which an ink droplet is ejected once from the nozzle 651 to form a single dot for the sake of simplicity, and a black circle is an ink. A dot formed by landing of a droplet is shown.

When the head unit 20 moves at a speed v in the main scanning direction, as shown in the figure, the interval D (in the main scanning direction) of dots formed by the landing of ink droplets and the speed v are: The relationship is as follows.
That is, when one dot is formed by one ink droplet ejection, the dot interval D is a value obtained by dividing the velocity v by the ink ejection frequency f (= v / f), in other words, the ink droplets This is indicated by the distance that the head unit 20 moves in the cycle (1 / f) of repeated ejection.
In the example of FIG. 4, the ink droplets ejected from the two rows of nozzles 651 are landed so as to be aligned in the same row on the print medium P, with the pitch Ph being proportional to the dot interval D by a coefficient n. I am letting. For this reason, as shown in (b), the dot interval in the sub-scanning direction is half of the dot interval in the main scanning direction. Needless to say, the arrangement of dots is not limited to the example shown in the figure.

By the way, in order to realize high-speed printing, simply, the speed v at which the head unit 20 moves in the main scanning direction may be increased. However, simply increasing the speed v increases the dot interval D. For this reason, in order to achieve high-speed printing while ensuring a certain level of resolution, it is necessary to increase the number of dots formed per unit time by increasing the ink ejection frequency f.
In addition to the printing speed, in order to increase the resolution, the number of dots formed per unit area may be increased. However, when the number of dots is increased, if the amount of ink is not reduced, not only the adjacent dots are combined but also the printing speed is reduced unless the ink ejection frequency f is increased.
As described above, in order to realize high-speed printing and high-resolution printing as described above, it is necessary to increase the ink ejection frequency f.

  On the other hand, as a method of forming dots on the print medium P, in addition to a method of ejecting ink droplets once to form one dot, ink droplets can be ejected twice or more in a unit period, A method of forming one dot (second method) by combining one or more ejected ink droplets and combining the landed one or more ink droplets, or combining these two or more ink droplets There is a method (third method) for forming two or more dots. In the following description, a case where dots are formed by the second method will be described.

In the present embodiment, the second method will be described assuming the following example. That is, in the present embodiment, for one dot, the ink is ejected at most twice to express four gradations of large dot, medium dot, small dot, and non-printing. In order to express these four gradations, in this embodiment, two types of drive signals COM-A and COM-B are prepared, and each has a first half pattern and a second half pattern in one cycle. In one period, the drive signals COM-A and COM-B are selected (or not selected) according to the gradation to be expressed and supplied to the piezoelectric element 60 in the first half and second half.
Therefore, the drive signals COM-A and COM-B will be described, and then the configuration for selecting the drive signals COM-A and COM-B will be described. The drive signals COM-A and COM-B are respectively generated by the drive circuit 50. For convenience, the drive circuit 50 is configured to select the drive signals COM-A and COM-B. This will be explained later.

FIG. 5 is a diagram illustrating waveforms of the drive signals COM-A and COM-B.
As shown in the figure, the drive signal COM-A has a trapezoidal waveform Adp1 arranged in the period T1 from the output of the control signal LAT (rise) to the output of the control signal CH in the printing cycle Ta. In the printing cycle Ta, the trapezoidal waveform Adp2 arranged in the period T2 from when the control signal CH is output until the next control signal LAT is output is a continuous waveform.

  In the present embodiment, the trapezoidal waveforms Adp1 and Adp2 are substantially the same as each other, and if each is supplied to one end of the piezoelectric element 60, a specific amount from the nozzle 651 corresponding to the piezoelectric element 60, specifically, Specifically, it is a waveform for ejecting a medium amount of ink.

  The drive signal COM-B has a waveform in which the trapezoidal waveform Bdp1 arranged in the period T1 and the trapezoidal waveform Bdp2 arranged in the period T2 are continuous. In the present embodiment, the trapezoidal waveforms Bdp1 and Bdp2 are different from each other. Among these, the trapezoidal waveform Bdp1 is a waveform for causing the ink near the opening of the nozzle 651 to vibrate and preventing the viscosity of the ink from increasing. For this reason, even if the trapezoidal waveform Bdp1 is supplied to one end of the piezoelectric element 60, ink droplets are not ejected from the nozzle 651 corresponding to the piezoelectric element 60. The trapezoidal waveform Bdp2 is different from the trapezoidal waveform Adp1 (Adp2). If the trapezoidal waveform Bdp2 is supplied to one end of the piezoelectric element 60, it is a waveform that causes an amount of ink smaller than the predetermined amount to be ejected from the nozzle 651 corresponding to the piezoelectric element 60.

  The voltage at the start timing and the voltage at the end timing of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all the same as the voltage Vc. That is, the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are waveforms that start at the voltage Vc and end at the voltage Vc, respectively.

FIG. 6 is a diagram illustrating a configuration of the selection control unit 210 in FIG.
As shown in this figure, the selection control unit 210 is supplied with a clock signal Sck, a data signal Data, and control signals LAT and CH from the control unit 10. In the selection control unit 210, a set of a shift register (S / R) 212, a latch circuit 214, and a decoder 216 is provided corresponding to each of the piezoelectric elements 60 (nozzles 651).

The data signal Data defines the size of the dot when forming one dot of the image. In the present embodiment, in order to express four gradations of non-recording, small dots, medium dots, and large dots, the data signal Data is composed of two bits, an upper bit (MSB) and a lower bit (LSB).
The data signal Data is serially supplied from the control unit 100 in synchronization with the main scanning of the head unit 20 for each nozzle in synchronization with the clock signal Sck. The shift register 212 is a configuration for temporarily holding the serially supplied data signal Data for 2 bits corresponding to the nozzle.
Specifically, the shift registers 212 having the number of stages corresponding to the piezoelectric elements 60 (nozzles) are connected in cascade, and the serially supplied data signal Data is sequentially transferred to the subsequent stage according to the clock signal Sck. ing.
When the number of piezoelectric elements 60 is m (m is a plurality), in order to distinguish the shift register 212, one stage, two stages,..., M stages in order from the upstream side to which the data signal Data is supplied. It is written.

The latch circuit 214 latches the data signal Data held in the shift register 212 at the rising edge of the control signal LAT.
The decoder 216 decodes the 2-bit data signal Data latched by the latch circuit 214 and outputs selection signals Sa and Sb for each of the periods T1 and T2 defined by the control signal LAT and the control signal CH. The selection by the selection unit 230 is defined.

FIG. 7 is a diagram showing the decoding contents in the decoder 216.
In this figure, the latched 2-bit print data Data is expressed as (MSB, LSB). For example, if the latched print data Data is (0, 1), the decoder 216 sets the logic levels of the selection signals Sa and Sb to H and L levels in the period T1 and to L and H levels in the period T2, respectively. , Which means output.
Note that the logic levels of the selection signals Sa and Sb are shifted to higher amplitude logic by a level shifter (not shown) than the logic levels of the clock signal Sck, the print data Data, and the control signals LAT and CH.

FIG. 8 is a diagram illustrating a configuration of the selection unit 230 corresponding to one piezoelectric element 60 (nozzle 651) in FIG.
As shown in this figure, the selection unit 230 includes inverters (NOT circuits) 232a and 232b and transfer gates 234a and 234b.
The selection signal Sa from the decoder 216 is supplied to the positive control terminal that is not circled in the transfer gate 234a, while being logically inverted by the inverter 232a and negative control that is circled in the transfer gate 234a. Supplied to the end. Similarly, the selection signal Sb is supplied to the positive control terminal of the transfer gate 234b, while logically inverted by the inverter 232b and supplied to the negative control terminal of the transfer gate 234b.
The drive signal COM-A is supplied to the input terminal of the transfer gate 234a, and the drive signal COM-B is supplied to the input terminal of the transfer gate 234b. The output ends of the transfer gates 234a and 234b are connected in common and connected to one end of the corresponding piezoelectric element 60.
When the selection signal Sa is at the H level, the transfer gate 234a conducts (turns on) between the input end and the output end, and when the selection signal Sa is at the L level, the transfer gate 234a does not conduct between the input end and the output end. (Off). Similarly, the transfer gate 234b is turned on / off between the input end and the output end according to the selection signal Sb.

  Next, operations of the selection control unit 210 and the selection unit 230 will be described with reference to FIG.

The data signal Data is serially supplied from the control unit 100 for each nozzle in synchronization with the clock signal Sck, and sequentially transferred in the shift register 212 corresponding to the nozzle. Then, when the control unit 100 stops the supply of the clock signal Sck, the data signal Data corresponding to the nozzle is held in each of the shift registers 212. The data signal Data is supplied in the order corresponding to the last m stages,..., Two stages, and one stage nozzles in the shift register 222.
Here, when the control signal LAT rises, each of the latch circuits 214 simultaneously latches the data signal Data held in the shift register 212. In FIG. 5, L1, L2,..., Lm indicate data signals Data obtained by latching the data signal Data by the latch circuit 214 corresponding to the first, second,.

The decoder 216 outputs the logic levels of the selection signals Sa and Sa with contents as shown in FIG. 7 in each of the periods T1 and T2 in accordance with the dot size defined by the latched data signal Data.
That is, first, when the data signal Data is (1, 1) and the size of the large dot is defined, the decoder 216 sets the selection signals Sa and Sb to the H and L levels in the period T1, and the period At T2, the H and L levels are set. Second, when the data signal Data is (0, 1) and the size of the medium dot is defined, the decoder 216 sets the selection signals Sa and Sb to the H and L levels in the period T1, and in the period T2. L and H levels. Third, when the data signal Data is (1, 0) and the size of the small dot is defined, the decoder 216 sets the selection signals Sa and Sb to L and L levels in the period T1, and in the period T2. L and H levels. Fourth, when the data signal Data is (0, 0) and non-recording is specified, the decoder 216 sets the selection signals Sa and Sb to L and H levels in the period T1, and to select L and L in the period T2. Set to L level.

FIG. 9 is a diagram illustrating a voltage waveform of a drive signal that is selected according to the data signal Data and supplied to one end of the piezoelectric element 60.
When the data signal Data is (1, 1), since the selection signals Sa and Sb are at the H and L levels in the period T1, the transfer gate 234a is turned on and the transfer gate 234b is turned off. For this reason, the trapezoidal waveform Adp1 of the drive signal COM-A is selected in the period T1. Since the selection signals Sa and Sb are at the H and L levels also during the period T2, the selection unit 230 selects the trapezoidal waveform Adp2 of the drive signal COM-A.
As described above, when the trapezoidal waveform Adp1 is selected in the period T1, and the trapezoidal waveform Adp2 is selected in the period T2, and supplied to one end of the piezoelectric element 60 as a drive signal, the nozzle 651 corresponding to the piezoelectric element 60 causes A certain amount of ink is ejected in two steps. Therefore, the respective inks land on the print medium P and coalesce, and as a result, large dots as defined by the data signal Data are formed.

When the data signal Data is (0, 1), the selection signals Sa and Sb are at the H and L levels in the period T1, so that the transfer gate 234a is turned on and the transfer gate 234b is turned off. For this reason, the trapezoidal waveform Adp1 of the drive signal COM-A is selected in the period T1. Next, since the selection signals Sa and Sb are at the L and H levels in the period T2, the trapezoidal waveform Bdp2 of the drive signal COM-B is selected.
Therefore, medium and small amounts of ink are ejected from the nozzle in two steps. For this reason, the respective inks land and merge on the print medium P, and as a result, medium dots as defined by the data signal Data are formed.

When the data signal Data is (1, 0), the selection signals Sa and Sb are both at the L level in the period T1, so that the transfer gates 234a and 234b are turned off. For this reason, neither trapezoidal waveform Adp1 nor Bdp1 is selected in the period T1. When the transfer gates 234a and 234b are both turned off, the path from the connection point between the output ends of the transfer gates 234a and 234b to one end of the piezoelectric element 60 is in a high impedance state that is not electrically connected to any part. . However, the piezoelectric element 60 holds the voltage (Vc−V _BS ) immediately before the transfer gate is turned off due to the capacitance of the piezoelectric element 60.

  Next, since the selection signals Sa and Sb are at the L and H levels in the period T2, the trapezoidal waveform Bdp2 of the drive signal COM-B is selected. Therefore, since a small amount of ink is ejected from the nozzle 651 only in the period T2, small dots as defined by the data signal Data are formed on the print medium P.

When the data signal Data is (0, 0), the selection signals Sa and Sb are at the L and H levels in the period T1, so that the transfer gate 234a is turned off and the transfer gate 234b is turned on. For this reason, the trapezoidal waveform Bdp1 of the drive signal COM-B is selected in the period T1. Next, since the selection signals Sa and Sb are both at the L level in the period T2, neither of the trapezoidal waveforms Adp2 and Bdp2 is selected.
For this reason, in the period T1, the ink in the vicinity of the opening of the nozzle 651 only vibrates slightly, and the ink is not ejected. Become a record.

As described above, the selection unit 230 selects (or does not select) the drive signals COM-A and COM-B in accordance with an instruction from the selection control unit 210 and supplies the drive signals COM-A and COM-B to one end of the piezoelectric element 60. For this reason, each piezoelectric element 60 is driven in accordance with the dot size defined by the data signal Data.
Note that the drive signals COM-A and COM-B shown in FIG. 5 are merely examples. Actually, various combinations of waveforms prepared in advance are used according to the moving speed of the head unit 20 and the properties of the print medium P.
In addition, here, the example in which the piezoelectric element 60 bends upward as the voltage increases has been described. However, when the voltage supplied to the electrodes 611 and 612 is reversed, the piezoelectric element 60 increases as the voltage increases. Will bend downward. For this reason, in the configuration in which the piezoelectric element 60 bends downward as the voltage increases, the drive signals COM-A and COM-B illustrated in the figure have waveforms that are inverted with respect to the voltage Vc.

As described above, in the present embodiment, one dot is formed on the printing medium P in units of the period Ta, which is a unit period. For this reason, in this embodiment in which one dot is formed by ejecting ink droplets twice (at most) in the period Ta, the ink ejection frequency f is 2 / Ta, and the dot interval D is the moving speed v of the head unit. Is divided by the ink ejection frequency f (= 2 / Ta).
In general, in the case where the ink droplets can be ejected Q (Q is an integer of 2 or more) times in the unit period T and one dot is formed by ejecting the ink droplets Q times, the ink ejection frequency f is Q / T can be expressed.
As in this embodiment, the case where dots of different sizes are formed on the print medium P is required to form one dot as compared to the case where one dot is formed by ejecting one ink droplet. Even if the time (cycle) is the same, it is necessary to shorten the time because one ink droplet is ejected once.
The third method for forming two or more dots without combining two or more ink droplets will not require any special explanation.

Next, the drive circuits 50-a and 50-b will be described. Of these, one drive circuit 50-a will be summarized as follows. The drive signal COM-A is generated as follows. That is, the drive circuit 50-a first converts the data dA supplied from the control unit 100 into an analog signal, and secondly feeds back the output drive signal COM-A and also outputs the drive signal COM-A. Is corrected with the high frequency component of the drive signal COM-A to generate a modulation signal according to the corrected signal, and thirdly, according to the modulation signal An amplified modulated signal is generated by switching the transistor, and fourthly, the amplified modulated signal is smoothed by a low-pass filter, and the smoothed signal is output as the drive signal COM-A.
The other drive circuit 50-b has the same configuration, and differs only in that the drive signal COM-B is output from the data dB. Therefore, in FIG. 10 below, the drive circuits 50-a and 50-b will be described as the drive circuit 50 without distinction.
However, input data and output drive signals are expressed as dA (dB), COM-A (COM-B), etc., and in the case of the drive circuit 50-a, data dA is input. The drive signal COM-A is output, and in the case of the drive circuit 50-b, the data dB is input and the drive signal COM-B is output.

FIG. 10 is a diagram illustrating a circuit configuration of the drive circuit 50.
As shown in this figure, the drive circuit 50 includes an LSI 500, transistors M3 and M4, and various elements such as resistors and capacitors.

  An LSI (Large Scale Integration) 500 outputs a gate signal to each of the transistors M3 and M4 based on 10-bit data dA (dB) input from the control unit 100 via pins D0 to D9. In order to output such a gate signal, the LSI 500 includes a DAC (Digital to Analog Converter) 502, adders 504 and 506, an integral attenuator 512, an attenuator 514, a comparator 520, a NOT circuit 522, And gate drivers 533 and 534.

The DAC 502 converts data dA (dB) that defines the waveform of the drive signal COM-A (COM-B) into an analog signal Aa and supplies the analog signal Aa to the input terminal (−) of the adder 504. The voltage amplitude of the analog signal Aa is, for example, about 0 to 2 volts, and the drive signal COM-A is obtained by amplifying this voltage about 20 times. That is, the analog signal Aa is a target signal before amplification of the drive signal COM-A.
The integral attenuator 512 attenuates the voltage of the terminal Out input via the pin Vfb, that is, the drive signal COM-A, integrates it, and supplies it to the input terminal (+) of the adder 504.
The adder 504 supplies a voltage signal Ab obtained by subtracting the voltage at the input terminal (−) from the voltage at the input terminal (+) to one of the input terminals of the adder 506.
The power supply voltage of the circuit from the DAC 502 to the NOT circuit 522 is 3.3 volts with a low amplitude. For this reason, while the voltage of the analog signal Aa is about 2 volts at the maximum, the voltage of the drive signal COM-A may exceed 40 volts at the maximum, so that the amplitude range of both voltages is matched when obtaining the deviation. Therefore, the voltage of the drive signal COM-A (COM-B) is attenuated by the integral attenuator 512.

The attenuator 514 attenuates the high frequency component of the drive signal COM-A (COM-B) input via the pin Ifb and supplies the attenuated high frequency component to the other input terminal of the adder 506. The adder 506 supplies a voltage signal As obtained by adding the voltage at one of the input terminals and the voltage at the other to the comparator 520. The attenuation by the attenuator 514 is to adjust the amplitude when the drive signal COM-A (COM-B) is fed back, similarly to the integral attenuator 512.
The voltage of the signal As output from the adder 506 is a voltage obtained by subtracting the voltage of the analog signal Aa from the attenuation voltage of the signal supplied to the pin Vfb and adding the attenuation voltage of the signal supplied to the pin Ifb. . For this reason, the voltage of the signal As by the adder 506 is obtained by taking a deviation obtained by subtracting the voltage of the target analog signal Aa from the attenuation voltage of the drive signal COM-A (COM-B) output from the terminal Out. It can be said that the signal is corrected by the high frequency component of the drive signal COM-A (COM-B).

The comparator 520 outputs a modulation signal Ms pulse-modulated as follows based on the addition voltage from the adder 506. Specifically, the comparator 520 is at the H level when the signal As output from the adder 506 rises when the voltage rises to the voltage threshold Vth1 or more, and when the signal As is at the voltage fall, A modulation signal Ms that becomes L level when the threshold value Vth2 is below is output. As will be described later, the voltage threshold is
Vth1> Vth2
The relationship is set.

  The modulation signal Ms by the comparator 520 is supplied to the gate driver 534 through logic inversion by the NOT circuit 522. On the other hand, the modulation signal Ms is supplied to the gate driver 533 without undergoing logic inversion. For this reason, the logic levels supplied to the gate drivers 533 and 534 are mutually exclusive.

  The logic levels supplied to the gate drivers 533 and 534 may actually be controlled so that they do not become H level at the same time (so that the transistors M3 and M4 are not turned on at the same time). For this reason, the term “exclusive” here means that it is not H level at the same time (the transistors M3 and M4 are not turned on at the same time).

  By the way, the modulation signal here is the modulation signal Ms in a narrow sense, but if it is considered that the signal is pulse-modulated according to the signal Aa, the negative signal of the modulation signal Ms (the output signal of the NOT circuit 522) is also converted into the modulation signal. included. That is, the modulation signal pulse-modulated according to the signal Aa includes not only the modulation signal Ms but also a signal obtained by inverting the logic level of the modulation signal Ms and a signal whose timing is controlled.

Since the comparator 520 outputs the modulation signal Ms, the circuits up to the comparator 520, that is, the DAC 502, the adders 504 and 506, the integral attenuator 512, the attenuator 514, and the comparator 520 are displayed. Can be referred to as a modulation circuit that generates the modulation signal Ms.
In the configuration shown in FIG. 10, the digital data dA (dB) is converted into the analog signal Aa by the DAC 502, but the signal Aa is supplied from an external circuit, for example, according to an instruction from the control unit 100 without passing through the DAC 502. You may receive. Whether it is digital data dA (dB) or analog signal Aa, it defines the target value for generating the waveform of the drive signal COM-A (COM-B), so that it is the source signal There is no change.

The gate driver 533 level-shifts the low logic amplitude modulation signal Ms, which is the output signal of the comparator 520, to a high logic amplitude, and supplies it as a gate signal from the pin Hdr to the gate electrode of the transistor M3 via the resistor R8.
The gate driver 534 shifts the level of the low logic amplitude obtained by logically inverting the modulation signal Ms by the NOT circuit 522 to the high logic amplitude, and supplies it as a gate signal from the pin Ldr to the gate electrode of the transistor M4 via the resistor R9.

The transistors M3 and M4 are, for example, N-channel FETs (Field Effect Transistors). Among these, in the high-side transistor M3, a voltage Vh (for example, 42 volts) is applied to the drain electrode. For the low-side transistor M4, the source electrode is grounded.
Each of the transistors M3 and M4 is turned on when the gate signal is at the H level. Therefore, a modulation amplification signal obtained by amplifying the modulation signal Ms appears at the connection point Sd between the source electrode of the transistor M3 and the drain electrode of the transistor M4, that is, one end of the inductor L2. For this reason, the transistors M3 and M4 output a modulated amplified signal obtained by amplifying the modulated signal Ms.

  The other end of the inductor L2 is a terminal Out that is output from the drive circuit 50, and a drive signal COM-A (COM-B) is sent from the terminal Out to the head unit 20 to the flexible cable 190 (FIGS. 1 and 2). Reference).

  The terminal Out is connected to one end of the capacitor C10, one end of the capacitor C22, and one end of the resistor R4. Among these, the other end of the capacitor C10 is grounded. For this reason, the inductor L2 and the capacitor C10 function as an LPF (Low Pass Filter) that smoothes the amplified modulation signal appearing at the connection point of the transistors M3 and M4.

  The other end of the resistor R4 is connected to the pin Vfb and one end of the resistor R23, and the voltage Vh is applied to the other end of the resistor R23. As a result, the drive signal COM-A (COM-B) from the terminal Out is pulled up and fed back to the pin Vfb.

  The other end of the capacitor C22 is connected to one end of the resistor R5 and one end of the resistor R32. Among these, the other end of the resistor R5 is grounded. For this reason, the capacitor C22 and the resistor R5 function as an HPF (High Pass Filter) that passes a high-frequency component equal to or higher than the cutoff frequency in the drive signal COM-A (COM-B) from the terminal Out. Note that the cutoff frequency of the HPF is set to about 9 MHz, for example.

The other end of the resistor R32 is connected to one end of the capacitor C20 and one end of the capacitor C58. Among these, the other end of the capacitor C58 is grounded. For this reason, the resistor R32 and the capacitor C58 function as an LPF (Low Pass Filter) that allows a low-frequency component having a frequency equal to or lower than the cutoff frequency to pass through among the signal components that have passed through the HPF. Note that the cutoff frequency of the LPF is set to about 160 MHz, for example.
Since the cut-off frequency of the HPF is set lower than the cut-off frequency of the LPF, the HPF and the LPF pass a frequency component in a predetermined frequency region in the drive signal COM-A (COM-B). It functions as a BPF (Band Pass Filter).

  The other end of the capacitor C20 is connected to the pin Ifb of the LSI 500. As a result, the DC component of the frequency component of the drive signal COM-A (COM-B) that has passed through the BPF is cut back to the pin Ifb.

By the way, the drive signal COM-A (COM-B) output from the terminal Out is a signal obtained by smoothing the amplified modulation signal at the connection point Sd of the transistors M3 and M4 by the low-pass filter including the inductor L2 and the capacitor C10. . This drive signal COM-A (COM-B) is integrated / subtracted via the pin Vfb and then fed back to the adder 504. Therefore, a feedback delay (a delay due to smoothing of the inductor L2 and the capacitor C10) The self-excited oscillation occurs at a frequency determined by the transfer function of the feedback).
However, since the delay amount of the feedback path via the pin Vfb is large, the frequency of the self-excited oscillation and the waveform accuracy of the drive signal COM-A (COM-B) can be increased only by the feedback via the pin Vfb. It cannot be made high enough to be secured.

  Therefore, in the present embodiment, when the entire circuit is viewed by providing a path for feeding back the high frequency component of the drive signal COM-A (COM-B) via the pin Ifb separately from the path via the pin Vfb. The delay is small. For this reason, the frequency of the signal As obtained by adding the high-frequency component of the drive signal COM-A (COM-B) to the signal Ab is higher than that in the case where there is no path via the pin Ifb. The accuracy of the signal COM-A (COM-B) is sufficiently secured.

The drive circuit 50 has two paths, a path via the pin Vfb and a path via the pin Ifb, as feedback paths. For this reason, the feedback circuit of the drive circuit 50 includes two paths of resistors R4 and R23 related to the path via the pin Vfb, resistors R5 and R32 related to the path via the pin Ifb, and capacitors C20, C22 and C56. Consists of a minute circuit.
Although not shown in FIG. 10, the drive circuit 50 may be expressed as a feedback circuit Fbc including resistors R4, R5, R23, and R32 and capacitors C20, C22, and C56.

FIG. 11 is a diagram showing the waveforms of the signal As and the modulation signal Ms in association with the waveform of the analog signal Aa.
As shown in this figure, the signal As is a triangular wave, and its oscillation frequency varies according to the voltage (input voltage) of the analog signal Aa. Specifically, it is highest when the input voltage is an intermediate value, and decreases as the input voltage increases from the intermediate value or decreases.

In addition, the slope of the triangular wave in the signal As is approximately equal on the rise (voltage rise) and the fall (voltage drop) when the input voltage is near the intermediate value. Therefore, the duty ratio of the modulation signal Ms, which is the result of comparing the signal As with the voltages Vth1 and Vth2 by the comparator 520, is approximately 50%. When the input voltage increases from the intermediate value, the downward slope of the signal As becomes gentle. For this reason, the period during which the modulation signal Ms is at the H level is relatively long, and the duty ratio is increased. On the other hand, as the input voltage decreases from the intermediate value, the upward slope of the signal As becomes gentle. For this reason, the period during which the modulation signal Ms is at the L level becomes relatively short, and the duty ratio becomes small.
Therefore, the modulation signal Ms is a pulse density modulation signal as follows. That is, the duty ratio of the modulation signal Ms is approximately 50% at the intermediate value of the input voltage, and increases as the input voltage becomes higher than the intermediate value, and decreases as the input voltage becomes lower than the intermediate value.

The gate driver 533 turns on / off the transistor M3 based on the modulation signal Ms as described above. That is, the gate driver 533 turns on the transistor M3 when the modulation signal Ms is at the H level, and turns off the transistor M3 when the modulation signal Ms is at the L level. The gate driver 534 turns on / off the transistor M4 based on the logic inversion signal of the modulation signal Ms. That is, the gate driver 534 turns off the transistor M4 when the modulation signal Ms is at the H level, and turns on the transistor M4 when the modulation signal Ms is at the L level.
Therefore, the voltage of the drive signal COM-A (COM-B) obtained by smoothing the amplified modulated signal at the connection point Sd of the transistors M3 and M4 with the inductor L2 and the capacitor C10 increases as the duty ratio of the modulated signal Ms increases. As the duty ratio decreases, the driving signal COM-A (COM-B) is controlled and output so as to be a signal obtained by expanding the voltage of the analog signal Aa. .

Since this drive circuit 50 uses pulse density modulation, there is an advantage that a change width of the duty ratio can be increased as compared with pulse width modulation in which the modulation frequency is fixed.
That is, since the minimum positive pulse width and negative pulse width that can be handled by the entire circuit are limited by the circuit characteristics, in the pulse width modulation with a fixed frequency, the duty ratio change width is within a predetermined range (for example, from 10%). Only 90%). On the other hand, in pulse density modulation, the oscillation frequency decreases as the input voltage moves away from the intermediate value. Therefore, the duty ratio can be increased in a region where the input voltage is high, and the region where the input voltage is low. In, the duty ratio can be further reduced. For this reason, in the self-excited oscillation type pulse density modulation, a wider range (for example, a range from 5% to 95%) can be secured as a change width of the duty ratio.

In addition, the drive circuit 50 is self-excited and does not require a circuit that generates a high-frequency carrier wave like the separately excited oscillation. For this reason, there is an advantage that it is easy to integrate the functions of the LSI 500 other than the circuit that handles the high voltage.
In addition, in the drive circuit 50, as a feedback path of the drive signal COM-A (COM-B), not only a path via the pin Vfb but also a path for feeding back a high frequency component via the pin Ifb, the entire circuit The delay when viewed is reduced. For this reason, since the frequency of self-excited oscillation becomes high, the drive circuit 50 can generate the drive signal COM-A (COM-B) with high accuracy.

  Such a drive circuit 50 is configured by mounting various elements such as an LSI, a capacitor, and a resistor on a multilayer circuit board. Further, a plurality of sets of drive circuits 50 are mounted on one circuit board. Therefore, how the elements constituting these drive circuits are arranged and mounted on both sides of the circuit board in the drive circuits 50-a and 50-b will be described next.

  FIG. 12 is a diagram showing an arrangement of elements mounted on a front surface as a second mounting surface of the circuit board when the circuit board is viewed in plan view. FIG. 13 shows the circuit board. It is a figure which shows arrangement | positioning of the element mounted in the back surface as a 1st mounting surface in the state seen through from the said surface. Note that the front surface and the back surface are in a relative relationship, and are merely a notation for convenience to distinguish one of the two surfaces. That is, when one surface is assumed to be the front surface, the other surface is the back surface.

  In these drawings, in order to distinguish the elements constituting the drive circuits 50-a and 50-b, the elements constituting the drive circuit 50-a among the elements shown without distinction in FIG. , “−a” is added to the end of the reference numeral, and elements constituting the drive circuit 50-b are indicated with “−b” at the end of the reference sign. For example, the inductor L2-a is an element that configures the drive circuit 50-a, and the transistor M3-b is an element that configures the drive circuit 50-b.

  As shown in these drawings, on the back surface of the circuit board, transistors M3-a and M4-a, an inductor L2-a, a capacitor C10-a, and a feedback circuit Fbc-a constituting the drive circuit 50-a, An LSI 500-b, transistors M3-b and M4-b, an inductor L2-b, a capacitor C10-b, and a feedback circuit Fbc-b constituting the drive circuit 50-b are mounted. That is, in the drive circuits 50-a and 50-b, the constituent elements of the low-pass filter and the constituent elements of the feedback circuits Fbc-a and Fbc-b are all mounted on the back surface on the same side.

  On the other hand, the LSI 500-a constituting the drive circuit 50-a is mounted on the surface of the circuit board at a position that does not overlap with the LSI 500-a mounted on the back surface when viewed in plan. Resistors R8-a and R9-a constituting a and resistors R8-b and R9-b constituting a drive circuit 50-b are mounted.

  In the drive circuit 50-a, the gate signal output from the pin Hdr of the LSI 500-a mounted on the surface passes through the resistor R8-a mounted on the surface, and then passes through a through hole (via) (not shown). Then, it is supplied to the gate electrode of the transistor M3-a mounted on the back surface. The same applies to the gate signal output from the pin Ldr, and is supplied to the gate electrode of the transistor M4-a mounted on the back surface through the through hole after passing through the resistor R9-a mounted on the front surface. . Further, in the drive circuit 50-a, the two feedback signals via the feedback circuit Fbc-a mounted on the back surface pass through the through holes (not shown) and the pins Vfb and Ifb of the LSI 500-a mounted on the front surface. Returned to

  On the other hand, in the drive circuit 50-b, after the gate signal output from the pin Hdr of the LSI 500-b mounted on the back surface is supplied to one end of the resistor R8-b mounted on the front surface through the through hole. Then, the other end of the resistor R8-b is led to the back surface again through the through hole and supplied to the gate electrode of the transistor M3-b. The same applies to the gate signal output from the pin Ldr. After being supplied to one end of the resistor R9-b mounted on the front surface from the pin Ldr of the LSI 500-b mounted on the back surface through the through hole, The other end of the resistor R9-b is led to the back surface again through the through hole and supplied to the gate electrode of the transistor M4-b. In the drive circuit 50-b, the two feedback signals through the feedback circuit Fbc-a mounted on the back surface are fed back to the pins Vfb and Ifb of the LSI 500-b without passing through the through holes as they are.

  In the drive circuit 50 shown in FIG. 10, when the transistors M3 and M4 are turned on / off (switched), a relatively large current of about several amperes flows through the transistors M3 and M4 and the low-pass filter. For this reason, the transistors M3 and M4 and the inductor L2 constituting the low-pass filter are likely to generate heat (first problem), and secondly, noise due to spike current is generated and malfunction is likely to occur (second Two problems have been pointed out.

  Of these, for the first problem, a heat sink, a blower fan, or the like may be installed to promote heat dissipation of the heating element. In the present embodiment, elements that easily generate heat, specifically, the transistors M3-a, M4-a, M3-b, and M4-b, and the inductors L2-a and L2-b are concentrated on the back surface. It is only necessary to take measures against heat generation on the back surface, and the configuration for heat dissipation can be simplified as compared with a configuration in which heating elements are distributed and mounted on both surfaces.

The second problem is that, in FIG. 10, among the inductor L2 and the capacitor C10 constituting the low-pass filter, noise is superimposed on the signal fed back via the pins Vfb and Ifb, particularly by the inductance component parasitic on the capacitor C10. It has been confirmed by the inventor's simulation that it causes malfunction.
Therefore, regarding the second problem, in the present embodiment, among the elements constituting the low-pass filter, the constituent elements of the capacitor C10-a (C10-b) and the feedback circuit Fbc-a (Fbc-b) are all the same. This is dealt with by mounting on the back surface of the side and patterning the ground on the back surface as follows.

FIG. 14 is a diagram showing a wiring pattern on the back surface of the circuit board, and particularly shows the drive circuit 500-b. FIG. 15 is a plan view showing the arrangement of elements constituting the drive circuit 500-b in relation to the wiring pattern shown in FIG. 14 on the circuit board.
As shown in these drawings, the other end X1 of the capacitor C10-b is connected to the ground pattern G1 as the first ground wiring. Further, the ground terminals X2 and X3 in the constituent elements of the feedback circuit Fbc-b are connected to the ground pattern G2 as the second ground wiring. As shown in FIG. 14, the ground patterns G1 and G2 are electrically common ground patterns formed on the back surface.
In FIG. 10, the ground terminal X2 is the other end of the resistor R5, and the ground terminal X3 is the other end of the capacitor C58. The source electrode of the transistor M4-b is also connected to the common ground pattern.

By the way, when the components of the drive circuit 50 are mounted on both sides of the circuit board, some elements can be mounted on the front surface, and other elements can be mounted on the back surface. However, in the configuration in which, for example, the capacitor C10 is mounted on one surface and the feedback circuit Fbc is mounted on the other surface, the grounds of both are connected through a through hole. For this reason, when driving at a relatively high frequency as in the present embodiment, it becomes equivalent to a state in which a relatively large inductance component is parasitic on the other end of the capacitor C10, which causes the above malfunction.
On the other hand, in the present embodiment, the constituent elements of the capacitor C10-b and the feedback circuit Fbc-b are all mounted on the back surface on the same side, and the other end X1 of the capacitor is connected to the ground terminals X2, X3 of the feedback circuit. Is used as an integrated common ground pattern, so that the effect of parasitic inductance components is reduced compared to the configuration in which the other end of the capacitor is connected to the grounding end of the feedback circuit via a through-hole. Can do it.

In FIG. 14, a through hole N1 is provided in a pattern including a terminal Out (output) which is a connection point between the other end of the inductor L2-b and one end of the capacitor C10-b. In the feedback circuit Fbc-b, a through hole N2 is provided in a pattern including a connection point between one end of the capacitor C22 and one end of the resistor R4. Here, in the circuit diagram of FIG. 10, the terminal Out is divided into two systems and fed back to the pins Vfb and Ifb of the LSI 500, but actually, as shown in FIG. 14 and FIG. It is led from the through hole N1 of the out to the interpolated wiring pattern (not shown) and led to the back surface again through the through hole N2 before the LSI 500, and branches to one end of the resistor R4 and one end of the capacitor C22. It is the composition to do. Among these, the path on the resistor R4 side is fed back to the pin Vfb, and the path on the capacitor C22 side is fed back to the pin Ifb.
The interpolated wiring pattern here is a wiring layer interpolated between the front surface and the back surface when the front surface wiring pattern is the first layer and the back surface wiring pattern is g (g is an integer of 3 or more). That is, it means a wiring pattern composed of the second layer, the third layer,..., The (g-1) th layer.

  A through hole N3 is provided in the pattern to which the drain electrode of the transistor M3-b is connected. A through hole N4 is provided in the pattern connected to the other end of the resistor R23 in the feedback circuit Fcb-b. These through holes N3 and N4 are connected to an interpolation pattern (not shown) and applied with a voltage Vh.

  A through hole N6 is provided in the pattern including the connection point between the source electrode of the transistor M3-b and the drain electrode of the transistor M4-b. A through hole N7 is provided in a pattern connected to one end of the inductor L2-b. From the through hole N6, it is led to an interpolated wiring pattern (not shown) and again led to the back surface through the through hole N7. Thereby, the connection point Sd and one end of the inductor L2-b are electrically connected.

  Although the wiring pattern of the drive circuit 50-b has been described here, the wiring pattern in the drive circuit 50-a, particularly the periphery of the transistors M3-a and M3-a, the inductor L2-a, and the capacitor C10-a. 14 and 15, the line pattern of the drive circuit 50-b is substantially symmetric with respect to the straight line E in FIG. However, the feedback circuit Fbc-a is shifted to the right side in the drawing, that is, the side where the transistors M3-a and M4-a are located. Also in the drive circuit 50-a, although not shown in particular, it is an integrated common ground pattern from the other end of the capacitor C10-a to the ground end of the feedback circuit Fbc-a.

  The present invention is not limited to the above-described embodiments, and various modifications and applications as described below are possible, for example. In addition, the aspect of the deformation | transformation and application described below can also combine suitably arbitrarily selected 1 or several.

  In the embodiment, the LSI 500-b is mounted on the back surface on the same side as the transistors M3-b, M4-b, the inductor L2-b, the capacitor C10-b, and the feedback circuit Fbc-b. good. Further, since the transistors M3-b and M4-b and the inductor L2-b are preferably mounted on the same surface from the viewpoint of heat dissipation as described above, the transistors M3-a, M4-a and inductor Along with L2-a, it may be mounted not on the back surface but on the front surface.

In the embodiment, the drive circuit 50 is configured to feed back the drive signal COM-A (COM-B) obtained by smoothing the amplified modulated signal with a low-pass filter when generating the modulated signal Ms. However, the drive signal 50 feeds back the modulated signal Ms itself. May be. For example, although not particularly illustrated, an error between the modulation signal Ms and the input signal As is calculated, and a signal obtained by delaying the error is added to or subtracted from the target signal Aa. It is good also as composition to do.
Note that the amplified modulated signal appearing at the connection point Sd with the transistors M3 and M4 only differs in logic amplitude from the modulated signal Ms, and therefore, for example, after the amplified modulated signal is attenuated, the amplified signal is fed back in the same manner as the modulated signal Ms. What should I do?

In the embodiment shown in FIG. 2, for convenience of explanation, the number of nozzles is relatively small, and the two drive circuits 50-a and 50-b respectively drive the signals COM-A and COM-B. However, a drive circuit that outputs drive signals COM-C, COM-D,... May be provided. That is, the number of drive circuits is not limited to “2”.
For the printing apparatus 1, a head unit having a plurality of nozzles 651 is not in a form of ejecting ink while reciprocating in the main scanning direction, and the nozzles are arranged in a direction orthogonal or oblique to the sub-scanning direction. A so-called line printer in which a plurality of head units are provided and the head units are fixed to the housing may be used.

  In the embodiment, the piezoelectric element 60 that ejects ink has been described as an example of the drive target of the drive circuit 50. However, the drive target is not limited to the piezoelectric element 60, and for example, an ultrasonic motor, a touch panel, a flat speaker, and a liquid crystal It may be a capacitive load such as a display. That is, the drive circuit 50 may be any capacitive load drive circuit that drives such a capacitive load.

DESCRIPTION OF SYMBOLS 1 ... Printing apparatus (liquid discharge apparatus), 10 ... Control unit, 20 ... Head unit, 50 ... Drive circuit, 60 ... Piezoelectric element, 520 ... Comparator, L2 ... Inductor, C10 ... Capacitor, M3, M4 ... Transistor, 600 ... discharge part, 631 ... cavity, 651 ... nozzle.

Claims (5)

A drive circuit for driving a capacitive load by a drive signal,
A modulation circuit that generates a modulation signal obtained by pulse-modulating the source signal;
A transistor for amplifying the modulated signal to generate an amplified modulated signal;
Includes an inductor and a capacitor, a low pass filter to generate the drive signal by smoothing the amplified modulated signal,
A feedback circuit for feeding back the drive signal to the modulation circuit;
A circuit board on which the modulation circuit, the transistor, the low-pass filter, and the feedback circuit are mounted;
With
The circuit board is
Including a first mounting surface and a second mounting surface;
On the first mounting surface,
The capacitor and the feedback circuit are mounted, and a first ground wiring connected to the capacitor and a second ground wiring connected to the feedback circuit are provided,
On the second mounting surface,
At least one of the modulation circuit, the transistor, and the inductor is mounted .
A driving circuit for driving a capacitive load, wherein the transistor and the inductor are mounted on the same mounting surface . The drive circuit for driving a capacitive load according to claim 1, wherein the frequency of the modulation signal is 1 MHz or more and 8 MHz or less. The drive circuit for driving a capacitive load according to claim 1, wherein the first ground wiring and the second ground wiring are an integrated pattern. A drive circuit according to any one of claims 1 to 3,
A piezoelectric element that is the capacitive load and is displaced by application of the drive signal;
Inside and droplets are filled, the cavity internal volume is changed by the displacement of the piezoelectric element,
A nozzle provided for discharging the liquid in the cavity according to a change in the internal volume of the cavity;
A liquid ejection apparatus comprising: In the first mounting surface,
And the plurality of capacitors, with a plurality of said feedback circuit is implemented, according to claim 4, a plurality of the first ground wiring, characterized in that a plurality of the second ground wiring is provided Liquid ejection device.

Images