JP6972686B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

The electric power steering device has a motor that is a source of assist force. The motor is driven by, for example, a drive circuit. The drive circuit is composed of a group of switching elements arranged on a substrate to generate three-phase AC power.

Japanese Unexamined Patent Publication No. 2010-195219

By the way, in the drive circuit shown in Patent Document 1, a field effect transistor (FET) which is a component of the drive circuit of each phase (U phase, V phase, W phase) is arranged on a substrate. When the FET is arranged on the substrate, the drive circuits of each phase are usually arranged adjacent to each other on one side of the substrate (see FIG. 6 as a comparative example). In this case, for example, the electric power supplied from the battery is transmitted to the motor through the U-phase drive circuit and then to the ground through the W-phase drive circuit. In such a path, the length of the path through which the current flows (wiring loop) becomes the largest, and the interlinkage magnetic flux with respect to this wiring loop also becomes large. Then, when the interlinkage magnetic flux of the drive circuit becomes large, the surge voltage in switching becomes large. In addition, the torque ripple also increases. Therefore, there has been a demand for a method of reducing the interlinkage magnetic flux of the drive circuit.

Not only when the wiring loop becomes the largest, for example, the electric power supplied from the battery is transmitted to the motor through the U-phase drive circuit and then to the ground through the V-phase drive circuit. Even in such cases, it is significant to reduce the interlinkage magnetic flux. This is because even in this case, the surge voltage in switching can be reduced.

The present invention is to provide a semiconductor device capable of reducing the interlinkage magnetic flux.

A semiconductor device capable of achieving the above object includes a substrate and a plurality of half bridges arranged on the substrate and connected in series with an upper switching element connected to a power source and a lower switching element grounded. In a semiconductor device in which the plurality of half bridges are arranged in parallel, at least one upper switching element is arranged on the first surface of the substrate, and the plurality of half bridges are arranged on the second surface of the substrate opposite to the first surface. The lower switching element is arranged, and the substrate is provided with a path for electrically connecting the upper switching element and the lower switching element belonging to the same half bridge, and the path is the path. It has a portion that penetrates the substrate.

First, as a comparative example, when trying to arrange the upper switching element and the lower switching element of each phase on the same surface of the substrate, there is a half between the upper switching element of one half bridge and the upper switching element of another half bridge. The lower switching element of the bridge will be placed. Therefore, the length of the plurality of half bridges in the semiconductor device in the line-up direction becomes long.

In this regard, by providing a path that electrically connects both sides of the substrate through the substrate, the upper switching element and the lower switching element belonging to the same half bridge can be separately arranged on both sides of the substrate. .. It is not necessary to arrange the lower switching element of a certain half bridge between the upper switching element of one half bridge and the upper switching element of another half bridge. Therefore, the length of the plurality of half bridges in the semiconductor device in the line-up direction can be shortened. As a result, the wiring loop (area when viewed from the direction orthogonal to the surface on which the wiring is provided) of the semiconductor device can be reduced, so that the interlinkage magnetic flux can be further reduced.

In the above semiconductor device, it is preferable that the upper switching element and the lower switching element belonging to the same half bridge are arranged side by side in a direction orthogonal to the direction in which the plurality of phase half bridges are arranged.

According to this configuration, the upper switching element and the lower switching element belonging to the same half bridge can be separately arranged on both sides of the board by providing a path for electrically connecting both sides of the board through the board. .. As a result, even if the upper switching element and the lower switching element belonging to the same half bridge are provided at the same position in the direction in which the plurality of half bridges are lined up, they do not interfere with each other. By arranging the upper switching element and the lower switching element belonging to the same half bridge side by side in the direction orthogonal to the direction in which the plurality of half bridges are lined up, the upper switching element and the lower switching element belonging to a certain half bridge are arranged. It is also possible to arrange the upper switching element and the lower switching element of another half bridge adjacent to each other. Therefore, the length of the plurality of half bridges in the line-up direction in the semiconductor device can be made shorter, so that the interlinkage magnetic flux can be made smaller.

In the above semiconductor device, in the upper switching element and the lower switching element, the direction in which the source electrode and the drain electrode are arranged is such that the wiring between the upper switching element and the lower switching element in the half bridge extends. It is preferable that it matches the direction.

As a comparative example, when the direction in which the source electrodes and drain electrodes of the upper switching element and the lower switching element are arranged is orthogonal to the direction in which the wiring between the upper switching element and the lower switching element extends, a plurality of semiconductor devices are used. The length of the phase half bridge in the line-up direction becomes long. This is because the wiring coming out from the direction in which the source electrode and the drain electrode of the upper switching element and the lower switching element are lined up must finally go in the direction of the wiring between the upper switching element and the lower switching element. This is because an extra part is generated.

On the other hand, if the direction in which the source electrode and the drain electrode are lined up coincides with the direction of the wiring between the upper switching element and the lower switching element, there is no extra portion, and the plurality of phases in the semiconductor device are not generated. The length of the half bridges in the line-up direction can be shortened. Therefore, the interlinkage magnetic flux can be made smaller.

In the above semiconductor device, when the substrate is viewed from the opposite direction of the first surface and the second surface, the upper switching element and the lower switching element belonging to the same half bridge are the same. It is preferable that the half bridges are arranged at positions offset by a predetermined amount from each other in a direction orthogonal to the direction in which the plurality of half bridges are lined up.

In the above semiconductor device, a shunt resistor for detecting a current flowing through each phase is arranged on the substrate, and when the substrate is viewed from the opposite direction of the first surface and the second surface, The shunt resistor is arranged at a position deviated by a predetermined amount of deviation from at least one of the upper switching element and the lower switching element of the same phase in a direction orthogonal to the direction in which the plurality of half bridges are lined up. Is preferable.

According to these configurations, the heat radiated from the upper switching element and the heat radiated from the lower switching element are generated by the deviation between the upper switching element and the lower switching element by a predetermined amount of deviation. Can be suppressed from overlapping. Further, the heat radiated from at least one of the upper switching element and the lower switching element and the shunt due to the shunt resistance being displaced by a predetermined deviation amount with respect to at least one of the upper switching element and the lower switching element. It is possible to suppress the overlap with the heat radiated from the resistor.

In the above semiconductor device, power is supplied to the power supply target via the half bridge, and the direction of the current flowing from the power supply to the power supply target via the upper switching element is from the power supply target to the lower side. It is preferable that the direction is deviated from the direction opposite to or orthogonal to the direction of the current flowing to the ground via the side switching element.

According to this configuration, the direction of the current flowing from the power supply to the power supply target via the upper switching element is opposite to the direction of the current flowing from the power supply target to the power supply target via the lower switching element. The magnetic fluxes generated by the electric current cancel each other out. Further, the direction of the current flowing from the power supply to the power supply target via the upper switching element is deviated from the direction orthogonal to the direction of the current flowing from the power supply target to the ground via the lower switching element. A component is generated in which the magnetic fluxes generated by both currents cancel each other out. Since the magnetic fluxes generated by both currents cancel each other out, the interlinkage magnetic flux can be reduced.

In the above semiconductor device, each switching element has two surfaces in a direction orthogonal to the direction in which the plurality of half bridges are lined up, and the two surfaces have terminals and drains corresponding to source electrodes, respectively. Terminals corresponding to the electrodes are extended, and these terminals are electrically connected to the path at a position overlapping the path when the substrate is viewed from the direction in which the first surface and the second surface face each other. It is preferable to be connected.

According to this configuration, the wiring loop of the semiconductor device is reduced, so that the interlinkage magnetic flux can be reduced.

According to the semiconductor device of the present invention, the interlinkage magnetic flux can be made smaller.

The circuit diagram which shows the schematic structure of the drive device for a vehicle which used the drive circuit of 1st Embodiment. (A) is a structural diagram showing a schematic configuration when the drive circuit of the first embodiment is viewed from the upper surface of the substrate, and (b) is a cross section showing a schematic cross section of the W phase drive circuit in FIG. 2 (a). figure. (A) is a diagram for explaining the positional relationship between the upper MOS arranged on the substrate and the lower MOS, and (b) is a comparative example of the positional relationship between the lower MOS arranged on the substrate and the shunt resistance. Illustration to explain. (A) is a structural diagram showing a schematic structure of a switching element of a drive circuit of the first embodiment, (b) is a structural diagram showing a schematic configuration of a switching element of a drive circuit of another embodiment, (c) is a structural diagram. , A structural diagram showing a schematic configuration of a switching element of a drive circuit of another embodiment. (A) is a structural diagram showing the mounting structure of the lower MOS in the vicinity of the via in the drive circuit of the first embodiment on the substrate, and (b) is the lower side in the vicinity of the via in the drive circuit of another embodiment. A structural diagram showing a structure for mounting a MOS on a substrate. Top view for explaining the magnitude of the interlinkage magnetic flux generated in the drive circuit of the comparative example. (A) is a top view for explaining the magnitude of the interlinkage magnetic flux generated in the drive circuit of the drive circuit of the first embodiment, and (b) is along the 7b-7b cross-sectional line of FIG. 7 (a). Schematic cross-sectional view partially showing a U-phase drive circuit and a W-phase drive circuit. (A) is a structural diagram showing a schematic configuration when the drive circuit of the second embodiment is viewed from the upper surface of the substrate, and (b) is a cross section showing a schematic cross section of the W phase drive circuit in FIG. 8 (a). figure. (A) is a structural diagram showing a schematic configuration when the drive circuit of another embodiment is viewed from the upper surface of the substrate, and (b) is a cross section showing a schematic cross section of the W-phase drive circuit in FIG. 9 (a). figure.

<First Embodiment>
Hereinafter, a first embodiment in which a drive circuit as a semiconductor device is applied to a drive device for a vehicle will be described.

The drive device 1 shown in FIG. 1 is for supplying electric power to a motor 2 (power supply target) for applying an assist force to the steering system of a vehicle. As the motor 2, a three-phase (U-phase, V-phase, W-phase) brushless motor is adopted. The drive device 1 includes a drive circuit 3 that supplies electric power to the motor 2, and a microcomputer 4 (microcomputer) that controls the operation of the drive circuit 3.

The drive circuit 3 has a plurality of switching elements. The drive circuit 3 converts DC power from the battery 11 mounted on the vehicle into three-phase AC power by turning on or off a plurality of switching elements. As the switching element, a MOS-FET (field effect transistor: metal-oxide-semiconductor field-effect-transistor) is adopted.

The drive circuit 3 has first to third upper side MOS12Hu, 12Hv, 12Hw connected to the battery side, and first to third lower side MOS12Lu, 12Lv, 12Lw connected to the ground side. The drive circuit 3 is formed by connecting the first to third switching arms 13u, 13v, and 13w, which are a set of two switching elements, in parallel. The first switching arm 13u is formed by connecting the first upper side MOS12Hu and the first lower side MOS12Lu in series. The second switching arm 13v is formed by connecting the second upper side MOS12Hv and the second lower side MOS12Lv in series. The third switching arm 13w is formed by connecting the third upper side MOS12Hw and the third lower side MOS12Lw in series.

The drain electrodes de of the first to third upper MOS12Hu, 12Hv, 12Hw are connected to the battery 11 via the drain wirings 15u, 15v, 15w, respectively. The source electrodes se of the first to third lower MOS12Lu, 12Lv, 12Lw are connected to the ground via the source wirings 16u, 16v, 16w, respectively. Further, the source electrodes se of the first to third upper MOS12Hu, 12Hv, 12Hw and the drain electrodes de of the first to third lower MOS12Lu, 12Lv, 12Lw are connected to each other via intermediate wirings 17u, 17v, 17w. ing. The intermediate wirings 17u, 17v, 17w (midpoints of the first to third switching arms 13u, 13v, 13w) are connected to the motor coils 2u, 2v, 2w of each phase via the power lines 18u, 18v, 18w, respectively. It is connected.

The microcomputer 4 is connected to the gate electrodes g of the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw via the gate wirings 19u, 19v, 19w, 22u, 22v, 22w, respectively. It is connected. The microcomputer 4 takes in state quantities such as steering torque and rotation angle of the motor 2 detected by various sensors mounted on the vehicle, and generates a motor control signal (voltage signal) based on these state quantities. Then, the microcomputer 4 controls the on / off of the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw by applying the motor control signal to each gate electrode g. The DC power of the battery 11 is converted into three-phase AC power by turning on and off the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw according to the motor control signal. .. The converted three-phase AC power is supplied to the motor 2 via the power lines 18u, 18v, 18w.

Further, the drive circuit 3 is provided with first to third motor relays 14u, 14v, 14w. The first to third motor relays 14u, 14v, 14w are provided in the middle of the power lines 18u, 18v, 18w. For example, MOS-FETs are used as the first to third motor relays 14u, 14v, 14w. The first to third motor relays 14u, 14v, 14w are normally maintained in the ON state. These first to third motor relays 14u, 14v, 14w are switched to the off state when, for example, a disconnection failure or a short circuit failure occurs in the drive circuit 3. By cutting off the power supply path (power lines 18u, 18v, 18w) between the drive circuit 3 and the motor 2, the power supply from the drive circuit 3 to the motor 2 is cut off. The gate electrodes g of the first to third motor relays 14u, 14v, 14w are connected to the microcomputer 4 via gate wirings 20u, 20v, 20w, respectively. The microcomputer 4 controls the on / off of the first to third motor relays 14u, 14v, 14w by applying or stopping the voltage signal.

Further, in order to detect the current actually applied to the motor 2, the first to third shunt resistors 21u, 21v between the first to third switching arms 13u, 13v, 13w of each phase and the ground, respectively. , 21w are provided. The microcomputer 4 detects the actual current value flowing in each phase of the motor 2 by detecting the voltage across the first to third shunt resistors 21u, 21v, 21w when the current flows.

Next, the schematic configuration of the drive circuit 3 will be described with reference to FIGS. 2 (a) and 2 (b). In FIG. 2A, for convenience, each wiring which is a component of the drive circuit 3 provided on the front surface (first surface) of the substrate B is provided on the back surface (second surface) of the substrate B. It is shown larger than the components. Further, in FIG. 2A, when the substrate B is viewed from the front surface side, the components on the front surface of the drive circuit 3 are represented by solid lines, and the components on the back surface are represented by broken lines.

As shown in FIG. 2A, first to third upper MOS12Hu, 12Hv, 12Hw, first to third lower MOS12Lu, 12Lv, 12Lw, first to third motors, which are components of the drive circuit 3, The relays 14u, 14v, 14w and the first to third shunt resistors 21u, 21v, 21w are separately arranged on both sides of the substrate B. As the substrate B, for example, a printed circuit board is adopted. The U-phase portion of the drive circuit 3 is referred to as a U-phase drive circuit 3u, the V-phase portion is referred to as a V-phase drive circuit 3v, and the W-phase portion is referred to as a W-phase drive circuit 3w.

The U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w are arranged in the Y direction (vertical direction in FIG. 2A) of the substrate B. The U-phase drive circuit 3u and the V-phase drive circuit 3v, and the V-phase drive circuit 3v and the W-phase drive circuit 3w are arranged adjacent to each other in the Y direction.

When the substrate B is viewed from the surface side, the first upper MOS12Hu, the first lower MOS12Lu, the first motor relay 14u, and the first shunt resistor 21u, which are the components of the U-phase drive circuit 3u, are in the X direction (FIG. 2 (a) are arranged side by side in the left-right direction) and are electrically connected to each other. Specifically, the first upper MOS12Hu and the first motor relay 14u are arranged side by side in the X direction on the surface of the substrate B, and the first lower MOS12Lu and the first shunt resistor 21u are arranged in the X direction on the back surface of the substrate B. They are arranged side by side. Similarly, the V-phase drive circuit 3v and the W-phase drive circuit 3w have their respective components arranged side by side in the X direction, and the respective components are electrically connected to each other.

Next, the drive circuit 3 (3u, 3v, 3w) will be described in detail with reference to FIGS. 2 (a) and 2 (b). The drain electrodes de and source electrodes of the first to third upper MOS12Hu, 12Hv, 12Hw, the first to third lower MOS12Lu, 12Lv, 12Lw, and the first to third motor relays 14u, 14v, 14w, respectively. se is formed on the surface of the substrate B side. For the sake of simplification of the drawings, the drain electrode de, the source electrode se, and the gate electrode ge are not shown in FIG. 2A, and the gate electrode ge is shown in FIG. 2B. It is omitted.

First, the W phase drive circuit 3w will be described in detail.
As shown in FIGS. 2A and 2B, wirings Wmw, Wpw1 and Wpw2 are arranged in order from the left on the surface of the substrate B. The wiring Wmw is connected to the motor terminal Tm corresponding to the W phase of the motor 2. The wiring Wmw constitutes a part of the power line 18w. Further, the wiring Wpw2 is connected to the power supply terminal Tp, which is a path through which the DC power flows, which is connected to the battery 11. The wiring Wpw2 constitutes a part of the drain wiring 15w. A third upper side MOS12Hw is arranged between the wiring Wpw2 and the wiring Wpw1. The drain electrode de of the third upper side MOS12Hw is connected to the wiring Wpw2, and the source electrode se of the third upper side MOS12Hw is connected to the wiring Wpw1. Further, a third motor relay 14w is arranged between the wiring Wpw1 and the wiring Wmw. The drain electrode de of the third motor relay 14w is connected to the wiring Wpw1, and the source electrode se of the third motor relay 14w is connected to the wiring Wmw. The wiring Wpw1 constitutes a part of the intermediate wiring 17w and the power line 18w.

Wiring Wgw1, Wgw2, Wgw3 are arranged in order from the left on the back surface of the substrate B. The wiring Wgw3 is connected to the ground terminal Tg. The wiring Wgw3 constitutes a part of the source wiring 16w. A third shunt resistor 21w is arranged between the wiring Wgw3 and the wiring Wgw2. Further, a third lower side MOS12Lw is arranged between the wiring Wgw2 and the wiring Wgw1. The drain electrode de of the third lower side MOS12Lw is connected to the wiring Wgw2, and the source electrode se of the third lower side MOS12Lw is connected to the wiring Wgw1. The wiring Wgw2 constitutes a part of the source wiring 16w.

Further, when the drive circuit 3 is viewed from the Z direction (the direction of the paper surface in FIG. 2A) orthogonal to the surface of the substrate B, the third lower side MOS12Lw overlaps with the wiring Wpw1 (opposes via the substrate B). It is arranged like this. Further, when the drive circuit 3 is viewed from the Z direction, the third upper side MOS12Hw is arranged so as to overlap with the wiring Wgw2. Further, when the drive circuit 3 is viewed from the Z direction, the third shunt resistor 21w is arranged so as to overlap the wiring Wpw2. Further, the directions of the source electrode se and the drain electrode de of the third upper side MOS12Hw, the third lower side MOS12Lw, and the third motor relay 14w coincide with each other in the X direction.

The substrate B is provided with a via Vw that electrically connects the wiring Wpw1 and the wiring Wgw1. As a result, the source electrode se of the third upper MOS12Hw and the drain electrode de of the third motor relay 14w and the source electrode se of the third lower MOS12Lw are electrically connected by the via Vw. As the via Vw, for example, a through-hole type via is adopted. The via Vw is a circular hole penetrating the substrate B in the Z direction, and the inner wall surface of the hole is plated with copper to electrically connect the wiring Wpw1 and the wiring Wgw1. .. Further, a plurality of vias Vw are provided in order to increase the conductivity between the wiring Wpw1 and the wiring Wgw1.

Next, the U-phase drive circuit 3u will be described. However, the detailed description of the configuration similar to that of the W phase will be omitted.
Wiring Wmu, Wpu1 and Wpu2 are arranged in order from the left on the surface of the substrate B. The wiring Wmu is connected to the motor terminal Tm (U phase). Further, the wiring Wpu2 is connected to the power supply terminal Tp. A first upper side MOS12Hu is arranged between the wiring Wpu2 and the wiring Wpu1. Further, a first motor relay 14u is arranged between the wiring Wpu1 and the wiring Wmu. Wiring Wgu1, Wgu2, and Wgu3 are arranged in order from the left on the back surface of the substrate B. The wiring Wgu3 is connected to the ground terminal Tg. Further, a first shunt resistor 21u is arranged between the wiring Wgu3 and the wiring Wgu2.

Further, the substrate B is provided with a via Vu that electrically connects the wiring Wpu1 and the wiring Wgu1. That is, the source electrode se of the first upper MOS12Hu and the drain electrode de of the first motor relay 14u and the source electrode se of the first lower MOS12Lu are electrically connected by a via Vu.

Next, the V-phase drive circuit 3v will be described.
Wiring Wmv, Wpv1, Wpv2 are arranged in order from the left on the surface of the substrate B. The wiring Wmv is connected to the motor terminal Tm (V phase). Further, the wiring Wpv2 is connected to the power supply terminal Tp. A second upper side MOS12Hv is arranged between the wiring Wpv2 and the wiring Wpv1. Further, a second motor relay 14v is arranged between the wiring Wpv1 and the wiring Wmv. Wiring Wgv1, Wgv2, Wgv3 are arranged in order from the left on the back surface of the substrate B. The wiring Wgv3 is connected to the ground terminal Tg. Further, a second shunt resistor 21v is arranged between the wiring Wgv3 and the wiring Wgv2.

Further, the substrate B is provided with a via Vv that electrically connects the wiring Wpv1 and the wiring Wgv1. That is, the source electrode se of the second upper MOS12Hv and the drain electrode de of the second motor relay 14v and the source electrode se of the second lower MOS12Lv are electrically connected by a via Vv.

Further, as shown in FIG. 3A, the third upper side MOS12Hw and the third lower side MOS12Lw are arranged at positions deviated from each other in the X direction when viewed from the Y direction. The deviation width between the third upper side MOS12Hw and the third lower side MOS12Lw is set to be equal to or larger than the thickness of the substrate B (predetermined amount of deviation). As shown by the broken line in FIG. 3A, it is considered that the heat transferred from the third upper MOS12Hw and the third lower MOS12Lw to the substrate B diffuses at about 45 degrees with respect to the front surface and the back surface of the substrate. This is because it is done. Although the heat generated by the third upper MOS12Hw spreads by the thickness of the substrate B when it is transferred from the front surface to the back surface of the substrate B, the third upper MOS12Hw and the third lower MOS12Lw are provided at positions deviated by the substrate thickness or more. Therefore, it is considered that the heat generated in the third upper side MOS12Hw is not transferred to the third lower side MOS12Lw. Further, it is considered that the heat generated in the third lower side MOS12Lw also spreads by the thickness of the substrate B when it is transmitted from the back surface to the front surface of the substrate B, but is not transferred to the third upper side MOS12Hw. Further, in the substrate B, it is considered that there is no place where the heat diffused from the third upper side MOS12Hw and the heat diffused from the third lower side MOS12Lw overlap (transmit together). Therefore, by setting the deviation width between the third upper MOS12Hw and the third lower MOS12Lw to be equal to or larger than the thickness of the substrate, the heat diffused from the third upper MOS12Hw and the heat diffused from the third lower MOS12Lw overlap. The part can be suppressed.

As shown in FIG. 2B, the third shunt resistor 21w is also arranged at a position shifted in the X direction with respect to the third upper MOS12Hw when viewed from the Y direction. The deviation width between the third shunt resistor 21w and the third upper side MOS12Hw is set to be equal to or larger than the thickness of the substrate.

Next, the third lower side MOS12Lw will be described in detail.
FIG. 4A shows the back surface (the surface on the substrate B side) of the third lower side MOS12Lw. The third lower side MOS 12Lw has a main body portion 30 including a semiconductor element (MOS-FET) and the like, and a plurality of terminals 31 and 32 extending from the main body portion 30. The main body 30 is packaged by covering the semiconductor element with an insulating resin. As an example, the terminal 31 corresponds to the drain electrode de, and the terminal 32 corresponds to the source electrode se. A part of the plurality of terminals 31 may be a gate electrode ge, the rest of the plurality of terminals 31 may be a drain electrode de, and a part of the plurality of terminals 32 may be a gate electrode ge. , The rest of the plurality of terminals 32 may be the source electrode se. Further, it may be provided on the surface of the main body 30 on the substrate B side or the surface opposite to the substrate B. Not only the third lower side MOS12Lw but also other switching elements such as the third upper side MOS12Hw have the same structure.

As shown in FIG. 5A, the third lower side MOS12Lw is attached to the substrate B so that the terminal 32 (source electrode se) is in contact with the wiring Wgw1 and the via Vw. The third lower side MOS12Lw is arranged on the substrate B so that at least a part of each terminal 32 overlaps with the via Vw when the substrate B is viewed from the Z direction. Further, not only the third lower side MOS12Lw but also other switching elements provided in the vicinity of the via Vu, Vv, Vw, similarly, when the substrate B is viewed from the Z direction, the terminals of the respective switching elements are the via Vu, It is provided so as to overlap Vv and Vw.

The operation and effect of this embodiment will be described.
(1) First, as a comparative example, as shown in FIG. 6, a case where U-phase, V-phase, and W-phase drive circuits are arranged on the same plane of the substrate B so as to be adjacent to each other will be examined. Here, when the wiring loop is considered to be the largest, that is, the electric power supplied from the battery 11 via the power supply terminal Tp is transmitted to the motor 2 through the U-phase upper MOS and the U-phase motor relay. The interlinkage magnetic flux when transmitted from the ground terminal to the ground through the W-phase motor relay, the W-phase lower MOS, and the W-phase shunt resistance will be described.

In this case, the current I1 flowing from the U-phase power supply terminal to the U-phase motor terminal via the U-phase upper MOS and the U-phase motor relay is passed through the W-phase motor relay, the W-phase lower MOS, and the W-phase shunt resistor. The direction is opposite to the current I2 flowing from the W-phase motor terminal to the W-phase ground terminal. It is assumed that the path through which the current I1 flows and the path through which the current I2 flows are separated by a distance L2. The distance L2 is a relatively long distance. This is because, on the same plane of the substrate B, it is necessary to make a connection point between the intermediate wirings 17u, 17v, 17w and the power lines 18u, 18v, 18w in FIG. The U-phase lower side MOS will be placed at the position. Therefore, in the present embodiment, the length of the U-phase drive circuit in the Y direction is considered to be about one MOS-FET, but in the comparative example, it is considered to be about two MOS-FETs. It gets bigger in the Y direction. Further, since it is considered that the V-phase drive circuit and the W-phase drive circuit also increase in the Y direction, the distance L2 becomes long.

By the way, magnetic fields M1 and M2 are generated by the flow of currents I1 and I2. Since the magnetic fields M1 and M2 have opposite directions corresponding to the directions of the currents I1 and I2, they cancel each other out. However, since the magnitude of the magnetic field is inversely proportional to the square of the distance, even if the magnitudes of the magnetic fields M1 and M2 are the same, they cannot completely cancel each other out. Since the magnetic fields M1 and M2 cannot be sufficiently canceled, the interlinkage magnetic flux increases, and the inductance, which is a proportional coefficient between the interlinkage magnetic flux and the current flowing through the drive circuit 3, also increases. The magnitude of the interlinkage magnetic flux is also related to the wiring loop length and the magnitude of the area of the drive circuit 3 when viewed from the Z direction. This is because the area of the drive circuit 3 when viewed from the Z direction can be seen as the area when the interlinkage magnetic flux interlinks the drive circuit 3. The larger the wiring loop, that is, the larger the area of the wiring loop when the substrate B is viewed from the Z direction, the larger the interlinkage magnetic flux. The interlinkage magnetic flux is a magnetic flux interlinking with each wiring among the magnetic fluxes generated by supplying electric power to the drive circuit 3. The larger the interlinkage magnetic flux, the larger the surge voltage in switching. Further, when the interlinkage magnetic flux is large, ringing is likely to occur. Further, when the interlinkage magnetic flux is large, the torque ripple in which the motor torque fluctuates when the motor 2 is rotated becomes large.

On the other hand, in the present embodiment, the components of the U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w are separately arranged on both sides of the substrate B. Similar to the case of FIG. 6, here, the interlinkage magnetic flux when the wiring loop is considered to be the largest will be described.

As shown in FIGS. 7A and 7B, the electric power supplied from the battery 11 via the power supply terminal Tp is transmitted to the motor 2 via the first upper MOS12Hu and the first motor relay 14u. After that, the electric power supplied to the motor 2 reaches the ground via the third motor relay 14w, the third lower MOS12Lw, and the third shunt resistor 21w.

In this case, the current I3 flowing from the power supply terminal Tp to the motor terminal Tm via the first upper MOS12Hu and the first motor relay 14u passes through the third motor relay 14w, the third lower MOS12Lw, and the third shunt resistor 21w. The current is opposite to the current I4 flowing from the motor terminal Tm to the ground terminal Tg. Here, the path of the current I3 and the path of the current I4 are separated by a distance L1. The distance L1 is shorter than the distance L2. This is because, even if it is necessary to make a connection point between the intermediate wirings 17u, 17v, 17w and the power lines 18u, 18v, 18w in FIG. 1, when the first upper MOS12Hu is arranged on the surface of the substrate B, the first If the lower side MOS12Lu is arranged on the back surface of the substrate B, the first lower side MOS12Lu can be arranged at almost the same position in the Y direction as the first upper side MOS12Hu. Therefore, in the present embodiment, the length of the U-phase drive circuit 3u in the Y direction is about one MOS-FET, so that the U-phase drive circuit 3u is suppressed from becoming large in the Y direction. Further, the V-phase drive circuit 3v and the W-phase drive circuit 3w are also suppressed from becoming larger in the Y direction. Therefore, the distance L1 is smaller than the distance L2.

Magnetic fields M3 and M4 are generated by the flow of currents I3 and I4. Since the magnetic fields M3 and M4 have opposite directions corresponding to the directions of the currents I3 and I4, they cancel each other out. Again, although the magnetic fields M3 and M4 cannot completely cancel each other out, the magnetic fields M3 and M4 have a shorter distance L1 between the path through which the current I3 flows and the path through which the current I4 flows than the distance L2. , More cancel each other out. Therefore, since the inductance of the drive circuit 3 can be made smaller, the interlinkage magnetic flux can also be made smaller.

By the way, in the present embodiment, although the length of the drive circuit 3 in the Y direction can be expected to be shortened, the components of the U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w are mounted on the substrate B. The length of the drive circuit 3 in the Z direction becomes longer due to the arrangement on both sides of the drive circuit 3. Even in this case, the wiring loop length of the drive circuit 3 becomes shorter depending on the relationship between the body shape of the MOS-FET and the thickness of the substrate B, so that the interlinkage magnetic flux becomes smaller. Further, due to the relationship between the physique of the MOS-FET and the thickness of the substrate B, it can be expected that the interlinkage magnetic flux becomes smaller even when the wiring loop of the drive circuit 3 becomes large. This is because the front surface and the back surface of the substrate B are conductive by the vias Vu, Vv, and Vw, but the component in the Z direction of the wiring of the drive circuit 3 does not affect the interlinkage magnetic flux so much. This is because the vias Vu, Vv, and Vw have physical lengths, but as long as they are conductive in the Z direction, they do not contribute to the area of the drive circuit 3 when viewed from the Z direction.

As described above, it is possible to reduce the interlinkage magnetic flux by separately arranging each component of the drive circuit 3 on both sides of the substrate B.
(2) As shown in FIG. 4A, each MOS-FET is provided with terminals 31 and 32 corresponding to its source electrode se and drain electrode de. When the vias Vu, Vv, Vw are provided, the vias Vu, Vv, Vw are arranged so that the first to third lower MOS12Lu, 12Lv, 12Lw overlap with the vias Vu, Vv, Vw in the X direction. It can be placed in the vicinity.

As shown in FIG. 5A, the third lower side MOS12Lw is fixed so that its terminal 32 is in contact with the via Vw. Thereby, in the X direction, the gap between the MOS and FET (for example, between the third lower side MOS 12Lw and the third motor relay 14w when the drive circuit 3 is viewed from the Z direction) can be reduced. Therefore, it can be expected that the area of the drive circuit 3 when viewed from the Z direction can be reduced and the interlinkage magnetic flux can also be reduced.

(3) When the heat transferred from the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw to the substrate B diffuses to the front surface and the back surface of the substrate B at about 45 degrees. Conceivable. By setting the deviation width between the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw to be equal to or larger than the thickness of the substrate B, the first to third upper MOS12Hu, 12Hv , The portion where the heat diffused from 12Hw and the heat diffused from the first to third lower MOS12Lu, 12Lv, 12Lw overlap can be eliminated.

Further, the first to third upper MOS12Hu, 12Hv, 12Hw are arranged at positions deviated from the first to third shunt resistors 21u, 21v, 21w by a thickness equal to or more than the thickness of the substrate B. As a result, it is possible to eliminate the overlapping portion between the heat diffused from the first to third upper MOS 12Hu, 12Hv, 12Hw and the heat diffused from the first to third shunt resistors 21u, 21v, 21w.

As a result, heat generation from each component of the drive circuit 3 is suppressed from being concentrated in a specific place, and heat can be dissipated more accurately.
(4) Source electrodes of each MOS-FET (first to third upper MOS12Hu, 12Hv, 12Hw, first to third lower MOS12Lu, 12Lv, 12Lw, and first to third motor relays 14u, 14v, 14w). The directions of se and the drain electrode de coincide with the direction of each wiring. As a result, the wiring length of the drive circuit 3 can be made shorter, so that the interlinkage magnetic flux can be made smaller. For example, if the direction of each wiring is orthogonal to the direction of the source electrode se and the drain electrode de of each FET, the wiring length of the drive circuit 3 becomes long, so that the interlinkage magnetic flux becomes large.

(5) The U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w are arranged in parallel with each other. As a result, the wiring length of the drive circuit 3 can be shortened by the amount that the lengths of the U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w in the Y direction can be shortened, and the interlinkage magnetic flux can be further reduced. Can be made smaller.

(6) By reducing the interlinkage magnetic flux of the drive circuit 3, the surge voltage at the time of switching can be reduced, and the occurrence of ringing can be reduced. Since the torque ripple of the motor 2 is suppressed, it is possible to perform motor control with good followability and stability, and it is possible to secure a better steering feeling.

<Second Embodiment>
Hereinafter, a second embodiment in which a drive circuit as a semiconductor device is applied to a drive device for a vehicle will be described.

As shown in FIGS. 8A and 8B, the first to third upper MOS12Hu, 12Hv, 12Hw are arranged on the surface of the substrate B, and the first to third lower MOS12Lu, 12Lv, 12Lw are of the substrate B. It is located on the back side. The first to third upper MOS12Hu, 12Hv, 12Hw are provided so as to face the first to third lower MOS12Lu, 12Lv, 12Lw via the substrate B. That is, when the drive circuit 3 is viewed from the Z direction, the first to third upper MOS12Hu, 12Hv, 12Hw are provided at the same positions as the first to third lower MOS12Lu, 12Lv, 12Lw. When the drive circuit 3 is viewed from the Z direction, the first to third upper MOS12Hu, 12Hv, 12Hw may be provided so as to slightly overlap with the first to third lower MOS12Lu, 12Lv, 12Lw.

The length of the wiring Wpu2, Wpv2, Wpw2, Wgu2, Wgv2, Wgw2 in the X direction by the amount that the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw are not shifted in the X direction. Can be shortened. Further, the length of the drive circuit 3 in the X direction can be shortened, and the mounting area of each component of the drive circuit 3 when viewed from the Z direction becomes small. That is, since the area of the drive circuit 3 when viewed from the Z direction can be reduced, the interlinkage magnetic flux is also reduced.

In addition, each embodiment may be changed as follows. In addition, the following other embodiments can be combined with each other to the extent that they are technically consistent.
-In each embodiment, in the drive circuit 3, the U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w are arranged in this order, but the order may be changed.

-The first to third motor relays 14u, 14v, 14w may not be provided.
-In each embodiment, a three-shunt method using the first to third shunt resistors 21u, 21v, 21w is adopted, but the present invention is not limited to this. For example, a one-shunt system in which only one shunt resistor is provided may be used. Further, the present invention is not limited to the current detecting means using a shunt resistor. That is, the first to third shunt resistors 21u, 21v, 21w may not be provided.

-In each embodiment, a MOS-FET is used as the switching element, but the present invention is not limited to this. For example, an IGBT (insulated gate bipolar transistor) may be used as the switching element.

-In each embodiment, a three-phase drive circuit is adopted as the drive circuit 3, but any drive circuit having two or more phases may be used.
-It may be made redundant by arranging two drive circuits 3 side by side.

As shown in FIG. 4B, the third lower side MOS12Lw (each MOS-FET) may be provided so that the terminal 32 covers the back surface (the surface on the substrate B side) of the main body portion 30. In this case, as shown in FIG. 5B, the third lower side MOS12Lw is arranged on the substrate B so that the terminal 32 completely covers the via Vw. As a result, the distance between the MOS and FET (for example, between the third lower side MOS 12Lw and the third motor relay 14w when the drive circuit 3 is viewed from the Z direction) can be further shortened, so that the distance can be further shortened from the Z direction. The area of the drive circuit 3 when viewed can be reduced.

When the substrate B is viewed from the Z direction, the terminals of the first to third lower MOS12Lu, 12Lv, 12Lw may be arranged so as not to overlap the vias Vu, Vv, Vw.
As shown in FIG. 4C, a heat dissipation pad may be provided on the surface (the surface opposite to the substrate B) of the main body 30 of the third lower MOS12Lw (each MOS-FET). In this case, the heat generated in the third lower side MOS12Lw is dissipated not only from the substrate B side but also from the heat dissipation pad.

In each embodiment, in the U-phase drive circuit 3u, the first upper MOS12Hu and the first motor relay 14u are provided on the front surface of the substrate B, and the first lower MOS12Lu and the first shunt resistor 21u are provided on the back surface. In this case, the W-phase drive circuit 3w is also arranged in the same manner as the U-phase drive circuit 3u. At this time, referring to FIGS. 7A and 7B, the current I3 passes through the front surface of the substrate B, while the current I4 passes through the back surface of the substrate B.

While the U-phase drive circuit 3u arranges its components in the same manner as described above, in the W-phase drive circuit 3w, the third lower side MOS12Lw and the third shunt resistor 21w are provided on the front surface of the substrate B and on the back surface. The third upper side MOS 12Hw and the third motor relay 14w may be provided. In this case, the current I3 flowing from the power supply terminal Tp to the motor terminal Tm via the first upper MOS12Hu and the first motor relay 14u passes through the surface of the substrate B, the third motor relay 14w, the third lower MOS12Lw, and the third. The current I4 flowing from the motor terminal Tm to the ground terminal Tg via the 3 shunt resistor 21w also passes through the surface of the substrate B. As a result, for the W-phase drive circuit 3w located farthest from the U-phase drive circuit 3u, the currents I3 and I4 pass through the same surface of the substrate B, so that the wiring loop is further formed by the thickness of the substrate B. It can be shortened and the interlinkage magnetic flux can be made smaller.

-In the first embodiment, the first to third upper MOS12Hu, 12Hv, 12Hw, the first to third lower MOS12Lu, 12Lv, 12Lw, the first to third motor relays 14u, 14v, 14w, and the first to third motor relays 14u, 14v, 14w. The three shunt resistors 21u, 21v, 21w are arranged at positions offset from each other when viewed from the Z direction, but the present invention is not limited to this. If heat is not a particular problem, the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw are arranged at slightly overlapping positions when viewed from the Z direction. You may. Further, for example, as shown in FIG. 3B, when the third lower side MOS 12Lw and the third shunt resistor 21w are both arranged on the back surface of the substrate B, the heat diffused from the third lower side MOS 12Lw and the third shunt resistance 21w are arranged. It becomes easy to overlap with the heat diffused from. Even in this case, if heat is not a particular problem, the third lower side MOS 12Lw and the third shunt resistor 21w may be arranged at close positions.

-In the first embodiment, when viewed from the Z direction, the first to third upper sides are between the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third shunt resistors 21u, 21v, 21w. MOS12Lu, 12Lv, 12Lw are arranged, but the present invention is not limited to this.

As shown in FIGS. 9A and 9B, if heat is not a particular problem, the first to third upper MOS12Hu, 12Hv, 12Hw and the first to third lower MOS12Lu, 12Lv, 12Lw are used. The position may be changed in the X direction while keeping the surface of the substrate B on which the substrate B is arranged. In this case, the first to third lower MOS12Lu, 12Lv, 12Lw are adjacent to the first to third shunt resistors 21u, 21v, 21w.

In each embodiment, the components of each of the U-phase drive circuit 3u, the V-phase drive circuit 3v, and the W-phase drive circuit 3w are arranged on both sides of the substrate B, but any one of the drive circuits 3 is used. Only the phase may be arranged on both sides of the substrate B.

-Any material may be used for the substrate B as long as it is an insulating material such as a resin.
The vias Vu, Vv, and Vw may be through holes in which the inner surface of the holes is plated, or the holes may be filled with a conductor paste. That is, any path may be used as long as it can secure the conductivity on both sides of the substrate B.

-The drive circuit 3 of each embodiment is a three-phase drive circuit corresponding to a three-phase brushless motor, but the present invention is not limited to this. For example, it suffices to have a plurality of phases of a half bridge including an upper switching element and a lower switching element. Further, the target to which the drive circuit 3 supplies electric power is not limited to the motor 2, and may be any target.

1 ... Drive device, 2 ... Motor (power supply target), 2u, 2v, 2w ... Motor coil, 3 ... Drive circuit (semiconductor device), 3u ... U-phase drive circuit, 3v ... V-phase drive circuit, 3w ... W-phase drive Circuit, 4 ... Microcomputer, 11 ... Battery, 12Hu, 12Hv, 12Hw ... 1st to 3rd upper MOS, 12Lu, 12Lv, 12Lw ... 1st to 3rd lower MOS, 13u, 13v, 13w ... 1st to 3rd Switching arm, 14u, 14v, 14w ... 1st to 3rd motor relays, 15u, 15v, 15w ... Drain wiring, 16u, 16v, 16w ... Source wiring, 17u, 17v, 17w ... Intermediate wiring, 18u, 18v, 18w ... Power line, 19u, 19v, 19w, 20u, 20v, 20w ... Gate wiring, 21u, 21v, 21w ... 1st to 3rd shunt resistance, 30 ... Main body, 31, 32 ... Terminal, B ... Board, de ... Drain Electrodes, ge ... gate electrodes, se ... source electrodes, I1 to I4 ... currents, M1 to M4 ... magnetic fields, Vu, Vv, Vw ... vias (paths, parts penetrating the substrate), Wmu, Wmv, Wmw, Wpu1 to 2 , Wpv1-2, Wpw1-2, Wgu1-3, Wgv1-3, Wgw1-3 ... Wiring.

Claims (6)

It has a board and a plurality of half bridges in which an upper switching element arranged on the board and connected to a power supply and a lower switching element grounded are connected in series, and the plurality of half bridges are arranged in parallel. In semiconductor devices
At least one upper switching element is arranged on the first surface of the substrate, and the lower switching element is arranged on the second surface of the substrate opposite to the first surface.
The substrate is provided with a path for electrically connecting the upper switching element and the lower switching element belonging to the same half bridge, and the path has a portion penetrating the substrate .
When the substrate is viewed from the direction in which the first surface and the second surface face each other,
A semiconductor device in which the upper switching element and the lower switching element belonging to the same half bridge are arranged at positions shifted by a predetermined amount of deviation from each other . In the semiconductor device according to claim 1,
The upper switching element and the lower switching element belonging to the same half bridge are semiconductor devices arranged side by side in a direction orthogonal to the direction in which the plurality of phase half bridges are arranged. In the semiconductor device according to claim 1 or 2.
The direction in which the source electrode and the drain electrode of the upper switching element and the lower switching element are arranged coincides with the extending direction of the wiring between the upper switching element and the lower switching element in the half bridge. Semiconductor device. In the semiconductor device according to any one of claims 1 to 3.
A shunt resistor for detecting the current flowing through each phase is arranged on the substrate.
When the substrate is viewed from the direction in which the first surface and the second surface face each other,
The shunt resistor is displaced by a predetermined deviation amount with respect to at least one of the upper switching element and the lower switching element belonging to the same half bridge in a direction orthogonal to the direction in which the plurality of half bridges are lined up. A semiconductor device located at a position. In the semiconductor device according to any one of claims 1 to 4.
Power is supplied to the three-phase motor to be fed via the half bridge.
The direction of the current flowing from the power supply to the power supply target via the upper switching element is the direction deviated from the direction opposite to or orthogonal to the direction of the current flowing from the power supply target to the ground via the lower switching element. A semiconductor device. In the semiconductor device according to any one of claims 1 to 5.
Each switching element has two surfaces in a direction orthogonal to the direction in which the plurality of half bridges are lined up, and each of the two surfaces has a terminal corresponding to a source electrode and a terminal corresponding to a drain electrode, respectively. These terminals are semiconductor devices that are elongated and are electrically connected to the path at a position overlapping the path when the substrate is viewed from the direction in which the first surface and the second surface face each other.

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