JP6971052B2 - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

There is FO-WLP (Fan Out Wafer Level Package) as a kind of package of semiconductor element. This is a package in which a pseudo wafer is formed by coating a plurality of semiconductor elements with a resin, and wiring or the like is provided on the pseudo wafer by applying the semiconductor element manufacturing process technology. The wiring provided for the pseudo wafer is called rewiring.

A method for producing FO-WLP (sometimes referred to simply as WLP) is described in, for example, Patent Document 1. First, the pressure-sensitive adhesive film is placed on the support substrate, and the semiconductor chip is placed on the pressure-sensitive adhesive film. At this time, the semiconductor chip is arranged with the circuit forming surface on which the wiring or the like is formed facing the adhesive film side. A heat sink may be joined to the opposite side of the circuit forming surface. Then, the semiconductor chip is covered with the mold resin to form a pseudo wafer. The adhesive film is peeled off, the support substrate is removed, and a rewiring layer is formed on the exposed circuit forming surface by a build-up method or the like. Further, the mold resin may be ground and removed from the back surface side to expose the semiconductor chip, and the heat sink may be joined.

Japanese Unexamined Patent Publication No. 2016-63178

In the conventional WLP, each step of coating with a mold resin, removing the support substrate, and forming the rewiring layer is indispensable, and it is difficult to further simplify the manufacturing process. Further, in order to join the heat radiating plate, a step of grinding and removing the mold resin is also indispensable, and it is further difficult to simplify the manufacturing process.

In the method for manufacturing a semiconductor device according to an embodiment of the present invention, a semiconductor element having a first surface provided with a connection terminal and a second surface opposite to the first surface is mounted on a substrate. The mounting process in which the two surfaces are placed so as to be in contact with the substrate, and
A sealing step of sealing the entire semiconductor element with the first resin, and
The present invention comprises a wiring forming step of forming a wiring conductor led out from the connection terminal to the surface of the first resin.

In the method for manufacturing a semiconductor device according to an embodiment of the present invention, a semiconductor element having a first surface provided with a connection terminal, a second surface opposite to the first surface, and a light emitting / receiving unit are provided. An optical semiconductor device having a third surface and a fourth surface opposite to the third surface is placed on a substrate so that the second surface and the fourth surface abut on the substrate. Placement process and
A sealing step of sealing the entire semiconductor element and the optical semiconductor element with a first resin,
A wiring forming step of forming a wiring conductor derived from the connection terminal to the surface of the first resin, and
The present invention comprises a light guide body forming step of forming a light guide body led out from the light receiving / receiving unit to the surface of the first resin.

A semiconductor device according to an embodiment of the present invention includes a semiconductor device having a first surface provided with a connection terminal and a second surface opposite to the first surface.
A first resin body in which the semiconductor element is sealed so that the second surface is exposed, and
A wiring conductor derived from the connection terminal to the surface of the first resin body is provided.

A semiconductor device according to an embodiment of the present invention includes a semiconductor device having a first surface provided with a connection terminal and a second surface opposite to the first surface.
An optical semiconductor device having a third surface provided with a light receiving / receiving unit and a fourth surface opposite to the third surface.
A first resin in which the semiconductor element and the optical semiconductor element are sealed so that the second surface and the fourth surface are exposed and the second surface and the fourth surface are located on the same virtual plane. With the body
The wiring conductor derived from the connection terminal to the surface of the first resin body,
A light guide body led out from the light receiving / receiving unit to the surface of the first resin body is provided.

According to the method for manufacturing a semiconductor device according to an embodiment of the present invention, the semiconductor element is mounted so that the second surface opposite to the first surface provided with the connection terminal is in contact with the substrate. The resin encapsulation of the semiconductor element with the first resin and the formation of the insulating layer of the wiring conductor corresponding to the rewiring can be performed in one step while the semiconductor element is placed on the substrate. Further, since it is not necessary to remove the substrate between the resin sealing and the formation of the wiring conductor, the manufacturing process can be simplified as compared with the conventional case.

According to the method for manufacturing a semiconductor device according to an embodiment of the present invention, the second surface opposite to the first surface provided with the connection terminal and the third surface opposite to the third surface provided with the light receiving / receiving unit are provided. Since the semiconductor element and the optical semiconductor element are placed so that the fourth surface is in contact with the substrate, the semiconductor element and the optical semiconductor element are sealed and rewired with the first resin while the semiconductor element and the optical semiconductor element are placed on the substrate. The formation of the insulating layer of the wiring conductor and the light guide corresponding to the above can be performed in one step. Further, since it is not necessary to remove the substrate between the resin sealing, the formation of the wiring conductor, and the formation of the light guide body, the manufacturing process can be simplified as compared with the conventional case.

According to the semiconductor device according to the embodiment of the present invention, the first resin body has a structure in which the conventional mold resin and the insulating resin layer of the rewiring layer are integrated, so that the first resin body can be miniaturized and is reliable. improves.

It is a schematic diagram which shows each process of the manufacturing method of 1st Embodiment. It is a schematic diagram which shows each process of the manufacturing method of 2nd Embodiment. It is sectional drawing of the semiconductor device 100 which is 3rd Embodiment. It is sectional drawing of the semiconductor device 200 which is 4th Embodiment. It is a schematic diagram which shows each process of the other manufacturing method of 5th Embodiment. It is a schematic diagram which shows each process of the other manufacturing method of 6th Embodiment. It is sectional drawing of the semiconductor device 300 which is 7th Embodiment. It is sectional drawing of the semiconductor device 400 which is 8th Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each of the drawings described below, the same components shall be designated by the same reference numerals. Further, the size of each member, the distance between the members, and the like are schematically shown, and the scale may differ from the actual one. The following embodiments are examples, and the present invention is not limited to these embodiments.

The first embodiment is a method for manufacturing a semiconductor device by FO-WLP (Fan Out Wafer Level Package). FIG. 1 is a schematic view showing each step of the manufacturing method of the first embodiment. As will be described later, in this embodiment, the support substrate 1 is used as the substrate. The support substrate 1 is called a dummy substrate, a carrier substrate, or the like, and plays a role of supporting and transporting a semiconductor element or the like during a manufacturing process. It is a substrate that is removed at the end of the process and does not constitute a semiconductor device.

FIG. 1A shows a preparation process. In the preparation step, the support substrate 1 for mounting the semiconductor element is prepared. The support substrate 1 of the present embodiment is a support substrate 1 with an adhesive layer 2 for fixing the mounted semiconductor element. The support substrate 1 has a flat surface on which a semiconductor element is placed, and is not deformed or expanded or contracted (dimensional change) due to environmental changes during the manufacturing process, or even if it occurs, it is within a certain range. Anything may be used, and for example, a silicon (Si) substrate, a glass substrate, an aluminum or other metal substrate, or an organic substrate such as a polyimide film or a printed circuit board can be used.

The pressure-sensitive adhesive layer 2 does not change in adhesiveness due to environmental changes during the manufacturing process so that the position of the semiconductor element does not change during the manufacturing process. When the support substrate 1 is removed, the adhesive layer 2 is on the WLP side. Anything that can be easily separated is sufficient. As the pressure-sensitive adhesive, for example, an epoxy resin-based, acrylic resin-based or urethane resin-based pressure-sensitive adhesive can be used. The pressure-sensitive adhesive layer 2 may be formed by applying a pressure-sensitive adhesive such as a liquid or a gel on the surface of the support substrate 1 on which the semiconductor element is placed, or a pressure-sensitive adhesive film may be attached. As the pressure-sensitive adhesive film, for example, one composed of a base material and a pressure-sensitive adhesive layer can be used.

FIG. 1B shows a mounting process. The semiconductor element 3 is placed on the surface of the support substrate 1 prepared in the preparation step where the pressure-sensitive adhesive layer 2 is provided. In the mounting step, for example, a plurality of semiconductor elements 3 are arranged in a matrix at equal intervals. The semiconductor element 3 is provided with a connection terminal 31 for connecting to an external circuit or the like. The connection terminal 31 is provided on the first surface 3a of the semiconductor element 3, and all the connection terminals 31 are integrated on the first surface 3a of the semiconductor element 3. The second surface 3b on the side opposite to the first surface 3a of the semiconductor element 3 is a flat surface, and the first surface 3a and the second surface 3b are parallel to each other.

In the mounting step of the present embodiment, the semiconductor element 3 is mounted on the support substrate 1 so that the second surface 3b of the semiconductor element 3 abuts on the surface of the support substrate 1. In other words, the semiconductor element 3 is placed on the support substrate 1 in a state where the first surface 3a faces upward and the connection terminal 31 is exposed.

FIG. 1 (c) shows a sealing process. With the semiconductor element 3 placed on the support substrate 1 as described above, the entire semiconductor element 3 is sealed with the first resin 4. If the uncured first resin 4 is liquid, it can be sealed by a curtain coating method, a slit coating method, a spray coating method, a casting method, or the like. When the first resin 4 is in the form of a film, it can be sealed by a vacuum laminating method or the like.

In the previous step, the first surface 3a of the semiconductor element 3 is exposed, that is, the connection terminal 31 is exposed, and in the main sealing step, the exposed first surface 3a is covered with the first resin 4. Seal with resin. Assuming that the thickness of the semiconductor element 3 (including the connection terminal 31) is, for example, 50 to 500 μm, the thickness of the first resin 4 (distance from the surface of the support substrate 1 to the surface of the first resin 4) is the thickness of the semiconductor element 3. If the thickness exceeds that, for example, 100 to 600 μm, the first resin 4 can surely cover the connection terminal 31. As described above, the first resin 4 also covers the connection terminal 31, so that the mold resin in the conventional WLP and the insulating resin layer of the rewiring layer are integrated.

As the first resin 4, any conventional resin for encapsulating a semiconductor element can be used, and for example, an epoxy resin, an acrylic resin, a polyimide resin, a liquid crystal polymer, or the like can be used. ..

FIG. 1D shows a terminal exposure process. In this step, the connection terminal 31 is exposed by forming a through hole 40 penetrating from the surface of the first resin 4 to the connection terminal 31. The through hole 40 can be formed, for example, by utilizing an etching process technique. An etching mask may be provided on the surface of the first resin 4, and the resin in the portion to be the through hole 40 may be removed by an etching gas or an etching solution. Further, by using a photosensitive resin for the first resin 4, the sealing step and the terminal exposure step can be performed by using the photolithography technique. For example, the semiconductor element 3 is covered with the uncured first resin 4, and the portion to be the through hole 40 remains uncured using a light-shielding mask, and the other portions are cured and developed to remove the uncured resin. The first resin 4 provided with the through hole 40 can be formed. FIG. 1 (e) shows the forming process. In this step, the through hole 40 is filled with a conductive material, or the inner wall of the through hole 40 is coated with the conductive material to form the through conductor 50, and the surface of the first resin 4 is electrically covered with the through conductor 50. The surface wiring 51 to be connected to is formed. Both the through conductor 50 and the surface wiring 51 can be formed by utilizing the organic substrate wiring technique. For example, the through conductor 50 and the surface wiring 51 can be formed by electroless plating or electrolytic plating. The terminal exposure step and the forming step are combined to form a wiring step, and the through conductor 50 and the surface wiring 51 form a wiring conductor.

FIG. 1 (f) shows a removal step. In this step, the support substrate 1 is peeled off together with the pressure-sensitive adhesive layer 2 to remove the support substrate 1. When an adhesive having a relatively weak adhesiveness is used, the support substrate 1 can be mechanically peeled off. Further, even if the adhesive has a relatively strong adhesiveness, if an adhesive whose adhesiveness is lowered by irradiation with ultraviolet light or whose adhesiveness is lowered by heating is used, a step prior to the removal step. Then, it can be firmly fixed and can be easily peeled off by reducing the adhesiveness in the removing step. Further, the support substrate 1 may be peeled off by dissolving and removing the pressure-sensitive adhesive layer 2 using a solvent that does not affect the first resin 4 but can solubilize the pressure-sensitive adhesive.

FIG. 1 (g) shows an individualization step. In this step, for example, a dicing device or the like is used to separate each semiconductor device 100 into individual pieces. The semiconductor device 100 can be obtained by the above manufacturing method.

The second embodiment is a method for manufacturing a semiconductor device by FO-WLP. FIG. 2 is a schematic view showing each step of the manufacturing method of the second embodiment. In this embodiment as well as in the first embodiment, the support substrate 1 is used as the substrate.

FIG. 2A shows the preparation process. In the preparation step, the support substrate 1 for mounting the semiconductor element and the optical semiconductor element is prepared. The support substrate 1 of the present embodiment is a support substrate 1 with an adhesive layer 2 for fixing the mounted semiconductor element and the optical semiconductor element. The support substrate 1 has a flat surface on which a semiconductor element and an optical semiconductor element are placed, and is not deformed or expanded or contracted (dimensional change) due to environmental changes during the manufacturing process, or is constant even if it occurs. Anything within the range may be used, and for example, a silicon (Si) substrate, a glass substrate, an aluminum or other metal substrate, or an organic substrate such as a polyimide film or a printed circuit board can be used.

The pressure-sensitive adhesive layer 2 is such that the adhesiveness does not change due to environmental changes during the manufacturing process so that the positions of the semiconductor element and the optical semiconductor element do not change during the manufacturing process, and when the support substrate 1 is removed. In addition, any material may be used as long as it does not remain on the WLP side and can be easily separated. As the pressure-sensitive adhesive, for example, an epoxy resin-based, acrylic resin-based or urethane resin-based pressure-sensitive adhesive can be used. The pressure-sensitive adhesive layer 2 may be formed by applying a pressure-sensitive adhesive to the surface of the support substrate 1 on which the semiconductor element and the optical semiconductor element are placed, or may be attached with a pressure-sensitive adhesive film. As the pressure-sensitive adhesive film, for example, one composed of a base material and a pressure-sensitive adhesive layer can be used.

FIG. 2B shows the mounting process. The semiconductor element 3 and the optical semiconductor element 6 are placed on the surface of the support substrate 1 prepared in the preparation step where the pressure-sensitive adhesive layer 2 is provided. In the mounting step, the combinations of the semiconductor element 3 and the optical semiconductor element 6 are arranged in a matrix at equal intervals, for example. The semiconductor element 3 is provided with a connection terminal 31 for connecting to an external circuit or the like. The connection terminal 31 is provided on the first surface 3a of the semiconductor element 3, and all the connection terminals 31 are integrated on the first surface 3a of the semiconductor element 3. The second surface 3b on the side opposite to the first surface 3a of the semiconductor element 3 is a flat surface, and the first surface 3a and the second surface 3b are parallel to each other. The optical semiconductor element 6 is provided with a connection terminal 61 and a light receiving / receiving unit 62 for electrically connecting to the semiconductor element 3. The connection terminal 61 and the light receiving / receiving unit 62 are provided on the third surface 6a of the optical semiconductor element 6, and all the connection terminals 61 and the light emitting / receiving unit 62 are integrated on the third surface 6a of the optical semiconductor element 6. There is. The fourth surface 6b on the side opposite to the third surface 6a of the optical semiconductor element 6 is a flat surface, and the third surface 6a and the fourth surface 6b are parallel to each other. The light receiving / receiving unit 62 is not limited to those that perform both light reception and light emission, but also include those that perform only light reception and those that perform only light emission.

In the mounting step of the present embodiment, the semiconductor element 3 is mounted on the support substrate 1 so that the second surface 3b of the semiconductor element 3 abuts on the surface of the support substrate 1. In other words, the semiconductor element 3 is placed on the support substrate 1 in a state where the first surface 3a faces upward and the connection terminal 31 is exposed. Further, the optical semiconductor element 6 is placed on the support substrate 1 so that the fourth surface 6b of the optical semiconductor element 6 abuts on the surface of the support substrate 1. In other words, the optical semiconductor element 6 is placed on the support substrate 1 in a state where the third surface 6a faces upward and the connection terminal 61 and the light receiving / receiving unit 62 are exposed.

FIG. 2 (c) shows the sealing process. With the semiconductor element 3 and the optical semiconductor element 6 placed on the support substrate 1 as described above, the entire semiconductor element 3 and the optical semiconductor element 6 are sealed with the first resin 4. For sealing with the first resin 4, for example, the support substrate 1 is set in the mold, the softened first resin 4 is injected into the mold to be cured, and the mold is released from the mold. If a wafer-shaped mold is used, a pseudo-wafer sealed with the first resin 4 can be obtained after mold release. The semiconductor manufacturing process technology can be easily applied to the pseudo wafer in the post-process.

In the previous step, the first surface 3a of the semiconductor element 3 and the third surface 6a of the optical semiconductor element 6 are exposed, that is, the connection terminals 31, 61 and the light emitting / receiving unit 62 are exposed. , The exposed first surface 3a and third surface 6a are resin-sealed so as to be covered with the first resin 4. The thickness of the semiconductor element 3 (including the connection terminal 31) is, for example, 100 to 500 μm, and the thickness of the optical semiconductor element 6 is, for example, 50 to 250 μm. The semiconductor element 3 and the optical semiconductor element 6 may have the same thickness or different thicknesses, but in the present embodiment, they are different. As described above, it is assumed that the optical semiconductor element 6 is thinner. The thickness of the first resin 4 (distance from the surface of the support substrate 1 to the surface of the first resin 4) exceeds the thickness of the thicker semiconductor element 3, for example, if the thickness is 150 to 600 μm, the first resin 4 is used. The connection terminals 31, 61 and the light receiving / receiving unit 62 can be reliably covered. As described above, the first resin 4 also covers the connection terminals 31, 61 and the light emitting / receiving portion 62, so that the mold resin in the conventional WLP and the insulating resin layer of the rewiring layer are integrated. ..

The first resin 4 is a resin that is photosensitive and transparent to light (for example, near infrared rays) to receive and emit light in order to function as a clad layer of an optical waveguide for the light receiving and receiving unit 62. Can be used. For example, epoxy resin, acrylic resin, polyimide resin, liquid crystal polymer, PBO (polybenzoxazole), COP (cycloolefin polymer), COC (cycloolefin copolyma) and the like can be used.

FIG. 2D shows a terminal exposure process. In this step, the connection terminals 31, 61 and the light emitting / receiving unit 62 are exposed by forming a through hole 40 penetrating from the surface of the first resin 4 to the connection terminals 31, 61 and the light emitting / receiving unit 62. The through hole 40 can be formed, for example, by using an etching process technique as in the first embodiment. Further, by using a photosensitive resin for the first resin 4, the sealing step and the terminal exposure step can be performed by using the photolithography technique. For example, the semiconductor element 3 and the optical semiconductor element 6 are covered with the uncured first resin 4, and the portion to be the through hole 40 is uncured by using a light-shielding mask, and the other portions are cured and undeveloped. The cured resin can be removed to form the first resin 4 provided with the through holes 40. FIG. 2E shows a light guide body forming step. In this step, a light guide body 70 for light emitted from the light emitting / receiving unit 62 to the outside or light received from the outside by the light receiving / receiving unit 62 is formed. The first resin 4 functions as a clad layer, and the light guide body 70 can be formed by filling the through hole 40 with a material that functions as a core layer. The material to be the core layer may be a transparent material having a refractive index larger than that of the first resin 4, and is selected from the same resin materials as the first resin 4 described above as the first resin 4. However, a resin material having a large refractive index may be selected. FIG. 2 (f) shows the forming process. In this step, the through hole 40 is filled with the conductive material as in the first embodiment, or the inner wall of the through hole 40 is coated with the conductive material to form the through conductor 50, and the surface of the first resin 4 is covered with the conductive material. , Form a surface wiring 51 to be connected to the through conductor 50. Further, a part of the connection terminal 31 and the connection terminal 61 can be connected by the surface wiring 51, and the semiconductor element 3 and the optical semiconductor element 6 can be electrically connected. The terminal exposure step, the light guide body forming step, and the forming step are combined to form a wiring step, and the through conductor 50 and the surface wiring 51 form a wiring conductor.

FIG. 2 (g) shows the removal step. In this step, the support substrate 1 is peeled off together with the pressure-sensitive adhesive layer 2 and the support substrate 1 is removed in the same manner as in the first embodiment.

FIG. 2 (h) shows the individualization process. In this step, as in the first embodiment, a dicing device or the like is used to separate each semiconductor device 200 into individual pieces. The semiconductor device 200 can be obtained by the above manufacturing method.

FIG. 3 is a cross-sectional view of the semiconductor device 100 according to the third embodiment. The semiconductor device 100 is manufactured by the manufacturing method of the first embodiment described above. In the semiconductor device 100, the semiconductor element 3 having the first surface 3a provided with the connection terminal 31, the second surface 3b on the opposite side of the first surface 3a, and the semiconductor element 3 are exposed by the second surface 3b. The first resin body 4A sealed as described above, and the through conductor 50 and the surface wiring 51, which are wiring conductors led out from the connection terminal 31 to the surface of the first resin body 4A, are provided.

In the conventional FO-WLP, a resin different from the sealing resin and the insulating resin in the rewiring layer is used. For example, due to the difference in the coefficient of thermal expansion, the sealing resin and the rewiring layer are used. There was a risk of delamination and disconnection. On the other hand, in the semiconductor device 100 of the present embodiment, since the sealing resin and the insulating resin of the wiring conductor are integrated as the first resin body 4A, the occurrence of delamination and disconnection is suppressed and the reliability is suppressed. Can be improved. Further, in the semiconductor device 100 of the present embodiment, the variation at the time of mounting is reduced, so that the variation in the characteristics such as the electrical characteristics after mounting is also reduced.

FIG. 4 is a cross-sectional view of the semiconductor device 200 according to the fourth embodiment. The semiconductor device 200 is manufactured by the manufacturing method of the second embodiment described above. The semiconductor device 200 includes a semiconductor element 3 having a first surface 3a provided with a connection terminal 31, a second surface 3b opposite to the first surface 3a, and a third surface 6a provided with a light emitting / receiving unit 62. The second surface 3b and the fourth surface 6b expose the optical semiconductor element 6 having the third surface 6a and the fourth surface 6b on the opposite side, the semiconductor element 3 and the optical semiconductor element 6, and the second surface 3b. The first resin body 4A sealed so that the fourth surface 6b is located on the same virtual plane, the through conductor 50 which is a wiring conductor led out from the connection terminal 31 to the surface of the first resin body 4A, and A surface wiring 51 and a light guide body 70 led out from the light receiving / receiving unit 62 to the surface of the first resin body 4A are provided. Further, the optical semiconductor element 6 has a connection terminal 61 on the third surface 6a, and is electrically connected to one of the connection terminals 31 of the semiconductor element 3 via a through conductor 50 and a surface wiring 51. ..

Similar to the semiconductor device 100, the semiconductor device 200 of the present embodiment also has the sealing resin and the insulating resin of the wiring conductor integrated as the first resin body 4A, so that delamination and disconnection are suppressed and reliability is suppressed. It is possible to improve the sex.

A fifth embodiment is another method for manufacturing a semiconductor device by FO-WLP. FIG. 5 is a schematic view showing each step of the other manufacturing method of the fifth embodiment. As will be described later, in this embodiment, the heat sink 8 is used as the substrate. In the manufactured semiconductor device, the heat radiating plate 8 dissipates heat generated from the semiconductor element during operation to cool the semiconductor element. Unlike the support substrate of the first embodiment, the semiconductor device is configured without being removed. During the manufacturing process, the heat sink 8 functions as the support substrate 1 described above. In the following description, since the steps other than the individualization step are similar to those of the first embodiment, detailed description may be omitted.

FIG. 5A shows the preparation process. In the preparation step, a heat sink 8 for mounting the semiconductor element is prepared. The heat sink 8 of the present embodiment is a heat sink 8 with a bonding material layer 9 for joining the mounted semiconductor elements. The heat radiating plate 8 may have a flat surface on which the semiconductor element is placed and may have a cooling capacity, and for example, aluminum, copper or other metal substrate may be used. For the bonding material layer 9, a bonding material capable of bonding the semiconductor element and the heat radiating plate 8 can be used, and for example, solder, a brazing material, a die attach material, or the like can be used.

FIG. 5B shows the mounting process. The semiconductor element 3 is placed on the surface of the heat radiating plate 8 prepared in the preparation step on which the bonding material layer 9 is provided, and is fixed by reflow or the like. In the mounting step, a plurality of semiconductor elements 3 are arranged in a matrix, for example, at equal intervals. The semiconductor element 3 is the same as the semiconductor element 3 of the above embodiment.

FIG. 5 (c) shows the sealing process. With the semiconductor element 3 placed on the support substrate 1 as described above, the entire semiconductor element 3 is sealed with the first resin 4. The sealing step of the present embodiment is the same as the sealing step of the above embodiment.

FIG. 5D shows a terminal exposure process. In this step, the connection terminal 31 is exposed by forming a through hole 40 penetrating from the surface of the first resin 4 to the connection terminal 31. FIG. 5 (e) shows the forming process. In this step, the through hole 40 is filled with a conductive material, or the inner wall of the through hole 40 is coated with the conductive material to form the through conductor 50, and the surface of the first resin 4 is connected to the through conductor 50. The surface wiring 51 is formed. The terminal exposure step and the forming step of the present embodiment are the same as the terminal exposing step and the forming step of the above-described embodiment. The terminal exposure step and the forming step are combined in the wiring forming step, and the wiring conductor is composed of the through conductor 50 and the surface wiring 51.

FIG. 5 (f) shows the individualization step. In this step, for example, a dicing device or the like is used to separate each semiconductor device 300 into individual pieces. Since the heat sink 8 also constitutes the semiconductor device 300, it is individualized in this step. The semiconductor device 300 can be obtained by the above manufacturing method.

A sixth embodiment is another method for manufacturing a semiconductor device using FO-WLP. FIG. 6 is a schematic view showing each step of the other manufacturing method of the sixth embodiment. Similar to the fifth embodiment, the present embodiment also uses the heat sink 8 as the substrate.

FIG. 6A shows the preparation process. In the preparation step, a heat sink 8 for mounting the semiconductor element and the optical semiconductor element is prepared. The heat sink 8 of the present embodiment is a heat sink 8 with a bonding material layer 9 for joining the mounted semiconductor element and the optical semiconductor element. The heat radiating plate 8 may have a flat surface on which the semiconductor element and the optical semiconductor element are placed and may have a cooling capacity, and for example, aluminum, copper or other metal substrate may be used. For the bonding material layer 9, a bonding material capable of bonding the semiconductor element and the heat radiating plate 8 can be used, and for example, solder, a brazing material, a die attach material, or the like can be used.

FIG. 6B shows the mounting process. The semiconductor element 3 and the optical semiconductor element 6 are placed on the surface of the heat radiating plate 8 prepared in the preparation step on which the bonding material layer 9 is provided, and are fixed by reflow or the like. In the mounting step, the combinations of the semiconductor element 3 and the optical semiconductor element 6 are arranged in a matrix at equal intervals. The semiconductor element 3 and the optical semiconductor element 6 are the same as the semiconductor element 3 and the optical semiconductor element 6 of the above-described embodiment.

FIG. 6 (c) shows the sealing process. With the semiconductor element 3 and the optical semiconductor element 6 placed on the heat radiating plate 8 as described above, the entire semiconductor element 3 and the optical semiconductor element 6 are sealed with the first resin 4. The sealing step of the present embodiment is the same as the sealing step of the above embodiment.

FIG. 6D shows a terminal exposure process. In this step, the connection terminals 31, 61 and the light emitting / receiving unit 62 are exposed by forming a through hole 40 penetrating from the surface of the first resin 4 to the connection terminals 31, 61 and the light emitting / receiving unit 62. Similar to the above embodiment, the light receiving / receiving unit 62 is not limited to those that perform both light reception and light emission, but also include those that perform only light reception and those that perform only light emission. FIG. 6E shows a light guide body forming step. In this step, a light guide body 70 for light emitted from the light emitting / receiving unit 62 to the outside or light received from the outside by the light receiving / receiving unit 62 is formed. FIG. 6 (f) shows the forming process. In this step, as in the fifth embodiment, the through hole 40 is filled with the conductive material, or the inner wall of the through hole 40 is coated with the conductive material to form the through conductor 50, and the surface of the first resin 4 is covered with the conductive material. , Form a surface wiring 51 to be connected to the through conductor 50. Further, the connection terminal 31 and the connection terminal 61 can be connected by the surface wiring 51, and the semiconductor element 3 and the optical semiconductor element 6 can be electrically connected. The terminal exposure step, the light guide body forming step, and the forming step of the present embodiment are the same as the terminal exposing step, the light guide body forming step, and the forming step of the above-described embodiment. The terminal exposure step, the light guide body forming step, and the forming step are combined to form a wiring step, and the through conductor 50 and the surface wiring 51 form a wiring conductor.

FIG. 6 (g) shows the individualization step. In this step, as in the fifth embodiment, a dicing device or the like is used to separate each semiconductor device 400 into individual pieces. Since the heat sink 8 also constitutes the semiconductor device 400, it is individualized in this step. The semiconductor device 400 can be obtained by the above manufacturing method.

FIG. 7 is a cross-sectional view of the semiconductor device 300 according to the seventh embodiment. The semiconductor device 300 is manufactured by the manufacturing method of the fifth embodiment described above. The semiconductor device 300 includes a semiconductor element 3, a first resin body 4A, a through conductor 50 which is a wiring conductor, a surface wiring 51, and a heat sink 8.

In the conventional FO-WLP, a resin different from the sealing resin and the insulating resin in the rewiring layer is used. For example, due to the difference in the coefficient of thermal expansion, delamination or disconnection in the rewiring layer occurs. There was a risk of causing such problems. On the other hand, in the semiconductor device 300 of the present embodiment, since the sealing resin and the insulating resin of the wiring conductor are integrated as the first resin body 4A, the occurrence of delamination and disconnection is suppressed and the reliability is suppressed. Can be improved. Further, in the conventional FO-WLP, in order to bond the heat sink to the semiconductor element, the sealing resin is ground to expose the semiconductor element. Since an external force is applied during grinding, cracks may occur in the sealing resin, or the sealing resin and the semiconductor element may be partially peeled off to form voids. Further, when the heat radiating plate is joined after grinding, the heat conductivity may be lowered due to the unevenness remaining on the joint surface, and the heat radiating property may be lowered. On the other hand, since the semiconductor device 300 of the present embodiment is manufactured in a state where the semiconductor element 3 and the heat radiating plate 8 are joined in advance, there is no unevenness on the joint surface, the thermal conductivity is improved, and the heat radiating property is improved. Can be improved.

FIG. 8 is a cross-sectional view of the semiconductor device 400 according to the eighth embodiment. The semiconductor device 400 is manufactured by the manufacturing method of the sixth embodiment described above. The semiconductor device 400 includes a semiconductor element 3, an optical semiconductor element 6, a first resin body 4A, a through conductor 50 and a surface wiring 51 which are wiring conductors, a light guide body 70, and a second surface 3b of the semiconductor element 3. Further, a heat radiating plate 8 abutting on the fourth surface 6b of the optical semiconductor element 6 is further provided.

Similar to the semiconductor device 300, the semiconductor device 400 of the present embodiment also has the sealing resin and the insulating resin of the wiring conductor integrated as the first resin body 4A, so that delamination and disconnection are suppressed and reliability is suppressed. It is possible to improve the sex. Further, in the conventional FO-WLP described in Patent Document 1, two types of semiconductor chips having different thicknesses are used, and since the circuit forming surfaces are aligned on the support substrate, the height of the back surface of the semiconductor chips is high. Is different. When joining the heat sink to the back surface, two types of heat sinks are required, and one of the heat sinks is buried in the mold resin, so that sufficient heat sink characteristics cannot be obtained. On the other hand, in the semiconductor device 400 of the present embodiment, since the second surface 3b and the fourth surface 6b, which are the back surfaces of the semiconductor element 3 and the optical semiconductor element 6, are on a virtual plane, one heat sink 8 is used. Since it can be shared and is not buried in the resin, sufficient heat dissipation characteristics can be obtained.

1 Support substrate 2 Adhesive layer 3 Semiconductor element 3a 1st surface 3b 2nd surface 4 1st resin 4A 1st resin body 6 Optical semiconductor element 6a 3rd surface 6b 4th surface 8 Heat sink 9 Bonding material layer 31 Connection terminal 40 Through hole 50 Through conductor 51 Surface wiring 61 Connection terminal 62 Light receiving / emitting unit 70 Light guide 100, 200, 300, 400 Semiconductor device

Claims (5)

A semiconductor device having a first surface provided with a connection terminal and a second surface opposite to the first surface, a third surface provided with a light emitting / receiving unit, and a third surface opposite to the third surface. A mounting step of mounting an optical semiconductor device having four surfaces on a substrate so that the second surface and the fourth surface are in contact with the substrate.
A sealing step of sealing the entire semiconductor element and the optical semiconductor element with a first resin,
A wiring forming step of forming a wiring conductor derived from the connection terminal to the surface of the first resin, and
A method for manufacturing a semiconductor device, comprising a light guide body forming step of forming a light guide body led out from the light receiving / receiving unit to the surface of the first resin. Wherein the substrate comprises a heat sink manufacturing method of a semiconductor device according to claim 1, wherein. The substrate includes a support substrate.
Production method of the after wiring formation step and the light guide body forming step, which further comprising a support removal step of removing the substrate, a semiconductor device according to claim 1, wherein. A semiconductor device having a first surface provided with a connection terminal and a second surface opposite to the first surface.
An optical semiconductor device having a third surface provided with a light receiving / receiving unit and a fourth surface opposite to the third surface.
A first resin in which the semiconductor element and the optical semiconductor element are sealed so that the second surface and the fourth surface are exposed and the second surface and the fourth surface are located on the same virtual plane. With the body
The wiring conductor derived from the connection terminal to the surface of the first resin body,
A semiconductor device including a light guide body led out from the light receiving / receiving unit to the surface of the first resin body. The semiconductor device according to claim 4 , further comprising a heat sink that is in contact with the second surface of the semiconductor element and the fourth surface of the optical semiconductor element.

Images