JP6960868B2 - Semiconductor module and its manufacturing method - Google Patents

Semiconductor module and its manufacturing method Download PDF

Info

Publication number
JP6960868B2
JP6960868B2 JP2018018665A JP2018018665A JP6960868B2 JP 6960868 B2 JP6960868 B2 JP 6960868B2 JP 2018018665 A JP2018018665 A JP 2018018665A JP 2018018665 A JP2018018665 A JP 2018018665A JP 6960868 B2 JP6960868 B2 JP 6960868B2
Authority
JP
Japan
Prior art keywords
linear body
metal wire
semiconductor module
semiconductor chip
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018018665A
Other languages
Japanese (ja)
Other versions
JP2019135761A (en
Inventor
知洋 井口
晃也 木村
陽光 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2018018665A priority Critical patent/JP6960868B2/en
Priority to DE102019200634.5A priority patent/DE102019200634B4/en
Publication of JP2019135761A publication Critical patent/JP2019135761A/en
Application granted granted Critical
Publication of JP6960868B2 publication Critical patent/JP6960868B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0217—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02185—Shape of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0333—Manufacturing methods by local deposition of the material of the bonding area in solid form
    • H01L2224/03334—Manufacturing methods by local deposition of the material of the bonding area in solid form using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
    • H01L2224/48993—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48998—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H01L2224/78314—Shape
    • H01L2224/78315—Shape of the pressing surface, e.g. tip or head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85196—Translational movements involving intermediate connecting steps before cutting the wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/1302—GTO - Gate Turn-Off thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

本発明の実施形態は、半導体モジュールおよびその製造方法に関する。 Embodiments of the present invention relate to semiconductor modules and methods for manufacturing them.

電力用の半導体モジュールでは、半導体チップに大電流が流せるように、半導体チップと外部端子とは複数の金属ワイヤーを介して電気的に接続されている。更に、半導体チップ内に電流が集中しないように、各金属ワイヤーは半導体チップの複数の領域にボンディングされている。 In a semiconductor module for electric power, the semiconductor chip and an external terminal are electrically connected via a plurality of metal wires so that a large current can flow through the semiconductor chip. Further, each metal wire is bonded to a plurality of regions of the semiconductor chip so that the current does not concentrate in the semiconductor chip.

このため、金属ワイヤーには、できるだけ低い比抵抗を有する金属が望まれる。ボンディングワイヤー用の金属として一般的な金（Ａｕ）およびアルミニウム（Ａｌ）より比抵抗の低い金属として銅（Ｃｕ）がある。 Therefore, a metal having as low a resistivity as possible is desired for the metal wire. As a metal for a bonding wire, there are general gold (Au) and copper (Cu) as a metal having a lower resistivity than aluminum (Al).

然しながら、銅ワイヤーは、同じサイズの金ワイヤーおよびアルミニウムワイヤーに比べて剛性が高いので、配線時にループ形成が困難になるため、信頼性の確保が難しいという問題がある。 However, since the copper wire has higher rigidity than the gold wire and the aluminum wire of the same size, it is difficult to form a loop at the time of wiring, so that there is a problem that it is difficult to secure reliability.

すなわち、剛性が低いワイヤーの場合にはワイヤーを曲げる、いわゆるループの形成が容易であり、熱膨張と収縮の繰り返しによる疲労を緩和する効果が得られやすい。これに対し、銅ワイヤーのように剛性が高い材料の場合には、従来のループ形成方法では金やアルミニウムに較べてループの曲率を大きくせざるを得ないため、半導体チップの小型化が困難となる。 That is, in the case of a wire having low rigidity, it is easy to bend the wire, that is, to form a so-called loop, and it is easy to obtain the effect of alleviating fatigue due to repeated thermal expansion and contraction. On the other hand, in the case of a material with high rigidity such as copper wire, the conventional loop forming method has no choice but to increase the curvature of the loop as compared with gold or aluminum, which makes it difficult to miniaturize the semiconductor chip. Become.

特開平６−１６３６２９号公報Japanese Unexamined Patent Publication No. 6-163629

本発明が解決しようとする課題は、半導体チップに大電流を通電可能で信頼性の高い半導体モジュールおよびその製造方法を提供することにある。 An object to be solved by the present invention is to provide a highly reliable semiconductor module capable of energizing a semiconductor chip with a large current and a method for manufacturing the same.

別の実施形態によれば、半導体モジュールの製造方法は、第１の面に第１の領域と第２の領域とを有する第１電極が設けられた第１半導体チップを用意する工程と、前記第１の領域と前記第２の領域との間の領域に線状体を配置する工程と、金属ワイヤーを、前記第１の領域に接合し、前記金属ワイヤーが挿通されたボンディングツールを、前記金属ワイヤーが前記線状体に漸近するように斜め上方に移動させ、前記金属ワイヤーが前記線状体に当接し、更に前記第１電極に当接するまで下降させるにあたって、前記金属ワイヤーが前記第１電極に当接する前に、前記ボンディングツールを前記線状体に近づく方向に移動させ、前記線状体に当接した前記金属ワイヤーを前記線状体から離間させる、ことにより、前記線状体を支えとして前記第１の面より上方に湾曲させ、前記第２の領域に接合する工程と、を具備する。 According to another embodiment, the method for manufacturing a semiconductor module includes a step of preparing a first semiconductor chip provided with a first electrode having a first region and a second region on a first surface, and the above-mentioned step. The step of arranging the linear body in the region between the first region and the second region, and the bonding tool in which the metal wire is joined to the first region and the metal wire is inserted are described. The metal wire is moved diagonally upward so as to approach the linear body, and the metal wire is lowered until it abuts on the linear body and further abuts on the first electrode. Before abutting on the electrode, the bonding tool is moved in a direction approaching the linear body, and the metal wire abutting on the linear body is separated from the linear body, whereby the linear body is separated. As a support, a step of bending upward from the first surface and joining to the second region is provided.

実施形態１に係る半導体モジュールを示す図。The figure which shows the semiconductor module which concerns on Embodiment 1. FIG. 実施形態１ に係る半導体モジュールを示す斜視図。The perspective view which shows the semiconductor module which concerns on Embodiment 1. FIG. 実施形態１に係る半導体装置モジュールの回路図。The circuit diagram of the semiconductor device module according to Embodiment 1. 比較例に係る半導体モジュールを示す斜視図。The perspective view which shows the semiconductor module which concerns on a comparative example. 実施形態１に係る半導体モジュールの製造工程を示すフローチャート。The flowchart which shows the manufacturing process of the semiconductor module which concerns on Embodiment 1. 実施形態１に係る半導体モジュールの製造工程の要部を順に示す断面図。The cross-sectional view which shows the main part of the manufacturing process of the semiconductor module which concerns on Embodiment 1 in order. 実施形態１に係る半導体モジュールの製造工程の要部を順に示す断面図。The cross-sectional view which shows the main part of the manufacturing process of the semiconductor module which concerns on Embodiment 1 in order. 実施形態２に係る半導体モジュールを示す図。The figure which shows the semiconductor module which concerns on Embodiment 2. 実施形態２の変形例１に係る半導体モジュールを示す平面図。The plan view which shows the semiconductor module which concerns on the modification 1 of Embodiment 2. 実施形態２の変形例２に係る半導体モジュールを示す図。The figure which shows the semiconductor module which concerns on the modification 2 of Embodiment 2. 実施形態３に係る半導体モジュールを示す断面図。FIG. 5 is a cross-sectional view showing a semiconductor module according to the third embodiment. 実施形態３の変形例に係る半導体モジュールを示す断面図。FIG. 5 is a cross-sectional view showing a semiconductor module according to a modified example of the third embodiment. 実施形態４に係る半導体モジュールを示す平面図。The plan view which shows the semiconductor module which concerns on Embodiment 4. FIG. 実施形態４に係る半導体モジュールの回路図。The circuit diagram of the semiconductor module according to Embodiment 4. 実施形態４に係る別の半導体モジュールの回路図。The circuit diagram of another semiconductor module according to Embodiment 4.

以下、図面を参照しつつ本発明の実施形態を説明する。なお、以下の説明では、同一又は類似の部材等には同一の符号を付し、一度説明した部材等については適宜その説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members and the like are designated by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

（実施形態１）
本実施形態に係る半導体モジュールは、第１の面に第１の領域と第２の領域とを有する第１電極が設けられた第１半導体チップと、第１の面より上方に湾曲する湾曲部を有し、湾曲部の両端が第１の領域と第２の領域とに接続された金属ワイヤーと、湾曲部と第１の面との間に配置された線状体と、を具備している。 (Embodiment 1)
The semiconductor module according to the present embodiment includes a first semiconductor chip provided with a first electrode having a first region and a second region on the first surface, and a curved portion curved upward from the first surface. A metal wire having both ends of the curved portion connected to the first region and the second region, and a linear body arranged between the curved portion and the first surface. There is.

図１は本実施形態の半導体モジュールを示す図で、図１（ａ）はその平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印方向に眺めた断面図である。図２は半導体モジュールを示す斜視図である。図３は半導体モジュールの回路図である。なお、図２の斜視図においては、後述する金属ワイヤーを図１（ａ）の平面図より間引きして描いている。 FIG. 1 is a diagram showing a semiconductor module of the present embodiment, FIG. 1 (a) is a plan view thereof, and FIG. 1 (b) is cut along the line AA of FIG. 1 (a) and viewed in the direction of an arrow. It is a cross-sectional view. FIG. 2 is a perspective view showing a semiconductor module. FIG. 3 is a circuit diagram of a semiconductor module. In the perspective view of FIG. 2, the metal wire described later is thinned out from the plan view of FIG. 1 (a).

はじめに、半導体モジュールの概要を説明する。 First, an outline of the semiconductor module will be described.

図１乃至図３に示すように、本実施形態の半導体モジュール１０は、第１半導体チップ１１と、第２半導体チップ１２とを備えている。第１半導体チップ１１上には、線状体１３が配置されている。 As shown in FIGS. 1 to 3, the semiconductor module 10 of this embodiment includes a first semiconductor chip 11 and a second semiconductor chip 12. A linear body 13 is arranged on the first semiconductor chip 11.

本明細書において、「半導体チップ上に」という語句には、半導体チップに接して、保護膜または電極膜を介して、または半導体チップに非接触で上方に、などの概念が含まれている。 As used herein, the phrase "on a semiconductor chip" includes concepts such as in contact with a semiconductor chip, via a protective film or electrode film, or above the semiconductor chip in a non-contact manner.

第１半導体チップ１１と第２半導体チップ１２とは、 金属ワイヤー１４を介して電気的に接続されている。金属ワイヤー１４の一側は、第２半導体チップ１２に接続されている。金属ワイヤー１４の他側は、線状体１３を跨ぐ湾曲部を有し、線状体１３の両側で第１半導体チップ１１に電気的に接続されている。 The first semiconductor chip 11 and the second semiconductor chip 12 are electrically connected via a metal wire 14. One side of the metal wire 14 is connected to the second semiconductor chip 12. The other side of the metal wire 14 has a curved portion straddling the linear body 13, and is electrically connected to the first semiconductor chip 11 on both sides of the linear body 13.

金属ワイヤー１４は、第１半導体チップ１１に大電流が流せるように、ワイヤー１本あたり５Ａ以上の電流を流せる断面積を有している。金属ワイヤー１４は、例えば線径が３００μｍφ以上のワイヤーである。金属ワイヤー１４は、第１半導体チップ１１に電流を流す際に電流が集中しないように、ダイオード１１の複数の領域に接続されている。 The metal wire 14 has a cross-sectional area that allows a current of 5 A or more to flow per wire so that a large current can flow through the first semiconductor chip 11. The metal wire 14 is, for example, a wire having a wire diameter of 300 μmφ or more. The metal wire 14 is connected to a plurality of regions of the diode 11 so that the current does not concentrate when the current is passed through the first semiconductor chip 11.

金属ワイヤー１４は、ボンディングワイヤー用の金属として一般的な金（Ａｕ）およびアルミニウム（Ａｌ）より比抵抗の低い金属ワイヤーで、例えば銅（Ｃｕ）ワイヤーである。銅ワイヤーは、同じサイズ（径、長さ）の金ワイヤーおよびアルミニウムワイヤーより剛性が高いので、曲げ難くなる。 The metal wire 14 is a metal wire having a lower specific resistance than gold (Au) and aluminum (Al), which are generally used as metals for bonding wires, and is, for example, a copper (Cu) wire. Copper wire is more rigid than gold wire and aluminum wire of the same size (diameter, length), making it harder to bend.

線状体１３は、剛性が高い金属ワイヤー１４を上凸状に湾曲させて、例えば接続点間の直線距離である長さが３ｍｍ以下、接続点からワイヤー最高部の高さが２ｍｍ以下の湾曲部を形成するための支えとして機能するものである。 The linear body 13 is formed by bending a highly rigid metal wire 14 in an upward convex shape, for example, a length of 3 mm or less, which is a linear distance between connection points, and a curve in which the height of the highest part of the wire from the connection point is 2 mm or less. It functions as a support for forming the part.

金属ワイヤー１４は、第１半導体チップ１１および第２半導体チップ１２に電流を流した時には発熱により膨張し、電流を停止した時には冷却されることにより収縮する。金属ワイヤー１４に湾曲部を持たせることにより、膨張と収縮の繰り返しによる金属ワイヤー１４の疲労破断が防止される。なお、湾曲部はループとも称される。 The metal wire 14 expands due to heat generation when an electric current is passed through the first semiconductor chip 11 and the second semiconductor chip 12, and contracts when the electric current is stopped by being cooled. By providing the metal wire 14 with a curved portion, fatigue fracture of the metal wire 14 due to repeated expansion and contraction is prevented. The curved portion is also referred to as a loop.

これにより、大電流を通電可能で信頼性の高い半導体モジュール１０を得ることが可能である。 This makes it possible to obtain a highly reliable semiconductor module 10 capable of energizing a large current.

以下、半導体モジュールの詳細を説明する。 The details of the semiconductor module will be described below.

ここでは、第１半導体チップ１１がダイオード、第２半導体チップ１２が絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ：Insulated Gate Bipolar Transistor）である態様を例として説明する。ダイオード１１およびＩＧＢＴ１２は、半導体基板、例えばシリコン（Ｓｉ）基板に形成されている。 Here, an embodiment in which the first semiconductor chip 11 is a diode and the second semiconductor chip 12 is an insulated gate bipolar transistor (IGBT) will be described as an example. The diode 11 and the IGBT 12 are formed on a semiconductor substrate, for example, a silicon (Si) substrate.

なお、第１半導体チップ１１はダイオードに、第２半導体チップ１２はＩＧＢＴに限定されるものではなく、大電流で動作する半導体素子であればよい。半導体素子としては、例えば、絶縁ゲート電界効果トランジスタ（ＭＯＳＦＥＴ：Metal-Oxide Semiconductor Field Effect Transistor）、接合型電界効果トランジスタ（ＪＦＥＴ：Junction Field Effect Transistor）、バイポーラトランジスタ（Bipolar Transistor）、サイリスタ、ゲートターンオフサイリスタ（ＧＴＯ：Gate Turn-Off Thyristor）等があげられる。 The first semiconductor chip 11 is not limited to a diode, and the second semiconductor chip 12 is not limited to an IGBT, and any semiconductor element that operates with a large current may be used. Examples of semiconductor elements include isolated gate electric field effect transistors (MOSFETs: Metal-Oxide Semiconductor Field Effect Transistors), junction field effect transistors (JFETs), bipolar transistors (Bipolar Transistors), cyclists, and gate turn-off thyristors. (GTO: Gate Turn-Off Thyristor) and the like.

第１、第２半導体チップ１１、１２は異種の半導体チップの組み合わせでも、同種の半導体チップの組み合わせでもかまわない。また、半導体基板は、ＳｉＣ基板、ＧａＮ基板等としてもよい。 The first and second semiconductor chips 11 and 12 may be a combination of different types of semiconductor chips or a combination of semiconductor chips of the same type. Further, the semiconductor substrate may be a SiC substrate, a GaN substrate, or the like.

ダイオード１１は、第１の面１１ａと、第１の面１１ａと反対側の第２の面１１ｂとを有している。第１の面１１ａ側がアノードであり、第２の面１１ｂ側がカソードである。第１の面１１ａにはアノード電極（第１電極）１５が設けられている。第２の面１１ｂにはカソード電極（図示せず）が設けられている。 The diode 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. The first surface 11a side is the anode and the second surface 11b side is the cathode. An anode electrode (first electrode) 15 is provided on the first surface 11a. A cathode electrode (not shown) is provided on the second surface 11b.

アノード電極１５上には、Ｙ方向（第１の方向）に延在する線状体１３が配置されている。線状体１３はアノード電極１５の一端近傍から他端近傍まで延在している。ここでは、線状体１３として、第１線状体１３ａおよび第２線状体１３ｂがＹ方向と交差するＸ方向（第２の方向）に沿って離間して配置されている。線状体１３の断面は、例えば円形である。線状体１３は、単数の場合もありえる。 A linear body 13 extending in the Y direction (first direction) is arranged on the anode electrode 15. The linear body 13 extends from the vicinity of one end to the vicinity of the other end of the anode electrode 15. Here, as the linear body 13, the first linear body 13a and the second linear body 13b are arranged apart from each other along the X direction (second direction) where the first linear body 13a and the second linear body 13b intersect the Y direction. The cross section of the linear body 13 is, for example, circular. The linear body 13 may be singular.

ＩＧＢＴ１２は、第１の面１２ａと、第１の面１２ａと反対側の第２の面１２ｂとを有している。第１の面１２ａ側がエミッタであり、第２の面１２ｂ側がコレクタである。第１の面１２ａにはエミッタ電極（第２電極）１６が設けられている。第２の面１２ｂにはコレクタ電極（図示せず）が設けられている。 The IGBT 12 has a first surface 12a and a second surface 12b opposite to the first surface 12a. The first surface 12a side is the emitter, and the second surface 12b side is the collector. An emitter electrode (second electrode) 16 is provided on the first surface 12a. A collector electrode (not shown) is provided on the second surface 12b.

ダイオード１１とＩＧＢＴ１２とは、絶縁性基板（図示せず）上でＹ方向と交差するＸ方向（第２の方向）に並置され、電気的に並列接続されている。Ｙ方向とＸ方向とは、直交していてよい。 The diode 11 and the IGBT 12 are juxtaposed in the X direction (second direction) intersecting the Y direction on an insulating substrate (not shown), and are electrically connected in parallel. The Y direction and the X direction may be orthogonal to each other.

ダイオード１１のアノードとＩＧＢＴ１２のエミッタとが、金属ワイヤー１４を介して電気的に接続されている。ダイオード１１のカソードとＩＧＢＴ１２のコレクタとが、絶縁性基板に設けられた導電層（図示せず）を介して電気的に接続されている。 The anode of the diode 11 and the emitter of the IGBT 12 are electrically connected via a metal wire 14. The cathode of the diode 11 and the collector of the IGBT 12 are electrically connected via a conductive layer (not shown) provided on the insulating substrate.

金属ワイヤー１４は、Ｘ方向に延在している。金属ワイヤー１４の一端側は、ＩＧＢＴ１２のエミッタ電極１６にワイヤーボンディングされている。エミッタ電極１６のワイヤーボンディングは、ボールボンディングである。エミッタ電極１６のワイヤーボンディングは、ステッチボンディング（ウェッジボンディング）であってもよい。 The metal wire 14 extends in the X direction. One end side of the metal wire 14 is wire-bonded to the emitter electrode 16 of the IGBT 12. The wire bonding of the emitter electrode 16 is ball bonding. The wire bonding of the emitter electrode 16 may be stitch bonding (wedge bonding).

金属ワイヤー１４の他端側は、線状体１３を跨ぐ湾曲部を有し、湾曲部の両端は線状体１３の両側でアノード電極１５にワイヤーボンディングされている。アノード電極１５のワイヤーボンディングは、ステッチボンディングである。 The other end side of the metal wire 14 has a curved portion straddling the linear body 13, and both ends of the curved portion are wire-bonded to the anode electrodes 15 on both sides of the linear body 13. The wire bonding of the anode electrode 15 is stitch bonding.

より具体的には、金属ワイヤー１４の一端側は、ボールボンディング部１７を介してエミッタ電極１６に接続されている。
金属ワイヤー１４の他端側は、（１）第１湾曲部１４ａを有して第１線状体１３ａより＋Ｘ方向側の第１の領域１５ａに第１ステッチボンディング部１８ａを介して接続され、（２）第１線状体１３ａを跨ぐ第２湾曲部１４ｂを有して第１線状体１３ａと第２線状体１３ｂとの間の第２の領域１５ｂに第２ステッチボンディング部１８ｂを介して接続され、（３）第２線状体１３ｂを跨ぐ第３湾曲部１４ｃを有して第２線状体１３ｂより−Ｘ方向側の第３の領域１５ｃに第３ステッチボンディング部１８ｃを介して接続されている。 More specifically, one end side of the metal wire 14 is connected to the emitter electrode 16 via a ball bonding portion 17.
The other end side of the metal wire 14 has (1) a first curved portion 14a and is connected to a first region 15a on the + X direction side of the first linear body 13a via a first stitch bonding portion 18a. (2) A second stitch bonding portion 18b is provided in a second region 15b between the first linear body 13a and the second linear body 13b having a second curved portion 14b straddling the first linear body 13a. A third stitch bonding portion 18c is provided in a third region 15c on the −X direction side of the second linear body 13b, which has a third curved portion 14c straddling the second linear body 13b. Connected via.

金属ワイヤー１４の径は、ワイヤー１本あたり５Ａ以上の電流を流せる３００μｍφ以上である。 The diameter of the metal wire 14 is 300 μmφ or more, which allows a current of 5 A or more to flow per wire.

第２湾曲部１４ｂの長さＬ１ａ、即ち第１の領域１５ａにおける金属ワイヤー１４の接続点と第２の領域１５ｂにおける金属ワイヤー１４の接続点との直線距離は３ｍｍ以下である。同様に、第３湾曲部１４ｃの長さＬ１ｂ、即ち第２の領域１５ｂにおける金属ワイヤー１４の接続点と第３の領域１５ｃにおける金属ワイヤー１４の接続点との直線距離も３ｍｍ以下である。第２湾曲部１４ｂおよび第３湾曲部１４ｃの長さＬ１ａ、Ｌ１ｂは、第１湾曲部１４ａの長さＬ２より小さくすることができる（Ｌ１ａ、Ｌ１ｂ＜Ｌ２）。 The length L1a of the second curved portion 14b, that is, the linear distance between the connection point of the metal wire 14 in the first region 15a and the connection point of the metal wire 14 in the second region 15b is 3 mm or less. Similarly, the length L1b of the third curved portion 14c, that is, the linear distance between the connection point of the metal wire 14 in the second region 15b and the connection point of the metal wire 14 in the third region 15c is also 3 mm or less. The lengths L1a and L1b of the second curved portion 14b and the third curved portion 14c can be made smaller than the length L2 of the first curved portion 14a (L1a, L1b <L2).

第２湾曲部１４ｂの高さＨ１ａ、即ちアノード電極１５から金属ワイヤー１４の最高部の高さは２ｍｍ以下である。同様に、第３湾曲部１４ｃの高さＨ１ｂ、即ちアノード電極１５から金属ワイヤー１４の最高部の高さも２ｍｍ以下である。第２湾曲部１４ｂおよび第３湾曲部１４ｃの高さＨ１ａ、Ｈ１ｂは、第１湾曲部１４ａの高さＨ２より小さくすることができる（Ｈ１ａ、Ｈ１ｂ＜Ｈ２）。 The height H1a of the second curved portion 14b, that is, the height of the highest portion of the metal wire 14 from the anode electrode 15 is 2 mm or less. Similarly, the height H1b of the third curved portion 14c, that is, the height of the highest portion of the metal wire 14 from the anode electrode 15 is also 2 mm or less. The heights H1a and H1b of the second curved portion 14b and the third curved portion 14c can be made smaller than the height H2 of the first curved portion 14a (H1a, H1b <H2).

即ち、第１、第２湾曲部１４ｂ、１４ｃは、第１湾曲部１４ａに比べて短・低湾曲部である。 That is, the first and second curved portions 14b and 14c are shorter and lower curved portions than the first curved portion 14a.

金属ワイヤー１４となる銅ワイヤーには、純銅ワイヤーだけでなく、銅合金ワイヤーおよび銅を主材とし銅と異なる金属で被覆されたワイヤーも含まれる。 The copper wire to be the metal wire 14 includes not only a pure copper wire but also a copper alloy wire and a wire having copper as a main material and coated with a metal different from copper.

銅合金ワイヤーとは、純銅（例えば純度４Ｎ、９９．９９％以上）に所定の元素が微量（パーセントオーダ以下の割合）添加された銅ワイヤーである。添加できる元素の例としては、カルシウム（Ｃａ）、ホウ素（Ｂ）、燐（Ｐ）、アルミニウム（Ａｌ）、銀（Ａｇ）、セレン（Ｓｅ）等が挙げられる。これらの元素を添加すると、高い伸び特性が得られ、ボンディングワイヤーの強度がより向上することが期待される。 The copper alloy wire is a copper wire in which a predetermined element is added in a small amount (percentage order or less) to pure copper (for example, purity 4N, 99.99% or more). Examples of elements that can be added include calcium (Ca), boron (B), phosphorus (P), aluminum (Al), silver (Ag), selenium (Se) and the like. When these elements are added, high elongation characteristics are obtained, and it is expected that the strength of the bonding wire will be further improved.

また、その他の元素の例として、ベリリウム（Ｂｅ）、錫（Ｓｎ）、亜鉛（Ｚｎ）、ジルコニウム（Ｚｒ）、クロム（Ｃｒ）、鉄（Ｆｅ）、酸素（Ｏ）、硫黄（Ｓ）、水素（Ｈ）などが挙げられる。銅以外の元素が０．００１重量％以上含まれることにより、高い伸び特性が期待される。 Examples of other elements include beryllium (Be), tin (Sn), zinc (Zn), zirconium (Zr), chromium (Cr), iron (Fe), oxygen (O), sulfur (S), and hydrogen. (H) and the like can be mentioned. High elongation characteristics are expected when an element other than copper is contained in an amount of 0.001% by weight or more.

銅を主材とし銅と異なる金属で被覆されたワイヤーとは、例えばパラジウム（Ｐｄ）メッキおよび金（Ａｕ）メッキが施された銅ワイヤーである。これらのメッキ層は銅の酸化を抑制するために設けられている。 The wire having copper as the main material and coated with a metal different from copper is, for example, a copper wire plated with palladium (Pd) and gold (Au). These plating layers are provided to suppress the oxidation of copper.

銅の比抵抗（略１．６８×１０−８Ωｍ）は、金の比抵抗（略２．４４×１０−８Ωｍ）およびアルミニウムの比抵抗（略２．８２×１０−８Ωｍ）より小さい。銅ワイヤーは、同じサイズ（径、長さ）を有する金ワイヤー及びアルミニウムワイヤーより抵抗が低くなるので、大電流を流すワイヤーとして適している。 The resistivity of copper (approximately 1.68 × 10-8 Ωm) is smaller than the resistivity of gold (approximately 2.44 × 10-8 Ωm) and the resistivity of aluminum (approximately 2.82 × 10-8 Ωm). .. Copper wire has lower resistance than gold wire and aluminum wire having the same size (diameter, length), and is therefore suitable as a wire through which a large current flows.

一方、銅のヤング率（略１３０ＧＰａ）は、金のヤング率（略８０ＧＰａ）およびアルミニウムのヤング率（略７０ＧＰａ）より大きい。銅ワイヤーは、同じサイズ（径、長さ）を有する金ワイヤー及びアルミニウムワイヤーより剛性が高くなるので、曲がり難くなる。即ち、長さおよび高さが小さい湾曲部（短・低湾曲部）ほど形成するのが困難である。 On the other hand, the Young's modulus of copper (approximately 130 GPa) is larger than the Young's modulus of gold (approximately 80 GPa) and the Young's modulus of aluminum (approximately 70 GPa). Copper wire has higher rigidity than gold wire and aluminum wire having the same size (diameter, length), so that it is difficult to bend. That is, it is more difficult to form a curved portion (short / low curved portion) having a smaller length and height.

本実施形態では、アノード電極１５上に線状体１３が配置されているので、線状体１３を支えとして金属ワイヤー１４を強制的に上凸状に曲げることができる。その結果、同じサイズを有する金ワイヤー及びアルミニウムワイヤーより剛性の高い金属ワイヤー１４でも、線状体１３を跨ぐ湾曲部を有してアノード電極１５にステッチボンディングすることが可能となる。 In the present embodiment, since the linear body 13 is arranged on the anode electrode 15, the metal wire 14 can be forcibly bent upwardly convex with the linear body 13 as a support. As a result, even a metal wire 14 having a higher rigidity than a gold wire and an aluminum wire having the same size can be stitch-bonded to the anode electrode 15 with a curved portion straddling the linear body 13.

尚、金属ワイヤー１４が疲労破断するモードとしては、第１乃至第３ステッチボンディング部１８ａ、１８ｂ、１８ｃの剥離、金属ワイヤー１４の断線等がある。 Modes in which the metal wire 14 is fatigue-fractured include peeling of the first to third stitch bonding portions 18a, 18b, and 18c, disconnection of the metal wire 14, and the like.

線状体１３は、導電性でも絶縁性でもよい。金属ワイヤー１４と線状体１３とは接触していても、接触していなくてもよい。 The linear body 13 may be conductive or insulating. The metal wire 14 and the linear body 13 may or may not be in contact with each other.

線状体１３が導電性で、金属ワイヤー１４と接触している場合、金属ワイヤー１４とアノード電極１５との接触面積の拡大につながる。これにより、ダイオード１１に流れる電流分布をより均一化することが可能である。 When the linear body 13 is conductive and is in contact with the metal wire 14, the contact area between the metal wire 14 and the anode electrode 15 is expanded. This makes it possible to make the current distribution flowing through the diode 11 more uniform.

線状体１３が導電性である場合、線状体１３は金属ワイヤー１４と同じ種類（材質、線径）の金属ワイヤーとすることができる。線状体１３は、金属ワイヤー１４と同様にアノード電極１５にステッチボンディングすることができる。 When the linear body 13 is conductive, the linear body 13 can be a metal wire of the same type (material, wire diameter) as the metal wire 14. The linear body 13 can be stitch-bonded to the anode electrode 15 in the same manner as the metal wire 14.

なお、半導体モジュール１０は、単一のスイッチング素子である。ＩＧＢＴ１２がオン状態からオフ状態に切り替わると、回路のインダクタンス成分により、ＩＧＢＴ１２のエミッタ電極に誘導起電力が加わる。これにより、ダイオード１１が動作し、誘導起電力を吸収する。ダイオード１１はＦＷＤ（Free Wheel Diode）として機能する。 The semiconductor module 10 is a single switching element. When the IGBT 12 is switched from the on state to the off state, an induced electromotive force is applied to the emitter electrode of the IGBT 12 due to the inductance component of the circuit. As a result, the diode 11 operates and absorbs the induced electromotive force. The diode 11 functions as an FWD (Free Wheel Diode).

次に、比較例の半導体モジュールについて説明する。 Next, the semiconductor module of the comparative example will be described.

図４は比較例の半導体モジュールを示す斜視図である。比較例の半導体モジュールとは、線状体を有しない半導体モジュールのことである。 FIG. 4 is a perspective view showing a semiconductor module of a comparative example. The semiconductor module of the comparative example is a semiconductor module having no linear body.

図４に示すように、比較例の半導体モジュール３０は、ダイオード１１のアノード電極１５上に線状体が配置されていない点を除いて、本実施形態の半導体モジュール１０と同様である。 As shown in FIG. 4, the semiconductor module 30 of the comparative example is the same as the semiconductor module 10 of the present embodiment except that the linear body is not arranged on the anode electrode 15 of the diode 11.

比較例の半導体モジュール３０では、アノード電極１５上に線状体が配置されていないので、金属ワイヤー１４は線状体を支えとして強制的に上凸状に曲げられた湾曲部を有していない。 In the semiconductor module 30 of the comparative example, since the linear body is not arranged on the anode electrode 15, the metal wire 14 does not have a curved portion that is forcibly bent upwardly convex with the linear body as a support. ..

金属ワイヤー１４の他側は、（１）第１湾曲部１４ａを有して第１の領域１５ａに第１ステッチボンディング部１８ａを介して接続され、（２）第１直線部１４ｄを有して第２の領域１５ｂに第２ステッチボンディング部１８ｂを介して接続され、（３）第２直線部１４ｅを有して第３の領域１５ｃに第３ステッチボンディング部１８ｃを介して接続されている。 The other side of the metal wire 14 has (1) a first curved portion 14a and is connected to the first region 15a via a first stitch bonding portion 18a, and (2) has a first straight portion 14d. It is connected to the second region 15b via the second stitch bonding portion 18b, and (3) has the second straight line portion 14e and is connected to the third region 15c via the third stitch bonding portion 18c.

比較例の半導体モジュール３０においても、金属ワイヤー１４はダイオード１１およびＩＧＢＴ１２の通電による発熱に応じて膨張と収縮を繰り返すことは、本実施形態の金属ワイヤー１４と同様である。然しながら、金属ワイヤー１４の第１直線部１４ｄおよび第２直線部１４ｅは、両端が第１乃至第３ステッチボンディング部１８ａ、１８ｂ、１８ｃで固定されている。 Also in the semiconductor module 30 of the comparative example, the metal wire 14 repeats expansion and contraction in response to heat generated by energization of the diode 11 and the IGBT 12, which is the same as that of the metal wire 14 of the present embodiment. However, both ends of the first straight line portion 14d and the second straight line portion 14e of the metal wire 14 are fixed by the first to third stitch bonding portions 18a, 18b, and 18c.

即ち、金属ワイヤー１４は、自由に伸縮できる湾曲部を有していないので、膨張と収縮の繰り返しにより、疲労破断する恐れがある。従って、大電流を通電可能で信頼性の高い半導体モジュールが得られない。 That is, since the metal wire 14 does not have a curved portion that can be freely expanded and contracted, there is a risk of fatigue fracture due to repeated expansion and contraction. Therefore, it is not possible to obtain a highly reliable semiconductor module that can carry a large current.

次に、半導体モジュールの製造方法について説明する。 Next, a method of manufacturing a semiconductor module will be described.

図５は半導体モジュールの製造工程を示すフローチャート、図６および図７は半導体モジュールのワイヤーボンディング工程を順に示す断面図である。 FIG. 5 is a flowchart showing a manufacturing process of the semiconductor module, and FIGS. 6 and 7 are cross-sectional views showing the wire bonding process of the semiconductor module in order.

図５に示すように、絶縁性基板にダイオード１１およびＩＧＢＴ１２をＸ方向に並置する（ステップＳ１０）。 As shown in FIG. 5, the diode 11 and the IGBT 12 are juxtaposed in the X direction on the insulating substrate (step S10).

ダイオード１１のアノード電極１５上にＹ方向に延在する線状体１３を配置する。ここでは、線状体１３は金属ワイヤー１４と同じ種類の金属ワイヤーとし、２本配置する。線状体１３の一側をアノード電極１５のＹ方向の一端近傍にステッチボンディングし、他側をＹ方向の他端近傍にステッチボンディングする。なお、同じ種類とは、材料および線径が同じであることを意味している（ステップＳ１１）。 A linear body 13 extending in the Y direction is arranged on the anode electrode 15 of the diode 11. Here, the linear body 13 is a metal wire of the same type as the metal wire 14, and two wires are arranged. One side of the linear body 13 is stitch-bonded to the vicinity of one end in the Y direction of the anode electrode 15, and the other side is stitch-bonded to the vicinity of the other end in the Y direction. The same type means that the material and the wire diameter are the same (step S11).

ＩＧＢＴ１２のエミッタ電極１６上に、金属ワイヤー１４の一側をボールボンディングする（ステップＳ１２）。 One side of the metal wire 14 is ball-bonded onto the emitter electrode 16 of the IGBT 12 (step S12).

第１湾曲部１４ａを形成して、金属ワイヤー１４の他側をアノード電極１５の第１の領域１５ａにステッチボンディングする（ステップＳ１３）。 The first curved portion 14a is formed, and the other side of the metal wire 14 is stitch-bonded to the first region 15a of the anode electrode 15 (step S13).

線状体１６ａを跨ぐ第２湾曲部１４ｂを形成して、金属ワイヤー１４の他側をアノード電極１５の第２の領域１５ｂにステッチボンディングする（ステップＳ１４）。 A second curved portion 14b straddling the linear body 16a is formed, and the other side of the metal wire 14 is stitch-bonded to the second region 15b of the anode electrode 15 (step S14).

線状体１６ｂを跨ぐ第３湾曲部１４ｃを形成して、金属ワイヤー１４の他側をアノード電極１５の第３の領域１５ｃにステッチボンディングする（ステップＳ１５）。 A third curved portion 14c straddling the linear body 16b is formed, and the other side of the metal wire 14 is stitch-bonded to the third region 15c of the anode electrode 15 (step S15).

全ての金属ワイヤー１４のボンディングが完了したか否かを判定する（ステップＳ１６）。完了していなければ（ステップＳ１６のＮＯ）、ステップＳ１２に戻り、ステップＳ１２乃至ステップＳ１６を完了するまで繰り返し実行する。完了していれば（ステップＳ１６のＹＥＳ）ワイヤーボンディングを終了する。 It is determined whether or not the bonding of all the metal wires 14 is completed (step S16). If it is not completed (NO in step S16), the process returns to step S12 and is repeatedly executed until steps S12 to S16 are completed. If it is completed (YES in step S16), the wire bonding is completed.

図６はステップＳ１４におけるボンディング工程を順に示す断面図である。ボンディングツール４０は、金属ワイヤー１４が挿通されるキャピラリー４１と、金属ワイヤー１４をクランプするためのクランパー４２と、金属ワイヤー１４を超音波接合するための超音波接合冶具４３と、金属ワイヤー１４を切断するためのカッター４４とを備えている。矢印Ａ乃至Ｅは、ボンディングツール４０の軌跡を示している。 FIG. 6 is a cross-sectional view showing the bonding steps in step S14 in order. The bonding tool 40 cuts the capillary 41 through which the metal wire 14 is inserted, the clamper 42 for clamping the metal wire 14, the ultrasonic bonding tool 43 for ultrasonically bonding the metal wire 14, and the metal wire 14. It is provided with a cutter 44 for making a wire. Arrows A to E indicate the locus of the bonding tool 40.

図６（ａ）に示すように、アノード電極１５の第１の領域１５ａに第１ステッチボンディング部１８ａを形成した後、ボンディングツール４０を矢印Ａに示すように上昇（＋Ｚ方向）させ、矢印Ｂに示すように左斜め上（＋Ｚ方向および−Ｘ方向）に移動させる。 As shown in FIG. 6A, after forming the first stitch bonding portion 18a in the first region 15a of the anode electrode 15, the bonding tool 40 is raised (+ Z direction) as shown by arrow A, and arrow B As shown in, move diagonally upward to the left (+ Z direction and -X direction).

この移動は、キャピラリー４１が線状体１３ａより−Ｘ方向側の第２の領域１５ｂの上方に至るまでおこなう。これにより、金属ワイヤー１４はキャピラリー４１から略直線状に引き出され、線状体１３ａに漸近する。 This movement is performed until the capillary 41 extends above the second region 15b on the −X direction side from the linear body 13a. As a result, the metal wire 14 is pulled out from the capillary 41 in a substantially linear shape and asymptotically approaches the linear body 13a.

図６（ｂ）に示すように、ボンディングツール４０を矢印Ｃに示すように左斜め下（−Ｚ方向および−Ｘ方向）に移動させる。この移動は、キャピラリー４１がアノード電極１５の第２の領域１５ｂに近接するところまで行う。これにより、金属ワイヤー１４は線状体１３ａに当接し、線状体１３ａを支えとして強制的に曲げられるので、湾曲部が形成される。 As shown in FIG. 6B, the bonding tool 40 is moved diagonally downward to the left (−Z direction and −X direction) as shown by arrow C. This movement is performed until the capillary 41 is close to the second region 15b of the anode electrode 15. As a result, the metal wire 14 comes into contact with the linear body 13a and is forcibly bent with the linear body 13a as a support, so that a curved portion is formed.

仮に、アノード電極１５上に線状体１３ａが配置されていないとすると、金属ワイヤー１４は同じサイズの金ワイヤー及びアルミニウムワイヤーより剛性が高いので、自然に上凸状に曲がることはない。その結果、破線で示す第１直線部１４ｄが形成されることになる。 If the linear body 13a is not arranged on the anode electrode 15, the metal wire 14 has higher rigidity than the gold wire and the aluminum wire of the same size, so that the metal wire 14 does not naturally bend upwardly and convexly. As a result, the first straight line portion 14d shown by the broken line is formed.

図６（ｃ）に示すように、ボンディングツール４０を矢印Ｄのように水平（＋Ｘ方向）に移動させて、金属ワイヤー１４と線状体１３ａとの間に若干のゆとりを与えてから、矢印Ｅに示すように下降（−Ｚ方向）させる。この移動は、金属ワイヤー１４がアノード電極１５の第２の領域１５ｂに当接するまで行う。 As shown in FIG. 6 (c), the bonding tool 40 is moved horizontally (in the + X direction) as shown by the arrow D to give a slight clearance between the metal wire 14 and the linear body 13a, and then the arrow. As shown in E, it is lowered (in the −Z direction). This movement is performed until the metal wire 14 comes into contact with the second region 15b of the anode electrode 15.

超音波接合冶具４３にて金属ワイヤー１４を押圧しながら超音波を印加し、金属ワイヤー１４をアノード電極１５の第２の領域１５ｂに接合する。これにより、第２ステッチボンディング部１８ｂが形成される。 Ultrasonic waves are applied while pressing the metal wire 14 with the ultrasonic bonding tool 43 to bond the metal wire 14 to the second region 15b of the anode electrode 15. As a result, the second stitch bonding portion 18b is formed.

これにより、長さＬ１ａおよび高さＨ１ａを有する第２湾曲部１４ｂが形成される。なお、ボンディングツール４０を矢印Ｄのように水平に移動させる量に応じて、線状体１３と金属ワイヤー１４の位置関係、即ち線状体１３と金属ワイヤー１４とが接触しているかまたは離間しているか、を調節することができる。 As a result, the second curved portion 14b having a length L1a and a height H1a is formed. The positional relationship between the linear body 13 and the metal wire 14, that is, the linear body 13 and the metal wire 14 are in contact with each other or separated from each other according to the amount of horizontal movement of the bonding tool 40 as shown by the arrow D. You can adjust whether it is or not.

ステップＳ１５におけるボンディング工程も、ステップ１４におけるボンディング工程と同様である。線状体１３ｂを支えとして金属ワイヤー１４を強制的に曲げることにより、長さＬ１ｂおよび高さＨ１ｂを有する第３湾曲部１４ｃを形成し、第３ステッチボンディング部１８ｃを形成する。 The bonding step in step S15 is the same as the bonding step in step 14. By forcibly bending the metal wire 14 with the linear body 13b as a support, a third curved portion 14c having a length L1b and a height H1b is formed, and a third stitch bonding portion 18c is formed.

更に、カッター４４を下降させて金属ワイヤー１４をハーフカットし、クランパー４２で金属ワイヤー１４をクランプし、ボンディングツール４０を上昇（＋Ｚ方向）することにより、金属ワイヤー１４を引きちぎるようにして切断する。 Further, the cutter 44 is lowered to half-cut the metal wire 14, the clamper 42 clamps the metal wire 14, and the bonding tool 40 is raised (in the + Z direction) to tear the metal wire 14 and cut it.

一方、ステップＳ１３におけるボンディング工程では、第１湾曲部１４ａは線状体が無くても形成することができる。第１湾曲部１４ａの長さＬ２および高さＨ２が、金属ワイヤー１４の剛性に応じて定まる湾曲可能な範囲にあるためである。 On the other hand, in the bonding step in step S13, the first curved portion 14a can be formed without the linear body. This is because the length L2 and the height H2 of the first curved portion 14a are within a bendable range determined according to the rigidity of the metal wire 14.

図７（ａ）に示すように、エミッタ電極１６にボールボンディング部１７を形成した後、ボンディングツール４０を矢印Ａに示すように上昇（＋Ｚ方向）させ、矢印Ｂ乃至Ｄに示すようコ字状（＋Ｘ→＋Ｚ→−Ｘ方向）に移動させる。 As shown in FIG. 7A, after forming the ball bonding portion 17 on the emitter electrode 16, the bonding tool 40 is raised (+ Z direction) as shown by arrow A, and has a U-shape as shown by arrows B to D. Move in (+ X → + Z → -X direction).

この移動は、キャピラリー４１が線状体１３ａより＋Ｘ方向側の第１の領域１５ａの上方に至るまでおこなう。これにより、金属ワイヤー１４はキャピラリー４１から自然と上凸状に曲がるくせが付けられて引き出される。 This movement is performed until the capillary 41 extends above the first region 15a on the + X direction side of the linear body 13a. As a result, the metal wire 14 is naturally bent upwardly from the capillary 41 and is pulled out.

図７（ｂ）に示すように、ボンディングツール４０を矢印Ｅに示すように左斜め下（−Ｚ方向および−Ｘ方向）に移動させる。この移動は、キャピラリー４１がアノード電極１５の第１の領域１５ａに当接するまで行う。これにより、第１湾曲部１４ａが形成される。 As shown in FIG. 7B, the bonding tool 40 is moved diagonally downward to the left (−Z direction and −X direction) as shown by arrow E. This movement is performed until the capillary 41 comes into contact with the first region 15a of the anode electrode 15. As a result, the first curved portion 14a is formed.

超音波接合冶具４３にて金属ワイヤー１４を押圧しながら超音波を印加し、金属ワイヤー１４をアノード電極１５の第１の領域１５ａに接合する。これにより、第１ステッチボンディング部１８ａが形成される。 Ultrasonic waves are applied while pressing the metal wire 14 with the ultrasonic bonding tool 43 to bond the metal wire 14 to the first region 15a of the anode electrode 15. As a result, the first stitch bonding portion 18a is formed.

上述した製造工程により、図１に示す半導体モジュール１０が得られる。 The semiconductor module 10 shown in FIG. 1 is obtained by the manufacturing process described above.

以上説明したように、本実施形態の半導体モジュール１０では、ダイオード１１のアノード電極１５上に線状体１３が配置されている。金属ワイヤー１４は、線状体１３を支えとして強制的に上凸状に曲げられることにより、線状体１３を跨ぐ湾曲部を有し、湾曲部の両端は線状体１３の両側でアノード電極１５に接続されている。 As described above, in the semiconductor module 10 of the present embodiment, the linear body 13 is arranged on the anode electrode 15 of the diode 11. The metal wire 14 has a curved portion straddling the linear body 13 by being forcibly bent upwardly and convexly with the linear body 13 as a support, and both ends of the curved portion are anode electrodes on both sides of the linear body 13. It is connected to 15.

その結果、ダイオード１１およびＩＧＢＴ１２の通電発熱に応じて金属ワイヤー１４が膨張と収縮を繰り返すことによる疲労破断が防止される。従って、大電流を通電可能で信頼性の高い半導体モジュールが得られる。 As a result, fatigue fracture due to repeated expansion and contraction of the metal wire 14 in response to energization heat generation of the diode 11 and the IGBT 12 is prevented. Therefore, a highly reliable semiconductor module that can carry a large current can be obtained.

ここでは、アノード電極１５上に線状体１３を２本配置する場合について説明したが、配置する線状体の数には特に制限はなく、１本でも、３本以上でもかまわない。ダイオード１１のサイズ等に応じて適宜定めることができる。 Here, the case where two linear bodies 13 are arranged on the anode electrode 15 has been described, but the number of linear bodies to be arranged is not particularly limited and may be one or three or more. It can be appropriately determined according to the size of the diode 11 and the like.

線状体１３は、断面が円形である場合について説明したが、円形に限られず金属ワイヤーと線状体が滑らかに当接できるような上凸形状であればよい。 The case where the linear body 13 has a circular cross section has been described, but the linear body 13 is not limited to a circular shape and may have an upward convex shape so that the metal wire and the linear body can smoothly contact each other.

線状体１３が導電体である場合について説明したが、絶縁体でも構わない。線状体が、例えば樹脂の場合、ディスペンサーにより樹脂をアノード電極１５に塗布し、熱硬化させることにより、線状体を形成することもできる。 Although the case where the linear body 13 is a conductor has been described, an insulator may be used. When the linear body is, for example, a resin, the linear body can be formed by applying the resin to the anode electrode 15 with a dispenser and heat-curing the resin.

第１半導体チップ１１は、第１の面１１ａと第２の面１１ｂとの間に電流が流れる縦型半導体素子である場合について説明したが、第１の面と平行な方向に電流が流れる横型半導体素子とすることもできる。第２半導体チップ１２も、同様に横型半導体チップとすることができる。 Although the case where the first semiconductor chip 11 is a vertical semiconductor element in which a current flows between the first surface 11a and the second surface 11b has been described, the first semiconductor chip 11 is a horizontal type in which a current flows in a direction parallel to the first surface. It can also be a semiconductor element. Similarly, the second semiconductor chip 12 can be a horizontal semiconductor chip.

（実施形態２）
本実施形態に係る半導体モジュールについて、図８を用いて説明する。図８は本実施形態の半導体モジュールを示す図で、図８（ａ）はその平面図、図８（ｂ）は図８（ａ）のＡ−Ａ線に沿って切断し矢印方向に眺めた断面図である。 (Embodiment 2)
The semiconductor module according to this embodiment will be described with reference to FIG. 8A and 8B are views showing the semiconductor module of the present embodiment, FIG. 8A is a plan view thereof, and FIG. 8B is cut along the line AA of FIG. 8A and viewed in the direction of an arrow. It is a cross-sectional view.

本実施形態が実施形態１と同様の部分の説明は省略し、異なる点について説明する。本実施形態が実施形態１と異なる点は、線状体が第１電極とは異なる部材上に配置されている点にある。その他に関しては実施形態１と同様である。 The description of the part where the present embodiment is the same as that of the first embodiment will be omitted, and the differences will be described. The difference between the present embodiment and the first embodiment is that the linear body is arranged on a member different from the first electrode. Others are the same as in the first embodiment.

即ち、図８に示すように、本実施形態の半導体モジュール１００は、アノード電極１５と線状体１３との間に配置された中間部材１０１を有している。中間部材１０１とは、例えば線状体１３をアノード電極１５上に固定するための接着剤として機能するものである。 That is, as shown in FIG. 8, the semiconductor module 100 of the present embodiment has an intermediate member 101 arranged between the anode electrode 15 and the linear body 13. The intermediate member 101 functions as, for example, an adhesive for fixing the linear body 13 on the anode electrode 15.

中間部材１０１は、例えばＹ方向に延在し、Ｘ方向に離間して配置されたストライプ状の第１中間部材１０１ａおよび第２中間部材１０１ｂを有している。第１中間部材１０１ａは、アノード電極１５と線状体１３ａとの間に配置されている。第２中間部材１０１ｂは、アノード電極１５と線状体１３ｂとの間に配置されている。 The intermediate member 101 has, for example, a striped first intermediate member 101a and a second intermediate member 101b extending in the Y direction and arranged apart from each other in the X direction. The first intermediate member 101a is arranged between the anode electrode 15 and the linear body 13a. The second intermediate member 101b is arranged between the anode electrode 15 and the linear body 13b.

中間部材１０１は、例えばディスペンサーを用いて液状の接着剤をアノード電極１５上に塗布することにより形成される。接着剤を第１の領域１５ａと第２の領域１５ｂとの間にストライプ状に塗布することにより、第１中間部材１０１ａが得られる。液状の接着剤を、第２の領域１５ｂと第３の領域１５ｃとの間にストライプ状に塗布することにより、第２中間部材１０１ｂが得られる。 The intermediate member 101 is formed by applying a liquid adhesive onto the anode electrode 15 using, for example, a dispenser. By applying the adhesive in a stripe shape between the first region 15a and the second region 15b, the first intermediate member 101a is obtained. The second intermediate member 101b is obtained by applying the liquid adhesive in a stripe shape between the second region 15b and the third region 15c.

第１線状体１３ａを第１中間部材１０１ａ上に載置することにより、第１線状体１３ａは接着性を有する第１中間部材１０１ａ上に固定される。同様に、第２線状体１３ｂを第２中間部材１０１ｂ上に載置することにより、第２線状体１３ｂは、第２中間部材１０１ｂ上に固定される。 By placing the first linear body 13a on the first intermediate member 101a, the first linear body 13a is fixed on the first intermediate member 101a having adhesiveness. Similarly, by placing the second linear body 13b on the second intermediate member 101b, the second linear body 13b is fixed on the second intermediate member 101b.

アノード電極１５にステッチボンディングできない線状体、例えば絶縁性線状体、ボンディングツールの処理範囲を超える太さを有する線状体等でも、中間部材１０１により、線状体１３をアノード電極１５上に固定することができる利点が得られる。これにより、第１半導体チップ１１上に、線状体１３が配置される。 Even for a linear body that cannot be stitch-bonded to the anode electrode 15, for example, an insulating linear body or a linear body having a thickness exceeding the processing range of the bonding tool, the linear body 13 is placed on the anode electrode 15 by the intermediate member 101. The advantage of being able to be fixed is obtained. As a result, the linear body 13 is arranged on the first semiconductor chip 11.

以上説明したように、本実施形態の半導体モジュール１００では、アノード電極１５と線状体１３との間に配置された中間部材１０１を有している。その結果、中間部材１０１を接着剤として、線状体１３をアノード電極１５上に固定することができる。本実施形態においても、実施形態１と同様の効果を得ることができる。 As described above, the semiconductor module 100 of the present embodiment has an intermediate member 101 arranged between the anode electrode 15 and the linear body 13. As a result, the linear body 13 can be fixed on the anode electrode 15 using the intermediate member 101 as an adhesive. Also in this embodiment, the same effect as that of the first embodiment can be obtained.

中間部材１０１が液状の接着剤を塗布したものである場合について説明したが、両面に接着性を有するテープ、所謂両面テープを貼り付けたものであってもよい。 Although the case where the intermediate member 101 is coated with a liquid adhesive has been described, a tape having adhesiveness on both sides, that is, a so-called double-sided tape may be attached.

さらに、中間部材１０１の厚さに応じて、線状体１３のアノード電極１５からの高さを自由に調節することができる。線状体１３の高さが嵩上げされるので、第２、第３湾曲部１４ｂ、１４ｃの高さＬ１ａ、Ｌ１ｂを高くしたい場合、線状体１３自体の径を大きくしなくてもすむ利点がある。 Further, the height of the linear body 13 from the anode electrode 15 can be freely adjusted according to the thickness of the intermediate member 101. Since the height of the linear body 13 is raised, there is an advantage that it is not necessary to increase the diameter of the linear body 13 itself when it is desired to increase the heights L1a and L1b of the second and third curved portions 14b and 14c. be.

この場合、中間部材１０１はリジットなものが好ましく、接着性を有していても、有していなくてもよく、導電体でも絶縁体でも構わない。 In this case, the intermediate member 101 is preferably rigid, and may or may not have adhesiveness, and may be a conductor or an insulator.

（変形例１）
本実施形態の変形例１に係る半導体モジュールについて説明する。図９は本変形例の半導体モジュールを示す平面図である。その断面図は、図８（ｂ）に示す断面図と同様のため省略する。 (Modification example 1)
The semiconductor module according to the first modification of the present embodiment will be described. FIG. 9 is a plan view showing the semiconductor module of this modified example. The cross-sectional view is the same as the cross-sectional view shown in FIG. 8 (b), and is therefore omitted.

図９に示すように、本変形例の半導体モジュール２００では、第１中間部材２０１ａおよび第２中間部材２０１ｂがそれぞれＹ方向に複数に分割されている点において半導体モジュール２００と異なっている。その他の点に関しては、半導体モジュール２００と同様である。 As shown in FIG. 9, the semiconductor module 200 of this modification is different from the semiconductor module 200 in that the first intermediate member 201a and the second intermediate member 201b are each divided into a plurality of parts in the Y direction. The other points are the same as those of the semiconductor module 200.

分割された第１中間部材２０１ａの各部分を第１部分、分割された第２中間部材２０１ｂの各部分を第２部分と称する。第１部分は、平面視で第１線状体１３ａと金属ワイヤー１４の交点近傍に配置されている。第２部分は、平面視で第２線状体１３ｂと金属ワイヤー１４の交点近傍に配置されている。 Each part of the divided first intermediate member 201a is referred to as a first part, and each part of the divided second intermediate member 201b is referred to as a second part. The first portion is arranged near the intersection of the first linear body 13a and the metal wire 14 in a plan view. The second portion is arranged near the intersection of the second linear body 13b and the metal wire 14 in a plan view.

中間部材２０１により嵩上げされた線状体１３を支えとして金属ワイヤー１４を上凸状に曲げるとき、中間部材２０１は平面視で線状体１３と金属ワイヤー１４の交点近傍に配置されていれば十分であり、Ｙ方向にストライプ状に配置されていなくてもよい。 When the metal wire 14 is bent upwardly with the linear body 13 raised by the intermediate member 201 as a support, it is sufficient that the intermediate member 201 is arranged near the intersection of the linear body 13 and the metal wire 14 in a plan view. It does not have to be arranged in a stripe shape in the Y direction.

隣り合う第１部分同士の間に位置する第１線状体１３ａは、アノード電極１５より中間部材２０１ａの厚さ分だけ離間していても、垂れてアノード電極１５に接していてもよい。隣り合う第２部分の同士の間に位置する第２線状体１３ｂは、アノード電極１５より中間部材２０１ｂの厚さ分だけ離間していても、垂れてアノード電極１５に接していてもよい。 The first linear body 13a located between the adjacent first portions may be separated from the anode electrode 15 by the thickness of the intermediate member 201a, or may hang down and be in contact with the anode electrode 15. The second linear body 13b located between the adjacent second portions may be separated from the anode electrode 15 by the thickness of the intermediate member 201b, or may hang down and be in contact with the anode electrode 15.

第１部分および第２部分は、例えばディスペンサーを用いて液状の接着剤をアノード電極１５上に離散的に塗布（ポッテイング）することにより形成することができる。 The first portion and the second portion can be formed by, for example, using a dispenser to discretely apply (potting) a liquid adhesive onto the anode electrode 15.

中間部材２０１をＹ方向に複数に分割したことにより、中間部材２０１の形成が容易になるとともに、中間部材２０１の材料を削減できる利点がある。 By dividing the intermediate member 201 into a plurality of parts in the Y direction, there is an advantage that the intermediate member 201 can be easily formed and the material of the intermediate member 201 can be reduced.

（変形例２）
本実施形態の変形例２に係る半導体モジュールについて説明する。図１０は本変形例の半導体モジュールを示す平面図、図１０（ｂ）はＡ−Ａ線に沿って切断し矢印方向に眺めた断面図である。 (Modification 2)
The semiconductor module according to the second modification of the present embodiment will be described. FIG. 10 is a plan view showing the semiconductor module of this modified example, and FIG. 10B is a cross-sectional view taken along the line AA and viewed in the direction of the arrow.

図１０に示すように、本変形例の半導体モジュール３００では、金属ワイヤー１４の第１電極１５への接続が完了した後に、線状体１３が除去されている点において、半導体モジュール１００、２００と異なっている。その他の点については同様である。 As shown in FIG. 10, in the semiconductor module 300 of the present modification, the semiconductor modules 100 and 200 are in that the linear body 13 is removed after the connection of the metal wire 14 to the first electrode 15 is completed. It's different. The same applies to other points.

第１および第２線状体１３ａ、１３ｂは、半導体モジュールの特性に影響を与えないので、金属ワイヤー１４のボンディングが完了した後に、除去されても構わない。金属ワイヤー１４の第２、第３湾曲部１４ｂ、１４ｃは、両端が既に第１乃至第３ステッチボンディング部１８ａ、１８ｂ、１８ｃにより固定されているので、第１および第２線状体１３ａ、１３ｂが無くても自立することができる。 Since the first and second linear bodies 13a and 13b do not affect the characteristics of the semiconductor module, they may be removed after the bonding of the metal wire 14 is completed. Since both ends of the second and third curved portions 14b and 14c of the metal wire 14 are already fixed by the first to third stitch bonding portions 18a, 18b and 18c, the first and second linear bodies 13a and 13b You can stand on your own even if you don't have.

第１および第２線状体１３ａ、１３ｂの除去は、例えば以下のように行うことができる。金属ワイヤー１４のボンディングが完了した後に、溶剤を用いて中間部材１０１、２０１を溶解し、第１および第２線状体１３ａ、１３ｂを浮き上がらせて剥離する。中間部材２０１は複数の部分に分割されているので、溶剤との接触面積が大きい。中間部材２０１は、ストライプ状の中間部材１０１より除去が容易である。 The removal of the first and second linear bodies 13a and 13b can be performed, for example, as follows. After the bonding of the metal wire 14 is completed, the intermediate members 101 and 201 are dissolved using a solvent, and the first and second linear bodies 13a and 13b are lifted and peeled off. Since the intermediate member 201 is divided into a plurality of portions, the contact area with the solvent is large. The intermediate member 201 is easier to remove than the striped intermediate member 101.

また、第１および第２線状体１３ａ、１３ｂ自体を、溶剤に可溶な材質のワイヤーとすることもできる。 Further, the first and second linear bodies 13a and 13b themselves can be made of a wire made of a solvent-soluble material.

金属ワイヤー１４のボンディングが完了した後に、線状体１３を除去しておくと、第１および第２半導体チップ１１、１２の通電発熱により、線状体および中間部材が劣化する恐れがなくなる利点がある。 If the linear body 13 is removed after the bonding of the metal wire 14 is completed, there is an advantage that the linear body and the intermediate member are not deteriorated due to the energization heat generation of the first and second semiconductor chips 11 and 12. be.

（実施形態３）
本実施形態に係る半導体モジュールについて、図１１を用いて説明する。図１１は本実施形態の半導体モジュールを示す断面図である。 (Embodiment 3)
The semiconductor module according to this embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view showing the semiconductor module of the present embodiment.

本実施形態が実施形態１と同様の部分の説明は省略し、異なる点について説明する。本実施形態が実施形態１と異なる点は、隣接する半導体チップ同士が線状体を跨ぐ湾曲部を有する金属ワイヤーにより電気的に接続されている点にある。その他に関しては実施形態１と同様である。 The description of the part where the present embodiment is the same as that of the first embodiment will be omitted, and the differences will be described. The difference between the present embodiment and the first embodiment is that adjacent semiconductor chips are electrically connected to each other by a metal wire having a curved portion straddling the linear body. Others are the same as in the first embodiment.

即ち、図１１に示すように、本実施形態の半導体モジュール４００では、第１半導体チップ４１１および第２半導体チップ４１２は、絶縁性基板（図示せず）上でＸ方向に近接して並置されている。 That is, as shown in FIG. 11, in the semiconductor module 400 of the present embodiment, the first semiconductor chip 411 and the second semiconductor chip 412 are juxtaposed close to each other in the X direction on an insulating substrate (not shown). There is.

第１半導体チップ４１１と第２半導体チップ４１２とは、同種または異種の半導体チップで、電気的に並列接続または直列接続されている。 The first semiconductor chip 411 and the second semiconductor chip 412 are semiconductor chips of the same type or different types, and are electrically connected in parallel or in series.

第１半導体チップ４１１上に第１線状体４１３ａが配置されている。第２半導体チップ４１２上に第２線状体４１３ｂが配置されている。第２線状体４１３ｂより第１半導体チップ４１１寄りの第２半導体チップ４１２上に第３線状体４１３ｃが配置されている。 The first linear body 413a is arranged on the first semiconductor chip 411. The second linear body 413b is arranged on the second semiconductor chip 412. The third linear body 413c is arranged on the second semiconductor chip 412 closer to the first semiconductor chip 411 than the second linear body 413b.

第１半導体チップ４１１には第１電極４１５が設けられ、第１線状体４１３ａは第１電極４１５上に配置されている。同様に、第２半導体チップ４１２には第２電極４１６が設けられ、第２線状体４１３ｂは第２電極４１６上に配置されている。第３線状体４１３ｃは、第２線状体４１３ｂより第１半導体チップ４１１寄りの第２電極４１６上に配置されている。 The first semiconductor chip 411 is provided with a first electrode 415, and the first linear body 413a is arranged on the first electrode 415. Similarly, the second semiconductor chip 412 is provided with the second electrode 416, and the second linear body 413b is arranged on the second electrode 416. The third linear body 413c is arranged on the second electrode 416 closer to the first semiconductor chip 411 than the second linear body 413b.

金属ワイヤー４１４は、一側が第２半導体チップ４１２に接続され、他側が第１半導体チップ４１１に接続されている。 One side of the metal wire 414 is connected to the second semiconductor chip 412, and the other side is connected to the first semiconductor chip 411.

より具体的には、金属ワイヤー４１４の一側は、（１）第２電極４１６上であって第２線状体４１３ｂより＋Ｘ方向の第１の領域４１６ａにステッチボンディングされ、（２）第２線状体４１３ｂを跨ぐ湾曲部４１４ａを有し、第２電極４１６上であって第２線状体４１３ｂと第３線状体４１３ｃとの間の第２領域４１６ｂにステッチボンディングされている。 More specifically, one side of the metal wire 414 is (1) stitch-bonded to the first region 416a on the second electrode 416 from the second linear body 413b in the + X direction, and (2) the second. It has a curved portion 414a that straddles the linear body 413b, and is stitch-bonded to a second region 416b on the second electrode 416 and between the second linear body 413b and the third linear body 413c.

金属ワイヤー４１４の他側は、（３）第３線状体４１３ｃを跨ぐ湾曲部４１４ｂを有し、第１電極４１５上であって第１線状体４１３ａより＋Ｘ方向の第３の領域４１５ａにステッチボンディングされ、（４）第１線状体４１３ａを跨ぐ湾曲部４１４ｃを有し、第１電極４１５上であって第１線状体４１３ａより−Ｘ方向の第４の領域４１５ｂにステッチボンディングされている。 The other side of the metal wire 414 has (3) a curved portion 414b straddling the third linear body 413c, and is located on the first electrode 415 and in the third region 415a in the + X direction from the first linear body 413a. Stitch-bonded, (4) has a curved portion 414c straddling the first linear body 413a, and is stitch-bonded to a fourth region 415b on the first electrode 415 in the −X direction from the first linear body 413a. ing.

第３線状体４１３ｃを第２半導体チップ４１２上に配置することにより、金属ワイヤー４１４において隣接する第１半導体チップ４１１上の接続点と第２半導体チップ４１２上の接続点との距離を、金属ワイヤー４１４の剛性に応じて定まる接続可能な最短距離より短くすることができる。即ち、第１半導体チップ４１１および第２半導体チップ４１２を、より近接して並置することができるので、半導体モジュール４００をより小型化することが可能である。 By arranging the third linear body 413c on the second semiconductor chip 412, the distance between the connection point on the first semiconductor chip 411 adjacent to the metal wire 414 and the connection point on the second semiconductor chip 412 can be set to the metal. It can be shorter than the shortest connectable distance determined by the rigidity of the wire 414. That is, since the first semiconductor chip 411 and the second semiconductor chip 412 can be juxtaposed closer to each other, the semiconductor module 400 can be further miniaturized.

以上説明したように、本実施形態の半導体モジュール４００では、第１半導体チップ４１１寄りの第２半導体チップ４１２上に第３線状体４１３ｃが配置されている。その結果、第１半導体チップ４１１および第２半導体チップ４１２を、より近接して並置することができる。従って、半導体モジュール４００をより小型化することができる。 As described above, in the semiconductor module 400 of the present embodiment, the third linear body 413c is arranged on the second semiconductor chip 412 near the first semiconductor chip 411. As a result, the first semiconductor chip 411 and the second semiconductor chip 412 can be juxtaposed closer to each other. Therefore, the semiconductor module 400 can be further miniaturized.

なお、第３線状体４１３ｃは、第２半導体チップ４１２寄りの第１半導体チップ４１１上に配置することもできる。 The third linear body 413c can also be arranged on the first semiconductor chip 411 near the second semiconductor chip 412.

（変形例）
図１２は本実施形態の変形例に係る半導体モジュールを示す断面図である。変形例の半導体モジュール５００では、第１半導体チップと第２半導体チップとの間に線状体が配置されている点で、半導体モジュール４００とは異なっている。その他の点については同様である。 (Modification example)
FIG. 12 is a cross-sectional view showing a semiconductor module according to a modified example of the present embodiment. The semiconductor module 500 of the modified example is different from the semiconductor module 400 in that a linear body is arranged between the first semiconductor chip and the second semiconductor chip. The same applies to other points.

即ち、図１２に示すように、半導体モジュール５００では、金属ワイヤー５１４は大電流、例えば１０Ａ／本、を通電できるように、図１１に示す金属ワイヤー４１４より線径が太い金属ワイヤーである。金属ワイヤー５１４の剛性は、金属ワイヤー４１４の剛性より大きい。 That is, as shown in FIG. 12, in the semiconductor module 500, the metal wire 514 is a metal wire having a larger wire diameter than the metal wire 414 shown in FIG. 11 so that a large current, for example, 10 A / wire can be energized. The rigidity of the metal wire 514 is greater than the rigidity of the metal wire 414.

剛性が大きくなるほど、線状体を支点として金属ワイヤーを上凸状に湾曲させることにより接続可能な２点間の距離は、大きくなる。即ち、第１半導体チップ４１１と第２半導体チップ４１２との間に隙間が生じるので、第３線状体５１３ｃを第１半導体チップ４１１と第２半導体チップ４１２との間に配置することが可能になる。 As the rigidity increases, the distance between two points that can be connected by bending the metal wire in an upward convex shape with the linear body as a fulcrum increases. That is, since a gap is formed between the first semiconductor chip 411 and the second semiconductor chip 412, the third linear body 513c can be arranged between the first semiconductor chip 411 and the second semiconductor chip 412. Become.

第３線状体５１３ｃを第１半導体チップ４１１と第２半導体チップ４１２との間に配置することにより、より剛性の高い金属ワイヤー５１４を用いても、第１半導体チップ４１１および第２半導体チップ４１２をより近接して並置することができる。従って、半導体モジュール５００をより小型化することが可能である。 By arranging the third linear body 513c between the first semiconductor chip 411 and the second semiconductor chip 412, the first semiconductor chip 411 and the second semiconductor chip 412 can be used even if the metal wire 514 having higher rigidity is used. Can be juxtaposed closer together. Therefore, the semiconductor module 500 can be made smaller.

（実施形態４）
本実施形態に係る半導体モジュールについて、図１３および図１４を用いて説明する。図１３は本実施形態の半導体モジュールを示す平面図である。図１４は半導体モジュールの回路図である。 (Embodiment 4)
The semiconductor module according to this embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 is a plan view showing the semiconductor module of the present embodiment. FIG. 14 is a circuit diagram of the semiconductor module.

本実施形態が実施形態１と同様の部分の説明は省略し、異なる点について説明する。本実施形態が実施形態１と異なる点は、実施形態１の半導体モジュールを複数組み合わせた半導体モジュールとしたことにある。 The description of the part where the present embodiment is the same as that of the first embodiment will be omitted, and the differences will be described. The difference between this embodiment and the first embodiment is that a semiconductor module obtained by combining a plurality of semiconductor modules of the first embodiment is obtained.

即ち、図１３および図１４に示すように、本実施形態の半導体モジュール５０は、実施形態１に示す半導体モジュール１０を６つ用いて３相フルブリッジ回路を構成したものである。絶縁性基板５１に、６つの半導体モジュール１０ａ〜１０ｆが配置されている。絶縁性基板５１は、パッケージ５２に収納されている。 That is, as shown in FIGS. 13 and 14, the semiconductor module 50 of the present embodiment comprises six semiconductor modules 10 shown in the first embodiment to form a three-phase full bridge circuit. Six semiconductor modules 10a to 10f are arranged on the insulating substrate 51. The insulating substrate 51 is housed in the package 52.

絶縁性基板５１には、ダイオード１１のカソードとＩＧＢＴ１２のコレクタとを電気的に接続する導電層（図示せず）が設けられ、半導体モジュール１０ａ〜１０ｆ間を接続する配線（図示せず）、ＩＧＢＴ１２のゲート電極にＰＷＭ信号を入力するための配線（図示せず）等が設けられている。 The insulating substrate 51 is provided with a conductive layer (not shown) that electrically connects the cathode of the diode 11 and the collector of the IGBT 12, and is a wiring (not shown) that connects the semiconductor modules 10a to 10f. Wiring (not shown) for inputting a PWM signal is provided in the gate electrode of the above.

半導体モジュール５０は、例えば入力された直流電圧Ｖｉｎを３相交流に変換するＤＣ／ＡＣコンバータに用いられる。半導体モジュール１０ａ〜１０ｆを適切なタイミングでスイッチングさせることで、３相モータ５３への通電が行われる。 The semiconductor module 50 is used, for example, in a DC / AC converter that converts an input DC voltage Vin into a three-phase alternating current. By switching the semiconductor modules 10a to 10f at appropriate timings, the three-phase motor 53 is energized.

複数の半導体モジュール１０によって、ブリッジ回路が構成されている場合、１つの半導体モジュール１０がオン状態からオフ状態に切り替わると、ブリッジ回路のインダクタンス成分により、半導体モジュール１０のエミッタ電極に誘導起電力が加わる。これにより、この半導体モジュール１０において、ダイオード１１が動作し、誘導起電力を吸収する。ダイオード１１はＦＷＤ（Free Wheel Diode）として機能する。 When a bridge circuit is composed of a plurality of semiconductor modules 10, when one semiconductor module 10 is switched from an on state to an off state, an induced electromotive force is applied to the emitter electrode of the semiconductor module 10 due to the inductance component of the bridge circuit. .. As a result, in the semiconductor module 10, the diode 11 operates and absorbs the induced electromotive force. The diode 11 functions as an FWD (Free Wheel Diode).

以上説明したように、本実施形態の半導体モジュール５０は、半導体モジュール１０ａ〜１０ｆを用いて３相フルブリッジ回路を構成している。３相モータが組み込まれる電気機器に大電流を信頼性よく供給することができる。 As described above, the semiconductor module 50 of the present embodiment constitutes a three-phase full bridge circuit by using the semiconductor modules 10a to 10f. A large current can be reliably supplied to an electric device incorporating a three-phase motor.

図１５は、本実施形態に係る別の半導体モジュールを示す回路図である。
図１５に示すように、半導体モジュール６０は、実施形態１に示す半導体モジュール１０を４つ用いて単相フルブリッジ回路を構成したものである。半導体モジュール６０は、例えば、入力された直流電圧Ｖｉｎを、異なる直流電圧Ｖｏｕｔに変換するフルブリッジ型ＤＣ／ＤＣコンバータに用いられる。 FIG. 15 is a circuit diagram showing another semiconductor module according to the present embodiment.
As shown in FIG. 15, the semiconductor module 60 comprises four semiconductor modules 10 shown in the first embodiment to form a single-phase full bridge circuit. The semiconductor module 60 is used, for example, in a full-bridge type DC / DC converter that converts an input DC voltage Vin into a different DC voltage Vout.

半導体モジュール１０ａ〜１０ｄを適切なタイミングでスイッチングさせることで、トランス６１への通電が行われる。トランス６１の１次巻き線には、キャパシタ６２が接続されていてもよい。 By switching the semiconductor modules 10a to 10d at an appropriate timing, the transformer 61 is energized. A capacitor 62 may be connected to the primary winding of the transformer 61.

以上、いくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although some embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

なお、以下の付記に記載されているような構成が考えられる。
（付記１） 前記線状体は、前記第１電極上に配置されている請求項１記載の半導体モジュール。
（付記２） 前記線状体は、前記第１電極上に設けられた中間部材上に配置されている請求項１記載の半導体モジュール。
（付記３） 前記線状体は、前記湾曲部と前記第１半導体チップの前記第１の面との間、または前記湾曲部と前記第２半導体チップの前記第１の面との間に配置されている請求項３記載の半導体モジュール。
（付記４） 前記線状体は、前記第１半導体チップと前記第２半導体チップとの間に配置されている請求項３記載の半導体モジュール。 The configuration described in the following appendix can be considered.
(Appendix 1) The semiconductor module according to claim 1, wherein the linear body is arranged on the first electrode.
(Appendix 2) The semiconductor module according to claim 1, wherein the linear body is arranged on an intermediate member provided on the first electrode.
(Appendix 3) The linear body is arranged between the curved portion and the first surface of the first semiconductor chip, or between the curved portion and the first surface of the second semiconductor chip. The semiconductor module according to claim 3.
(Appendix 4) The semiconductor module according to claim 3, wherein the linear body is arranged between the first semiconductor chip and the second semiconductor chip.

１０、３０、５０、６０、１００、２００、３００、４００、５００ 半導体モジュール
１１、４１１ 第１半導体チップ
１２、４１２ 第２半導体チップ
１１ａ、１２ａ 第１の面
１１ｂ、１２ｂ 第２の面
１３、４１３ 線状体
１４、４１４、５１４ 金属ワイヤー
１４ａ〜１４ｃ、４１４ａ〜４１４ｃ、５１４ａ〜５１４ｃ 第１〜第３湾曲部
１４ｄ、１４ｅ 第１、第２直線部
１５、４１５ 第１電極
１５ａ〜１５ｃ 第１〜第３の領域
１６、４１６ 第２電極
１７ ボールボンディング部
１８ａ〜１８ｃ 第１〜第３ステッチボンディング部
４０ ボンディングツール
４１ キャピラリー
４２ クランパー
４３ 超音波接合冶具
４４ カッター
５１ 絶縁性基板
５２ パッケージ
５３ 三相モータ
６１ トランス
６２ キャパシタ
１０１、２０１ 中間部材 10, 30, 50, 60, 100, 200, 300, 400, 500 Semiconductor module 11,411 First semiconductor chip 12,412 Second semiconductor chip 11a, 12a First surface 11b, 12b Second surface 13,413 Linear bodies 14, 414, 514 Metal wires 14a to 14c, 414a to 414c, 514a to 514c First to third curved portions 14d, 14e First and second straight portions 15, 415 First electrodes 15a to 15c First 1 to Third Region 16, 416 Second Electrode 17 Ball Bonding Part 18a-18c First 1st to 3rd Stitch Bonding Part 40 Bonding Tool 41 Capacitor 42 Clamper 43 Ultrasonic Bonding Jig 44 Cutter 51 Insulating Substrate 52 Package 53 Three-Phase Motor 61 Transformer 62 Capacitor 101, 201 Intermediate member

Claims (3)

第１の面に第１の領域と第２の領域とを有する第１電極が設けられた第１半導体チップを用意する工程と、
前記第１の領域と前記第２の領域との間の領域に線状体を配置する工程と、
金属ワイヤーを、前記第１の領域に接合し、前記金属ワイヤーが挿通されたボンディングツールを、前記金属ワイヤーが前記線状体に漸近するように斜め上方に移動させ、前記金属ワイヤーが前記線状体に当接し、更に前記第１電極に当接するまで下降させるにあたって、前記金属ワイヤーが前記第１電極に当接する前に、前記ボンディングツールを前記線状体に近づく方向に移動させ、前記線状体に当接した前記金属ワイヤーを前記線状体から離間させる、ことにより、前記線状体を支えとして前記第１の面より上方に湾曲させ、前記第２の領域に接合する工程と、
を具備する半導体モジュールの製造方法。 A step of preparing a first semiconductor chip provided with a first electrode having a first region and a second region on the first surface, and a step of preparing the first semiconductor chip.
The step of arranging the linear body in the region between the first region and the second region, and
The metal wire is joined to the first region, and the bonding tool through which the metal wire is inserted is moved diagonally upward so that the metal wire approaches the linear body, and the metal wire is linear. In lowering the metal wire until it abuts on the body and further abuts on the first electrode, the bonding tool is moved in a direction approaching the linear body before the metal wire abuts on the first electrode. A step of separating the metal wire in contact with the body from the linear body, thereby bending the metal wire upward from the first surface with the linear body as a support and joining to the second region.
A method for manufacturing a semiconductor module. 第１の面に第２電極が設けられた第２半導体チップを、前記第１半導体チップと並置する工程と、
前記金属ワイヤーの一側を前記第２電極に接続し、前記金属ワイヤーの他側を前記第１電極に接続する工程と、
を具備する請求項１記載の半導体モジュールの製造方法。 A step of juxtaposing the second semiconductor chip provided with the second electrode on the first surface with the first semiconductor chip, and
A step of connecting one side of the metal wire to the second electrode and connecting the other side of the metal wire to the first electrode.
The method for manufacturing a semiconductor module according to claim 1. 更に前記線状体を除去する工程を有する請求項１または２記載の半導体モジュールの製造方法。 The method for manufacturing a semiconductor module according to claim 1 or 2, further comprising a step of removing the linear body.
JP2018018665A 2018-02-05 2018-02-05 Semiconductor module and its manufacturing method Active JP6960868B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018018665A JP6960868B2 (en) 2018-02-05 2018-02-05 Semiconductor module and its manufacturing method
DE102019200634.5A DE102019200634B4 (en) 2018-02-05 2019-01-18 Process for manufacturing a semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018018665A JP6960868B2 (en) 2018-02-05 2018-02-05 Semiconductor module and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2019135761A JP2019135761A (en) 2019-08-15
JP6960868B2 true JP6960868B2 (en) 2021-11-05

Family

ID=67308970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018018665A Active JP6960868B2 (en) 2018-02-05 2018-02-05 Semiconductor module and its manufacturing method

Country Status (2)

Country Link
JP (1) JP6960868B2 (en)
DE (1) DE102019200634B4 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7334655B2 (en) * 2020-03-06 2023-08-29 三菱電機株式会社 semiconductor equipment
JP7293155B2 (en) 2020-03-12 2023-06-19 株式会社東芝 Semiconductor device and wire bonding method
EP4120341A1 (en) * 2021-07-13 2023-01-18 Siemens Aktiengesellschaft Semiconductor assembly comprising a semiconductor element, a substrate and bonding means

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5051260A (en) 1973-09-07 1975-05-08
JPH05335365A (en) * 1992-05-29 1993-12-17 Toshiba Corp Manufacture of semiconductor device and semiconductor device
JP2003110401A (en) * 2001-09-27 2003-04-11 Mitsubishi Electric Corp Surface acoustic wave device and its manufacturing method
JP2003188378A (en) * 2001-12-14 2003-07-04 Mitsubishi Electric Corp Semiconductor device
US20040217488A1 (en) 2003-05-02 2004-11-04 Luechinger Christoph B. Ribbon bonding
JP2005234152A (en) * 2004-02-19 2005-09-02 Sharp Corp Liquid crystal display device
DE102008008853B4 (en) 2008-02-13 2010-05-06 Semikron Elektronik Gmbh & Co. Kg Circuit arrangement with bond connection
CN102487025B (en) 2010-12-08 2016-07-06 飞思卡尔半导体公司 For the long supporter in conjunction with wire
JP2012195459A (en) * 2011-03-16 2012-10-11 Sharp Corp Wire bonding method and semiconductor device
JP5707302B2 (en) * 2011-11-02 2015-04-30 株式会社 日立パワーデバイス Power semiconductor module
JP2015185570A (en) * 2014-03-20 2015-10-22 三菱電機株式会社 power semiconductor device
JP2016086003A (en) * 2014-10-23 2016-05-19 三菱電機株式会社 Manufacturing method of power semiconductor device
DE102016224631B4 (en) 2016-12-09 2020-06-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Electrically conductive connection between at least two electrical components on a carrier equipped with electronic and / or electrical components, which is formed with a bonding wire

Also Published As

Publication number Publication date
JP2019135761A (en) 2019-08-15
DE102019200634A1 (en) 2019-08-08
DE102019200634B4 (en) 2023-06-29

Similar Documents

Publication Publication Date Title
KR102419302B1 (en) Power overlay structure having wirebonds and method of manufacturing the same
JP6960868B2 (en) Semiconductor module and its manufacturing method
KR101524545B1 (en) Power device package and the method of fabricating the same
CN107615464B (en) Method for manufacturing power semiconductor device and power semiconductor device
JP2004336043A (en) Ribbon bonding
JP6487122B2 (en) Power semiconductor device
US9196577B2 (en) Semiconductor packaging arrangement
US20150206830A1 (en) Method Of Manufacturing Semiconductor Device And The Semiconductor Device
US11749633B2 (en) Power semiconductor module with laser-welded leadframe
JP2012109455A (en) Semiconductor device and method of manufacturing the same
JP2019216214A (en) Semiconductor device, lead frame and method of manufacturing semiconductor device
JP2018190930A (en) Power semiconductor module, method for manufacturing the same, and power conversion device
JP2018067611A (en) Semiconductor device and power conversion device
JP6667737B1 (en) Semiconductor module and power converter
JP2016086003A (en) Manufacturing method of power semiconductor device
US10872846B2 (en) Solid top terminal for discrete power devices
WO2012053129A1 (en) Semiconductor device, and manufacturing method for same
JP6410998B1 (en) Semiconductor module, semiconductor module manufacturing method, and power conversion device
US8901569B2 (en) Power semiconductor device
US11557531B2 (en) Semiconductor device with metal film, power conversion device with the semiconductor device, and method of manufacturing the semiconductor device
JP2021077777A (en) Semiconductor device
JP6737024B2 (en) Method of manufacturing semiconductor device and semiconductor device
JP7237192B2 (en) Semiconductor device, manufacturing method thereof, and power conversion device
JP2013026316A (en) Semiconductor device and manufacturing method therefor
WO2022249951A1 (en) Power semiconductor device and power conversion device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190918

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200629

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200811

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201008

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210329

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210421

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210913

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20211012

R151 Written notification of patent or utility model registration

Ref document number: 6960868

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151