JP6952936B1 - Protective relay device - Google Patents

Abstract

It has a first protection control calculation means, a first control circuit, a second protection control calculation means, and a second control circuit. Both control circuits control circuit breakers provided in the power system based on the determination results of both protection control calculation means. Both control circuits generate a key code. Both protection control means generate a key synthesis code based on the key code. Both control circuits control circuit breakers provided in the power system on the condition that the key code and the key synthesis code correspond to each other.

Description

Embodiments of the present invention relate to a protective relay device.

The power system for distributing the power supplied from the power plant to the consumers is provided with a circuit breaker for protecting various facilities of the power system. The circuit breaker is controlled by a protective relay device that detects an accident on the power system, or is controlled by a monitoring control device. High reliability is required for the protective relay device, but there is a problem that the structure becomes complicated in order to improve the reliability.

Japanese Unexamined Patent Publication No. 56-139025 Japanese Unexamined Patent Publication No. 57-106330 Japanese Unexamined Patent Publication No. 5-207637 Japanese Patent No. 2839030

An object to be solved by the present invention is to provide a protective relay device capable of simplifying the structure without impairing reliability.

The protection relay device of the embodiment includes a first protection control calculation means, a first control circuit, a second protection control calculation means, and a second control circuit. The first protection control calculation means makes a determination based on the information obtained by converting the analog information indicating the state of the power system into digital information. The first control circuit controls the circuit breaker provided in the power system based on the determination result of the first protection control calculation means. The second protection control calculation means makes a determination based on the information obtained by converting the analog information indicating the state of the power system into digital information. The second control circuit controls the circuit breaker provided in the power system based on the determination result of the second protection control calculation means. The first control circuit includes a first key code generation circuit that generates a first key code. The first protection control calculation means has a first key synthesis code generation circuit that generates a first key synthesis code based on the first key code. The second control circuit has a second key code generation circuit that generates a second key code. The second protection control calculation means has a second key synthesis code generation circuit that generates a second key synthesis code based on the second key code. The first control circuit has a first decoding / collation circuit that determines whether or not the first key synthesis code and the first key code correspond to each other, and the first key synthesis code and the first key code correspond to each other. The circuit breaker provided in the power system is controlled on condition that the power system is operated. The second control circuit has a second decoding / collation circuit that determines whether or not the second key synthesis code and the second key code correspond to each other, and the second key synthesis code and the second key code correspond to each other. The circuit breaker provided in the power system is controlled on condition that the power system is operated.

The functional block block diagram of the protection relay device 10 of 1st Embodiment. The functional block block diagram of the protection relay device 10 of the 2nd Embodiment. The functional block block diagram of the protection relay device 10 of the 3rd Embodiment. The functional block block diagram of the protection relay device 10 of 4th Embodiment. The figure which shows the 1st configuration example of the hardware of the protection relay device 10. The figure which shows the 2nd configuration example of the hardware of the protection relay device 10. The figure which shows the 3rd configuration example of the hardware of the protection relay device 10.

Hereinafter, the protective relay device of the embodiment will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a functional block configuration diagram of the protective relay device 10 of the first embodiment. The protective relay device 10 controls, for example, a circuit breaker provided in the power system for distributing the power supplied from the power plant to consumers. The protective power relay device 10 controls the power supply destination and the power supply amount in the power system by controlling the circuit breaker in a cut-off state and an energized state. The protective relay device 10 is not limited to a device for eliminating an accident in the event of an accident, but can also be applied as a monitoring and control device that constantly switches the system.

The protective relay device 10 includes a main processing unit 100 and a fail-safe processing unit 200. Analog information is input to the protection relay device 10 by, for example, a transformer in the power system. The analog information is input to the main processing unit 100 and the fail-safe processing unit 200, respectively. The analog information includes state information such as current value and voltage value measured in the power system. The protection relay device 10 outputs control information for controlling the circuit breaker to the circuit breaker 20.

The circuit breaker 20 is provided, for example, on a power transmission line. Based on the control information from the protective power relay device 10, the circuit breaker 20 sets the portion of the transmission line where the circuit breaker 20 is installed in the cutoff state or the energized state. The circuit breaker 20 includes a first switch 22 and a second switch 24.

When the circuit breaker 20 is in a cut-off state, power is not supplied to the equipment on the downstream side from the location where the circuit breaker 20 is installed in the transmission line. For example, when the equipment on the downstream side of the circuit breaker 20 fails, the circuit breaker 20 is set to the cutoff state and the equipment in which the failure occurs is temporarily disconnected from the sound power system. After that, for example, the circuit breaker 20 is left in the circuit breaker state and waits for the arc to be extinguished due to a failure of the equipment or the like, and then the circuit breaker 20 is returned to the energized state. The disconnector 30 is a switch that opens and closes in a state where no current flows through the transmission line SL. The disconnector 30 plays a role of disconnecting the device from the power source (power generation device 2), for example, when changing the connection or inspecting / repairing the device. On the other hand, when the circuit breaker 20 is energized, electric power is supplied to the equipment on the downstream side from the location where the circuit breaker 20 is installed in the transmission line.

The protection relay device 10 has a redundant configuration by including a main processing unit 100 and a fail-safe processing unit 200. The protective relay device 10 has a redundant configuration to prevent erroneous control due to a transient defect of the system component of the protective relay device 10.

The main processing unit 100 includes, for example, a main protection / control calculation means (an example of a first protection control calculation means) 110 and a main control circuit (an example of a first control circuit) 120. The fail-safe processing unit 200 includes a fail-safe protection / control calculation means (an example of a second protection control calculation means) 210 and a fail-safe control circuit (an example of a second control circuit) 220.

The main protection / control calculation means 110 in the main processing unit 100 includes, for example, an AD (Analog-digital) conversion circuit 112, a main control calculation unit 114, a main protection calculation unit 116, and a main key synthesis code generation circuit (first). (Example) 118 of the key synthesis code generation circuit. The main control circuit 120 includes an energization control circuit 122, a main key code generation circuit (an example of a first key code generation circuit) 124, and a main key synthesis code decoding / verification circuit (an example of a first decoding / verification circuit) 126. , Equipped with.

The AD conversion circuit 112 holds analog information input by the power system at regular time intervals, and converts the held analog information into digital information. The state information includes information detected by a state sensor such as a voltage / current value sensor and converted from analog information, and temperature information output by the temperature sensor depending on the protection target. The AD conversion circuit 112 outputs the state information to the main protection calculation unit 116.

Further, the information input to the AD conversion circuit 112 by the contact input is converted into digital information, and includes instruction information for shutting off or energizing the circuit breaker 20. The instruction information is, for example, information input by an operator or the like using an input device or the like, and is information for instructing whether the circuit breaker 20 is to be in the cutoff state or the energized state. Of the digital information, the instruction information is output to the main control calculation unit 114.

The main control calculation unit 114 determines whether to shut off or energize the circuit breaker 20 based on the instruction information output by the AD conversion circuit 112. The main control calculation unit 114 generates cutoff / energization control information based on a determination result of whether to shut off or energize the circuit breaker 20. The shut-off / energization control information includes the cut-off control information for shutting off the circuit breaker 20 and the energization control information for energizing the circuit breaker 20. The main control calculation unit 114 outputs the generated cutoff / energization control information to the main control circuit 120.

The main protection calculation unit 116 determines whether or not to forcibly shut off the circuit breaker 20 based on the state information output by the AD conversion circuit 112. The main protection calculation unit 116 generates the forced cutoff control information based on the determination result that the circuit breaker 20 is forced.

The main protection calculation unit 116 compares, for example, the measured value of each state information with the threshold value set in advance for each state information. The main protection calculation unit 116 generates forced cutoff control information when the value indicated by the state information exceeds the threshold value. The main protection calculation unit 116 outputs the generated forced cutoff control information to the main control circuit 120.

The main key synthesis code generation circuit 118 performs arithmetic processing using the synthesis function code. The synthetic function code used by the main key synthetic code generation circuit 118 for arithmetic processing is, for example, a synthetic function code for performing a known logical operation. The logical operation used in the composite function code may be any operation, for example, an operation including an AND operation and an inversion operation.

The main key synthesis code generation circuit 118 performs a logical operation using the synthesis function code on the main key code (an example of the first key code) output by the main control circuit 120, and performs a logical operation on the main key synthesis code (first key synthesis code). Generate an example of key synthesis code). The main key synthesis code generation circuit 118 outputs the generated main key synthesis code to the main key synthesis code decoding / verification circuit 126 of the main control circuit 120.

The main key synthesis code generation circuit 118 may output the main key synthesis code at any timing. The main key synthesis code generation circuit 118 may generate a main key synthesis code each time a main key code is input and output the main key synthesis code to the main control circuit 120, for example. The main key synthesis code generation circuit 118 may generate a main key synthesis code when outputting the forced cutoff control information to the main control circuit 120, add it to the forced cutoff control information, and output the forced cutoff control information to the main control circuit 120. ..

The energization control circuit 122 in the main control circuit 120 controls the circuit breaker 20 based on the determination result in the main control circuit 120 based on the interruption / energization control information output by the main control calculation unit 114. The energization control circuit 122 controls the circuit breaker 20 based on the determination result in the main control circuit 120 based on the forced cutoff control information output by the main protection calculation unit 116.

When the main control calculation unit 114 outputs the cutoff control information, the energization control circuit 122 outputs the cutoff information to the first switch 22 and controls the circuit breaker 20 to be in the cutoff state. When the main control calculation unit 114 outputs the energization control information, the energization control circuit 122 outputs the energization information to the first switch 22 of the circuit breaker 20 and controls the circuit breaker 20 to be in the energized state. When the forced cutoff control information is output by the main protection calculation unit 116, the energization control circuit 122 sends the forced cutoff information to the first switch 22 on condition that the main key code and the main key synthesis code, which will be described later, correspond to each other. The output is output, and the circuit breaker 20 is controlled so as to be forcibly shut off.

The main key code generation circuit 124 generates a random number every predetermined cycle, for example, every 30 seconds to generate the main key code. The predetermined period for generating the random number may be a time other than 30 seconds. The form and composition of the main key code are not limited, and the main key code may be other than one that generates random numbers at predetermined intervals. The more complicated the key code, the stronger the security. The synthetic function code in the main key synthesis code generation circuit 118 may be matched to the main key code generated by the main key code generation circuit 124, and may be other than the synthetic function code.

The main key code generation circuit 124 outputs the generated main key code to the main key synthesis code generation circuit 118 and the main key synthesis code decoding / verification circuit 126. The main key code is used as the main key synthesis code in the main key synthesis code generation circuit 118.

The main key synthesis code decoding / verification circuit 126 decodes the main key synthesis code output by the main key synthesis code generation circuit 118 and collates it with the main key code generated by the main key code generation circuit 124. The main key synthesis code decoding / verification circuit 126 includes the same synthesis function code as the synthesis function code included in the main key synthesis code generation circuit 118.

The main key synthesis code decoding / verification circuit 126 performs a logical operation using the synthesis function code on the main key code output by the main key code generation circuit 124 to generate a verification code. The main key synthesis code decoding / collation circuit 126 decodes the main key synthesis code output by the main protection / control calculation means 110 and collates it with the calculated verification code. The main key synthesis code decoding / verification circuit 126 collates the result obtained by performing a logical operation using the synthetic function code included in the main key synthesis code generation circuit 118 with respect to the main key code generated by the main key code generation circuit 124. It may be stored in advance as a code.

When the forced cutoff control information is output, the main control circuit 120 determines whether or not the main key code and the main key synthesis code correspond to each other by the matching in the main key synthesis code decoding / verification circuit 126. Correspondence between the main key code and the main key synthesis code means that the main key synthesis code and the verification code match.

It is assumed that the main control circuit 120 determines in the main key synthesis code decoding / verification circuit 126 that the main key code and the main key synthesis code correspond to each other. In this case, the main control circuit 120 forcibly controls the circuit breaker 20 to the cutoff state in the energization control circuit 122. When the circuit breaker 20 is forcibly controlled to the circuit breaker state, the main control circuit 120 outputs the forced circuit breaker control information to the circuit breaker 20.

It is assumed that the main control circuit 120 determines in the main key synthesis code decoding / verification circuit 126 that the main key code and the main key synthesis code do not correspond to each other. In this case, the main control circuit 120 does not control the circuit breaker 20 to be forcibly cut off in the energization control circuit 122. Therefore, the main control circuit 120 does not output the forced cutoff control information for forcibly controlling the circuit breaker 20 to the cutoff state to the circuit breaker 20.

The fail-safe protection / control calculation means 210 in the fail-safe processing unit 200 includes, for example, an AD conversion circuit 212, a fail-safe control calculation unit 214, a fail-safe protection calculation unit 216, and a fail-safe key synthesis code generation circuit (second). An example of a key synthesis code generation circuit) 218.

The fail-safe control circuit 220 includes an energization control circuit 222, a fail-safe key code generation circuit (an example of a second key code generation circuit) 224, and a fail-safe key synthesis code decoding / verification circuit (an example of a second decoding / verification circuit). ) 226 and. The AD conversion circuit 212, the fail-safe control calculation unit 214, the fail-safe protection calculation unit 216, and the energization control circuit 222 in the fail-safe processing unit 200 are the AD conversion circuit 112, the main control calculation unit 114, and the main protection in the main processing unit 100. It has the same functions as the arithmetic unit 116 and the energization control circuit 122.

The fail-safe key synthesis code generation circuit 218 of the fail-safe protection / control calculation means 210 uses a composite function code for the fail-safe key code (an example of the second key code) output by the fail-safe control circuit 220. Performs a logical operation to generate a fail-safe key synthesis code (an example of a second key synthesis code). The fail-safe key synthesis code generation circuit 218 outputs the generated fail-safe key synthesis code to the fail-safe key synthesis code decoding / verification circuit 226 of the fail-safe control circuit 220.

The fail-safe key synthesis code decoding / verification circuit 226 performs a logical operation using the synthetic function code on the fail-safe key code output by the fail-safe key code generation circuit 224 to generate a verification code. The fail-safe key synthesis code decoding / verification circuit 226 decodes the main key synthesis code output by the fail-safe protection / control calculation means 210 and collates it with the calculated verification code.

The fail-safe key code generated by the fail-safe key code generation circuit 224 is a key code different from the main key code generated by the main key code generation circuit 124. The fail-safe key code may be the same key code as the main key code. The synthetic function code included in the fail-safe key synthetic code generation circuit 218 is a synthetic function code different from the synthetic function code included in the main key synthetic code generation circuit 118. The same synthetic function code as the synthetic function code included in the main key synthetic code generation circuit 118 may be used.

The verification code used in the fail-safe key synthesis code decoding / verification circuit 226 may be a fail-safe key code output by the fail-safe key code generation circuit 224 obtained by performing a logical operation using a synthetic function code. The verification code used in the fail-safe key synthesis code decoding / verification circuit 226 is a logic using the fail-safe key code generated by the fail-safe key code generation circuit 224 and the synthesis function code provided in the fail-safe key synthesis code generation circuit 218. It may be stored in advance as a result obtained by performing the calculation.

The energization control circuit 222 in the fail-safe control circuit 220 controls the circuit breaker 20 based on the interruption / energization control information output by the fail-safe control calculation unit 214. When the fail-safe control calculation unit 214 outputs the cutoff control information, the energization control circuit 222 outputs the cutoff information to the second switch 24 of the circuit breaker 20 and controls the circuit breaker 20 to be in the cutoff state. .. The energization control circuit 222 outputs the energization information to the second switch 24 of the circuit breaker 20 when the fail-safe control calculation unit 214 outputs the energization control information, and controls the circuit breaker 20 to be in the energized state. .. The energization control circuit 222 is the second switch 24 of the circuit breaker 20, provided that the fail-safe key code and the fail-safe key synthesis code correspond to each other when the forced cutoff control information is output by the fail-safe protection calculation unit 216. The forced shutoff information is output to the circuit breaker 20 to control the circuit breaker 20 to be forced into the shutoff state.

The circuit breaker 20 is controlled to an energized state or a cutoff state based on the cutoff information, the energization information, and the forced cutoff information output by the main processing unit 100 and the fail-safe processing unit 200. The first switch 22 and the second switch 24 are directly connected. The first switch 22 sets the voltage generation source and the second switch 24 in a connected state or an open state. Information output by the main processing unit 100 is input to the control terminal of the first switch 22. The first switch 22 is opened when the cutoff information is output by the main control circuit 120, and is connected when the energization information is output. The first switch 22 is forcibly put into a connected state when the forced cutoff information is output by the main control circuit 120.

The second switch 24 sets the connection state or the open state between the first switch 22 and the power system. The cutoff information, energization information, and forced cutoff information output by the fail-safe control circuit 220 are input to the control terminal of the second switch 24. The second switch 24 is in the open state when the cutoff information is output by the fail-safe control circuit 220, and is in the connected state when the energization information is output. The second switch 24 is forcibly put into the connected state when the forced cutoff control information is output by the fail-safe control circuit 220.

Therefore, when the forced cutoff information is output by the main processing unit 100 and the fail-safe processing unit 200, the first switch 22 and the second switch 24 are both connected. The circuit breaker 20 is forcibly cut off when both the first switch 22 and the second switch 24 are connected.

In the protection relay device 10 of the first embodiment, a key code and a key synthesis code are input / output between the main control circuit 120 and the main protection / control calculation means 110 when making a determination for forcibly shutting off the circuit breaker 20. do. Similarly, in the protection relay device 10, the key code and the key synthesis code are input / output between the fail-safe control circuit 220 and the fail-safe protection / control calculation means 210. The main control circuit 120 blocks on the condition that the verification code generated by the key code and the key synthesis code output by the main protection / control calculation means 110 match and the key code and the key synthesis code correspond to each other. Control is performed to forcibly shut off the vessel 20. Similarly, in the fail-safe control circuit 220, the verification code generated by the key code and the key synthesis code output by the fail-safe protection / control calculation means 210 match, and the key code and the key synthesis code correspond to each other. The condition is that control is performed to forcibly shut off the circuit breaker 20.

Therefore, for example, even if there is a malfunction due to a transient defect in the component of the system in the protection relay device 10, by looking at the correspondence between the key code and the key synthesis code, the malfunction due to the component of the system It is possible to suppress a malfunction (erroneous cutoff) of the circuit breaker 20. Therefore, when controlling the circuit breaker 20, the credibility of the control command information intended by the control for forcibly shutting off the circuit breaker 20 can be enhanced. Therefore, since the reliability of the protective relay device 10 can be improved, the reliability can be sufficiently maintained even if each electronic component is mounted on one substrate, for example. As a result, the structure can be simplified without compromising reliability.

The protection relay device 10 of the first embodiment generates a random number at a predetermined cycle in the main key code generation circuit 124 to generate the main key code. Therefore, since the key code is changed at predetermined intervals, unauthorized duplication of the key code outside the protective relay device 10 can be suppressed. Therefore, the reliability of the protective relay device 10 can be further improved.

The protection relay device 10 of the first embodiment can also be used as a security incident countermeasure by determining the correspondence between the key code and the key synthesis code. For example, even if an arithmetic element in the protective power transfer device 10, for example, a CPU is attacked and affected by a security threat, it is affected by determining the correspondence between the key code and the key synthesis code. The control of the circuit breaker 20 in the case can be stopped. Therefore, the soundness of the protective relay device 10 can be confirmed, and the reliability of the protective relay device 10 can be improved in combination with the redundancy. The protective relay 10 of the first embodiment can standardize the hardware, which is a general merit of the digital relay. The protective relay device 10 of the first embodiment can easily add an automatic inspection / automatic monitoring function.

<< Second Embodiment >>
Next, the second embodiment will be described. FIG. 2 is a functional block configuration diagram of the protective relay device 10 of the second embodiment. The protective relay device 10 of the second embodiment has the same configuration as the protective relay device 10 of the first embodiment. In the protection relay device 10 of the second embodiment, the main key code generation circuit 124 generates a main key code having a bit string of a plurality of bits, for example, 16 bits, as the main key code. A spare bit is provided in the main key code. Similar spare bits are provided in each code described below.

The main key synthesis code generation circuit 118 includes a synthesis function code for the number of bit strings included in the main key code. The main key synthesis code generation circuit 118 uses a synthesis function code based on the main key code output by the main key code generation circuit 124, and has the same number of bit strings as the number of bit strings, in this case, a main key synthesis having a 16-bit bit string. Generate code.

According to the protective relay device 10 of the second embodiment, the same operation and effect as the protective relay device 10 of the first embodiment can be obtained. Further, the protection relay device 10 of the second embodiment uses a main key code having a plurality of bits, for example, 16 bits. Therefore, the protective relay device 10 can increase the security strength when controlling the circuit breaker 20.

<< Third Embodiment >>
Next, the third embodiment will be described. FIG. 3 is a functional block configuration diagram of the protective relay device 10 of the third embodiment. The protective relay device 10 of the third embodiment has the same configuration as the protective relay device 10 of the first embodiment. The AD conversion circuit 112 of the protection relay device 10 of the third embodiment includes a composite function code. The synthetic function code included in the AD conversion circuit 112 is a synthetic function code different from the synthetic function code included in the main key synthetic code generation circuit 118.

Similar to the second embodiment, the main key code generation circuit 124 in the main control circuit 120 generates a main key code including a bit string of a plurality of bits and outputs the main key code to the main protection / control calculation means 110. The synthetic function code included in the main key synthetic code generation circuit 118 is a synthetic function code for performing a logical operation on all the bits of the main key. The synthetic function code included in the AD conversion circuit 112 is a synthetic function code for performing a logical operation on some bits of the main key.

The AD conversion circuit 112 generates a main key synthesis code (hereinafter, AD main key synthesis code) obtained by a logical operation using a synthesis function code. The AD main key synthesis code is generated, for example, by performing a logical operation using a synthetic function code for a specific part of the main key code. The main protection / control calculation means 110 outputs the AD main key synthesis code generated by the AD conversion circuit 112 to the main control circuit 120.

The main key synthesis code decoding / verification circuit 126 in the main control circuit 120 includes a verification code for collating the main key synthesis code, and a part of the main key code that generates an AD main key synthesis code (hereinafter, AD). A verification code for collating the AD main key synthesis code is generated using the main key code). This collation code can be obtained, for example, by performing a logical operation on a part of the main key code used when generating the AD main key synthesis code by using the synthesis function code provided in the AD conversion circuit 112.

When the forced cutoff control information is output, the main control circuit 120 determines whether or not the main key code and the main key synthesis code correspond to each other by the matching in the main key synthesis code decoding / verification circuit 126. At this time, the main control circuit 120 determines whether or not the AD main key code and the AD main key synthesis code correspond to each other by the collation in the main key synthesis code decoding / verification circuit 126.

When the main control circuit 120 determines that the main key code and the main key synthesis code, and the AD main key code and the AD main key synthesis code all correspond to each other, the main key code and the main key synthesis code change in the first embodiment. Perform the same processing as when it is determined that it corresponds. When it is determined that the main key code and the main key synthesis code, and the AD main key code and the AD main key synthesis code do not correspond to each other, the main control circuit 120 determines that the main key code and the main key synthesis code do not correspond to each other, or the main key code and the main key code in the first embodiment. Performs the same processing as when it is determined that the key synthesis code does not correspond.

Similar to the main processing unit 100, the fail-safe processing unit 200 is a fail-safe key synthesis code obtained by performing a logical operation using a synthetic function code in the AD conversion circuit 212 (hereinafter, AD fail-safe key synthesis). Code) is generated. The fail-safe processing unit 200 generates a fail-safe key synthesis code in the fail-safe key synthesis code generation circuit 218 by using a part of the fail-safe key code (hereinafter, AD fail-safe key code).

When the forced cutoff control information is output, the fail-safe processing unit 200 determines whether or not the fail-safe key code and the fail-safe key synthesis code correspond to each other by the verification in the fail-safe key synthesis code decoding / verification circuit 226. do. At this time, the fail-safe processing unit 200 determines whether or not the AD fail-safe key code and the AD fail-safe key synthesis code correspond to each other by the verification in the fail-safe key synthesis code decoding / verification circuit 226.

When the fail-safe processing unit 200 determines that the fail-safe key code and the fail-safe key synthesis code correspond to each other, and the AD fail-safe key code and the AD fail-safe key synthesis code correspond to each other, the fail-safe key code in the first embodiment Performs the same processing as when it is determined that the fail-safe key synthesis code corresponds to. In the first embodiment, when the fail-safe processing unit 200 determines that the fail-safe key code and the fail-safe key synthesis code, and the AD fail-safe key code and the AD fail-safe key synthesis code do not correspond to each other or both. Performs the same processing as when it is determined that the fail-safe key code and the fail-safe key synthesis code do not correspond.

According to the protective relay device 10 of the third embodiment, the same operation and effect as the protective relay device 10 of the first embodiment can be obtained. Further, the protection relay device 10 of the third embodiment sets the AD main key synthesis code and the AD fail-safe key synthesis code in the AD conversion circuit 112 of the main processing unit 100 and the AD conversion circuit 212 of the fail-safe processing unit 200, respectively. Generate. In the main key synthesis code decoding / verification circuit 126 and the fail-safe key synthesis code decoding / verification circuit 226, the AD main key synthesis code and the AD fail-safe key synthesis code correspond to the AD main key code and the AD fail-safe key code, respectively. It is determined whether or not the circuit breaker 20 is controlled. Therefore, it is possible to suppress a malfunction (erroneous cutoff) of the circuit breaker 20 due to a failure of the AD conversion circuits 112 and 212 in the main processing unit 100 and the fail-safe processing unit 200.

<< Fourth Embodiment >>
Next, the fourth embodiment will be described. FIG. 4 is a functional block configuration diagram of the protective relay device 10 according to the fourth embodiment. The protection relay device 10 of the fourth embodiment has an analog filter circuit (Analog filter circuit, hereinafter referred to as AF circuit) 119 in the main protection / control calculation means 110 as compared with the protection relay device 10 of the third embodiment. The point to prepare is different. Further, it is different in that the AF circuit 219 of the fail-safe protection / control calculation means 210 is provided. Other than that, it has the same configuration as the protective relay device 10 of the third embodiment. The AF circuits 119 and 219 may also be provided in the first to third embodiments. In this case, the AF circuits 119 and 219 do not have to include the composite function code described later.

The AF circuit 119 filters the analog information input by the power system outside the protection relay device 10, and removes a predetermined component included in the analog information, for example, a high frequency component. The AF circuit 119 generates verification analog information in which the main key code output by the main control circuit 120 is superimposed on the analog information as a low frequency component. The AF circuit 119 passes the verification analog information and outputs it to the AD conversion circuit 112. The AF circuit 219 in the fail-safe processing unit 200 performs the same processing as the AF circuit 119 in the main processing unit 100.

The AF circuit 119 includes a composite function code. The synthetic function code included in the AF circuit 119 is a synthetic function code different from the synthetic function code included in the AD conversion circuit 112 and the main key synthetic code generation circuit 118. The AF circuit 219 includes a composite function code. The synthetic function code included in the AF circuit 219 is a synthetic function code different from the synthetic function code included in the AD conversion circuit 212 and the fail-safe key synthetic code generation circuit 218.

The AD conversion circuit 112 generates an AD main key synthesis code in the same manner as in the third embodiment. The AD conversion circuit 112 writes the digital information obtained by converting the main key code superimposed on the verification analog information to the spare bit in the AD main key synthesis code. The AD conversion circuit 112 outputs the code as digital information (hereinafter referred to as AF main key synthesis code) obtained by converting the main key code superimposed on the verification analog information to the main key synthesis code generation circuit 118 as it is. May be good. In this case, the main key synthesis code generation circuit 118 writes the AF main key synthesis code to the spare bits in the main key synthesis code. The main protection / control calculation means 110 outputs the AD main key synthesis code generated by the AD conversion circuit 112 to the main control circuit 120.

The main key synthesis code decoding / verification circuit (example of the verification unit) 126 in the main control circuit 120 collates the AF main key synthesis code in addition to the verification code for collating the main key synthesis code and the AD main key synthesis code. Generate a verification code for. This collation code can be obtained, for example, by performing a logical operation on a part of the main key code used when generating the AF main key synthesis code by using the synthesis function code included in the AD conversion circuit 112.

When the forced cutoff control information is output, the main processing unit 100 determines the main key code and the main key synthesis code, and the AD main key code and the AD main key code by collation in the main key synthesis code decoding / verification circuit 126. It is determined whether or not each of them corresponds. At this time, the main processing unit 100 determines whether or not the AF main key code and the AF main key synthesis code correspond to each other by the verification in the main key synthesis code decoding / verification circuit 126. The main key synthesis code decoding / verification circuit 126 verifies the operation of the AF circuit 119 by determining whether or not the AF main key code AF main key synthesis code corresponds. When the AF main key code AF main key synthesis code corresponds, the main key synthesis code decoding / verification circuit 126 determines that the operation of the AF circuit 119 is normal, and the AF main key code AF main key synthesis code does not correspond. In addition, it is determined that the operation of the AF circuit 119 is abnormal.

When the main processing unit 100 determines that the main key code and the main key synthesis code, and the AD main key code and the AD main key synthesis code correspond to both the AF main key code and the AF main key synthesis code, the first embodiment In, the same processing as when it is determined that the main key code and the main key synthesis code correspond to each other is performed. When the main processing unit 100 determines that at least one set of the main key code and the main key synthesis code, the AD main key code and the AD main key synthesis code, and the AF main key code and the AF main key synthesis code does not correspond to each other, In the first embodiment, the same processing as when it is determined that the main key code and the main key synthesis code do not correspond is performed.

The fail-safe processing unit 200 generates an AD main key synthesis code in the AD conversion circuit 212 in the same manner as in the third embodiment, similarly to the main processing unit 100. The AD conversion circuit 212 writes the digital information obtained by converting the fail-safe key code superimposed on the analog information into the spare bit in the AD main key synthesis code. The AD conversion circuit 212 outputs the code as digital information (hereinafter referred to as AF fail-safe key synthesis code) obtained by converting the fail-safe key code superimposed on the analog information to the fail-safe key synthesis code generation circuit 218 as it is. You may. In this case, the fail-safe key synthesis code generation circuit 218 writes the AF fail-safe key synthesis code in the spare bits in the fail-safe key synthesis code. The fail-safe protection / control calculation means 210 outputs the AD fail-safe key synthesis code generated by the AD conversion circuit 212 to the fail-safe control circuit 220.

The fail-safe key synthesis code decoding / verification circuit 226 in the fail-safe control circuit 220 collates the fail-safe key synthesis code and the AD fail-safe key synthesis code, as well as the AF fail-safe key synthesis code. Generate a verification code for. This collation code can be obtained, for example, by performing a logical operation on a part of the fail-safe key code used when generating the AF fail-safe key synthesis code by using the synthetic function code provided in the AD conversion circuit 212.

When the forced cutoff control information is output, the fail-safe processing unit 200 determines whether or not the fail-safe key code and the fail-safe key synthesis code correspond to each other by the verification in the fail-safe key synthesis code decoding / verification circuit 226. do. At this time, the fail-safe processing unit 200 determines whether or not the AF fail-safe key code and the AF fail-safe key synthesis code correspond to each other by collation in the fail-safe key synthesis code decoding / verification circuit 226. The fail-safe key synthesis code decoding / verification circuit 226 determines that the operation of the AF circuit 219 is normal when the AF main key code AF main key synthesis code corresponds, and the AF main key code AF main key synthesis code does not correspond. In this case, the operation of the AF circuit 219 is determined to be abnormal.

The fail-safe processing unit 200 has determined that the fail-safe key code and the fail-safe key synthesis code, and the AD fail-safe key code and the AD fail-safe key synthesis code correspond to both the AF fail-safe key code and the AF fail-safe key synthesis code. In this case, the same processing as in the case where it is determined that the fail-safe key code and the fail-safe key synthesis code correspond to each other in the first embodiment is performed. The fail-safe processing unit 200 supports at least one set of a fail-safe key code and a fail-safe key synthesis code, an AD fail-safe key code and an AD fail-safe key synthesis code, and an AF fail-safe key code and an AF fail-safe key synthesis code. When it is determined not to be performed, the same processing as when it is determined that the fail-safe key code and the fail-safe key synthesis code do not correspond in the first embodiment is performed.

According to the protective relay device 10 of the fourth embodiment, the same operation and effect as the protective relay device 10 of the first embodiment can be obtained. Further, the protection relay device 10 of the fourth embodiment generates an AF main key synthesis code and an AF fail-safe key synthesis code in the AF circuit 119 of the main processing unit 100 and the AF circuit 219 of the fail-safe processing unit 200, respectively. .. In the main key synthesis code decoding / verification circuit 126 and the fail-safe key synthesis code decoding / verification circuit 226, the AF main key synthesis code and the AF fail-safe key synthesis code correspond to the AF main key code and the AF fail-safe key code, respectively. It is determined whether or not the circuit breaker 20 is controlled. Therefore, it is possible to suppress a malfunction (erroneous cutoff) of the circuit breaker 20 due to a failure of the AF circuits 119 and 219 in the main processing unit 100 and the fail-safe processing unit 200.

In each of the above embodiments, the AD conversion circuits 112 and 212 are provided in the main processing unit 100 and the fail-safe processing unit 200, respectively, but other embodiments may be used. For example, one AD conversion circuit that outputs digital information to each of the main processing unit 100 and the fail-safe processing unit 200 may be provided outside the main processing unit 100 and the fail-safe processing unit 200. In the fourth embodiment, the AF circuits 119 and 219 are provided in the main processing unit 100 and the fail-safe processing unit 200, respectively, but other embodiments may be used. For example, one AF circuit that outputs analog information to each of the main processing unit 100 and the fail-safe processing unit 200 may be provided outside the main processing unit 100 and the fail-safe processing unit 200. When one AD conversion circuit is provided outside the main processing unit 100 and the fail-safe processing unit 200, an AF circuit that outputs analog information may be provided in the AD conversion circuit.

≪Hardware configuration≫
Next, the hardware configuration of the protective relay device 10 in each embodiment will be described. In the following description, each chip component mounted on the substrate does not specify a relative positional relationship, and each chip component can be arranged at an arbitrary position on the substrate.

<< First configuration example >>
FIG. 5 is a diagram showing a first configuration example of the hardware of the protective relay device 10. As shown in FIG. 5, in the first configuration example, the protective relay device 10 includes a substrate 500. The substrate 500 includes a first AF circuit 510, a first AD conversion circuit 520, a first CPU (Central Processing Unit) 530, a first FPGA (field-programmable gate array) 540, a second AF circuit 550, a second AD conversion circuit 560, a second CPU 570, and The second FPGA 580 is mounted.

The first AF circuit 510 functions as the AF circuit 119 of the main processing unit 100. The first AD conversion circuit 520 functions as the AD conversion circuit 112 of the main processing unit 100. The first CPU 530 functions as the main protection / control calculation means 110. The first FPGA 540 functions as the main control circuit 120.

The second AF circuit 550 functions as the AF circuit 219 of the fail-safe processing unit 200. The second AD conversion circuit 560 functions as the AD conversion circuit 212 of the fail-safe processing unit 200. The second CPU 570 functions as a fail-safe protection / control calculation means 210. The second FPGA 580 functions as a fail-safe control circuit 220.

As described above, in the first configuration example, the two CPUs and the FPGA are used as the main protection / control calculation means 110, the main control circuit 120, the fail-safe protection / control calculation means 210, and the fail-safe control circuit 220, respectively. I'm letting you. Other parts may be used as parts such as chip parts that fulfill their respective functions. For example, as a chip component used for the main protection / control calculation means 110 and the fail-safe protection / control calculation means 210, a component other than the CPU, for example, an FPGA may be used. For example, as a chip component used in the main control circuit 120 or the fail-safe control circuit 220, a component other than the FPGA, for example, a CPU may be used. In the following other configuration examples, suitable chip components may be appropriately used, such as using an FPGA instead of the CPU or using a CPU instead of the FPGA.

<< Second configuration example >>
FIG. 6 is a diagram showing a second configuration example of the hardware of the protective relay device 10. As shown in FIG. 6, in the second configuration example, the protective relay device 10 includes a substrate 600. The first AF circuit 610, the first AD conversion circuit 620, the common CPU (an example of the first chip component) 630, the first FPGA 640, the second AF circuit 650, the second AD conversion circuit 660, and the second FPGA 670 are mounted on the substrate 600.

The first AF circuit 610 functions as the AF circuit 119 of the main processing unit 100. The first AD conversion circuit 620 functions as the AD conversion circuit 112 of the main processing unit 100. The common CPU 630 functions as a main protection / control calculation means 110 and a fail-safe protection / control calculation means 210. The first FPGA 640 functions as the main control circuit 120.

The second AF circuit 650 functions as the AF circuit 219 of the fail-safe processing unit 200. The second AD conversion circuit 660 functions as the AD conversion circuit 212 of the fail-safe processing unit 200. The second FPGA 680 functions as a fail-safe control circuit 220.

Regarding the input / output of information between the common CPU 630 and the first FPGA 640 and the second FPGA, two signal lines are provided between the common CPU 630 and the first FPGA 640. Two signal lines are provided between the common CPU 630 and the second FPGA 680.

In the second configuration example, the common CPU 630 is used as a chip component that functions as the main protection / control calculation means 110 and the fail-safe protection / control calculation means 210. For this reason, even with a single board (calculation board) on which chip components such as a CPU are mounted, system redundancy is achieved while ensuring the soundness of functional calculations as the main processing unit 100 and the fail-safe processing unit 200. Can be planned. Therefore, it is possible to contribute to the simplification of the structure by reducing the number of substrates and reducing the number of chip parts.

Two signal lines are provided between the common CPU 630 and the first FPGA 640 and between the common CPU 630 and the second FPGA 680, respectively. Therefore, the main key code can be output from the first FPGA 640, the main key synthesis code can be output from the common CPU 630, the fail-safe key code can be output from the second FPGA 68, and the fail-safe key synthesis code can be output from the common CPU 630 at the same time. Therefore, time loss when inputting / outputting information can be suppressed.

<< Third configuration example >>
FIG. 7 is a diagram showing a third configuration example of the hardware of the protective relay device 10. As shown in FIG. 6, in the third configuration example, the protective relay device 10 includes a substrate 700. A first AF circuit 710, a first AD conversion circuit 720, a common CPU 730, a common FPGA (an example of a second chip component) 740, a second AF circuit 750, and a second AD conversion circuit 760 are mounted on the substrate 700.

The first AF circuit 710 functions as the AF circuit 119 of the main processing unit 100. The first AD conversion circuit 720 functions as the AD conversion circuit 112 of the main processing unit 100. The common CPU 730 functions as a main protection / control calculation means 110 and a fail-safe protection / control calculation means 210. The common FPGA 740 functions as a main control circuit 120 and a fail-safe control circuit 220.

The second AF circuit 750 functions as the AF circuit 219 of the fail-safe processing unit 200. The second AD conversion circuit 760 functions as the AD conversion circuit 212 of the fail-safe processing unit 200. Regarding the input / output of information between the common CPU 730 and the common FPGA 740, four signal lines are provided between the common CPU 630 and the common FPGA 740.

In the third configuration example, the common CPU 730 is used as a chip component that functions as the main protection / control calculation means 110 and the fail-safe protection / control calculation means 210. Further, a common FPGA is used as a chip component that functions as a main control circuit 120 and a fail-safe control circuit 220. Therefore, even with a single board (calculation board) on which chip components such as a CPU and FPGA are mounted, system redundancy is ensured while ensuring the soundness of functional calculations as the main processing unit 100 and the fail-safe processing unit 200. Can be achieved. Therefore, it is possible to contribute to the simplification of the structure by reducing the number of substrates and reducing the number of chip parts.

Four signal lines are provided between the common CPU 730 and the common FPGA 740. Therefore, the main key code and the fail-safe key code can be output from the common FPGA 740, and the main key synthesis code and the fail-safe key synthesis code can be output from the common CPU 730 at the same time. Therefore, time loss when inputting / outputting information can be suppressed.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and the equivalent scope thereof.

10 ... protection relay device, 20 ... circuit breaker, 100 ... main processing unit, 110 ... main protection / control calculation means, 112 ... AD conversion circuit, 114 ... main control calculation unit, 116 ... main protection calculation unit, 118 ... main Key synthesis code generation circuit, 119 ... AF circuit, 120 ... Main control circuit, 122 ... Energization control circuit, 124 ... Main key code generation circuit, 126 ... Main key synthesis code decoding / verification circuit, 200 ... Fail-safe processing unit, 210 ... Fail-safe protection / control calculation means, 212 ... AD conversion circuit, 214 ... Fail-safe control calculation unit, 216 ... Fail-safe protection calculation unit, 218 ... Fail-safe key synthesis code generation circuit, 219 ... AF circuit, 220 ... Fail-safe Control circuit, 222 ... Energization control circuit, 224 ... Fail-safe key code generation circuit, 226 ... Fail-safe key synthesis code decoding / verification circuit, 500, 600, 700 ... Board, 510, 610, 710 ... First AF circuit, 520, 620, 720 ... 1st AD conversion circuit, 530 ... 1st CPU, 540, 640 ... 1st FPGA, 550, 650 ... 2nd AF circuit, 560, 660 ... 2nd AD conversion circuit, 570 ... 2nd CPU, 580, 680 ... 2nd FPGA, 630, 730 ... common CPU, 740 ... common FPGA

Claims (7)

The first protection control calculation means that makes a judgment based on the information obtained by converting analog information indicating the state of the power system into digital information, and
Based on the determination result of the first protection control calculation means, the first control circuit for controlling the circuit breaker provided in the power system and the first control circuit.
A second protection control calculation means that makes a determination based on information obtained by converting analog information indicating the state of the power system into digital information, and
A second control circuit for controlling a circuit breaker provided in the power system based on a determination result of the second protection control calculation means is provided.
The first control circuit has a first key code generation circuit that generates a first key code.
The first protection control calculation means has a first key synthesis code generation circuit that generates a first key synthesis code based on the first key code.
The second control circuit has a second key code generation circuit that generates a second key code.
The second protection control calculation means has a second key synthesis code generation circuit that generates a second key synthesis code based on the second key code.
The first control circuit has a first decoding / collation circuit that determines whether or not the first key synthesis code and the first key code correspond to each other, and the first key synthesis code and the first key code correspond to each other. Control the circuit breaker provided in the power system on the condition that
The second control circuit has a second decoding / collation circuit that determines whether or not the second key synthesis code and the second key code correspond to each other, and the second key synthesis code and the second key code correspond to each other. Control the circuit breaker provided in the power system on condition that
Protective relay device. The first key code generation circuit and the second key code generation circuit generate random numbers at predetermined intervals, respectively, to generate a first key code and a second key code.
The protective relay device according to claim 1. The first key code and the second key code include a bit string of a plurality of bits.
The first key synthesis code generation circuit and the second key synthesis code generation circuit obtain the result of performing a known logical operation on each bit in the bit string of the first key code and the second key code. Generated as a key synthesis code and the second key synthesis code, respectively.
The first decoding / collation circuit performs verification based on the logical operation and determines whether or not the first key synthesis code and the first key code correspond to each other.
The second decoding / collation circuit performs verification based on the logical operation and determines whether or not the second key synthesis code and the second key code correspond to each other.
The protective relay device according to claim 1. The first protection control calculation means further includes a first AD conversion circuit that converts the analog information into the digital information.
A part of the first key synthesis code generation circuit is provided in the first AD conversion circuit.
The protective relay device according to claim 1. An analog filter circuit that filters analog information input from the outside,
A verification unit that generates verification analog information based on the first key synthesis code and verifies the operation of the analog filter circuit based on the verification analog information that has passed through the analog filter circuit is further provided.
The protective relay device according to claim 1. The first protection control calculation means and the second protection control calculation means are provided on a first chip component mounted on a substrate.
The protective relay device according to claim 1. The first control circuit and the second control circuit are provided on a second chip component mounted on the substrate and different from the first chip component.
The protective relay device according to claim 6.

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