JP6939932B1 - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of facilitating control for obtaining an output close to a desired AC waveform. A semiconductor device 11a includes a circuit pattern 16a, P terminals 19a, N terminals 19d, O terminals 19b, 19c, and first transistor chips 22a to 22d and second transistor chips 22e to 22h. The circuit pattern 16a electrically connects to the band-shaped first region 51a electrically connected to the P terminal 19a, the band-shaped second region 52a electrically connected to the N terminal 19d, and the O terminals 19b and 19c. Includes a third region 53a to be connected. The third region 53a includes a strip-shaped first branch portion 61a, a strip-shaped second branch portion 62a, and a connecting portion 63a. The first transistor chips 22a to 22d are electrically connected to the first region 51a and electrically connected to the first branch portion 61a. The second transistor chips 22e to 22h are electrically connected to the second branch portion 62a and electrically connected to the second region 52a. [Selection diagram] Fig. 1

Description

The present disclosure relates to semiconductor devices.

A semiconductor device having a P terminal, an N terminal, and an O terminal and having a plurality of semiconductor chips mounted on a circuit pattern is disclosed (see, for example, Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 2015-154079 Japanese Unexamined Patent Publication No. 2017-220627

When the semiconductor device disclosed in Patent Documents 1 and 2 is operated as an inverter, for example, the electrical connection between the P terminal and the O terminal is turned on, and the electrical connection between the O terminal and the N terminal is turned on. The first state in which is turned off, and the second state in which the electrical connection between the P terminal and the O terminal is turned off and the electrical connection between the O terminal and the N terminal is turned on. The state and the state are repeated alternately at high speed. In this way, an output close to the desired AC waveform is obtained. It is required to facilitate control for obtaining an output close to the desired AC waveform.

Therefore, one of the purposes is to provide a semiconductor device capable of facilitating control for obtaining an output close to a desired AC waveform.

A semiconductor device according to the present disclosure is mounted on an insulating substrate, a circuit pattern arranged on the substrate, P terminals, N terminals and O terminals electrically connected to the circuit pattern, and a circuit pattern. It includes a first transistor chip and a second transistor chip. The circuit pattern is electrically connected to the P terminal and extends along the first direction in a band-shaped first region, and is electrically connected to the N terminal in the second direction which is the width direction of the first region. A band-shaped second region extending along the first direction and electrically connected to the O terminal, which are arranged at intervals from the first region, are arranged at intervals from each of the first region and the second region. A third region is included. The third region is arranged with a band-shaped first branch extending along the first direction and a band-shaped second branch extending along the first direction at intervals from the first branch in the second direction. Includes a bifurcation and a connection that extends along a second direction and connects one end of the first bifurcation to one end of the second bifurcation. The first transistor chip is mounted in the first region and electrically connected to the first region, and is electrically connected to the first branch portion by the first wiring. The second transistor chip is mounted on the second branch portion and electrically connected to the second branch portion, and is electrically connected to the second region by the second wiring.

According to the above-mentioned semiconductor device, control for obtaining an output close to a desired AC waveform can be facilitated.

FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate. FIG. 2 is a schematic plan view showing only the substrate and the circuit pattern included in the semiconductor device shown in FIG. FIG. 3 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. FIG. 4 is a schematic plan view illustrating the flow of current flowing in the first state in the semiconductor device according to the first embodiment shown in FIG. FIG. 5 is a schematic plan view illustrating the flow of current flowing in the second state in the semiconductor device according to the first embodiment shown in FIG. FIG. 6 is a schematic plan view of the semiconductor device according to the second embodiment as viewed in the thickness direction of the substrate. FIG. 7 is a schematic plan view of the semiconductor device according to the third embodiment as viewed in the thickness direction of the substrate.

[Explanation of Embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes an insulating substrate, a circuit pattern arranged on the substrate, P terminals, N terminals and O terminals electrically connected to the circuit pattern, and a third mounted on the circuit pattern. It includes one transistor chip and a second transistor chip. The circuit pattern is electrically connected to the P terminal and extends along the first direction in a band-shaped first region, and is electrically connected to the N terminal in the second direction which is the width direction of the first region. A band-shaped second region extending along the first direction and electrically connected to the O terminal, which are arranged at intervals from the first region, are arranged at intervals from each of the first region and the second region. A third region is included. The third region is arranged with a band-shaped first branch extending along the first direction and a band-shaped second branch extending along the first direction at intervals from the first branch in the second direction. Includes a bifurcation and a connection that extends along a second direction and connects one end of the first bifurcation to one end of the second bifurcation. The first transistor chip is mounted in the first region and electrically connected to the first region, and is electrically connected to the first branch portion by the first wiring. The second transistor chip is mounted on the second branch portion and electrically connected to the second branch portion, and is electrically connected to the second region by the second wiring.

The present inventors have studied a configuration of a semiconductor device capable of facilitating control for obtaining an output close to a desired AC waveform, and have come up with the following configuration. In a semiconductor device, the P terminal is in the first state when the electrical connection between the P terminal and the O terminal is on and the electrical connection between the O terminal and the N terminal is off. Current flows from the circuit pattern, the transistor chip in the on state, and the circuit pattern again to the O terminal. Further, in the second state where the electrical connection between the P terminal and the O terminal is off and the electrical connection between the O terminal and the N terminal is on, the circuit pattern is displayed from the O terminal. , The transistor chip in the on state, and the current flows to the N terminal again through the circuit pattern. Here, in the conventional semiconductor device, depending on the arrangement on the circuit pattern, the current flows in the region where the transistor chips are mounted in the transistor chips that are in the off state among the plurality of transistor chips. The circuit pattern generates heat due to this current flow. As a result, heat dissipation from the transistor chip is hindered. Then, a difference in cooling rate occurs between the transistor chip arranged in the region where the current flows in the circuit pattern and the transistor chip arranged in the region where the current does not flow. As a result, the temperature difference between the plurality of transistor chips becomes large, and electrical control for obtaining an output close to a desired AC waveform becomes complicated during high-speed switching operation. Therefore, in the first state and the second state, it is considered to separate the path through which the current flows in the circuit pattern, respectively.

According to the semiconductor device of the present disclosure, in the first state, the first region of the circuit pattern from the P terminal, the first transistor chip in the on state, the first wiring, and the first branch portion of the third region of the circuit pattern. Then, a current flows through the connection portion in the third region of the circuit pattern to the O terminal. At this time, no current flows through the second branch portion of the third region of the circuit pattern on which the second transistor chip that is in the off state is mounted. Then, in the first state, it is possible to prevent the heat dissipation of the second transistor chip from being hindered by the heat generated by the second branch portion of the third region of the circuit pattern. On the other hand, in the second state, the connection portion of the third region of the circuit pattern from the O terminal, the second branch portion of the third region of the circuit pattern, the second transistor chip in the on state, the second wiring, and the circuit pattern. A current flows through the second region of the N terminal. At this time, no current flows in the first region of the circuit pattern on which the first transistor chip that is in the off state is mounted. Then, in the second state, it is possible to suppress the heat dissipation of the first transistor chip from being hindered by the heat generation in the first region of the circuit pattern. In this way, the path of the current flowing through the circuit pattern is separated between the first state and the second state. Then, the difference between the cooling rate of the first transistor chip and the cooling rate of the second transistor chip when they are in the off state can be reduced. Therefore, in such a semiconductor device, the temperature difference between the first transistor chip and the second transistor chip can be reduced. Therefore, it is possible to facilitate electrical control for obtaining an output close to a desired AC waveform.

In the above semiconductor device, a heat radiating plate having one surface in the thickness direction on which the substrate is mounted and a frame body that rises from the one surface and is arranged so as to surround the substrate in the thickness direction of the substrate are further provided. You may prepare. The outer shape of the substrate may be a rectangle whose long side extends in the first direction when viewed in the thickness direction of the substrate. The frame may include a first wall portion and a second wall portion corresponding to a pair of long sides of the substrate, respectively. The P terminal and the N terminal may be arranged on the side opposite to the second short side when viewed from the first short side of the substrate. The O terminal may be arranged on the side opposite to the first short side when viewed from the second short side. By doing so, the structure of the semiconductor device of the present disclosure can be easily achieved.

In the above semiconductor device, the first gate terminal attached to the first wall portion and electrically connected to the gate pad of the first transistor chip, and the gate pad and electricity of the second transistor chip attached to the second wall portion. A second gate terminal connected to the device may be further provided. In the second direction, the distance between the first wall and the first region is the distance between the first wall and the second region, the distance between the first wall and the first branch, and It may be smaller than any of the distances between the first wall portion and the second branch portion. In the second direction, the distance between the second wall and the second branch is the distance between the second wall and the first region, the distance between the second wall and the second region, and It may be smaller than any of the distances between the second wall portion and the first branch portion. By doing so, the length of the wiring connecting the first gate terminal and the gate pad of the first transistor chip and the length of the wiring connecting the second gate terminal and the gate pad of the second transistor chip are set respectively. Can be shortened. Therefore, the inductance can be reduced.

In the above semiconductor device, the first Kelvin source terminal attached to the first wall portion and electrically connected to the Kelvin source pad of the first transistor chip, and the Kelvin source attached to the second wall portion and electrically connected to the Kelvin source pad of the second transistor chip. It may further include a second Kelvin source terminal that is electrically connected to the pad. In the second direction, the distance between the first wall and the first region is the distance between the first wall and the second region, the distance between the first wall and the first branch, and It may be smaller than any of the distances between the first wall portion and the second branch portion. In the second direction, the distance between the second wall and the second branch is the distance between the second wall and the first region, the distance between the second wall and the second region, and It may be smaller than any of the distances between the second wall portion and the first branch portion. By doing so, the length of the wiring connecting the first Kelvin source terminal and the Kelvin source pad of the first transistor chip and the wiring connecting the second Kelvin source terminal and the Kelvin source pad of the second transistor chip Each length can be shortened. Therefore, the inductance can be reduced.

In the semiconductor device, the first wiring may include a first source wire that electrically connects the source pad of the first transistor chip and the first branch portion. The second wiring may include a second source wire that electrically connects the source pad of the second transistor chip to the second region. The length of the first source wire and the length of the second source wire may be the same. The number of first source wires and the number of second source wires may be the same. By doing so, it is possible to make it easy to make the values of inductance in each electrical path uniform. Therefore, the electrical characteristics of each route can be easily aligned, and electrical control can be facilitated.

In the semiconductor device, at least one of the first transistor chip and the second transistor chip may include a semiconductor layer made of SiC or GaN. Since the transistor chip including such a semiconductor layer can be switched at high speed, it is suitable for the semiconductor device of the present disclosure which is premised on switching the current path.

[Details of Embodiments of the present disclosure]
Next, an embodiment of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1)
The configuration of the semiconductor device according to the first embodiment of the present disclosure will be described. FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate. FIG. 2 is a schematic plan view showing only the substrate and the circuit pattern included in the semiconductor device shown in FIG. In FIG. 1 and the like, the boundary between the first branch portion and the connecting portion and the boundary between the second branch portion and the connecting portion, which will be described later, are indicated by broken lines. FIG. 3 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view of the case where the first transistor chip is included and cut along a plane parallel to the XZ plane.

With reference to FIGS. 1, 2 and 3, the semiconductor device 11a according to the first embodiment includes a heat sink 12, a frame 13, a metal plate 14a (see FIG. 3), a substrate 15a, and a circuit pattern 16a. , The solder portions 17a, 18a (see FIG. 3), the P terminal 19a, the O terminals 19b, 19c, the N terminal 19d, the first diode chips 21a, 21b, 21c, 21d, and the first transistor chip 22a, It includes 22b, 22c, 22d, second diode chips 21e, 21f, 21g, 21h, and second transistor chips 22e, 22f, 22g, 22h.

The heat sink 12 is made of metal. The heat sink 12 is made of, for example, copper. The surface of the heat radiating plate 12 may be nickel-plated. The outer shape of the heat radiating plate 12 is a rectangle in which the side extending in the X direction is the long side and the side extending in the Y direction is the short side when viewed in the thickness direction, and the corners are curved surfaces. The solder portion 17a is arranged on one surface 12a of the heat radiating plate 12 in the thickness direction. As the material of the solder portion 17a, for example, Sn-Ag-Cu-based solder or Sn-Sb-based solder is used.

The metal plate 14a is arranged on the solder portion 17a. The heat sink 12 and the metal plate 14a are joined by the solder portion 17a. The metal plate 14a is made of, for example, copper.

The substrate 15a is arranged on the metal plate 14a. The substrate 15a is mounted on one surface 12a of the heat sink 12. The substrate 15a is insulating. Examples of the material of the insulating substrate 15a include Al ₂ O ₃ , Al N, and Si _{3 N 4} . The thickness direction of the heat radiating plate 12 and the thickness direction of the substrate 15a are both in the Z direction. The outer shape of the substrate 15a is a rectangle whose long side extends in the X direction, which is the first direction described later, when viewed in the thickness direction of the substrate 15a. Specifically, with reference to FIG. 2, the outer shape of the substrate 15a is composed of a pair of long sides 33a and 33b and a pair of short sides 34a and 34b when viewed in the thickness direction of the substrate 15a. ..

The circuit pattern 16a is arranged on the substrate 15a. The circuit pattern 16a is made of, for example, copper. The specific configuration of the circuit pattern 16a will be described in detail later.

The frame body 13 rises from one surface 12a of the heat radiating plate 12 and is arranged so as to surround the substrate 15a when viewed in the thickness direction of the substrate 15a. The frame body 13 includes a first wall portion 13a, a second wall portion 13b, a third wall portion 13c, and a fourth wall portion 13d. The first wall portion 13a and the second wall portion 13b are arranged so as to face each other in the Y direction. The third wall portion 13c and the fourth wall portion 13d are arranged so as to face each other in the X direction. The frame body 13 is made of, for example, an insulating resin. The frame body 13 is fixed to the heat radiating plate 12 with, for example, an adhesive. The heat radiating plate 12 and the frame 13 form a case 20 included in the semiconductor device 11a. The space 30 inside the case 20 is filled with a resin filler (not shown).

The P terminal 19a, the O terminal 19b, 19c, and the N terminal 19d are plate-shaped and made of metal, respectively. The P terminal 19a, the O terminal 19b, 19c, and the N terminal 19d each have a bent band shape. In the present embodiment, the P terminal 19a, the O terminal 19b, 19c and the N terminal 19d are formed by bending, for example, a strip-shaped copper plate, respectively. When viewed in the thickness direction of the substrate 15a, the P terminal 19a and the N terminal 19d are arranged on one side of the substrate 15a where the third wall portion 13c is located, and the O terminals 19b and 19c sandwich the substrate 15a. It is arranged on the other side where the fourth wall portion 13d is located. The P terminal 19a and the N terminal 19d are arranged on the side opposite to the second short side 34b when viewed from the first short side 34a of the substrate 15a. The O terminals 19b and 19c are arranged on the side opposite to the first short side 34a when viewed from the second short side 34b.
The O terminals 19b and 19c are attached to the fourth wall portion 13d. The P terminal 19a and the N terminal 19d are attached to the third wall portion 13c. The semiconductor device 11a secures an electrical connection with the outside by means of P terminals 19a, O terminals 19b, 19c, and N terminals 19d. The direction from one side where the P terminal 19a and the N terminal 19d are arranged toward the O terminals 19b and 19c is indicated by the direction indicated by the arrow X in FIG. In the present embodiment, the first direction is the X direction indicated by the direction indicated by the arrow X or the opposite direction. The P terminal 19a, the O terminal 19b, 19c, and the N terminal 19d each have a portion exposed from the inner wall surface 27 of the frame body 13 to the space 30 side inside the case 20. Each wire is electrically connected using this portion.

The first diode chips 21a, 21b, 21c, 21d, the second diode chips 21e, 21f, 21g, 21h, the first transistor chips 22a, 22b, 22c, 22d and the second transistor chips 22e, 22f, 22g, 22h are SiC. Alternatively, it includes a semiconductor layer made of GaN. The first diode chips 21a, 21b, 21c, 21d and the second diode chips 21e, 21f, 21g, 21h are, for example, Schottky barrier diodes (SBDs). The first transistor chips 22a, 22b, 22c, 22d and the second transistor chips 22e, 22f, 22g, 22h are, for example, metal-oxide-semiconductor field effect transistors (MOSFETs).

The first transistor chip 22a is mounted on the circuit pattern 16a. The first transistor chip 22a is electrically joined to the circuit pattern 16a by the solder portion 18a. The first transistor chip 22a includes a drain electrode located at one end of the substrate 15a in the thickness direction, and a source pad, a gate pad, and a Kelvin source pad located at the other end of the substrate 15a in the thickness direction. And, including. The first transistor chip 22a is joined to the circuit pattern 16a by the solder portion 18a so that the drain electrode is in contact with the circuit pattern 16a. A current flows through the first transistor chip 22a in the thickness direction of the substrate 15a. The first transistor chip 22a is a vertical transistor chip. The same applies to the configurations of the other first transistor chips 22b to 22d and the second transistor chips 22e to 22h.

The first diode chip 21a is mounted on the circuit pattern 16a. The first diode chip 21a is electrically bonded to the circuit pattern 16a by the solder portion, similarly to the first transistor chip 22a. The first diode chip 21a includes a cathode pad located at one end of the substrate 15a in the thickness direction and an anode pad located at the other end of the substrate 15a in the thickness direction. The first diode chip 21a is joined to the circuit pattern 16a by the solder portion so that the cathode pad comes into contact with the circuit pattern 16a. A current flows through the first diode chip 21a in the thickness direction of the substrate 15a. The same applies to the configurations of the other first diode chips 21b to 21d and the second diode chips 21e to 21h.

The semiconductor device 11a includes a first gate terminal 41a, a second gate terminal 41b, a first Kelvin source terminal 42a, a second Kelvin source terminal 42b, a D terminal 43, and thermistor terminals 44a and 44b. The first gate terminal 41a, the first Kelvin source terminal 42a, the D terminal 43, and the thermistor terminals 44a, 44b are attached to the first wall portion 13a at intervals in the X direction, respectively. Specifically, from the side closer to the fourth wall portion 13d, the order is D terminal 43, first Kelvin source terminal 42a, first gate terminal 41a, and thermistor terminals 44a, 44b. The second gate terminal 41b and the second Kelvin source terminal 42b are attached to the second wall portion 13b, respectively. Part of the first gate terminal 41a, the second gate terminal 41b, the first Kelvin source terminal 42a, the second Kelvin source terminal 42b, the D terminal 43, and the thermistor terminals 44a, 44b are exposed in the internal space 30. It is attached. Further, the first gate terminal 41a, the second gate terminal 41b, the first Kelvin source terminal 42a, the second Kelvin source terminal 42b, the D terminal 43, and the thermistor terminals 44a and 44b each secure an electrical connection with the outside. Therefore, it has a portion protruding from the upper surface of the frame body 13.

Next, a specific configuration of the circuit pattern 16a will be described. The circuit pattern 16a includes a first region 51a, a second region 52a, a third region 53a, a fourth region 54a, a fifth region 55a, a sixth region 56a, a seventh region 57a, and an eighth region. It includes 58a and a ninth region 59a. The first region 51a, the second region 52a, the fourth region 54a, the fifth region 55a, the sixth region 56a, and the seventh region 57a are each strip-shaped and extend in the first direction. The third region 53a includes a first branch portion 61a, a second branch portion 62a, and a connection portion 63a. The first branch portion 61a and the second branch portion 62a are each strip-shaped and extend in the first direction. The connecting portion 63a is also strip-shaped. The connecting portion 63a extends in the second direction, which is the width direction of the first region 51a. In the present embodiment, the second direction is the Y direction indicated by the direction indicated by the arrow Y or vice versa. The connection portion 63a is an end portion on one side of the first branch portion 61a, in this case, an end portion on the side close to the fourth wall portion 13d, and an end portion on one side of the second branch portion 62a, in this case, the fourth. It is connected to the end portion on the side closer to the wall portion 13d. The eighth region 58a and the ninth region 59a each have a rectangular shape when viewed in the thickness direction of the substrate 15a. The eighth region 58a and the ninth region 59a are arranged side by side with an interval in the X direction when viewed in the thickness direction of the substrate 15a. The thermistor 28 included in the semiconductor device 11a is arranged so as to straddle the eighth region 58a and the ninth region 59a when viewed in the thickness direction of the substrate 15a. The thermistor 28 is electrically connected to the eighth region 58a and the ninth region 59a.

The first region 51a, the second region 52a, the fourth region 54a, the fifth region 55a, the sixth region 56a, the seventh region 57a, the first branch portion 61a, and the second branch portion 62a are spaced apart from each other in the second direction. Is placed open. In the present embodiment, in the second direction, the first branch portion 61a is arranged between the first region 51a and the second region 52a. In the second direction, the second region 52a is arranged between the first branch portion 61a and the second branch portion 62a. Specifically, when viewed in the thickness direction of the substrate 15a, from the side where the first wall portion 13a is arranged in the Y direction, the fourth region 54a, the fifth region 55a, the first region 51a, the first branch portion 61a, The second region 52a, the second branch portion 62a, the sixth region 56a, and the seventh region 57a are arranged in this order. The widths of the fourth region 54a, the fifth region 55a, the sixth region 56a, and the seventh region 57a are smaller than the widths of the first region 51a and the second region 52a, respectively.

In the second direction, the distance between the first wall portion 13a and the first region 51a is the distance between the first wall portion 13a and the second region 52a, and the distance between the first wall portion 13a and the first branch portion 61a. It is smaller than either the distance between the first wall portion 13a and the second branch portion 62a. Further, in the second direction, the distance between the second wall portion 13b and the second branch portion 62a is the distance between the second wall portion 13b and the first region 51a, and the distance between the second wall portion 13b and the second. It is smaller than either the distance between the region 52a and the distance between the second wall portion 13b and the first branch portion 61a.

The first diode chips 21a, 21b, 21c, 21d are arranged on the first region 51a. The first transistor chips 22a, 22b, 22c, 22d are arranged on the first region 51a. The first diode chips 21a to 21d and the first transistor chips 22a to 22d are arranged at intervals in the X direction, respectively. The first transistor chip 22a is arranged between the first diode chip 21a and the first diode chip 21b. The first transistor chip 22b is arranged between the first diode chip 21b and the first diode chip 21c. The first transistor chip 22c is arranged between the first diode chip 21c and the first diode chip 21d. The first transistor chip 22d is arranged in the X direction at a position opposite to the position where the first transistor chip 22c is arranged with respect to the first diode chip 21d. The distance between the first transistor chip 22b and the first diode chip 21c in the X direction is larger than the distance between the first transistor chip 22b and the first diode chip 21b in the X direction.

The second diode chips 21e, 21f, 21g, 21h are arranged on the second branch portion 62a. The second transistor chips 22e, 22f, 22g, 22h are arranged on the second branch portion 62a. The second diode chips 21e to 21h and the second transistor chips 22e to 22h are arranged at intervals in the X direction, respectively. The second transistor chip 22e is arranged between the second diode chip 21e and the second diode chip 21f. The second transistor chip 22f is arranged between the second diode chip 21f and the second diode chip 21g. A second transistor chip 22g is arranged between the second diode chip 21g and the second diode chip 21h. The second transistor chip 22h is arranged in the X direction at a position opposite to the position where the second transistor chip 22g is arranged with respect to the second diode chip 21h. The distance between the second transistor chip 22f and the second diode chip 21g in the X direction is larger than the distance between the second transistor chip 22f and the second diode chip 21f in the X direction.

The semiconductor device 11a includes a first wiring that electrically connects the first transistor chips 22a, 22b, 22c, 22d and the circuit pattern 16a. The first wiring includes wires 25a, 25b, 25c, 25d as first source wires that electrically connect the first transistor chips 22a, 22b, 22c, 22d and the first branch portion 61a. The semiconductor device 11a includes a second wiring that electrically connects the second transistor chips 22e, 22f, 22g, 22h and the circuit pattern 16a. The second wiring includes wires 25e, 25f, 25g, 25h as a second source wire that electrically connects the second transistor chips 22e, 22f, 22g, 22h and the second region 52a. Further, the semiconductor device 11a includes wires 23a, 23b, 23c, 23d, 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 29a, 29b, Includes 29c, 29d, 29e, 29f, 29g, 29h, 31a, 31b, 31c, 31d, 31e, 31f, 31g, 31h, 32a, 32b, 32c, 32d, 32e, 32f, 32g, 32h.

The P terminal 19a and the first region 51a are electrically connected by a wire 23a. The O terminal 19b and the connecting portion 63a are electrically connected by a wire 23b. The O terminal 19c and the connecting portion 63a are electrically connected by a wire 23c. The third region 53a including the connection portion 63a has the same potential as the O terminals 19b and 19c. The N terminal 19d and the second region 52b are electrically connected by a wire 23d.

The anode pads of the first diode chips 21a, 21b, 21c, and 21d and the first branch portion 61a are electrically connected by wires 24a, 24b, 24c, and 24d, respectively. The source pads of the first transistor chips 22a, 22b, 22c, and 22d and the first branch portion 61a are electrically connected by wires 25a, 25b, 25c, and 25d, respectively. The gate pads of the first transistor chips 22a, 22b, 22c, and 22d and the fifth region 55a are electrically connected by wires 31a, 31c, 31e, and 31g, respectively. The Kelvin source pads of the first transistor chips 22a, 22b, 22c, and 22d and the fourth region 54a are electrically connected by wires 31b, 31d, 31f, and 31h, respectively. The fifth region 55a and the first gate terminal 41a are electrically connected by a wire 26c. The fourth region 54a and the first Kelvin source terminal 42a are electrically connected by a wire 26b. The first region 51a and the D terminal 43 are electrically connected by a wire 26a. The eighth region 58a and the thermistor terminal 44a are electrically connected by a wire 26d. The ninth region 59a and the thermistor terminal 44b are electrically connected by a wire 26e.

The anode pads of the second diode chips 21e, 21f, 21g, and 21h and the second region 52a are electrically connected by wires 24e, 24f, 24g, and 24h, respectively. The source pads of the second transistor chips 22e, 22f, 22g, and 22h and the second region 52a are electrically connected by wires 25e, 25f, 25g, and 25h, respectively. The gate pads of the second transistor chips 22e, 22f, 22g, and 22h and the sixth region 56a are electrically connected by wires 32a, 32c, 32e, and 32g, respectively. The Kelvin source pads of the second transistor chips 22e, 22f, 22g, and 22h and the seventh region 57a are electrically connected by wires 32b, 32d, 32f, and 32h, respectively. The sixth region 56a and the second gate terminal 41b are electrically connected by a wire 26f. The seventh region 57a and the second Kelvin source terminal 42b are electrically connected by a wire 26g. The first region 51a and the D terminal 43 are electrically connected by a wire 26a.

Next, the current flow in the first state will be described. FIG. 4 is a schematic plan view illustrating the flow of the current flowing in the first state in the semiconductor device 11a according to the first embodiment shown in FIG. 4 shows a flow of current, from the P terminal 19a to the O terminal 19b by the arrow _{D 1.} FIG. 5 is a schematic plan view illustrating the flow of current flowing in the second state in the semiconductor device 11a according to the first embodiment shown in FIG. 5 shows a flow of current, from O terminal 19c to the N terminal 19d by the arrow _{D 2.}

First, referring to FIG. 4, the first transistor chips 22a, 22b, 22c, 22d are turned on, the electrical connection between the P terminal 19a and the O terminal 19b is turned on, and the O terminal 19c In the first state where the electrical connection with the N terminal 19d is in the off state, the wires 23a from the P terminal 19a, the first region 51a of the circuit pattern 16a, the first transistor chips 22a, 22b in the on state, 22c, 22d, the first wiring wires 25a, 25b, 25c, 25d, the first branch portion 61a of the third region 53a of the circuit pattern 16a, the connection portion 63a of the third region 53a of the circuit pattern 16a, and the wire 23b. A current flows through the O terminal 19b. At this time, no current flows through the second branch portion 62a of the third region 53a of the circuit pattern 16a on which the second transistor chips 22e, 22f, 22g, 22h that are in the off state are mounted. Then, in the first state, it is possible to prevent the heat dissipation of the second transistor chips 22e, 22f, 22g, 22h from being hindered by the heat generation of the second branch portion 62a of the third region 53a of the circuit pattern 16a. ..

On the other hand, with reference to FIG. 5, next, in the second state, the O terminal 19c to the wire 23c, the connection portion 63a of the third region 53a of the circuit pattern 16a, and the second of the third region 53a of the circuit pattern 16a. N through the branch portion 62a, the on-state second transistor chips 22e, 22f, 22g, 22h, the wires 25e, 25f, 25g, 25h as the second wiring, the second region 52a of the circuit pattern 16a, and the wire 23d. A current flows through the terminal 19d. At this time, no current flows in the first region 51a of the circuit pattern 16a on which the first transistor chips 22a, 22b, 22c, 22d that are in the off state are mounted. Then, in the second state, it is possible to prevent the heat dissipation of the first transistor chips 22a, 22b, 22c, 22d from being hindered by the heat generation of the first region 51a of the circuit pattern 16a.

In this way, the path of the current flowing through the circuit pattern 16a is separated between the first state and the second state. Then, the difference between the cooling rates of the first transistor chips 22a, 22b, 22c, and 22d and the cooling rates of the second transistor chips 22e, 22f, 22g, and 22h when they are in the off state can be reduced. Therefore, such a semiconductor device 11a can reduce the temperature difference between the first transistor chips 22a, 22b, 22c, 22d and the second transistor chips 22e, 22f, 22g, 22h. Therefore, it is possible to facilitate electrical control for obtaining an output close to a desired AC waveform.

In this embodiment, it is easy to make the wiring that is the current path between the P terminal 19a and the O terminal 19b and the wiring that is the current path between the O terminal 19c and the N terminal 19d symmetrical. That is, it is possible to easily make the wiring structure of one region divided by the alternate long and short dash line in FIG. 1 and the wiring structure of the other region symmetrical.

In the present embodiment, the semiconductor device 11a has a heat sink 12 having one surface 12a in the thickness direction on which the substrate 15a is mounted, and the substrate 15a rising from the one surface 12a and viewed in the thickness direction of the substrate 15a. Includes a frame 13 arranged so as to surround it. The outer shape of the substrate 15a is a rectangle whose long side extends in the first direction when viewed in the thickness direction of the substrate 15a. The frame body 13 includes a first wall portion 13a and a second wall portion 13b corresponding to a pair of long sides of the substrate 15a, respectively. The P terminal 19a and the N terminal 19d are arranged on the side opposite to the second short side when viewed from the first short side of the substrate 15a. The O terminals 19b and 19c are arranged on the side opposite to the first short side when viewed from the second short side. Therefore, it is a semiconductor device that can easily achieve the structure of the semiconductor device 11a.

In the present embodiment, the semiconductor device 11a has a first gate terminal 41a attached to the first wall portion 13a and electrically connected to the gate pads of the first transistor chips 22a, 22b, 22c, 22d, and a second gate terminal 41a. It includes a second gate terminal 41b attached to the wall portion 13b and electrically connected to the gate pad of the second transistor chips 22e, 22f, 22g, 22h. Further, in the second direction, the distance between the first wall portion 13a and the first region 51a is the distance between the first wall portion 13a and the second region 52a, and the distance between the first wall portion 13a and the first branch. It is smaller than either the distance between the portion 61a and the distance between the first wall portion 13a and the second branch portion 62a. In the second direction, the distance between the second wall portion 13b and the second branch portion 62a is the distance between the second wall portion 13b and the first region 51a, and the distance between the second wall portion 13b and the second region 52a. It is smaller than either the distance between the second wall portion 13b and the first branch portion 61a. Therefore, in such a semiconductor device 11a, the lengths of the wires 31a, 31c, 31e, 31g, which are the wirings for connecting the first gate terminal 41a and the gate pads of the first transistor chips 22a, 22b, 22c, 22d, and the first The lengths of the wires 32a, 32c, 32e, and 32g, which are the wirings connecting the two gate terminals 41b and the gate pads of the second transistor chips 22e, 22f, 22g, and 22h, can be shortened, respectively. Therefore, the inductance can be reduced.

The semiconductor device 11a has a first Kelvin source terminal 42a attached to the first wall portion 13a and electrically connected to the Kelvin source pad of the first transistor chips 22a, 22b, 22c, 22d, and a second wall portion 13b. Includes a second Kelvin source terminal 42b, which is attached to and electrically connected to the Kelvin source pad of the second transistor chips 22e, 22f, 22g, 22h. Further, in the second direction, the distance between the first wall portion 13a and the first region 51a is the distance between the first wall portion 13a and the second region 52a, and the distance between the first wall portion 13a and the first branch. It is smaller than either the distance between the portion 61a and the distance between the first wall portion 13a and the second branch portion 62a. In the second direction, the distance between the second wall portion 13b and the second branch portion 62a is the distance between the second wall portion 13b and the first region 51a, and the distance between the second wall portion 13b and the second region 52a. It is smaller than either the distance between the second wall portion 13b and the first branch portion 61a. Therefore, such a semiconductor device 11a has a length of wires 31b, 31d, 31f, 31h, which are wirings for connecting the first Kelvin source terminal 42a and the Kelvin source pads of the first transistor chips 22a, 22b, 22c, 22d. The lengths of the wires 32b, 32d, 32f, and 32h, which are the wirings connecting the second Kelvin source terminal 42b and the Kelvin source pads of the second transistor chips 22e, 22f, 22g, and 22h, can be shortened, respectively. Therefore, the inductance can be reduced.

In the present embodiment, the semiconductor device 11a is a wire 25a, 25b, 25c which is a first source wire for electrically connecting the source pad of the first transistor chips 22a, 22b, 22c, 22d and the first branch portion 61a. , 25d, and wires 25e, 25f, 25g, 25h, which are second source wires that electrically connect the source pads of the second transistor chips 22e, 22f, 22g, 22h and the second region 52a. The lengths of the wires 25a, 25b, 25c, 25d and the lengths of the wires 25e, 25f, 25g, 25h are the same. The number of wires 25a, 25b, 25c, 25d and the number of wires 25e, 25f, 25g, 25h are the same. Therefore, such a semiconductor device 11a can easily make the values of inductance in each electrical path uniform. Therefore, the electrical characteristics of each route can be easily aligned, and electrical control can be facilitated.

In the present embodiment, at least one of the first transistor chips 22a, 22b, 22c, 22d and the second transistor chips 22e, 22f, 22g, 22h includes a semiconductor layer made of SiC or GaN. Since the transistor chip including such a semiconductor layer can be switched at high speed, it is suitable for the semiconductor device of the present disclosure which is premised on switching the current path.

(Embodiment 2)
Next, the second embodiment, which is another embodiment, will be described. FIG. 6 is a schematic plan view of the semiconductor device according to the second embodiment as viewed in the thickness direction of the substrate. The semiconductor device of the second embodiment is different from the case of the first embodiment in that the substrate and the circuit pattern are divided.

With reference to FIG. 6, the substrate 15b included in the semiconductor device 11b according to the second embodiment is divided into a first substrate 80a and a second substrate 80b. The outer shape of the first substrate 80a and the outer shape of the second substrate 80b are rectangular when viewed in the thickness direction of the substrate 15b, respectively. The first substrate 80a and the second substrate 80b are arranged side by side at intervals in the X direction.

In the second embodiment, a part of the circuit pattern 16b arranged on the substrate 15b is also divided. Specifically, the circuit pattern 16b includes a first region 51b, 71b, a second region 52b, 72b, a third region 53b, a fourth region 54b, 74b, a fifth region 55b, 75b, and a sixth. It includes regions 56b, 76b, seventh regions 57b, 77b, eighth regions 58b, and ninth regions 59b. The third region 53b includes first branch portions 61b and 81b, second branch portions 62b and 82b, and a connection portion 63b. On the first substrate 80a, a first region 51b, a second region 52b, a fourth region 54b, a fifth region 55b, a sixth region 56b, a seventh region 57b, a first branch portion 61b, and a second branch portion 62b And the connection portion 63b is arranged. A first region 71b, a second region 72b, a fourth region 74b, a fifth region 75b, a sixth region 76b, a seventh region 77b, an eighth region 58b, and a ninth region 59b are arranged on the second substrate 80b. Will be done. The divided parts are electrically connected by wires. Specifically, the first region 51b on the first substrate 80a and the first region 71b on the second substrate 80b are electrically connected by a wire 29a. The second region 52b on the first substrate 80a and the second region 72b on the second substrate 80b are electrically connected by a wire 29b. The fourth region 54b on the first substrate 80a and the fourth region 74b on the second substrate 80b are electrically connected by a wire 29c. The fifth region 55b on the first substrate 80a and the fifth region 75b on the second substrate 80b are electrically connected by a wire 29d. The sixth region 56b on the first substrate 80a and the sixth region 76b on the second substrate 80b are electrically connected by a wire 29e. The seventh region 57b on the first substrate 80a and the seventh region 77b on the second substrate 80b are electrically connected by a wire 29f. The first branch portion 61b on the first substrate 80a and the first branch portion 81b on the second substrate 80b are electrically connected by a wire 29g. The second branch portion 62b on the first substrate 80a and the second branch portion 82b on the second substrate 80b are electrically connected by a wire 29h.

In this way, even when the substrate 15b and the circuit pattern 16b on the substrate 15b are divided, it is sufficient that the respective parts are electrically connected. Such a configuration also facilitates electrical control to obtain an output close to the desired AC waveform. According to this embodiment, the stress generated based on the difference in the coefficient of thermal expansion of each member can be relaxed.

(Embodiment 3)
Next, the third embodiment, which is still another embodiment, will be described. FIG. 7 is a schematic plan view of the semiconductor device according to the third embodiment as viewed in the thickness direction of the substrate. In the semiconductor device of the third embodiment, the arrangement of the circuit pattern arranged on the substrate is different from that of the first embodiment.

With reference to FIG. 7, the semiconductor device 11c according to the third embodiment includes a substrate 15c and a circuit pattern 16c arranged on the substrate 15c. The circuit pattern 16c arranged on the substrate 15c includes a first region 51c, a second region 52c, a third region 53c, a fourth region 54c, a fifth region 55c, a sixth region 56c, and a seventh region. The region 57c, the eighth region 58c, and the ninth region 59c are included. The third region 53c includes a first branch portion 61c, a second branch portion 62c, and a connection portion 63c.

In the present embodiment, in the second direction, the second branch portion 62c is arranged between the first region 51c and the second region 52c. In the second direction, the first region 51c is arranged between the first branch portion 61c and the second branch portion 62c. Specifically, when viewed in the thickness direction of the substrate 15a, from the side where the first wall portion 13a is arranged in the Y direction, the fourth region 54c, the fifth region 55c, the first branch portion 61c, the first region 51c, The second branch portion 62c, the second region 52c, the sixth region 56c, and the seventh region 57c are arranged in this order.

Such a configuration also facilitates electrical control to obtain an output close to the desired AC waveform. According to the present embodiment, the first transistor chips 22a to 22d and the second transistor chips 22e to 22h can be arranged in a region near the center of the heat radiating plate 12 when viewed in the thickness direction of the substrate 15a, so that heat is radiated. The sex can be improved.

(Other embodiments)
In the above embodiment, in the second direction, either the first region or the second region is arranged between the first branch portion and the second branch portion. However, for example, in the second direction, both the first region and the second region may be arranged between the first branch portion and the second branch portion. Further, in the second direction, the first branch portion and the second branch portion may be arranged between the first region and the second region.

Further, in the above embodiment, the outer shape of the substrate is rectangular when viewed in the thickness direction of the substrate, but the present invention is not limited to this, and other shapes such as trapezoidal shape, circular shape, and elliptical shape are available. You may.

In the above embodiment, a wire for electrically connecting each member is used, but the present invention is not limited to this, and for example, a ribbon wire or a bus bar for electrically connecting each member is used. May be good.

It should be understood that the embodiments disclosed here are exemplary in all respects and are not restrictive in any way. The scope of the present invention is defined by the scope of claims, not the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

The semiconductor devices of the present disclosure can be applied particularly advantageously when it is required to facilitate control to obtain an output close to the desired AC waveform.

11a, 11b, 11c Semiconductor device 12 Heat dissipation plate 12a Surface 13 Frame 13a First wall 13b Second wall 13c Third wall 13d Fourth wall 14a Metal plate 15a, 15b, 15c, 80a, 80b Substrate 16a, 16b, 16c Circuit pattern 17a, 18a Solder part 19a P terminal 19b, 19c O terminal 19d N terminal 20 Case 21a, 21b, 21c, 21d First diode chip 21e, 21f, 21g, 21h Second diode chip 22a, 22b, 22c , 22d 1st transistor chip 22e, 22f, 22g, 22h 2nd transistor chip 23a, 23b, 23c, 23d, 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 25a, 25b, 25c, 25d, 25e , 25f, 25g, 25h, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 29a, 29b, 29c, 29d, 29e, 29f, 29g, 29h, 31a, 31b, 31c, 31d, 31e, 31f, 31g , 31h, 32a, 32b, 32c, 32d, 32e, 32f, 32g, 32h Wire 27 Inner wall surface 28 Thermistor 30 Space 33a, 33b Long side 34a, 34b Short side 41a First gate terminal 41b Second gate terminal 42a First Kelvin Source terminal 42b Second Kelvin Source terminal 44a, 44b Thermistor terminals 51a, 51b, 51c, 71b First region 52a, 52b, 52c, 72b Second region 53a, 53b, 53c Third region 54a, 54b, 54c, 74b Fourth Regions 55a, 55b, 55c, 75b 5th region 56a, 56b, 56c, 76b 6th region 57a, 57b, 57c, 77b 7th region 58a, 58b, 58c 8th region 59a, 59b, 59c 9th region 61a, 61b , 61c, 81b 1st branch 62a, 62b, 62c, 82b 2nd branch 63a, 63b, 63c Connection D ₁ , D ₂ Arrow

Claims (9)

Insulating board and
The circuit pattern arranged on the board and
A P terminal, an N terminal, and two O terminals that are electrically connected to the circuit pattern,
The first transistor chip and the second transistor chip mounted on the circuit pattern,
A first diode chip and a second diode chip mounted on the circuit pattern are provided.
The circuit pattern is
A band-shaped first region electrically connected to the P terminal and extending along the first direction,
A strip-shaped second region that is electrically connected to the N terminal, is arranged at intervals from the first region in a second direction that is the width direction of the first region, and extends along the first direction. When,
Includes a third region that is electrically connected to the O terminal and is spaced apart from each of the first and second regions.
The third region is
A strip-shaped first branch extending along the first direction,
A strip-shaped second branch portion that is arranged at a distance from the first branch portion in the second direction and extends along the first direction.
Includes a connecting portion that extends along the second direction and connects one end of the first branch to one end of the second branch.
The first transistor chip is mounted in the first region and electrically connected to the first region, and is electrically connected to the first branch portion by the first wiring.
The second transistor chip is mounted on the second branch portion and electrically connected to the second branch portion, and is electrically connected to the second region by the second wiring.
The first diode chip is mounted in the first region and electrically connected to the first region, and is electrically connected to the first branch portion by a wire.
The second diode chip is mounted on the second branch portion and electrically connected to the second branch portion, and is electrically connected to the second region by a wire.
The first transistor chip and the first diode chip are arranged side by side along the first direction.
The second transistor chip and the second diode chip are arranged side by side along the first direction .
The P terminal and the first region are connected by a wire extending along the first direction.
The N terminal and the second region are connected by a wire extending along the first direction.
One of the O terminals and the third region are connected by a wire extending along the first direction.
The other O terminal and the third region are connected by a wire extending along the first direction.
The position of the first diode chip and the position of the second diode chip extend along the first direction when viewed in the thickness direction of the substrate, and are a region in which the first transistor chip is arranged. With respect to a dividing line located in the middle of the region where the second transistor chip is arranged and dividing the region where the first transistor chip is arranged and the region where the second transistor chip is arranged. Symmetrical
The position of the first wiring and the position of the second wiring are symmetrical with respect to the dividing line.
The position of the wire connecting the first diode chip and the first branch portion and the position of the wire connecting the second diode chip and the second region are symmetrical with respect to the dividing line.
The position of the P terminal and the position of the N terminal are symmetrical with respect to the dividing line.
The position of the O terminal on one side and the position of the O terminal on the other side are symmetrical with respect to the dividing line.
When the first transistor chip is on and the second transistor chip is off, the wire connecting the P terminal to the first region from the P terminal, the first region, the first transistor chip, and the like. A current flows through the first wiring, the first branch portion, and the wire connecting the two O terminals and the first branch portion to the two O terminals.
When the first transistor chip is in the off state and the second transistor chip is in the on state, a wire connecting the two O terminals and the second branch portion from the two O terminals, the second branch portion, and the like. A semiconductor device in which a current flows through the second transistor chip, the second wiring, the second region, and a wire connecting the second region and the N terminal to the N terminal. Insulating board and
The circuit pattern arranged on the board and
A P terminal, an N terminal, and two O terminals that are electrically connected to the circuit pattern,
A plurality of first transistor chips and a plurality of second transistor chips mounted on the circuit pattern,
A plurality of first diode chips and a plurality of second diode chips mounted on the circuit pattern are provided.
The circuit pattern is
A band-shaped first region electrically connected to the P terminal and extending along the first direction,
A strip-shaped second region that is electrically connected to the N terminal, is arranged at intervals from the first region in a second direction that is the width direction of the first region, and extends along the first direction. When,
Includes a third region that is electrically connected to the O terminal and is spaced apart from each of the first and second regions.
The third region is
A strip-shaped first branch extending along the first direction,
A strip-shaped second branch portion that is arranged at a distance from the first branch portion in the second direction and extends along the first direction.
Includes a connecting portion that extends along the second direction and connects one end of the first branch to one end of the second branch.
Each of the plurality of first transistor chips is arranged along the first direction, mounted in the first region, electrically connected to the first region, and the first branch portion is provided by the first wiring. Electrically connected to
Each of the plurality of second transistor chips is arranged along the first direction, is mounted on the second branch portion, is electrically connected to the second branch portion, and is connected to the second branch portion by the second wiring. Electrically connected to the area,
Each of the plurality of first diode chips is arranged along the first direction, mounted in the first region, electrically connected to the first region, and electrically connected to the first branch portion by a wire. Connected to
Each of the plurality of second diode chips is arranged along the first direction, is mounted on the second branch portion, is electrically connected to the second branch portion, and is connected to the second region by a wire. Electrically connected
The plurality of first transistor chips and the plurality of first diode chips are arranged alternately side by side along the first direction.
The plurality of second transistor chips and the plurality of second diode chips are arranged alternately side by side along the first direction .
The P terminal and the first region are connected by a wire extending along the first direction.
The N terminal and the second region are connected by a wire extending along the first direction.
One of the O terminals and the third region are connected by a wire extending along the first direction.
The other O terminal and the third region are connected by a wire extending along the first direction.
The position of the first diode chip and the position of the second diode chip extend along the first direction when viewed in the thickness direction of the substrate, and are a region in which the first transistor chip is arranged. With respect to a dividing line located in the middle of the region where the second transistor chip is arranged and dividing the region where the first transistor chip is arranged and the region where the second transistor chip is arranged. Symmetrical
The position of the first wiring and the position of the second wiring are symmetrical with respect to the dividing line.
The position of the wire connecting the first diode chip and the first branch portion and the position of the wire connecting the second diode chip and the second region are symmetrical with respect to the dividing line.
The position of the P terminal and the position of the N terminal are symmetrical with respect to the dividing line.
The position of the O terminal on one side and the position of the O terminal on the other side are symmetrical with respect to the dividing line .
When the first transistor chip is on and the second transistor chip is off, the wire connecting the P terminal to the first region from the P terminal, the first region, the first transistor chip, and the like. A current flows through the first wiring, the first branch portion, and the wire connecting the two O terminals and the first branch portion to the two O terminals.
When the first transistor chip is in the off state and the second transistor chip is in the on state, a wire connecting the two O terminals and the second branch portion from the two O terminals, the second branch portion, and the like. A semiconductor device in which a current flows through the second transistor chip, the second wiring, the second region, and a wire connecting the second region and the N terminal to the N terminal. A heat sink having one surface in the thickness direction on which the substrate is mounted,
A frame body that rises from one of the surfaces and is arranged so as to surround the substrate when viewed in the thickness direction of the substrate is further provided.
The outer shape of the substrate is a rectangle whose long side extends in the first direction when viewed in the thickness direction of the substrate.
The frame includes a first wall portion and a second wall portion corresponding to a pair of long sides of the substrate, respectively.
The P terminal and the N terminal are arranged on the side opposite to the second short side when viewed from the first short side of the substrate.
The semiconductor device according to claim 1 or 2, wherein the O terminal is arranged on the side opposite to the first short side when viewed from the second short side. A first gate terminal attached to the first wall portion and electrically connected to the gate pad of the first transistor chip.
A second gate terminal attached to the second wall portion and electrically connected to the gate pad of the second transistor chip is further provided.
In the second direction, the distance between the first wall portion and the first region is the distance between the first wall portion and the second region, and the distance between the first wall portion and the first branch. It is smaller than either the distance between the parts and the distance between the first wall part and the second branch part.
In the second direction, the distance between the second wall portion and the second branch portion is the distance between the second wall portion and the first region, and the distance between the second wall portion and the second branch portion. The semiconductor device according to claim 3, which is smaller than either the distance between the regions and the distance between the second wall portion and the first branch portion. A first Kelvin source terminal attached to the first wall portion and electrically connected to the Kelvin source pad of the first transistor chip.
A second Kelvin source terminal attached to the second wall portion and electrically connected to the Kelvin source pad of the second transistor chip is further provided.
In the second direction, the distance between the first wall portion and the first region is the distance between the first wall portion and the second region, and the distance between the first wall portion and the first branch. It is smaller than either the distance between the parts and the distance between the first wall part and the second branch part.
In the second direction, the distance between the second wall portion and the second branch portion is the distance between the second wall portion and the first region, and the distance between the second wall portion and the second branch portion. The semiconductor device according to claim 3 or 4, which is smaller than either the distance between the regions and the distance between the second wall portion and the first branch portion. The first wiring includes a first source wire that electrically connects the source pad of the first transistor chip and the first branch portion.
The second wiring includes a second source wire that electrically connects the source pad of the second transistor chip and the second region.
The length of the first source wire and the length of the second source wire are the same.
The semiconductor device according to any one of claims 1 to 5, wherein the number of the first source wires and the number of the second source wires are the same. The semiconductor device according to any one of claims 1 to 6, wherein at least one of the first transistor chip and the second transistor chip includes a semiconductor layer made of SiC or GaN. The first branch portion is arranged between the first region and the second region in the second direction.
The semiconductor device according to any one of claims 1 to 7, wherein the second region is arranged between the first branch portion and the second branch portion in the second direction. The first region is divided and arranged side by side in the first direction, and the divided portions are electrically connected by wires.
The second region is divided and arranged side by side in the first direction, and the divided portions are electrically connected by wires.
The first branch portion is divided and arranged side by side in the first direction, and the divided portions are electrically connected by wires.
The semiconductor according to any one of claims 1 to 8, wherein the second branch portion is divided and arranged side by side in the first direction, and the divided portions are electrically connected by wires. Device.

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