JP6936558B2 - Signal processing circuits, microcontrollers, hosts, devices - Google Patents

Description

The present invention relates to a microcontroller having a memory and a processor.

An arithmetic processing system including a CPU (Central Processing Unit) 2 is used in various electronic devices. The program executed by the CPU 2 and various data are stored in the ROM (Read Only Memory) 4p. 1 (a) and 1 (b) are block diagrams of the arithmetic processing system examined by the present inventor. In the arithmetic processing system 1r of FIG. 1A, the ROM (Read Only Memory) 4p includes a parallel interface corresponding to the CPU bus 6 of the processor 2.

In recent years, due to the demand for space saving and pin reduction, the replacement of the parallel interface ROM4p with the serial interface ROM4s has been progressing. The CPU 2 cannot directly access the ROM 4s of the serial interface. Therefore, the arithmetic processing system 1s of FIG. 1B further includes a RAM (Random Access Memory) 8. The RAM 8 includes ^{a serial interface such as an I 2} C (Inter IC) interface and an SPI (Serial Peripheral Interface), and the data of the ROM 4s is once read into the RAM 8 and the CPU 2 passes through the CPU bus 6 to the RAM 8 through the CPU bus 6. Access the data stored in.

Japanese Unexamined Patent Publication No. 2011-129017

In the architecture of FIG. 1B, when a program is loaded from the ROM 4s to the RAM 8, if some communication error occurs, the correct program cannot be read into the RAM 8, and if the CPU 2 executes the wrong program, the system becomes abnormal. There is a problem that it works.

The present invention has been made in view of the above problems, and one of the exemplary objects of the embodiment is to provide a microcontroller and a signal processing circuit capable of suppressing a malfunction.

One aspect of the present invention relates to a signal processing circuit. The signal processing circuit includes a processor, a volatile memory, a non-volatile memory for storing a program executed by the processor, and a loader for reading a program from the non-volatile memory and writing the program to the volatile memory. The loader includes a comparator that compares the program written in the volatile memory with the program stored in the non-volatile memory and detects anomalies.

According to this aspect, it is possible to detect the failure and abnormality of the volatile memory, the destruction of the program due to the communication error when the program is loaded from the non-volatile memory to the volatile memory, and the like, and prevent the malfunction.

The comparator may reset the processor when it detects an anomaly. This will allow you to reboot the system and prevent the processor from continuing to run corrupted programs.

The program stored in the non-volatile memory may include an error detection code. The loader may further include an error detector that detects a communication error based on the error detection code contained in the program read from the non-volatile memory.
As a result, it is possible to detect a communication error when loading a program from the non-volatile memory to the volatile memory, and it is possible to improve reliability.

When the error detector detects a communication error, it may prompt the loader to reload the program. The error detector may reset the processor when it detects a communication error.

Another aspect of the invention is also a signal processing circuit. This signal processing circuit includes a processor, a volatile memory, a non-volatile memory for storing a program executed by the processor, and a loader for reading a program from the non-volatile memory and writing the program to the volatile memory. The program stored in the non-volatile memory contains an error detection code, and the loader includes an error detector that detects a communication error based on the error detection code included in the program read from the non-volatile memory.

According to this aspect, it is possible to detect a communication error when loading a program from the non-volatile memory to the volatile memory, and it is possible to improve reliability.

The processor, the volatile memory and the loader are integrated in the first semiconductor chip, and the second semiconductor chip in which the first semiconductor chip and the non-volatile memory are integrated may be incorporated in one module.
"Integration" includes the case where all the components of the circuit are formed on the semiconductor substrate and the case where the main components of the circuit are integrally integrated, and some resistors for adjusting the circuit constants. Or a capacitor or the like may be provided outside the semiconductor substrate.

Another aspect of the invention relates to a host that supplies a bus voltage to the device. The host communicates with the device and negotiates the voltage level of the bus voltage with the receptacle to which the cable is detachably connected, the power supply circuit that generates the bus voltage, and the switch provided between the output of the power supply circuit and the receptacle. At the same time, a signal processing circuit for controlling the switch may be provided.

Another aspect of the invention relates to a device that receives bus voltage from a host. The device communicates with the host, a receptacle to which the cable is detachably connected, a load circuit that operates by receiving the bus voltage, a switch provided between the input of the load circuit and the receptacle, and the voltage level of the bus voltage. It may be provided with a signal processing circuit that controls the switch while negotiating.

Yet another aspect of the present invention relates to a microcontroller connected to a non-volatile memory and executing a program stored in the non-volatile memory. The microcontroller includes a processor, a volatile memory, and a loader that reads a program from the non-volatile memory and writes it to the volatile memory. The loader includes a comparator that compares the program written in the volatile memory with the program stored in the non-volatile memory and detects anomalies.

Yet another aspect of the invention is also a microcontroller. The microcontroller includes a processor, a volatile memory, and a loader that reads a program from the non-volatile memory and writes it to the volatile memory. The program stored in the volatile memory contains an error detection code, and the loader further includes an error detector that detects a communication error based on the error detection code contained in the program read from the non-volatile memory.

The microcontroller may be integrated into one semiconductor chip.

It should be noted that any combination of the above components and those in which the components and expressions of the present invention are mutually replaced between methods, devices, systems and the like are also effective as aspects of the present invention.

According to an aspect of the present invention, malfunction can be suppressed.

1 (a) and 1 (b) are block diagrams of the arithmetic processing system examined by the present inventor. It is a block diagram of the signal processing circuit which concerns on 1st Embodiment. It is a block diagram of the signal processing circuit which concerns on 2nd Embodiment. It is a block diagram of the signal processing circuit which concerns on 3rd Embodiment. It is a block diagram of a host and a device provided with a signal processing circuit.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention, but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected to each other. It also includes the case of being indirectly connected via another member that does not affect the connection state or interfere with the function. Further, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also an electrical connection. It also includes cases of being indirectly connected via other members that do not affect the state or interfere with the function.

(First Embodiment)
FIG. 2 is a block diagram of the signal processing circuit 100 according to the first embodiment. The signal processing circuit 100 includes a non-volatile memory 102, a processor 202, a volatile memory 204, and a loader 206, and is housed in one package. For example, the non-volatile memory 102 is integrated on one semiconductor chip, and the processor 202, the volatile memory 204, and the loader 206 are integrated on another semiconductor chip. The circuit block including the processor 202, the volatile memory 204, and the loader 206 is referred to as a microcontroller 200.

The processor 202 is a CPU (Central Processing Unit) and executes a program. The volatile memory 204 is a RAM (Random Access Memory), which temporarily stores programs and data. The processor 202 and the volatile memory 204 are connected via the CPU bus 210. The non-volatile memory 102 is an EEPROM or a flash memory, and stores a program executed by the CPU 202.

The loader 206 reads a program from the non-volatile memory 102 and writes it to the volatile memory 204. The non-volatile memory 102 includes a serial interface, and the non-volatile memory 102 and the loader 206 are connected via the serial bus 208. The loader 206 has a function of reading back a program once written in the volatile memory 204.

The loader 206 includes a comparator 220. The comparator 220 reads back the program written in the volatile memory 204, compares it with the program stored in the non-volatile memory 102, and detects an abnormality.

The above is the configuration of the signal processing circuit 100. Next, the operation will be described.

The comparator 220 becomes active immediately after the program is loaded by the loader 206. When the comparator 220 becomes active, the comparator 220 reads the corresponding parts of the program from the volatile memory 204 and the non-volatile memory 102, respectively, in units of one word or one byte, and determines whether or not they match. When a discrepancy is detected, it is determined to be abnormal. When the comparator 220 detects an abnormality, it asserts the reset signal RST (for example, high level) and resets the processor 202.

The comparator 220 may be activated at predetermined intervals. The microcontroller 200 may include a timer circuit for measuring a predetermined period.

The above is the operation of the signal processing circuit 100.
According to the signal processing circuit 100, it is possible to detect the failure and abnormality of the volatile memory 204, the destruction of the program due to the communication error when loading the program, and the like, and it is possible to prevent the malfunction.

(Second Embodiment)
FIG. 3 is a block diagram of the signal processing circuit 100a according to the second embodiment. Similar to the signal processing circuit 100 of FIG. 2, the signal processing circuit 100a includes a non-volatile memory 102, a processor 202, a volatile memory 204, and a loader 206a, and is housed in one package.

The program stored in the non-volatile memory 102 includes an error detection code such as CRC (Cyclic Redundancy Check). The loader 206a includes an error detector 222. The error detector 222 detects a communication error based on the error detection code included in the program read from the non-volatile memory 102.

The error detector 222 becomes active when the loader 206a loads the program. When the error detector 222 detects a communication error, the error detector 222 prompts the loader 206a to reload the program. At the time of reloading, the clock frequency may be lowered so that the program can be loaded more reliably. If the load fails a predetermined number of times, the reset signal RST may be asserted to reset the processor 202.

It is desirable that the loader 206a removes the error detection code from the program and writes it to the volatile memory 204. As a result, the capacity of the volatile memory 204 can be saved.

The above is the configuration of the signal processing circuit 100a. Next, the operation will be described. When the signal processing circuit 100a is activated, the loader 206a accesses the non-volatile memory 102 and reads the program from the non-volatile memory 102. Then, the error detector 222 is activated, and the presence or absence of a communication error is determined before the loader 206 writes the program to the volatile memory 204. Then, when no communication error has occurred, the loader 206a writes the program to the volatile memory 204.

The above is the operation of the signal processing circuit 100a. According to the signal processing circuit 100a, the correct program can be written to the volatile memory 204, so that the reliability can be improved.

(Third Embodiment)
FIG. 4 is a block diagram of the signal processing circuit 100b according to the third embodiment. Similar to the signal processing circuit 100 of FIG. 2, the signal processing circuit 100b includes a non-volatile memory 102, a processor 202, a volatile memory 204, and a loader 206b, and is housed in one package. The loader 206b includes a comparator 220 and an error detector 222.

According to the signal processing circuit 100b, the effects of the signal processing circuit 100 and the signal processing circuit 100a of the first and second embodiments can be obtained, and the reliability can be further improved.

(Use)
FIG. 5 is a block diagram of a host 300 and a device 400 including the signal processing circuits 100 (a, b). The device 400 is an electronic device such as a smartphone, a tablet terminal, a digital camera, a portable audio player, and a laptop computer. The host 300 is an electronic device such as a laptop computer, a desktop computer, or a television, or a charging adapter. The host 300 and the device 400 are connected via a cable 500. For example, the host 300 and the device 400 support the USB (Universal Serial Bus) -PD (Power Delivery) standard, and may support USB Type C.

The electronic device 300 supplies the _{bus voltage V BUS} to the device 400 via the cable 500. The host 300 includes a receptacle 302, a power supply circuit 304, a switch 306, and a signal processing circuit 308. A cable 500 is detachably connected to the receptacle 302. The power supply circuit 304 generates a _{bus voltage V BUS} to be supplied to the device 400. The switch 306 is provided between the output of the power supply circuit 304 and the VBUS pin of the receptacle 302. The signal processing circuit 308 controls the on / off of the switch 306.

The device 400 includes a receptacle 402, a switch 404, a load circuit 406, and a signal processing circuit 408. A cable 500 is detachably connected to the receptacle 402. The load circuit 406 includes a DC / DC converter, a battery charging circuit, and the like, and receives _{a bus voltage V BUS from the host 300.} The switch 404 is provided between the receptacle 402 and the input terminal of the load circuit 406. The signal processing circuit 408 controls the on / off of the switch 404.

The signal processing circuit 308 and the signal processing circuit 408 are connected to each other via CC pins, and can communicate with each other. In the USB-PD standard, the host 300 and the device 400 can communicate with each other and negotiate the voltage level of the _{bus voltage V BUS.} Specifically, the signal processing circuit 308 holds a list of bus voltages supported by the host 300. When the host 300 and the device 400 are connected, the signal processing circuit 308 transmits a list to the signal processing circuit 408. The signal processing circuit 408 selects the optimum voltage level for the load circuit 406 from the list and notifies the signal processing circuit 308. The signal processing circuit 308 instructs the power supply circuit 304 to generate the _{bus voltage V BUS} selected by the signal processing circuit 408.

The signal processing circuit 308 and the signal processing circuit 408 can be configured by the signal processing circuit 100 (a, b) described above. The use of the signal processing circuit 100 is not limited to the host 300 and the device 400, and can be used for general purposes.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted without departing from the ideas of the present invention.

100 ... signal processing circuit, 102 ... non-volatile memory, 200 ... microcontroller, 202 ... processor, 204 ... volatile memory, 206 ... loader, 208 ... serial bus, 210 ... CPU bus, 220 ... comparator, 222 ... error detection Instrument, 300 ... Host, 302 ... Receptacle, 304 ... Power circuit, 306 ... Switch, 308 ... Signal processing circuit, 400 ... Device, 402 ... Receptacle, 404 ... Switch, 406 ... Load circuit, 408 ... Signal processing circuit, 500 ... cable.

Claims (10)

With the processor
With volatile memory
A non-volatile memory that stores the program executed by the processor,
A loader that reads the program from the non-volatile memory and writes it to the volatile memory.
With
The program stored in the non-volatile memory contains an error detection code and contains an error detection code.
The loader
An error detector that becomes active during loading of the program and detects a communication error based on the error detection code included in the program read from the non-volatile memory before writing the program to the volatile memory. If the communication error has not occurred, the program is written to the volatile memory, the error detector, and the error detector.
A comparator that becomes active after the loading of the program is completed, compares the program written in the volatile memory with the program stored in the non-volatile memory, and detects an abnormality.
Including
When the error detector detects the communication error, the loader prompts the loader to reload the program, and the loader reloads the program at a clock frequency lower than the previous time. .. The signal processing circuit according to claim 1, wherein the comparator resets the processor when an abnormality is detected. The signal processing circuit according to claim 1 or 2 , wherein the error detector resets the processor when the communication error is detected. The processor, the volatile memory, and the loader are integrated on the first semiconductor chip.
The signal processing circuit according to any one of claims 1 to 3 , wherein the second semiconductor chip in which the first semiconductor chip and the non-volatile memory are integrated is incorporated in one module. A host that supplies bus voltage to the device
With a receptacle to which the cable is detachably connected,
The power supply circuit that generates the bus voltage and
A switch provided between the output of the power supply circuit and the receptacle,
The signal processing circuit according to any one of claims 1 to 4 , which communicates with the device, negotiates the voltage level of the bus voltage, and controls the switch.
A host characterized by having. A device that receives bus voltage from the host
With a receptacle to which the cable is detachably connected,
The load circuit that receives the bus voltage and
A switch provided between the input of the load circuit and the receptacle,
The signal processing circuit according to any one of claims 1 to 4 , which communicates with the host, negotiates the voltage level of the bus voltage, and controls the switch.
A device characterized by being equipped with. A microcontroller that is connected to a non-volatile memory and executes a program stored in the non-volatile memory.
With the processor
With volatile memory
A loader that reads the program from the non-volatile memory and writes it to the volatile memory.
With
The program stored in the non-volatile memory contains an error detection code and contains an error detection code.
The loader
An error detector that becomes active during loading of the program and detects a communication error based on the error detection code included in the program read from the non-volatile memory before writing the program to the volatile memory. If the communication error does not occur, the program is written to the volatile memory, the error detector, and the error detector.
A comparator that becomes active after the loading of the program is completed, compares the program written in the volatile memory with the program stored in the non-volatile memory, and detects an abnormality.
Including
When the error detector detects the communication error, the microcontroller prompts the loader to reload the program, and the loader reloads the program at a clock frequency lower than the previous time. The microcontroller according to claim 7 , wherein the comparator resets the processor when an abnormality is detected. The microcontroller according to claim 7 or 8 , wherein the error detector resets the processor when the communication error is detected. The microcontroller according to any one of claims 7 to 9 , wherein the microcontroller is integrated into one semiconductor chip.

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