JP6935691B2 - Electronic control device - Google Patents

Description

The present invention relates to an electronic control device that generates a pulse width modulated signal (hereinafter referred to as a PWM signal).

Conventionally, an electronic control device that generates a PWM signal starts operation when the CPU gives an instruction to start counting operation of the PWM timer, and when the count value of the PWM timer reaches the stored value of the duty setting register, the level of the PWM signal Is returned, and when the count value of the PWM timer reaches the stored value of the cycle setting register, the counting operation for one cycle of the PWM timer is terminated (see, for example, Patent Document 1).

According to the description of Patent Document 1, a cycle setting register (REGC) for storing the current cycle, a cycle setting register for the next PWM (BFREGC), a duty setting register (REGD), and a duty setting register for the next PWM (BFREGD). , It is possible to transfer the stored value of the next PWM cycle setting register to the cycle setting register and transfer the stored value of the next PWM duty setting register to the duty setting register. There is.

Japanese Unexamined Patent Publication No. 2001-16081

By the way, this kind of electronic control device may accept an immediate output fixed request (for example, an immediate on fixed request or an immediate off fixed request) while maintaining a command cycle of a PWM signal from an upper layer such as an application. Upon receiving these immediate output fixed requests, it is required to immediately forcibly change the output level of the PWM signal to the command fixed level (for example, on level, off level) corresponding to the immediate output fixed request.

However, although the inventors have realized the technique of immediate output fixed request by using the technique described in Patent Document 1, it is necessary to access various registers (storage units) many times, and complicated control must be executed. It has been found that it requires a large amount of processing time. Therefore, it is desired to reduce the processing time as much as possible.

An object of the present invention is that it is not necessary to access various storage units many times, and when an immediate output fixed request is received, the output level of the PWM signal is immediately set to a command fixed level corresponding to the immediate output fixed request. The purpose is to provide an electronic control device that enables it.

According to the invention of claim 1, the command cycle storage unit, the current duty storage unit, the next duty storage unit, the counter, the output unit, the edge polarity switching unit, and the next duty value setting unit are provided. Here, the command cycle storage unit stores the command cycle of the PWM signal. The current duty storage unit stores the command duty value of the current PWM signal. The next duty storage unit is configured to be able to transfer a stored value to the current duty storage unit, and stores the command duty of the next PWM signal. The counter counts up to the cycle count value corresponding to the command cycle stored in the command cycle storage unit.

Normally, the output unit is set to the first level when the counter starts counting from the initial value, and is set to the second level when the counter count value reaches the duty value corresponding to the command duty of the current duty register, and the counter count value is set to the second level. When the cycle count value corresponding to the command cycle of the cycle register is reached, the first level is set again. When the immediate output fixed request is received, the edge polarity switching unit raises / falls to the output level of the output unit according to the command fixed level of the immediate output fixed request while holding the command cycle of the PWM signal in the command cycle storage unit. Toggles whether or not the edge polarity of is changed. Then, when the next duty value setting unit sets a fixed duty value according to the command fixed level of the immediate output fixed request in the next duty storage unit, the fixed duty value is set according to whether or not the edge polarity is changed by the edge polarity switching unit. I try to do it.

Therefore, by setting the fixed duty value according to whether or not the edge polarity is changed by the edge polarity switching unit, the output level of the PWM signal can be immediately set to the command fixed level according to the immediate output fixed request, and various types of storage can be performed. It is no longer necessary to access the units (for example, the command cycle storage unit, the current duty storage unit, and the next duty storage unit) many times, and even when an immediate output fixed request is received, the command fixed level can be set immediately.

Block diagram schematically showing the internal configuration of the electronic control device according to the first embodiment Block diagram schematically showing the internal configuration of the PWM control unit Timing chart showing the output status of a normal PWM output circuit and the change in the value of each storage unit. Timing chart showing the flow when forced duty match is set Flowchart showing the processing content to be executed when an immediate fixed request is received Timing chart showing the output status of the PWM output circuit and the change in the value of each storage unit when an immediate on-fix request is received. Immediate off Timing chart showing the output status of the PWM output circuit and the change in the value of each storage unit when a fixed request is received. Regarding the second embodiment, a flowchart showing a processing content when a normal output return request is received after receiving an immediate fixed request. Immediate off Timing chart when a fixed output request is accepted and then a normal output return request is accepted Timing chart when a normal output return request is received after receiving an immediate on fixed request

Hereinafter, some embodiments of the electronic control device of the present invention will be described with reference to the drawings. In the second and subsequent embodiments, the same or similar parts as those in the first embodiment are designated by the same or similar reference numerals, and the description thereof will be omitted as necessary. Explain to.

(First Embodiment)
1 to 7 show explanatory views of the first embodiment. FIG. 1 shows a connection relationship between a part of electronic control units 1 among a large number of electronic control units (ECUs) mounted on a vehicle, and sensors 2, 3 and solenoid 4.

The electronic control device 1 functions as, for example, an engine ECU, and includes a microcomputer (hereinafter abbreviated as a microcomputer) 5, an input circuit 6, and an output circuit 7 inside. A vehicle speed sensor 2 and a rotation speed sensor 3 are connected to the electronic control device 1. The vehicle speed sensor 2 detects a signal corresponding to the speed of the vehicle and outputs this detection signal to the electronic control device 1. The rotation speed sensor 3 detects a signal corresponding to the rotation speed of the crank sensor (not shown) and outputs this detection signal to the electronic control device 1.

The microcomputer 5 includes a CPU 8 that is a main body of control commands, and a PWM control unit 9 that substantially controls by receiving commands from the CPU 8, and further includes a storage unit (not shown) by RAM, ROM, EEPROM, or the like. This storage unit is used as a non-transitional actual recording medium. The microcomputer 5 inputs a detection signal from the vehicle speed sensor 2 and the rotation speed sensor 3 to the CPU 8 through the input circuit 6, and the CPU 8 is required to PWM drive and control the solenoid 4 according to the program stored in the storage unit. Compute the value. The CPU 8 realizes functions as a next duty value setting unit and a forced duty match setting unit in response to executing a program stored in the storage unit. The CPU 8 outputs this value to the PWM control unit 9, and the PWM control unit 9 outputs a PWM signal through the output circuit 7 to control the solenoid 4 by PWM drive.

FIG. 2 is a block diagram schematically showing the internal configuration of the PWM control unit 9. The PWM control unit 9 includes a command cycle storage unit, a current cycle register 10 as a current cycle storage unit, a next cycle register 11 as a next cycle storage unit, a current duty register 12 as a current duty storage unit, and a next duty storage unit. Next time duty register 13, timer counter (counter equivalent) 14, first comparer 15, second comparer 16, forced duty match generation register 17 as forced duty match command storage unit, edge polarity switching unit 18, and output unit The block is provided by the PWM output circuit 19 as the above.

Period register 10 and the current duty register 12 now is a rewritable register of what can be directly read from the CPU 8, the next cycle register 11 and the next duty register 13 Ri rewritable register der, the next cycle register 11 The stored value can be transferred to the current cycle register 10 by a transfer command, and the stored value of the next duty register 13 can be transferred to the current duty register 12 by a transfer command.

Therefore, in order to update and rewrite the stored values of the current cycle register 10 and the current duty register 12, once the values are rewritten to the next cycle register 11 and the next duty register 13, the values of these registers 11 and 13 are rewritten. Is reloaded into the current cycle register 10 and the current duty register 12, respectively.

The timer counter 14 counts up when a clock signal is input from the CPU 8. The timer counter 14 counts the number of rising or falling edges of the input clock signal. The first comparator 15 compares the counter value of the timer counter 14 with the stored value of the current duty register 12, and when the counter value of the timer counter 14 is lower than the stored value of the current duty register 12, it is normally the first. When one level (for example, "1") is output to the edge polarity switching unit 18 as a comparison result and the counter value of the timer counter 14 becomes equal to or higher than the current storage value of the duty register 12, the second level (for example, "0") is normally used. ) Is output to the edge polarity switching unit 18 as a comparison result.

The first comparator 15 connects the forced duty match generation register 17 as a forced duty command storage unit. In the forced duty match generation register 17, even if the counter value of the timer counter 14 is lower than the current storage value of the duty register 12, the timer counter 14 has a flag for the duty match command set by the CPU 8. It has a function to forcibly consider and match the count value with the command duty of the current duty register 12, and change the comparison result of the first comparator 15 to the second level (for example, "0") to switch the edge polarity. This is a compulsory command register to be output to unit 18.

The second comparator 16 compares the counter value of the timer counter 14 with the stored value of the current cycle register 10, and when, for example, the counter value of the timer counter 14 is lower than the stored value of the current cycle register 10, the second comparator 16 is normally used. When the second level (for example, "0") is output to the edge polarity switching unit 18 as a comparison result and the counter value of the timer counter 14 becomes equal to or higher than the stored value of the current cycle register 10, the first level (for example, "1") is normally used. ”) Is output to the edge polarity switching unit 18 as a comparison result. The edge polarity switching unit 18 can switch the rise / fall edge polarity by a polarity switching command input from the CPU 8. The edge polarity switching unit 18 sets either the output level "ON" or "OFF" according to the output of the first and second comparators 15 and 16 and the polarity switching command, and outputs the output to the PWM output circuit 19.

Therefore, when the PWM output circuit 19 outputs the set output level (for example, on level “ON”, off level “OFF”), the output circuit 7 outputs a voltage corresponding to the output levels “ON” and “OFF”. By applying the voltage to the solenoid 4, the solenoid 4 can be controlled by PWM drive.
A specific example of the operation of the above-described configuration will be described with reference to the drawings of FIGS. 3 and 3 onward.

<About normal operation>
Normally, when the CPU 8 sets values in the next cycle register 11 and the next duty register 13, and the values are transferred to the current cycle register 10 and the current duty register 12, the PWM control unit 9 sends these registers 10. It operates based on the values stored in ~ 13 and outputs a PWM signal.

For example, as shown in FIG. 3, the CPU 8 sets T in the next cycle register 11 and T / 2 in the next duty register 13 as command cycles and command duties, and further sets T in the current cycle register 10 and T in the current duty register 12. The case where the T / 2 is transferred will be described as an example. As described above, the edge polarity by the edge polarity switching unit 18 can be switched and set to rise / fall, but in the example, the initial state is set to the rise edge.

When a clock signal is given from the CPU 8, the timer counter 14 counts up from the initial value (for example, 0) and counts until the stored value T of the current cycle register 10 is reached (see periods Ta, Tb, etc. in FIG. 3).

When the timer counter 14 starts counting, the second comparator 16 compares the stored value T of the current cycle register 10 with the counter value of the timer counter 14, and the counter value of the timer counter 14 is the stored value T of the current cycle register 10. The second level "0" is output when the value falls below. The first comparator 15 compares the current storage value T / 2 of the duty register 12 with the counter value of the timer counter 14, and when the counter value of the timer counter 14 is lower than the current storage value T / 2 of the duty register 12. The first level "1" is output. Therefore, the edge polarity switching unit 18 outputs the on-level “ON” by outputting the rise edge of the first level “1” output by the first comparator 15, and in response to this, the PWM output circuit 19 Outputs the on-level "ON" (see period Ta in FIG. 3).

When the count value of the timer counter 14 reaches T / 2, this value T / 2 currently matches the stored value T / 2 of the duty register 12, so that the first comparator 15 outputs the second level "0". .. It should be noted that the fact that the count value of the timer counter 14 matches the value corresponding to the duty is hereinafter referred to as "duty match" as necessary.

The edge polarity switching unit 18 outputs an off level “OFF” by outputting a rise edge of the second level “0” output by the first comparator 15, and the PWM output circuit 19 corresponds to the off level. Output "OFF". As a result, when the counter value of the timer counter 14 reaches the duty value T / 2 corresponding to the command duty of the duty register 12, the off level “OFF” is output (see the period Tb in FIG. 3).

Further, when the count value of the timer counter 14 reaches T, this value T matches the stored value T of the current cycle register 10, so that the second comparator 16 outputs the first level “1”. It should be noted that the fact that the count value of the timer counter 14 matches the value corresponding to the cycle is hereinafter referred to as "cycle match" as necessary.

The timer counter 14 inputs the output level “1” of the second comparator 16 and clears the timer counter 14 to an initial value (for example, 0). When the CPU 8 counts the count value T of this clock signal and makes a cycle match, it determines that one cycle has elapsed, reloads the stored value of the next cycle register 11 into the current cycle register 10, and reloads the stored value of the next duty register 13. Is currently reloaded into the duty register 12.

Therefore, normally, when the timer counter 14 starts counting from the initial value 0, the PWM output circuit 19 sets the first level to "1" when counting starts from the initial value, and the count value of the timer counter 14 is currently set to the duty register 12. When the duty value corresponding to the command duty is reached, the second level is set to "0", and when the count value of the timer counter 14 reaches the cycle count value corresponding to the command cycle T of the current cycle register 10, the first level "1" is set again. Is output.

Therefore, in the periods Ta and Tb of FIG. 3, when the next duty register 13 is set to the value T / 2, the value T / 2 of the next duty register 13 becomes the current duty register 12 at the beginning of the period Tc. The PWM output circuit 19 outputs a PWM signal having a period T and a duty value T / 2 (duty ratio 50%) even during the periods Tc and Td.

When the CPU 8 sets the value T / 4 in the next duty register 13 in the period Tc or the period Td, the value T / 4 of the next duty register 13 is the current duty register 12 in the output periods Te and Tf of the next PWM signal. Will be transferred to. Therefore, the PWM output circuit 19 outputs a PWM signal having a period T and a duty value T / 4 (duty ratio 25%) in the periods Te and Tf.

Although detailed description is omitted here, the CPU 8 sets a value different from the value T (for example, 2.T) in the next cycle register 11 at the output start timing of the PWM signal in the next cycle. The value 2 · T of the next cycle register 11 is reloaded into the current cycle register 10. At this time, the PWM output circuit 19 outputs a PWM signal having a period of 2 · T.

<Basic function of forced duty match>
When the CPU 8 sets a flag in the forced duty match generation register 17, the first comparator forcibly generates a compare match between the timer counter 14 and the current duty register 12 according to the set flag of the forced duty match generation register 17. be able to.

Therefore, as shown in FIG. 4, when the CPU 8 sets the flag in the forced duty match generation register 17 while the PWM output circuit 19 is outputting the on-level “ON”, regardless of the comparison result of the first comparator 15. , The first comparator 15 forcibly outputs the second level "0", and the edge polarity switching unit 18 turns off by outputting the output "0" of the first comparator 15 as the rise edge polarity. The level "OFF" is output, and in response to this, the PWM output circuit 19 continues to output the off level "OFF" until the next PWM signal is started to be generated. As a result, the output level can be fixed to the off level "OFF" without setting the next value in the duty register 13 next time, which is particularly convenient when immediacy is required when outputting the fixed off level "OFF". good. The flag of the forced duty match generation register 17 is immediately cleared in terms of hardware by ending the forced duty match setting process (see FlagSET in FIG. 4).

<Output level fixing function according to immediate fixing request>
As described above, when the CPU 8 sets a flag in the forced duty match generation register 17, a compare match between the timer counter 14 and the current duty register 12 can be forcibly generated, but the PWM output circuit 19 is turned off. When the output is forcibly switched to the on-level "ON" output while the "" is being output, the first comparator 15 sets the second level "0" even if the flag is set in the forced duty match generation register 17. The output will be forcibly continued, and the PWM output circuit 19 will continue to output the off level "OFF".

Therefore, in order to improve convenience in the present embodiment, the CPU 8 corresponds to both the on-level “ON” and the off-level “OFF” of the command fixed level of the immediate fixing request from the upper layer by the application. Execute the process shown in the flowchart of.

First, as shown in FIG. 5, the CPU 8 determines whether the command fixed level of the immediate fixing request is the on level “ON” or the off level “OFF” (S100). At this time, if the command fixed level is the ON level "ON" in S100, the CPU 8 once sets the duty ratio to 100% (S101), and then shifts to S103. That is, if the stored value of the current cycle register 10 is set to the value T, the CPU 8 sets the duty value T corresponding to the duty ratio 100% of the value T of this cycle to the next duty register 13 and then sets it to S103. Transition. On the contrary, if the command fixed level is the off level "OFF" in S100, the CPU 8 sets the duty ratio to 0% (S102) and then shifts to S103. That is, the CPU 8 sets the value 0 in the duty register 13 next time in S102 and shifts to S103.

<When the spare time cannot be secured at the time of processing S103>
Here, the CPU 8 determines whether or not the time until the periodic match is equal to or longer than the predetermined margin time (S103) at the time of executing the process of S103, and if it is not longer than the margin time (NO), this It exits the processing routine and waits until the transfer processing of the next cycle register 11 and the next duty register 13. Here, the condition that "there is more than the margin time" is that the former is more than the latter time by comparing "the time obtained by subtracting the current time from the scheduled time of the next periodic match" and "the time required for setting". The conditions are shown.

Once the processing routine is exited and the transfer processing is started, the values of the next cycle register 11 and the next duty register 13 are reloaded into the current cycle register 10 and the current duty register 12, respectively, at the output start timing of the PWM signal in the next cycle. ..

As a result, the PWM output circuit 19 fixedly outputs a PWM signal having a duty ratio of 100% or 0%, that is, an on-level “ON” or an off-level “OFF”. The CPU 8 can respond to an immediate fixed request at least at the next PWM signal output start timing when the time until the periodic match <the margin time, and can output this fixed level "ON" or "OFF". become.

<When a margin time can be secured at the time of processing S103>
On the other hand, when the processing of S103 is being executed, if the time until the periodic match is longer than the margin time (S103: YES), the CPU 8 executes the processing according to the set duty ratio (S105a, S106a). , S107: S105b, S106b).

<< When the command fixed level of the immediate fixing request is on level "ON": Fig. 6 >>
In FIG. 5, when the command fixed level is the on level “ON” and the duty ratio is set to 100% in S101, the CPU 8 determines YES in S104 and issues a polarity change command to the edge polarity switching unit 18 ( S105a), turn on the edge polarity change flag (S106a), set the next duty ratio to the value of the timer counter 14 corresponding to 0%, that is, the value 0 (S107), and set the flag in the forced duty match generation register 17. (S108).

When the CPU 8 gives an edge polarity change command in S105a, as shown in FIG. 6, the edge polarity switching unit 18 switches and changes the rise edge to the fall edge. Then, the CPU 8 turns on the edge polarity change flag in S106a, and sets the value 0 in the next duty register 13 in order to set the duty ratio to 0% in S107. Then, when the CPU 8 sets a flag in the forced duty match generation register 17 in S108, the first comparator 15 forcibly outputs the second level "0" regardless of the comparison result of the first comparator 15. The edge polarity switching unit 18 outputs the on-level “ON” by outputting the output level “0” of the first comparator 15 as a fall edge, and the PWM output circuit 19 outputs the on-level “ON” accordingly. (See timing t1 in FIG. 6). The flag of the forced duty match generation register 17 is cleared immediately in terms of hardware.

After that, at the time of the next cycle match, as shown in the timing t2 of FIG. 6, the stored value 0 of the next duty register 13 is reloaded to the current duty register 12 and the duty ratio is set to 0%, and even after this timing t2. , The on-level "ON" that is output in response to the immediate fixed request continues to be output.

As a result, the PWM output circuit 19 continues to output the on-level "ON" in response to the on-level "ON" of the command fixed level of the immediate fixing request. In this way, when the on-level "ON" is continuously output, the current cycle register 10 and the next cycle register 11 are not changed, so that the cycle match is repeated while maintaining the command cycle T at the time of receiving the request.

<< When the command fixing level of the immediate fixing request is the off level "OFF": Fig. 7 >>
In FIG. 5, when the command fixed level is the off level “OFF” and the duty ratio is set to 0% in S102, the command fixed level “OFF” is actually output by the PWM output circuit 19. Equal to the off level "OFF". Therefore, the edge switching process by the edge polarity switching unit 18 becomes unnecessary.

Therefore, the CPU 8 maintains the polarity by the edge polarity switching unit 18 (S105b: described with a broken line), and leaves the edge polarity change flag off (S106b: described with a broken line). The portion described by the broken line is not shown on the program code, and the processing time is substantially not required. Then, the CPU 8 sets a flag in the forced duty match generation register 17 (S108).

The CPU 8 holds the edge polarity in S105b, keeps the polarity change flag off in S106b, and sets the flag in the forced duty match generation register 17 in S108. Then, regardless of the comparison result of the first comparator 15, the first comparator 15 forcibly outputs the second level "0", and the edge polarity switching unit outputs the output "0" of the first comparator 15. By outputting "0" as a rise edge, the off-level "OFF" is continuously output. In response to this, the PWM output circuit 19 outputs an off level “OFF” (see timing t3 in FIG. 7).

After that, at the time of the next cycle match, the value 0 of the next duty register 13 is reloaded to the current duty register 12, and the off level "OFF" continues to be output even after that (see the timing t4 and later in FIG. 7). .. As a result, the PWM output circuit 19 continues to output the off level "OFF" in response to the immediate off fixing request. Even when the off-level "OFF" is continuously output in this way, the current cycle register 10 and the next cycle register 11 are not changed, so that the cycle match is repeated while maintaining the command cycle T at the time of receiving the request.

In this way, the only registers that the CPU 8 should update and set are the next duty register 13, the setting register of the edge polarity switching unit 18, and the forced duty match generation register 17, so that the number of register accesses can be reduced and control is simplified. Even when a non-rewritable microcomputer 5 is used for the current cycle register 10 and the current duty register 12, it is possible to immediately respond to an immediate output fixed request while fixing the current cycle T.

<Conceptual summary of this embodiment>
In short, according to the present embodiment, it has the following configuration and action / effect. The current cycle register 10 stores the command cycle (for example, T) of the PWM signal, and the current duty register 10 stores the command duty (for example, T / 2) of the current PWM signal. The next duty register 13 is currently configured to be able to transfer a stored value to the duty register 12. The timer counter 14 counts up to a cycle count value (for example, T) corresponding to the command cycle stored in the current cycle register 10.

Normally, the PWM output circuit 19 sets the ON level to "ON" when the timer counter 14 starts counting from the initial value, and the count value of the timer counter 14 reaches a duty value (for example, T / 2) according to the command duty. When it is done, the off level is set to "OFF" again. Further, when the count value of the timer counter 14 reaches the cycle count value T corresponding to the command cycle T of the current cycle register 10, the ON level “ON” is output again.

Further, when the edge polarity switching unit 18 receives the immediate output fixed request, the edge polarity switching unit 18 raises the output level according to the command fixed level of the immediate output fixed request while holding the command cycle T of the PWM signal in the current cycle register 10. Whether or not the edge polarity of the fall is changed is switched (S105a, S105b).

Then, the CPU 8 sets a fixed duty value according to the command fixed level “ON” or “OFF” in the next duty register 13, but when setting this fixed duty value, it depends on whether or not the edge polarity is changed by the edge polarity switching unit 18. The fixed duty value "0" is set in the next duty register 13 (S102, S107).

For example, when the command fixed level is the on level “ON”, the edge polarity switching unit 18 changes the edge polarity to the fall edge (S105a), and sets the fixed duty value “0” in the next duty register 13. (S107). On the contrary, for example, when the command fixed level is the off level "OFF", the fixed duty value "0" is set in the next duty register 13 while holding the edge polarity at the rise edge by the edge polarity switching unit 18 (S105b). (S102). Therefore, by setting the command duty value "0" according to whether or not the edge polarity is changed when the command fixed levels "ON" and "OFF" are received in the next duty register 13, the PWM signal by the PWM output circuit 19 can be obtained. The output level can be fixed to the on level "ON" or the off level "OFF", respectively.

As a result, the edge polarity is changed as necessary by the edge polarity switching unit 18, and the output level of the PWM signal is immediately turned on or turned “ON” by setting the fixed duty value “0” in the duty register 13 next time. Can be fixed to the off level "OFF". As a result, the number of times the register is accessed can be reduced and the processing speed can be improved.

For example, when the command fixed level is the ON level “ON”, the CPU 8 sets a flag in the forced duty match generation register 17 after changing the edge polarity by the edge polarity switching unit 18. Therefore, even if the command fixed level “ON” and the output state “OFF” after the occurrence of the duty match are different, the output level can be immediately fixed to the on level “ON”.

For example, when the command fixed level is the off level “OFF”, the CPU 8 sets a flag in the forced duty match generation register 17 under the condition that the edge polarity is maintained by the edge polarity switching unit 18. Therefore, the output level can be immediately fixed to the off level "OFF" simply by setting the duty ratio and setting the forced duty match.

Further, according to the present embodiment, the edge polarity switching unit 18 changes the edge polarity as necessary, sets a flag in the forced duty match generation register 17, forcibly performs duty matching, and sets it in the next duty register 13. By transferring the current duty value "0" to the current duty register 12, the PWM output circuit 19 can immediately output a fixed output level "ON" or "OFF". Therefore, even if the current cycle register 10 and the current duty register 12 are readable and unrewritable, the requirement can be satisfied.

(Second Embodiment)
8 to 10 show additional explanatory views of the second embodiment. In the second embodiment, when the immediate output fixed request is received, the edge polarity is changed by the edge polarity switching unit 18 according to the command fixed level of the immediate output fixed request, and then the immediate output fixed request is released to the normal output. When the normal output return request for recovery is received, the feature is that the edge polarity is restored. In this embodiment, the CPU 8 has a function as an edge polarity restoration unit.

As shown in the first embodiment, when the CPU 8 receives the immediate output fixing request, the edge polarity switching unit 18 changes or holds the edge polarity to fall edge / rise edge according to the command fixing level. Therefore, even after the output level of the PWM output circuit 19 is fixed, it is desirable that the normal PWM signal can be restored when the output is desired to be restored according to the set cycle and the set duty ratio. Therefore, in the present embodiment, when the CPU 8 receives the normal output return request after fixing the output to the command fixed level, the CPU 8 can return to the normal process by executing the process shown in FIG.

<When the normal output return request is received after receiving the immediate off fixed request "OFF">
FIG. 9 schematically shows a timing chart when a normal output return request is received after receiving an immediate off fixed request. In FIG. 9, a PWM signal having a period T1 and a duty value T1 / 2 (duty ratio 50%) is output from the on level “ON” after the timing t11, and at the timing t12, according to the current duty register value T1 / 2. After changing the output to the off level "OFF", an immediate off fixed request is received at timing t13, and then a PWM signal with a period T2 and a duty value T2 / 2 (duty ratio 50%) is output return request at timing t14. Is shown as an example of accepting.

When the CPU 8 receives an immediate fixed request of the fixed request level “OFF” from the application of the upper layer at the timing t13 of FIG. 9, the edge polarity is maintained by the edge polarity switching unit 18 in S105a of FIG. 5, and the polarity change flag is turned off. In S108, the flag is set in the forced duty match generation register 17. As a result, the output of the PWM output circuit 19 can be fixed to "OFF" (timing t13 or later in FIG. 9).

After that, when the CPU 8 receives the normal output return request at the timing t14 of FIG. 9, the CPU 8 determines whether or not the edge polarity change flag is turned on in S201 of FIG. Then, when it is confirmed that the edge polarity change flag is turned off in S201, it is determined as NO in S201, and the cycle register value of the next cycle register 11 and the next duty register 13 in S206 without changing the edge polarity. The duty value update process is started.

That is, at the timing t14 of FIG. 9, the CPU 8 sets the value T2 in the next cycle register 11, sets the value T2 / 2 corresponding to the duty ratio of 50% in the next duty register 13, and elapses the subsequent cycle T1. At the timing t15, the value of the next cycle register 11 is reloaded to the current cycle register 10, and the value of the next duty register 13 is reloaded to the current duty register 12. As a result, the value T2 of the current cycle register 10 and the value T2 / 2 of the current duty register 12 can be updated, and after this timing t15, the PWM output circuit 19 of these values T2 of the current cycle register 10 and the current duty register 12 A PWM signal corresponding to the value T2 / 2 can be output. The period values T1 and T2 may be the same or different from each other.
<When the normal output return request is received after receiving the immediate ON fixed request "ON">

FIG. 10 schematically shows a timing chart when a normal output return request is received after receiving an immediate on-fixed request. In FIG. 10, a PWM signal having a period T1 and a duty value T1 / 2 (duty ratio 50%) is output from the on level “ON” after the timing t11, and at the timing t12, according to the current duty register value T1 / 2. After changing the output to the off level "OFF", the immediate on fixed request is received at the timing t23 to change the output to the on level "ON", and then at the timing t24, the period T2 and the duty value T2 / 2 (duty). An example is shown in the case where the output return request is received for the PWM signal (ratio 50%).

On the other hand, when the CPU 8 receives an immediate fixed request of the fixed request level “ON” from the application of the upper layer at the timing t23 of FIG. 10, it issues an edge polarity change command to the edge polarity switching unit 18 in S105a of FIG. The polarity change flag is turned on, the value corresponding to the duty ratio of 0% (that is, 0) is set in the next duty register 13 in S107, and the flag is set in the forced duty match generation register 17 in S108. Therefore, the on-level “ON” can be fixedly output while the edge polarity by the edge polarity switching unit 18 is set as the fall edge (see the timing t23 in FIG. 10). After this, the PWM output circuit 19 continues to output the on-level "ON".

After that, when the CPU 8 receives the normal output return request at the timing t24 of FIG. 10, the CPU 8 has an edge polarity on condition that the time until the periodic match is secured for a margin time or more (YES in S202 of FIG. 8). Is restored (S203). That is, the CPU 8 returns and changes the edge polarity to the rise edge by issuing a polarity return command to the edge polarity switching unit 18.

Then, the CPU 8 sets the duty ratio to 100% in S204. Since the value of the current cycle register 10 is set to T1 at the time of S204, the value corresponding to 100% of the duty ratio, that is, the same value T1 as the value of the current cycle register 10 is set in the next duty register 13. .. Then, the CPU 8 changes the edge polarity change flag to off in S205 (see timing t24 in FIG. 10).

The reason why the duty ratio is once set to 100% in step S204 is that a periodic match occurs between changing the edge polarity flag to restore the edge polarity and updating the duty to the actual value. This is because the case is assumed. In this case, for example, after changing the edge polarity, if a cycle match occurs while "0" corresponding to the fixed on request is set in the duty register 13 next time, a PWM signal with a duty of 0% is output for one cycle. Become. In order to prevent the output level "OFF" opposite to the output level "ON" corresponding to the fixed on request from being output for one cycle, once the duty ratio is set to 100%, then the edge polarity change flag is set in S205. It is set to off.

Then, the CPU 8 updates both the current cycle register 10 and the current duty register 12 in S206. For example, when setting the value T2 / 2 having a cycle T2 and a duty ratio of 50%, the CPU 8 sets the value T2 in the next cycle register 11 and sets the set value T2 / 2 corresponding to the duty ratio 50% to the next duty. It is set in the register 13 (see timing t24 in FIG. 10). Then, the CPU 8 reloads the stored value T2 of the next cycle register 11 into the current cycle register 10 at the timing t25 that causes a cycle match according to the count of the timer counter 14, and sets the stored value T2 / 2 of the next duty register 13 to the current. Reload to duty register 12. As a result, the value T2 of the current cycle register 10 and the value T2 / 2 of the current duty register can be updated, and after this timing t25, the PWM output circuit 19 has these values T2 of the current cycle register and the value T2 / of the current duty register. The PWM signal corresponding to 2 will be output.
<Conceptual summary of the present embodiment>

In short, according to the present embodiment, when the edge polarity is changed by the edge polarity switching unit 18 in response to the command fixing level “ON” of the immediate output fixing request when the immediate output fixing request is received, the immediate on output is fixed. When the normal output return request for canceling the request and returning to the normal output is received, the edge polarity is restored (S203). Therefore, even if the edge polarity is changed by the edge polarity switching unit 18 in response to the immediate output fixing request, the edge polarity is restored when the normal output return request is received, so that the PWM signal can be output as usual. Will be.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and for example, the following modifications or extensions are possible. The configurations and functions of the plurality of embodiments described above may be combined. An embodiment in which a part of the above-described embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, any conceivable embodiment can be regarded as an embodiment without departing from the essence of the invention specified by the wording described in the claims.

Although the present disclosure has been described in accordance with the above-described embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure also includes various modifications and modifications within a uniform range. In addition, various combinations and forms, as well as other combinations and forms, including one element, more, or less, are also within the scope and ideology of the present disclosure.

In the drawing, 8 is a CPU (next duty value setting unit, forced duty match setting unit, edge polarity restoration unit), 10 is a current cycle register (command cycle storage unit), 12 is a current duty register (current duty storage unit), and 13 Is the next duty register (next duty storage unit), 14 is the timer counter (counter), 17 is the forced duty match generation register (forced duty match command storage unit), 18 is the edge polarity switching unit, and 19 is the PWM output circuit (output unit). ), Indicates.

Claims (7)

A command cycle storage unit (10) that stores the command cycle of the PWM signal, and
The current duty storage unit (12) that stores the command duty value of the current PWM signal, and
The next duty storage unit (13), which is configured to be able to transfer the stored value to the current duty storage unit and stores the command duty of the next PWM signal,
A counter (14) that counts up to the cycle count value corresponding to the command cycle stored in the command cycle storage unit, and
Normally, when the counter starts counting from the initial value, the first level is set, and when the count value of the counter reaches the duty value corresponding to the command duty of the current duty storage unit, the second level is set, and the count value of the counter is set. When the cycle count value corresponding to the command cycle of the command cycle storage unit is reached, the output unit (19) is set to the first level again.
A command fixed level that sets the output level of the output unit to the command fixed level of the immediate output fixed request when the command fixed level of the immediate output fixed request is received while holding the command cycle of the PWM signal in the command cycle storage unit. Setting unit (8) and
The instruction fixed in response to a command fixed level of the set by the level setting section immediately output fixing request to switch the change whether the rise / fall of the edge polarity output level of the output edge polarity switching unit (18, S105a, S105b) and
It is a block that sets a fixed duty value according to the command fixed level of the immediate output fixed request in the next duty storage unit, and when the fixed duty value is set, it depends on whether or not the edge polarity is changed by the edge polarity switching unit. Next-time duty value setting unit (8, S102, S107) to set a fixed duty value,
An electronic control device comprising. When the flag is set, the forced duty match command storage unit (17) forcibly regards and matches the count value of the counter with the command duty of the current duty storage unit, and
While changing the polarity by the edge polarity switching unit (S105a), a flag is set in the forced duty match command storage unit (S108), and the forced duty match setting unit (8)
The electronic control device according to claim 1, further comprising. When the flag is set, the forced duty match command storage unit (17) forcibly regards and matches the count value of the counter with the command duty of the current duty storage unit, and
The forced duty match setting unit (8), which sets a flag in the forced duty match command storage unit (S108) while maintaining the polarity of the edge polarity switching unit without changing it (S105b),
The electronic control device according to claim 1, further comprising. When the command fixing level of the immediate output fixing request is on level, the next command duty value is set to 0 in the next duty storage unit while changing the polarity by the edge polarity switching unit (S105a) (S107). After that, the electronic control device according to claim 2 is set with a flag in the forced duty match command storage unit by the forced duty match setting unit (S108). When the command fixing level of the immediate output fixing request is off level, the next command duty value is set to 0 in the next duty storage unit while maintaining the polarity by the edge polarity switching unit (S105b) (S102). After that, the electronic control device according to claim 3 is set with a flag in the forced duty match command storage unit by the forced duty match setting unit (S108). The next duty value setting unit (8) is composed of a CPU.
Before SL current duty storage portion is directly readable and rewritable from the CPU, and the next duty storage portion is directly rewritable constructed from the CPU,
A claim in which the fixed duty value of the next duty storage unit is transferred to the current duty storage unit by the CPU setting a fixed duty value corresponding to the command fixed level of the immediate output fixed request in the next duty storage unit. Item 5. The electronic control device according to any one of Items 1 to 5. When the edge polarity is changed by the edge polarity switching unit according to the command fixing level of the immediate output fixing request when the immediate output fixing request is received, the immediate output fixing request is canceled and the normal output is restored. The electronic control device according to any one of claims 1 to 6, further comprising an edge polarity restoration unit (8, S203) that restores the edge polarity when a normal output return request is received.

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