JP6922576B2 - Synchronous control method of inverter system and inverter system - Google Patents

Description

The present invention relates to a technique for establishing a common synchronization timing by using a serial transmission line for interconnection operation of a plurality of inverters using pulse width modulation.

"IEEE 1588: 2008" is known as a method (high-precision time protocol) that realizes synchronization between two masters / slaves using serial communication. This synchronization method has a reference timer individually, measures the transmission time and the reception time, respectively, and further, the measurement is performed by transmitting the time information to each other by communication. Assuming that the delay times of the bidirectional transmission lines are equal, the delay times of the serial transmission lines are calculated and corrected so that the synchronization timings of the serial transmission lines are exactly matched (Patent Document 1).

Further, EtherCAT (registered trademark) and the like are known as a synchronization method for a large number of devices. This starts the transmission of serial communication data from the master, transmits a plurality of slaves in order, returns it at the terminal slave, and returns it to the master via the plurality of slaves. Then, the time of bidirectional (transmission and reception) communication between each slave is measured, and the time information is transmitted in order to match the synchronization timing between a large number of units.

In general serial communication such as RS-232C, technologies such as asynchronous communication and synchronism detection are used.

In recent years, 8B10B encoding and clock data recovery (CDR) circuits have come to be used as transmission methods such as USB3 and PCI-Expree.

The 8B10B code converts 8-bit data (1 byte) into 10-bit data and transmits it as serial data. Byte data (256 types) and about 10 special codes are transmitted by utilizing the redundancy increased by 2 bits. The 10-bit data is appropriately selected, and the byte data is selected so that the number of consecutive "1" or "0" is up to 4 bits.

As a result, since the 10-bit data always contains several state changes, it is possible to restore the transmission clock (clock recovery) from the serial data. Since the frequencies [bps] of the transmission signals are known to each other, the sample timing can be generated by adjusting the sample time (corresponding to the phase of the PLL) by applying PLL control or the like based on the data change time as a synchronization reference.

Since the sample timing is determined based on the edge of the start bit in the pace synchronization detection and the like, erroneous packet data may be received if a large amount of jitter or noise is mixed.

On the other hand, when sample timing is generated from continuous transmission signals by PLL control, the timing information of many bits is statistically processed, so it is not easily affected by jitter and even if single noise occurs. The data only becomes abnormal and does not affect the next sample of received data.

In other words, from the viewpoint of synchronization timing, even in a transmission line where jitter exists, there is a feature that accurate time detection with statistical processing becomes possible, and since the influence of noise is not dragged, it is possible to repeat after a transmission abnormality. You can also return to synchronization at high speed.

Regarding the special code, the code in which "1" or "0" is continuous for 5 bits can be limited to the special code (K28.5, com). Then, instead of asynchronous communication (data is transmitted intermittently with a pause period in between), cyclic communication (data is always transmitted) is used, continuous transmission data is divided into blocks at equal intervals, and a COM code is inserted between them. do. By doing this, if a code in which "1" or "0" is continuous for 5 bits is detected, the COM code can be reliably separated, which not only replaces the start bit and stop bit of asynchronous communication, but also has a constant cycle. Even if COM is erroneously detected due to noise, it can be easily identified as abnormal by using the consistency of the occurrence time. As a result, it is possible to identify the code delimiter in units of 10 bits and the block data delimiter, so data restoration (data recovery) can be performed by demarcating continuous serial data.

The method of performing sample timing and data separation using the information embedded in the serial data as described above is called "clock data recovery (CDR)", and many studies and practical applications have already been carried out. ..

JP-A-2007-295647

"IEEE 1588: 2008" and "EtherCAT" adopt high-speed communication standards such as 100BASE-TX, which is a network technology called Ethernet (registered trademark), and this has the following problems. In order to realize a communication speed of 100 Mbps, a dedicated circuit such as PHY (physical layer of communication circuit) is required. In addition, since the communication protocol is also Ethernet compliant, the bucket configuration is complicated and the amount of data transmitted per packet is large, so it cannot be effectively used for small-scale, small-volume transmission systems. There is a lot of wasted overhead.

In view of the above circumstances, it is an object of the present invention to reduce unnecessary overhead and improve synchronization accuracy in a small-scale data transmission line applied to a carrier synchronization system.

Therefore, one aspect of the present invention is a synchronous control method for an inverter system having at least two or more inverter units.
The master circuit of one inverter unit, which is the master, synchronizes with the first carrier synchronization signal until the synchronization code indicating the synchronization timing and the slave circuit of the other inverter unit, which is the slave, receive and detect the synchronization code. Serial data including the predicted delay time and carrier cycle command of the other inverter unit is transmitted to the slave circuit of the other inverter unit.
The slave circuit of the other inverter unit generates the first reception timing signal of the synchronization code at the time when the synchronization code of the serial data is normally received or the entire block data including the synchronization code is received. Next, a second carrier synchronization signal is generated based on the first reception timing signal, the carrier cycle command, and the predicted delay time, and the second carrier synchronization signal is based on the time difference between the timings of the first reception timing signal and the second carrier synchronization signal. The difference time is measured, and then, in synchronization with the second carrier synchronization signal, the synchronization code and the serial data including the second difference time are transmitted as reply data to the master circuit of the one inverter unit.
The master circuit of one of the inverter units generates a second reception timing signal of the synchronization code at the time when the synchronization code of the reply data is normally received or when the entire block data including the synchronization code is received. Next, the first difference time based on the time difference between the second reception timing signal and the first carrier synchronization signal is measured, and the predicted delay time is corrected based on the first difference time and the second difference time.
The carrier generation comparator of the one inverter unit performs pulse width modulation based on the first carrier signal synchronized with the first carrier synchronization signal, and then performs pulse width modulation.
The carrier generation comparator of the other inverter unit performs pulse width modulation based on the second carrier signal synchronized with the second carrier synchronization signal.

In one aspect of the present invention, the slave circuit of the other inverter unit performs synchronous control to match the second difference time with the predicted delay time, and the master circuit of the one inverter unit performs the first difference. Synchronous control is performed to match the time with the second difference time.

In one aspect of the present invention, the master circuit of the one inverter unit has a synchronous control for matching the first difference time and the second difference time, and a synchronization control for matching the second difference time with the predicted delay time. And instead of correcting the predicted delay time based on the first difference time and the second difference time and storing it in the reply data, the second difference time and the predicted delay time are matched. The value of the output signal of the synchronous control to be caused is stored in the reply data, and the slave circuit of the other inverter unit has the first reception timing signal, the carrier cycle command, the second difference time, and the predicted delay time. The second carrier synchronization signal is generated based on the value of the output signal of the synchronization control that matches.

In one aspect of the present invention, the master circuit of the one inverter unit has a first frequency dividing circuit that divides the reference clock, and the first carrier synchronization signal is based on the output signal of the first frequency dividing circuit. And the first carrier signal are generated, and the slave circuit of the other inverter unit has a second frequency dividing circuit that divides the reference clock, and based on the output signal of the second frequency dividing circuit, the second A carrier synchronization signal and the second carrier signal are generated.

One aspect of the present invention is an inverter system in which one of the above inverter units and the other inverter unit are connected in parallel.

One aspect of the present invention is an inverter system having a plurality of inverter units functioning as a master or a slave, the first unit having the master circuit of the inverter unit functioning as the master, and the slave functioning as the slave. The number of the second unit is two or more, and the first unit corresponds to the number of the second unit. Are provided in parallel.

One aspect of the present invention is an inverter system having a plurality of inverter units that function as masters or slaves, the first unit having the above-mentioned inverter unit master circuit that functions as the master, and the master of the first unit. A second unit having the above slave circuit connected in series with the circuit and functioning as a slave, and the above master circuit connected in series with the slave circuit and functioning as a master, and the master circuit of the second unit. It has at least a third unit having the above-mentioned slave circuit connected in series with and functions as a slave.

In one aspect of the present invention, in the inverter system, a plurality of the second units are connected in series.

According to the above invention, it is possible to reduce unnecessary overhead and improve synchronization accuracy in a small-scale data transmission line applied to a carrier synchronization system.

An application example of the inverter system of the present invention. An application example of the inverter system of the present invention. An application example of the inverter system of the present invention. A signal waveform diagram illustrating various signals related to the pulse width modulation of the present invention. The block diagram of the inverter system of Embodiment 1 of this invention. The circuit block diagram of the transmission circuit of Embodiment 1. The circuit block diagram of the receiving circuit of Embodiment 1. The circuit block diagram of the clock restoration circuit of Embodiment 1. The block diagram of the inverter system of Embodiment 2 of this invention. The block diagram of the inverter system of Embodiment 3 of this invention. The block diagram of the inverter system of Embodiment 4 of this invention. The time chart of the synchronous control of Embodiment 1. The time chart of the synchronization control of the master side and the slave side of Embodiment 1.

An embodiment of the present invention will be described below with reference to the drawings.

[Embodiment 1]
The inverter system of the first embodiment is an inverter system including the two inverter units illustrated in FIGS. 1 and 2, and the outputs of the two inverter units are connected in parallel to expand the output current by about twice. It is a structure that can be done.

Further, in the inverter system of the present embodiment, as shown in FIG. 5, one inverter unit 1 (hereinafter, unit 1) functions as a master, and the other inverter unit 2 (hereinafter, unit 2) serves as a slave. Function. Then, the second carrier signal Cry2 of the slave side unit 2 follows the first carrier signal Cry1 of the unit 1 on the master side, so that the time synchronization of the inverter system of the present embodiment is realized.

In the signal waveform diagram shown in FIG. 4, various signals (symbols) related to general pulse width modulation (PWM) are defined.

Let Cry be the triangular wave carrier signal, and let Scry be the synchronization signal that has the carrier period (Tc) and is synchronized with the apex. (That is, Cry and Scry are synchronized.) Here, the synchronization timing is selected as the upper vertex of the triangular wave, but it may be the lower vertex or the intermediate level, and any location may be defined. ..

As a principle of generating the output voltage of pulse width modulation (PWM), a digital value of "1/0" is generated by comparing the magnitude of the carrier signal Cry and the voltage command Vref, and the inverter is based on this digital value. It drives the semiconductor switch inside and outputs a square wavy voltage pulse (PWM waveform) with the voltage vdc of the DC power supply as the amplitude.

In the inverter system shown in FIG. 5, carrier oscillation can be continued even if synchronization control is stagnant due to a transmission abnormality. That is, one unit 1 mounts the carrier generation unit CryGen1 and continuously generates the synchronization signal Scry1. The other unit 2 implements the carrier generation unit CryGen2 and continuously generates the synchronization signal Scry2.

In the figure, the symbols are numbered at the end, such as Scry2 on the master side and Scry2 on the slave side, so that the master and slave can be easily distinguished. Regarding the transmission line, the master-slave direction is represented as "12" and the reverse direction is represented as "21". The voltage command Vref is data with a value common to both the transmitting side and the receiving side, although there are differences such as transmission delay. Therefore, common symbols are attached without any particular distinction.

In addition, the figure shows the configuration of full-duplex intercommunication (Cmd_line and Ack_line), and this mutual transmission information is synchronized with the synchronization signal Scry1 by performing synchronous control (PLL1 and PLL2) with each other. Feedback control is performed so that the signal Scry2 is synchronized. As an example of this operation, for example, the time charts shown in FIGS. 12 and 13 are used. The same circuit is applied to the master and slave transmission circuits (Cmd_line and Ack_line) and the delay time for detecting synchronization deviation (Tdly1 and Tdly2), and the carrier generator (CryGen1, CryGen2) and synchronization control (PLL1, PLL2). And only the contents of the transmitted data have different functions.

The components common to and different from the units 1 and 2 in FIG. 5 will be described.

First, aspects of components common to the units 1 and 2 will be described.

(1) Reference clock: Clk1, Clk2
It is a reference clock signal of a digital circuit, to which a crystal oscillator is applied, and it is assumed that the frequency error is minute. In addition, each time (t1, t2) is the count of this reference clock.

Since the reference clocks (Clk1, Clk2) are also used for sample transmission waveforms, a frequency that is several times higher than the serial transmission frequency [bps] is usually used, and the timing at which stable data can be sampled should be selected. There is.

(2) Transmission circuit: TX12, TX21
The transmission circuit sends and receives data between each unit. Mutual transmission data is set in the data buffers TxBuf12 and TxBuf21, and these buffer data are selected in order and transmitted from the transmission circuit TX12 or the transmission circuit TX21. A configuration example of this transmitter is shown in FIG.

Although the details of FIG. 6 will be described later, a serial transmission signal is generated by selecting data, blocking and embedding a COM code, encoding (8B10B code conversion), serialization, and the like. In particular, the transmission of synchronization timing information is started at the same time when the synchronization signals Scry1 and Scry2 are generated. For example, synchronization timing information is embedded in serial data by transmitting a special synchronization code or a data block containing it. Data for synchronization timing is transmitted to each other. Information such as the carrier cycle command Tc_ref, the estimated transmission delay time Td_ref, and the voltage information Vref (current command if current control is used) is also transmitted from the master side (unit 1 side). On the other hand, from the slave side (unit 2 side), data including the time information Tdly2 that measures the time difference from the slave carrier synchronization timing (Ack_line transmission start timing) Scry2 to the reception timing Trx_12t is transmitted.

In this way, although the transmission and reception data contents are different between the master and slave, the transmission and operation delays are made equal by making the amount of data to be transmitted and the packet configuration the same, and also by making the transmission / reception circuit a common configuration.

(3) Serial transmission line: Cmd_line, Ack_line
The serial transmission line is a transmission line that transmits the signals of Tx12_data and Tx21_data output from the transmission units of the units 1 and 2 to the other unit, and corresponds to a transmission / reception module for optical transmission, an optical fiber, or the like.

(4) Reception circuit: RX12, RX21
The receiving circuit is a circuit that receives the data of the units 1 and 2, and FIG. 7 shows a detailed example of the RX12. The details of the receiving circuits RX12 and RX21 of the unit 1 will be described later, but the shifter (Deserializer) that converts serial data into 10-bit parallel data, the decoder (Decoder) that is the inverse conversion of 8B10B code, and the clock component from the received data It is equipped with a CDR circuit (CDR) that restores data components. This received data is stored in the buffer RxBuf12 by the selector (Sel). This buffer RxBuf12 is read from an external control unit. In addition, since the data for synchronization timing is transmitted by the trigger of Scry2 and Scry1, the receiving side normally receives the synchronization code, or the time when the entire block data including it is received, Srx21 and Srx12. Output the signal of. In the latter stage, the reception completion signal is used to latch the time t and measure the reception time T_rx required for synchronous control.

Regarding the details of the CDR circuit, FIG. 8 shows a functional block that can explain the operation and operation necessary for explaining the synchronous control. The details will be described later.

(5) Time measurement circuit: Latch circuit for T_cry1, T_cry2, T_rx21, T_rx12
The latch circuit for T_cry1 latches the time t1 by the transmission start signal Scry1 on the master side and outputs the transmission start time T_cry1.

The latch circuit for T_rx21 latches the time t1 by the reception completion signal Srx21 on the master side and outputs the reception completion time T_rx21.

The latch circuit for T_cry2 latches the time t2 by the transmission start signal Scry2 on the slave side and outputs the transmission start time T_cry2.

The latch circuit for T_rx12 latches the time t2 by the reception completion signal Srx12 on the slave side and outputs the reception completion time T_rx12.

(6) Time difference: Tdly1 and Tdly2 differ In the Tdly1 differ on the master side, the difference time from the transmission start time T_cry1 to the reception completion time T_rx21 is Tdly1.

In the Tdly2 diff on the slave side, the difference time from the transmission start time T_cry2 to the reception completion time T_rx12 is Tdly2.

Here, in the aspect of FIG. 5, the time of the difference is calculated after latching the time of each timing, but the purpose is to finally obtain the two delay times of Tdly1 and Tdly2, which is simple. It may be replaced with a delay time measurement counter.

(7) Carrier generation comparator: PWMcomp
As shown in FIG. 4, the carrier generation comparator PWMcomp compares the first carrier signal Cry1 and the second carrier signal Cry2 with the voltage command (Vref, common to master / slave) and outputs a pulse width modulation PWM output signal. To generate. Here, the output voltage command from the current control of each unit may be used instead of the common voltage command, but a common voltage command is transmitted as a typical example thereof.

(8) Inverter main circuit: INV1, INV2
Since the signal corresponding to the output voltage of the pulse width modulation PWM is output from the carrier generation comparator PWMcomp, the pulse width that actually drives the load in the main circuits INV1 and INV2 configured by using a power semiconductor switch or the like. Modulation Generates PWM voltage for PWM1 and PWM2.

Next, modes of different components in units 1 and 2 will be described.

(9) Carrier generation part: CryGen1, CryGen2
The carrier generation unit CryGen1 of the master (unit 1) generates the first carrier signal Cry1 having a fixed cycle set by the carrier cycle command Tc_ref set from the outside, and outputs the timing signal Scry1 synchronized with the first carrier signal Cry1.

Normally, Clk1 is treated as a digital value, and the up / down count is used as the first carrier signal Cry1.

The carrier generation section CryGen2 of the slave (unit 2) is based on the carrier cycle command Tc_ref2 transmitted from the master (unit 2), and the cycle is equal to the cycle correction output signal Tcomp2 output from the circuit of the synchronization control section PLL2. The cycle in which is increased or decreased is input as a command value, and the second carrier signal Cry2 of this corrected cycle is generated. Further, although the period of the second carrier signal Cry2 changes minutely, the signal Scry2 is output at the timing synchronized with the apex of the second carrier signal Cry2.

Although this aspect will be described later, Cry1 is always set to a constant frequency, and carrier synchronization control (fine adjustment of the cycle) is applied only to Cry2 on the slave side.

(10) Synchronous control unit on the slave (unit 2) side: PLL2
The synchronization control unit PLL2 inputs the estimated transmission delay time Td_ref transmitted from the master (unit 1), the carrier synchronization timing (Ack_line transmission start timing) Tcry2 of the slave described above, and the time difference Tdly2 of the reception timing Trx_12. .. If the delay time is longer than expected (Tdly2> Td_ref), a correction value that advances the phase of the second carrier signal Cry2 is output from the output signal Tcomp2, and conversely if it is shorter (Tdly2 <Td_ref), the output signal Tcomp2 is used. A correction value that delays the phase of the second carrier signal Cry2 is output. By the feedback loop of the correction command of PLL2 and the correction of the period of the carrier generator CryGen2, the signal Tdly2 = signal Td_ref is finally converged.

As a result, on the slave side, it is assumed that the time retroactive to the past by the predicted transmission delay time Td_ref with respect to the reception time Srx12 is the synchronization timing, and the second carrier signal and the transmission start timing are synchronized with this.

(11) Synchronous control unit on the master (unit 1) side: PLL1
The synchronization control unit PLL1 on the master side does not correct the carrier cycle as in the slave (unit 2), but corrects the predicted transmission delay time Td_ref to detect and correct the deviation component of the transmission delay time. .. As described above, the slave side synchronizes the carriers with respect to the reception time Srx12 based on the time retroactive by the predicted transmission delay time Td_ref, but the predicted delay amount Td_ref is the delay time of the actual transmission line. On the other hand, if there is an error, the synchronization state is not accurate. It appears as an error between the predicted delay amount Td_ref and the delay time Tdly1 on the master side, and includes the component of the slave synchronization delay time and the predicted deviation of the transmission delay from the slave. Assuming that the actual bidirectional transmission delays are equal, if the predicted delay amount Td_ref transmitted to the slave and the delay time Tdly1 on the master side are matched, the signal Scry1 and the signal Scry2, that is, the mutual transmission start timings are synchronized. .. Therefore, in PLL1, the value of Td_ref transmitted to the slave is slowly modified so as to approach the value of the measured value Tdly1. When this converges and Tdly1 = Tdly2 = Td_ref is finally established, the carrier synchronization of the signal Scry1 and the signal Scry2 is completed.

In other words, the synchronization control unit PLL1 detects and corrects variations in transmission delay and changes over time. As mentioned above, there are PLL controls for two different components, master and slave, but in order for these controls to operate stably, the response characteristics of the PLL control gain are set high so that PLL2 converges first. However, it is necessary to consider setting the response of PLL1 lower than that, or setting all responses considerably lower.

In FIG. 5, the circuit configuration having the master function in the unit 1 (the portion surrounded by the alternate long and short dash line in the unit 1 in FIG. 5) is referred to as a master circuit MST. Similarly, the circuit configuration having the slave function in the unit 2 (the part surrounded by the alternate long and short dash line in the unit 2 in FIG. 5) is referred to as a slave circuit SLB.

The operation and operation example of the first embodiment will be described with reference to FIGS. 6 to 8, 12, and 13.

In order to explain the functions and operations of each part of FIG. 5, detailed configuration examples are shown in FIGS. 6, 7, and 8. Regarding the time relationship, FIG. 12 shows the relationship between the carrier synchronization signal and the transmission / reception data such as the transmission timing, and FIG. 13 shows the operation for a longer time to explain the process from the start of synchronization to the convergence. ..

FIG. 6 is a block diagram showing a functional example of the transmission circuit TX12.

Here, an example of applying the 8B10B code is shown. Dbus (wr) for writing transmission data, signal Scry which is the transmission start timing, and reference clock Clk1 of the transmission circuit are input to this block, and serial data TX ₀ is output. Txbuf (0) to Txbuf (N-1) are buffers that store transmission data, Selector Sel is a selector that selects transmission data in order from Txbuf (0) to Txbuf (N-1), and 8B10B in the encoding section Encoder. Convert 8bit (1byte) data to 10bit serial transmission data using a code conversion table or the like.

Then, in the Serializer that outputs the final serial signal, the encoded 10-bit data is converted into serial data and output while shifting by 1 bit in order. The operation sequence of these functions is controlled by TxSeq, which takes the trigger signal of the signal Scry and the reference clock Clk1 as inputs, the selection signal n of the data buffer, the timing Sconv to encode the selected data, and the input data of the serializer. Outputs latch timing Ld, shift operation timing clksft, etc.

FIG. 7 is a block diagram showing the functions of the receiving circuit.

The serial data Rxi is converted to multi-bit data Dsft by a Deserializer such as a shift circuit, and it is restored to 8 bits (1 byte) by performing the inverse transformation of 8B10B coding by the code restoration unit Decoder. Then, the selector Sel stores (writes) in the receive buffer RxBuf corresponding to the address of the send buffer.

In the CDR circuit, various timings are restored from the serial data, and the sample timing clksft (shift operation timing of the Deserializer) of the serial data and the timing LD to latch and convert the Dsft to the inverse code conversion (Decoder) are output. There is. Further, since the received data is updated by the LD signal, it is written to the buffer RxBuf (n) in order by the storage buffer control RxDataSel and the selector Sel.

The CDR circuit also has a function of outputting a synchronization timing signal Srx when the synchronization data (special code for the synchronization signal) embedded in the serial data Rxi is detected. This timing signal Srx is used to latch the value of the timer counter t and measure the reception time t_rx.

FIG. 8 shows a configuration example of the CDR circuit. The components and functions are as follows. The received serial data Rxi is received by Shifter operating on the reference clock Clk2. Suppose that the width of 1 bit of the transmitted data is equivalent to 8 samples of the reference lock. The number of samples for one code (10 bits) of 8B10B encoding is (8 x 10) bits, and a shifter sequence that can store this is prepared. Then, when the data string of this shifter matches the pattern of the delimiter (K28.5, com) of the 8B10B code, SyncCodeDetecter outputs the detection signal of Scom_rx. Strictly speaking, COM detection has a time width of several samples, but processing such as detecting the intermediate time between rise and fall is performed inside PLLControl to recognize it as the timing of Scom_rx. Then, using this Scom_rx as a reference input, a sample timing LD of the received data is generated by the PLL operation. The method of restoring the clock (sample timing) by such COM detection and PLL function is less susceptible to jitter than the method based on the edge detection of the start bit such as RS232C's pace synchronization detection. You can get the timing. Since this "method of detecting COM code and generating Scom_rx timing" has already been put into practical use, the description thereof is omitted here.

In the example of FIG. 8, the reference clock is divided by the variable division counter ClkDriver which sets the division ratio based on the Ndiv from the PLL Control, the sample timing clksft is generated, and it is divided by 10 bits corresponding to 1 code. Furthermore, Scom_PLL corresponding to the self-oscillation signal of a general PLL configuration is generated by dividing by the insertion cycle of COM. Then, the occurrence time of Scom_PLL is finely adjusted by modifying the counter width of ClkDriver as Ndiv ± 1 so that the occurrence times of Scom_rx and Scom_PLL are synchronized. If this PLL is properly converged, it is possible to generate a stable sample timing clksft and a timing LD that latches 1 code (10 bits) of data even if some jitter is superimposed on the waveform of the serial signal. ..

The above is a description of a detailed circuit example for supplementing the first embodiment (FIG. 5).

The operation of the time charts of FIGS. 12 and 13 will be described using the signals defined above.

FIG. 12 shows the relationship between the carrier synchronization timing and other signals by limiting the carrier cycle to a short time width of about two times. FIG. 13 shows the process of activating carrier oscillation and establishing mutual carrier synchronization by showing the operation for a longer time than that. In the following description, FIG. 12 will be limited to the convergence operation of the synchronization timing.

In FIG. 12, the data in the second stage from the top and the data in the second stage from the bottom correspond to the signal on the master side, and the intermediate portion corresponds to the signal on the slave side. Each signal will be described below.

(1) Carrier synchronization signal Scry: This is the synchronization timing of the master carrier oscillator, and the slave follows this.

(2) TX12_data: Serial data transmitted from the master using Cmd_line, Sync_code is a special code for identifying carrier vertices, Tc_ref is the number of clocks indicating the carrier period, and Td_ref is the prediction of the delay time of the transmission line. , Vref is the operation information shared by the master and the slave, and here it assumes a three-phase voltage command. Although the COM code is omitted in FIG. 12, it is inserted before Sync_code or at the break of several data in order to realize the CDR function.

(3) RX12_data: Indicates the received data of the slave. It is shown a little later than Tx12_data to show the delay time of the transmission line.

(4) Srx12: A timing signal for completing reception of the synchronization code by the receiving circuit. Along with restoring the 10-bit code from RX12_data, Sync_code reception completion signal Srx12 is also generated. This signal Srx12 does not have to be limited only to the completion of reception of Sync_code, and may be the reception time of block data including it, or the timing of COM generated before and after that. It suffices if a fixed position can be detected with respect to the transmission cycle. However, depending on the type of timing to be selected, the assumed delay time Td_ref, which will be described later, is corrected to correspond.

(5) Scry2: A synchronization timing signal of the carrier generation unit CryGen2 on the slave side. By establishing synchronization, this signal Scry2 is matched with the timing of the signal Scry1. Since we want to start this signal Scry2 from the time synchronized as much as possible, we use the carrier cycle Tc_ref and predicted delay time Td_ref (contents are the initial setting value Td_ref_ini) of the transmission data from the master and the time T_rx12 of the previous reception timing Srx12. , The start time is calculated by the following formula (1).

T_cry2'＝ (T_rx12 ＋ Tc_ref) −Td_ref… (1)
This predicts the next reception time (T_rx12 + Tc_ref) using the information at time T_rx12, and assumes that the time that goes back by the estimated delay time Td_ref for transmission and detection is the synchronization timing. When the signal Scry2 is activated, the measurement of the time difference Tdly2 between the signal Scry2 and the signal Srx12 is also started.

(6) Tx21_data: Serial data returned from the slave side to the master side using Ack_line. When the signal Scry2 is activated, serial transmission is started in synchronization with it. Here, the reply data Tx21_data also includes the measured value of the signal Tdly2. Here, it is shown to be transmitted to the master immediately after the measurement of Tdly2, but since it is actually necessary to consider the processing time, it may be transmitted at the next transmission timing. The content of other transmission data is arbitrary, but it has the same data length as Tx12_data, and the data composition is equivalent by embedding Sync_code and COM in the same way and making the transmission and reply the same data composition (time). Make the process symmetrical).

(7) Rx21_data: Received data on the master side. Similar to Tx12_data, this is also drawn by delaying the timing of the transmission line by the delay time of the transmission line.

(8) Srx21: It is the reception timing of the synchronization code by the reception circuit on the master side, and it is generated by the reception completion timing of Sync_code by restoring the 10-bit code from RX21_data. This makes the detection delay time of the master and slave receiving circuits equal by using the same detection circuit as Srx12. When the carrier on the slave side starts and Srx21 starts to occur, the master side also starts measuring the time difference Tdly1 between the signal Scry1 and the signal Srx21.

The above is the definition of each signal, time and time difference.

An operation example of the synchronization control units PLL1 and PLL2 based on transmission / reception information will be described with reference to FIG.

<Scry1 (1)>
When CryGen1 starts oscillating, transmission from the master to the slave starts at the timing of signal Scry (1). The carrier cycle setting Tc_ref and the predicted reception delay Td_ref (Td_ref_ini) are included in this data. On the slave side, the timing of the synchronization signal reception timing Srx12 (1) is used as the reference for starting carrier oscillation.

<Scry1 (2)>
On the master side, the signal Scry1 (2) is generated after the time of the signal Tc_ref elapses from the signal Scry1 (1), and the next transmission is started. Also on the slave side, the timing corresponding to the signal Scry1 (2) on the master side is predicted from the time of the signal Srx12 (1) by the above equation (1), and carrier oscillation is started from the predicted time. At the same time, the signal Scry2 (2) is output and transmission from the slave side to the master is started. The delay time Tdly2 is sent based on this reply data, but appropriate dummy data is sent before the measurement has started.

As a result, mutual transmission starts, so the delay times Tdly1 (2) and Tdly2 (2) from the start of each other's transmission to the completion of reception of the synchronization code, etc. are measured, and synchronization control is performed from these delay time information. Initially, the synchronous control unit PLL1 does not operate, and on the slave side, the block of the synchronous control unit PLL2 works to reduce the carrier cycle so that the delay time Tdly2 (2) matches the value of the received signal Td_ref. Adjust (PLL control).

<Scry1 (3)>
The signal Tdly2 is gradually converging to the signal Td_ref due to the operation of the synchronization control unit PLL2 on the slave side. At this time, the difference between the signal Td_ref and the signal Tdly1 (3) includes both the tracking error component of the synchronization control unit PLL2 and the error component of the transmission delay time predicted by the signal Td_ref.

<Scry1 (p)>
If the operation of the synchronization control unit PLL2 on the slave side converges and the signal Tdly2 matches the signal Td_ref, there may be a slight time lag with the master, but the carrier cycle on the slave side is stable and in synchronization. It becomes. Then, the difference between the signal Td_ref and the signal Tdly1 (p) whose delay time measurement value on the master side is predicted is only the error component of Td_ref predicted as the delay time of the actual transmission line. Therefore, this time, correction is performed so that the signal Td_ref = signal Tdly1 (p) is established on the master side. Here, on the master side, the carrier frequency is not corrected, but specifically, the value of the signal Td_ref is only corrected so as to approach the value of the signal Tdly1 (p). Then, it waits for the convergence of the synchronization control unit PLL2 on the slave side.

<Scry1 (q)>
When both the master synchronization control unit PLL1 and the slave synchronization control unit PLL2 continue to operate, the signal Tdly1 (q) becomes the signal Td_ref (q) while maintaining the state of signal Tdly2 (q) ≒ signal Td_ref (q). It converges to q).

<Scry1 (r)>
Eventually, it converges to Td_ref (r) = Tdly1 (q) = Tdly2 (r), synchronization between the master and slave is established, the carrier frequency becomes stable, and at the same time, correction of the delay time of the transmission line is completed. do. After that, even if the delay time fluctuates, the synchronization control unit PLL1 operates to change the value of the signal Td_ref and continue the correction, so that accurate carrier synchronization can be maintained. If the master synchronization control unit PLL1 and the slave synchronization control unit PLL2 operate at the same time, they may interfere with each other and become unstable. Therefore, the convergence characteristic of the synchronization control unit PLL2 is increased (the response setting is increased). On the PLL1 side of the synchronization control unit, set the response setting low so that the signal Tdly1 does not change immediately even if it changes slightly.

According to the above-mentioned inverter system of the first embodiment, the following effects are obtained.

In this embodiment, 8B10B coding and a CDR circuit are used to improve the clock recovery accuracy on the receiving side, and the carrier synchronization signal is directly used as the transmission start signal. Compared to the two-step method that oscillates carriers based on the establishment of synchronization timing only like IEEE1588, the source signal of the carrier generator is used as the transmission timing, so the timing when passing through a multi-stage circuit. Misalignment is not mixed in, accurate timing can be measured, and accurate synchronization can be achieved. In addition, since the amount of calculation processing of transmission data and received data is small, it is not necessary to transfer a large amount of data at high speed such as 100 Mbps. Further, the transmission / reception circuit of FIGS. 6 and 7 and the CDR circuit of FIG. 8 do not use a special PHY circuit including an analog circuit, and a PLL control for extracting a clock from a serial signal is also performed by an FPGA or the like. Only digital arithmetic circuits can be configured.

Therefore, according to the present embodiment, the communication circuit can be simplified. The circuit is simplified as much as possible by using only the transmission line for digital communication with a relatively low transmission frequency and the digital logic circuit such as FPGA without using a special dedicated circuit such as PHY of the physical layer of Ethernet. At the same time, the number of parts and the mounting area can be reduced. Therefore, a special circuit such as PHY for 100BASE-TX is not required, and the digital transmission line and FPGA can be configured.

Further, the transmission data required for synchronization may be about several bytes. In addition, a special code of 8B10B code (COM, etc.) makes it easy to detect abnormal data, and if data reception timing is generated by CDR, accurate sample timing that suppresses the influence of jitter can be generated. Therefore, the reliability of the transmission signal can be improved as compared with a method in which a start bit is added to simple byte data (binary number) and transmitted as in the pace synchronization method. In other words, the synchronization signal can be detected accurately without adding a special circuit or special data area to prevent false detection, reliability can be ensured, and in the conventional method, it is increased to detect errors. The amount of transmitted data can also be reduced.

Therefore, according to the present embodiment, the amount of transmission data required to realize the synchronous control can be reduced. If the transmission frequency [bps] is kept low, the amount of data that can be transmitted during the synchronization cycle also decreases, but according to this embodiment, the amount of transmission data required for establishing synchronization can be reduced.

Further, since the inverter unit is liable to generate electromagnetic noise, it is desirable that the inverter unit is one in which noise such as an optical fiber is hard to be conducted in the serial transmission line between a large number of units. Then, unlike the multi-drob wiring of RS485, many units cannot be connected by one transmission line, and many one-to-one serial transmissions are combined. In this case, it is desirable to use a method in which synchronous control can be easily configured in multiple stages. Furthermore, even if a transmission abnormality occurs somewhere in this multi-stage connection, even if the synchronization control at both ends of the transmission line is interrupted, the system operation is continued by continuing the oscillation of the synchronization signal for a short time. It is desirable to have a configuration in which synchronous control is restarted when the transmission abnormality is resolved.

On the other hand, in the present embodiment, since all the transmission lines communicate on a one-to-one basis, an optical fiber or the like can be applied to the transmission lines, and conduction noise can be reduced as compared with metal wiring. In a multi-drop connection or the like, if noise is mixed in the transmission line, it is necessary to discard the received data of all the machines, but in this embodiment, even if there are many machines, only independent one-to-one communication is combined. Even if noise is mixed in one place, the synchronization is stopped only during that time, but the synchronization control of the other parts can be continuously operated without stopping.

Further, in the present embodiment, since the reference clock (the same frequency as the CDR) of the high-speed transmission circuit is applied to the measurement of the synchronization timing deviation time, the synchronization accuracy close to the resolution of this clock can be realized. The synchronization accuracy depends on the quality such as the frequency band of the transmission line and the waveform distortion characteristics, but according to the present embodiment, the synchronization timing can achieve a high accuracy of about submicroseconds. Specifically, for example, even when a transmission line of about 20 to 50 Mbps is used, a synchronization accuracy of about 0.1 μs can be obtained.

Further, in the present embodiment, the transmission circuit and the reception circuit having the same configuration are used as the full-duplex (bidirectional) transmission / reception circuit. The only difference between the transmitting circuit and the receiving circuit is the function of finely adjusting the frequencies of the PLL control part and the carrier generation part. Therefore, even when three or more inverter units are provided as in the fourth and fifth embodiments described later, it is sufficient to duplicate the paired circuit of transmission / reception as much as necessary, and the circuit design is performed even if a large number of units are synchronized. Is easy, and the delay time can be adjusted.

In order to measure the transmission delay between the master and the slave, it is necessary to assume that the transmission delay time of transmission and reply is equal. Therefore, it is necessary to equalize the delay time in the digital circuit by sharing the transmission / reception circuits of the master and the slave as much as possible (circuit copy). On the other hand, according to the present embodiment, as described above, the variation and fluctuation of the delay time of the transmission line can be measured and corrected, and the communication circuit can be shared as much as possible.

As described above, according to the inverter system of the first embodiment, it is possible to reduce unnecessary overhead and improve synchronization accuracy in the small-scale data transmission line applied to the carrier synchronization system.

[Embodiment 2]
In the inverter system of the second embodiment shown in FIG. 9, the function of the synchronous control unit PLL2 on the slave side is moved to the master side and further integrated with the function of the synchronous control unit PLL1 on the master side. It has the same mode as the inverter of.

In the first embodiment, two synchronous controls, a synchronous control unit PLL1 and a synchronous control unit PLL2, are configured, but if the response setting is set low, these may be operated at the same time. Further, the adjustment target of the synchronization control is only the period (phase) correction of the carrier generation part CryGen2 by Tcom2, and further, considering the stable state in which the synchronization is completed by converging with the two synchronization controls, the transmission delay time elapses. Only the correction, that is, the signal Td_ref, has changed. From this, the PLL control can be integrated into one. Therefore, the main point of the second embodiment is to move the function of the synchronization control unit PLL2 on the slave side to the master side, and further integrate the function with the synchronization control unit PLL1 to configure the synchronization control unit PLL3. This is intended to simplify the circuit configuration on the slave side as much as possible even if the amount of information on the transmission line increases a little.

The output of the synchronous control unit PLL3 (that is, the output of the synchronous control unit PLL2) Tcomp2 is a value corresponding to the output signal Tcomp2 of the synchronous control unit PLL2 of the first embodiment, and this is transmitted to the slave via the transmission line Cmd_line. The value of this output signal Tcomp2 is stored in Vref, etc of the serial data Tx12_data in FIG. Then, on the slave side, the phase of the carrier generation unit CryGen2 is corrected by the value of the received output signal Tcomp2 as in the first embodiment.

Further, in the first embodiment, the Td_ref value is changed by the synchronization control unit PLL1, but in the configuration of FIG. 9, this signal is included in the block of the PLL3 and does not appear to the outside. However, since CryGen2 can be oscillated from the exact start time by using the initial value Td_ref_ini of the predicted delay time, this initial value Td_ref_ini is transmitted together with the initial setting value such as Tc_ref.

Since other configurations and functions are the same as those in the first embodiment, the description thereof will be omitted.

Only the operations of the synchronous control units PLL1 and PLL2 and the data transmitted to each other are changed, and the other operations and operations are almost the same as those in the first embodiment. In particular, in the second embodiment, the operation of the synchronization control unit PLL2 is moved to the master side and integrated with the synchronization control unit PLL1 to form the synchronization control unit PLL3. The output signal Tcomp2 of the synchronous control unit PLL2 is transmitted from the synchronous control unit PLL3 to the slave through the transmission line. Further, since the adjustment value of the signal Td_ref is an internal variable of the synchronization control unit PLL3, only the correction information corresponding to the signal Td_ref (1) shown in FIG. 13 and used only at the start of the slave carrier is provided. It is transmitted as a signal Td_ref_ini. Other than that, the same operation as the time charts of FIGS. 12 and 13 is performed.

According to the above embodiment, by moving the PLL calculation process on the slave side to the master side, in addition to the effect of the first embodiment, the circuit on the slave side can be simplified. That is, the configuration on the slave side is simplified by implementing the arithmetic processing function only on the master side.

When actually applying the PLL control, it is necessary to set the initial value, perform operations such as multiplying the gain, and perform processing such as abnormality determination, and complicated processing needs to be realized by software such as a CPU. When a CPU is installed, the mounting area and the number of parts such as peripheral circuits and software writing terminals increase.

In addition, there are cases where it is not desirable to implement a complicated circuit such as numerical calculation on the slave side. The system that requires establishment of synchronization is not limited to unit parallel, and the slave side may implement only the function of detecting the voltage or current in the remote part. When detecting the current or voltage component including the pulse width tuning ripple, a method of detecting at the timing synchronized with the pulse width tuning is applied so that the harmonic component of the carrier frequency can be easily removed. In this case, a simple configuration such as a sensor, an AD converter, and an FPGA circuit is desirable. In other words, we want to execute the PLL control operation only on the master side without implementing complicated PLL control operation on the slave side. Instead, we want to be able to transmit information such as time correction required for carrier synchronization correction to the slave side by adding it to the communication data.

On the other hand, this embodiment can be realized only by FPGA if it is a counter or a simple sequence circuit, and if arithmetic processing is implemented only on the master side, the slave has a simple configuration, and the slave side has a simple configuration. The circuit scale can be significantly reduced. Also, even if the PLL processing is moved to the master side, the amount of CPU calculation does not increase so much, and the amount of data to be sent and received does not increase so much, so the effect of simplification on the slave side can be obtained as an advantage as it is from a system perspective. Be done.

[Embodiment 3]
Embodiments 1 and 2 employ a serial transmission between a master and a slave and a carrier synchronization method. Since the carrier generators CryGen1 and CryGen2 are configured to count up and down the reference clocks Clk1 and Clk2, the resolution of the pulse width modulation PWM pattern is set to the same high resolution as the communication reference clock.

However, since disturbances such as switching delays are mixed in the main circuit in the subsequent stage, even if the time resolution of the pulse width modulation pattern is increased, the effect cannot be obtained practically. Even if the resolution of the pattern is coarse, the cross current suppression effect can be obtained by accurately synchronizing the carriers and generating the same pulse width modulation pattern between the parallel units.

Therefore, the inverter system of the third embodiment uses a high frequency reference clock for circuits requiring high time resolution such as communication and synchronous control, and a low frequency reference clock for circuits where other low operating clocks are sufficient. Operate with a clock. The purpose of this is to suppress the power supply current and the amount of heat generated (temperature rise) in a digital circuit such as FPGA, and this function is realized in the third embodiment.

Although the inverter system of the third embodiment illustrated in FIG. 10 has been modified in the inverter system of the second embodiment, the same modification can be applied to the inverter system of the first embodiment.

Explaining the difference between the inverter system of the third embodiment and the second embodiment, the unit 1 on the master side divides the reference clock Clk1 by the first frequency divider circuit ClkDivider1 to generate a low frequency reference clock Clk1L. Then, this is used as the reference clock of the carrier generator CryGen1 and the PWM comp circuit. Therefore, the first carrier synchronization signal Scry1 and the first carrier signal Cry1 output by the carrier generation unit CryGen1 are generated based on the low frequency reference clock Clk1L. As a result, the operating frequency and current consumption of the carrier generator CryGen1 and the PWM comp circuit can be suppressed.

Similarly, the unit 2 on the slave side divides the reference clock Clk2 by the second frequency divider circuit ClkDivider2 to generate a low frequency reference clock Clk2L, which is used as the reference clock of the carrier generator CryGen2 and the PWM comp circuit. Therefore, the second carrier synchronization signal Scry2 and the second carrier signal Cry2 output by the carrier generator CryGen2 are generated based on the low frequency reference clock Clk2L. However, the second frequency divider circuit ClkDivider2 on the slave side has a variable frequency divider function. If the output signal Tcomp2 is a command to advance the synchronization time, the second division circuit ClkDivider2 reduces the division ratio to generate a clock with a short cycle to advance the synchronization timing generation time, and the output signal Tcomp2 synchronizes the phase. If it is a command to delay the time, the second division circuit ClkDivider2 increases the division ratio to generate a clock with a long cycle to delay the occurrence time of the synchronization timing. In other words, by indirectly adjusting the division ratio, it was possible to finally adjust the synchronization timing of the carriers. As a result, the carrier generation circuit can be operated with a low frequency reference clock, and the carrier synchronization accuracy can be controlled while maintaining the time resolution of the high frequency reference clock.

In the first and second embodiments, the cycle is finely adjusted by increasing or decreasing the amplitude of the carrier counter. On the other hand, in the third embodiment, a low clock obtained by dividing the reference clock of the communication circuit is used as the reference clock of the carrier generation unit, and the correction (increase / decrease) of the carrier period is indirectly performed by the divided clock. It is controlled by intermittently fine-tuning the upper limit count value.

Further, in the first and second embodiments, when the carrier cycle is changed, the counter upper limit value is adjusted to ± 1 clock. Also in the third embodiment, as an operation equivalent to the first and second embodiments, when the carrier counter reaches the upper limit, the upper limit value of the clock division counter is increased / decreased and corrected to adjust the clock cycle. As a result, the carrier synchronization operation equivalent to the first and second embodiments is realized. Further, the reference frequency of a PWM generation circuit using a carrier signal can be lowered.

For FPGAs, the current consumption increases due to the reference clock and internal logic changes, and it is desirable to operate the logic at the lowest possible frequency. In addition, in order to reduce the power consumption and heat generation of the FPGA, the transmission circuit is operated with the reference clock close to the highest of the FPGA, but for the PWM generation circuit, that is, the carrier signal to be synchronized, the reference clock with a low frequency is used. May be used. Therefore, when the frequencies of the reference clock of the transmission circuit and the reference clock of the carrier signal circuit are different (for example, when Fclk_srl = 160MHz of the transmission circuit is divided by 4 and the pulse width modulation PWM clock Fclk_pwm = 40MHz is set. ), High synchronization accuracy is desired.

On the other hand, in the third embodiment, a high-speed reference clock is adopted for the transmission circuit and the measurement circuit portion for the PLL to increase the measurement resolution of the transmission frequency and the time, and even at a low clock frequency (time resolution). The part related to the generation of good pulse width modulated PWM applies a low frequency reference clock. Therefore, the current consumption of the FPGA can be reduced, and as the clock cycle becomes longer, the allowable amount of propagation delay of the logic circuit increases, so that a larger amount of complicated operations can be executed within one clock. Further, since the synchronization control unit of the present embodiment performs measurement and phase correction using a high-speed reference clock, the same synchronization accuracy as that of the first and second embodiments can be maintained. In particular, if a crystal oscillator is applied to the reference clocks Clk1 and Clk2, the frequency error of the master and slave reference clocks becomes small.

[Embodiment 4]
The inverter system of the fourth embodiment is a combination of any of the units of the first to third embodiments. As the mode of the combination, the same signal is transmitted from two master circuits, and a parallel connection mode (Embodiment 4) in which the same signal is synchronized with two individually connected slaves, and data and a synchronization signal are sequentially connected. Examples of the mode of serial connection to be transmitted (Embodiment 5 described later) can be mentioned.

In the inverter system of the fourth embodiment shown in FIG. 3, the parallel connection method corresponds to establishing synchronization from unit 1 to unit 2 and unit 3.

Expressing this aspect as a master / slave transmission line, as in the inverter system shown in FIG. 11, transmission between the master circuit MST1b of the first unit 11 and the slave circuit SLB2 of the second unit 12 and the first This corresponds to communication between the master circuit MST1a of the first unit 11 and the slave circuit SLB3 of the second unit 13. The master circuit MST in any unit 1 of embodiments 1 to 3 is applied to the master circuits MST1a and MST1b, and the slave circuit SLB in any unit 2 of embodiments 1 to 3 is applied to the slave circuits SLB2 and SLB3. Will be done.

The two master circuits MST1b and the master circuit MST1a have a parallel connection configuration in which the same input signals Tc_ref, Scry, Vref, etc. are input. However, the CDR and synchronization control unit PLL1 and synchronization control unit PLL2 (or only PLL3) in each slave circuit operate individually to establish synchronization.

As described above, in the inverter system of the fourth embodiment, the aspects of the first to third embodiments are connected in parallel and the same command is given, but synchronization can be established independently.

[Embodiment 5]
The serial connection of the present embodiment corresponds to the configuration of the inverter system of FIG. 3 in which synchronization is established from unit 1 to unit 3 and then synchronization between unit 3 and unit 4 is established. By the two-stage synchronization control of this embodiment, the second carrier signals of both the unit 3 and the unit 4 are finally synchronized with the first carrier signal of the unit 1.

Expressing this aspect as a transmission line between the master and the slave, the transmission between the master circuit MST1a of the first unit 11 and the slave circuit SLB3 of the second unit 13 shown in FIG. 11 and the transmission of the second unit 13 This corresponds to a portion in which the master circuit MST3 and the slave circuit SLB4 of the third unit 14 are connected in series. First, the synchronization on the first stage side (between the master circuit MST1a and the slave circuit SLB3) is established, and then the synchronization on the second stage (MST3-SLB4) is established. The master circuit MST in any of the units 1 of the first to third embodiments is applied to the master circuits MST1a and MST3, and the slave circuit SLB in the unit 2 of any of the first to third embodiments is applied to the slave circuits SLB3 and SLB4. Will be done. In this embodiment, the two stages may be converged at the same time, but the response gains of the PLL control of the first stage and the subsequent stage may be different to cause interference or instability of synchronous control between a large number of transmission lines connected in series. Care must be taken not to cause it.

The signals required for the second stage synchronization of the serial connection are the carrier cycle setting value of the signal Tc_ref received by the slave circuit SLB3, the voltage command, and the synchronization signal Scry synchronized with the unit 1. The received information may be transferred as it is.

As described above, in the inverter system of the fifth embodiment, the aspects of the first to third embodiments are connected in series in multiple stages, and synchronization is established in order from the master side.

Further, the inverter system of the present invention is not limited to the mode of the inverter system of FIG. 11, and is an inverter system in which a plurality of second units 13 are connected in series between the first unit 11 and the third unit 14. It can also be in the mode of.

The present invention is not limited to the above-described embodiments 1 to 5, and can be implemented in various embodiments within the scope of the claims of the present invention.

1, 2 ... Unit (inverter unit)
11 ... 1st unit 12, 13 ... 2nd unit 14 ... 3rd unit
MST, MST1a, MST1b, MST3 ... Master circuit
SLB, SLB2, SLB3, SLB4 ... Slave circuit
TX12, TX21 ... Transmission circuit
RX12, RX21 ... Reception circuit
PWM comp… Carrier generation comparator
CryGen1, CryGen2 ... Carrier generation part
CDR ... Clock data recovery circuit
CryGen1, CryGen2 ... Carrier generation part
PLL1 ... Synchronous control unit on the master (unit 1) side
PLL2 ... Synchronous control unit on the slave (unit 2) side

Claims (8)

A synchronous control method for an inverter system having at least two or more inverter units.
The master circuit of one of the inverter units, which is the master, is
A serial including a synchronization code indicating the synchronization timing in synchronization with the first carrier synchronization signal, a predicted delay time until the slave circuit of the other inverter unit, which is a slave, receives and detects the synchronization code, and a carrier cycle command. Data is transmitted to the slave circuit of the other inverter unit,
The slave circuit of the other inverter unit is
The first reception timing signal of the synchronization code is generated at the time when the synchronization code of the serial data is normally received or the time when the entire block data including the synchronization code is completely received.
Next, a second carrier synchronization signal is generated based on the first reception timing signal, the carrier cycle command, and the predicted delay time.
The second difference time based on the time difference between the timing of the first reception timing signal and the timing of the second carrier synchronization signal is measured.
Next, in synchronization with the second carrier synchronization signal, the serial data including the synchronization code and the second difference time is transmitted as reply data to the master circuit of the one inverter unit.
The master circuit of one of the inverter units is
A second reception timing signal of the synchronization code is generated at the time when the synchronization code of the reply data is normally received or when the entire block data including the synchronization code is received.
Next, the first difference time based on the time difference between the second reception timing signal and the first carrier synchronization signal is measured, and the predicted delay time is corrected based on the first difference time and the second difference time.
The carrier generation comparator of one of the inverter units is
Pulse width modulation is performed based on the first carrier signal synchronized with the first carrier synchronization signal, and the pulse width modulation is performed.
The carrier generation comparator of the other inverter unit is
Performing pulse width modulation based on the second carrier signal synchronized with the second carrier synchronization signal.

A synchronous control method for an inverter system. The slave circuit of the other inverter unit performs synchronous control to match the second difference time with the predicted delay time.
The synchronous control method for an inverter system according to claim 1, wherein the master circuit of one of the inverter units performs synchronous control for matching the first difference time with the second difference time. The master circuit of the one inverter unit performs synchronous control for matching the first difference time and the second difference time and synchronous control for matching the second difference time with the predicted delay time, and performs the first difference. Instead of correcting the predicted delay time based on the time and the second difference time and storing it in the reply data, the output signal of the synchronization control that matches the second difference time with the predicted delay time. The value is stored in the reply data and
The slave circuit of the other inverter unit is based on the value of the first reception timing signal, the carrier cycle command, the second difference time, and the output signal of the synchronization control that matches the predicted delay time. The synchronous control method for an inverter system according to claim 1, wherein a synchronous signal is generated. The master circuit of the one inverter unit has a first frequency dividing circuit that divides the reference clock, and based on the output signal of the first frequency dividing circuit, the first carrier synchronization signal and the first carrier signal are combined. Generate and
The slave circuit of the other inverter unit has a second frequency dividing circuit that divides the reference clock, and based on the output signal of the second frequency dividing circuit, the second carrier synchronization signal and the second carrier signal The synchronous control method for an inverter system according to any one of claims 1 to 3, wherein the inverter system is generated. An inverter system in which one inverter unit according to any one of claims 1 to 4 and the other inverter unit are connected in parallel. An inverter system that has multiple inverter units that function as masters or slaves.
A first unit having a master circuit of the inverter unit according to any one of claims 1 to 4, which functions as the master.
A second unit having a slave circuit of the inverter unit according to any one of claims 1 to 4, which functions as a slave, is provided.
The number of the second unit is two or more,
The first unit is an inverter system characterized in that the master circuit is provided in parallel corresponding to the number of the second units. An inverter system that has multiple inverter units that function as masters or slaves.
A first unit having a master circuit of the inverter unit according to any one of claims 1 to 4, which functions as the master.
1. The slave circuit according to any one of claims 1 to 4, which is connected in series with the master circuit of the first unit and functions as a slave, and the slave circuit, which is connected in series with the slave circuit and functions as a master. A second unit having the master circuit according to any one of 4 to 4 and
An inverter system comprising at least a third unit having a slave circuit according to any one of claims 1 to 4, which is connected in series with the master circuit of the second unit and functions as a slave. .. The inverter system according to claim 7, wherein a plurality of the second units are connected in series.

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