JP6918552B2 - Read-out control circuit, solid-state image sensor, and how to drive the image sensor - Google Patents

Description

The present invention relates to a readout control circuit, a solid-state image sensor, and a method for driving the image sensor. Specifically, a plurality of signals having different sensitivities based on photoelectrons obtained by a photoelectric conversion unit are synthesized by a subsequent signal processing unit. It relates to a read-out control circuit, a solid-state image sensor, and a method of driving the image sensor, which are output so as to be possible.

Conventionally, in a solid-state image sensor, for example, a CMOS image sensor, a substantially linear output signal can be obtained according to the value of the signal charge accumulated in a unit pixel by photoelectric conversion. The dynamic range is determined by the noise ratio.

With such a solid-state image sensor, if the aperture of the camera lens is adjusted to a low-brightness subject, the signal of the high-brightness subject will be saturated. Since the signal of the above is buried in noise, there has been a demand for an image sensor having a sufficiently wide dynamic range, which can obtain a good image regardless of whether the brightness is high or low.

Then, it was required not only to expand the dynamic range but also to expand the dynamic range after satisfying the following items (1) to (4). That is, (1) the resolution characteristics can be made excellent without dividing the photoelectric conversion unit, (2) the moving image imaging characteristics can be made excellent without dividing the exposure time, (3) high sensitivity, It has been required that the trade-off between high S / N and wide dynamic range can be eliminated, and (4) high frame frequency can be read out with an ultra-multi-pixel.

Here, in order to expand the dynamic range of the output signal amount with respect to the incident light amount, two signals obtained by long-time exposure and short-time exposure are read multiple times from the same pixel, and the read sensitivities are different. There is known a method of synthesizing the signals of the above in the signal processing unit in the subsequent stage of the image pickup device (see Patent Document 1 and Non-Patent Document 1).

Further, in the prior art shown in FIG. 22, each pixel has a photodiode PD that receives light and generates an optical charge, a transfer transistor T that is provided adjacent to the PD and transfers an optical charge, and the transfer transistor T. A floating diffusion FD provided by connecting to the PD via the T, and a first storage capacity CSa and a second storage capacity CSb that store the light charge overflowing from the PD during the exposure storage operation through the T. , Equipped with. Further, in addition to these storage capacities CSa and CSb, a reset transistor R for discharging the signal charge in the FD, a first storage transistor Ca provided between the FD and the CSa, and the CSa A second storage transistor Cb provided between the CSb, an amplification transistor SF for reading the signal charges of the FD, the CSa, and the CSb as a voltage, and a pixel or a pixel block provided connected to the SF. It is provided with a selection transistor X for selecting.

In the prior art configured in this way, a plurality of pixels having the above configuration are integrated in a two-dimensional or one-dimensional array, and in each pixel, the transfer transistor T, the first storage transistor Ca, and the second storage transistor Ca. Each drive line is connected to the gate electrode of the storage transistor Cb and the reset transistor R, a pixel selection line driven from the row shift register is connected to the gate electrode of the selection transistor X, and the output of the selection transistor X is further connected. One output line OUT is connected to the side source and controlled by a column shift register, and any signal is output through this one output line OUT (see Patent Document 2).
Japanese Patent No. 3680366 Japanese Patent No. 50666704 Orly Yadid-Pecht and Eric R. Fossum, “Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.44, No.10, pp.1721-1723, Oct., 1997.

However, in the conventional technique described in Patent Document 1 and the like, the signal amount is not doubled in the method of synthesizing the signals by long-time exposure and short-time exposure, whereas the reading noises are integrated. Since it is doubled, the S / N deteriorates especially in low light.
Further, since the long-time exposure and the short-time exposure are imaged at different timings, there is a problem that the imaging times are deviated and the subjects moving at high speed appear to be deviated from each other. Further, since the number of readings per pixel is a plurality of times, the maximum frame frequency is lowered.

Further, in the prior art described in Patent Document 2, the pre-saturation signal and the supersaturated signal are read out by using a storage capacitance element, and the number of readings per pixel is a plurality of times, so that the maximum frame frequency is lowered. ..

The present invention has been made in view of the above circumstances, can realize excellent moving image imaging characteristics and resolution characteristics, and enables linear and high S / N signal acquisition without narrowing the saturation level in low illuminance. , Read control circuit, solid-state image sensor, which can enable good S / N in the linear region in high illuminance, can expand the dynamic range, and can suppress the decrease of the maximum frame frequency. An object of the present invention is to provide a method for driving an image pickup device.

The read control circuit of the present invention
In the read-out control circuit of the solid-state image sensor, the first floating diffusion capacitance means in which the signal from the photoelectric conversion unit is accumulated, the capacitance value is relatively small, and the conversion gain is large,
A second floating diffusion capacitance means having a relatively large capacitance value and a small conversion gain, in which a signal from the first floating diffusion capacitance means is input and accumulated via an overflow gate, is provided.
Both the first stray diffusion capacitance means and the second stray diffusion capacitance means include a unique pixel output circuit, and the pixel output circuits according to each of the first and second stray diffusion capacitance means are parallel to each other. It is configured so that each of the pixel output circuits outputs a pixel output signal at the same time for each horizontal scanning (H) line.
For light incident on the photoelectric conversion portion, the inclination of the first and second floating diffusion capacitance means respectively synthesized post-synthetic output signal of each said pixel output signal from the pixel output circuit according to the, the incident light is It is characterized in that it is configured to change from large to small in the region from the low strength side to the high strength side.
Further, the first stray diffusion capacitance means is configured by using four transistors including a transfer transistor, and the second stray diffusion capacitance means is configured by using four transistors including an overflow gate. be able to.
Further, the first stray diffusion capacitance means is configured by using three transistors not including a transfer transistor, and the second stray diffusion capacitance means is configured by using four transistors including an overflow gate. can do. In this case, it is preferable that the photoelectric conversion unit is composed of a photoelectric conversion film.

Further, the solid-state image sensor of the present invention is
With the above-mentioned read control circuit
It is characterized by including an output unit provided according to the pixel output circuit, which outputs an output signal from each of the above-mentioned unique pixel output circuits to a corresponding output signal line.

Further, the method of driving the image pickup device of the present invention is as follows.
This is a driving method for driving the solid-state image sensor described above.
When the first floating diffusion capacitance means and the second floating diffusion capacitance means are reset and photoelectrons move from the photoelectric conversion unit to the first floating diffusion capacitance means during the signal storage period,
When the saturation capacity of the first stray diffusion capacitance means is set with the gate voltage of the overflow gate as a predetermined value and photoelectrons overflow from the first stray diffusion capacitance means, the overflowing electrons are used as the first. It is moved to the floating diffusion capacitance means 2, and each signal voltage determined by the amount of photoelectrons and the conversion gain for the first floating diffusion capacitance means and the second floating diffusion capacitance means is set to each pixel output signal by the corresponding source follower element. After that, the two pixel output signals are output to the corresponding output signal lines.

According to the readout control circuit and the solid-state image sensor of the present invention, the first stray diffusion capacitance means has a small capacitance and a large conversion gain, so that a linear and high S / N signal without narrowing the saturation level in low illuminance. Can be obtained. The signal charge overflowing from the first floating diffusion capacitance means flows to the second floating diffusion capacitance means through the overflow gate. The second floating diffusion capacitance means has a large capacitance and a small conversion gain, so that the dynamic range can be expanded while achieving a good S / N in the linear region even in high illuminance.

By synthesizing the above two signals output from the solid-state image sensor in the signal processing unit in the subsequent stage, it is possible to obtain a signal having a high S / N in a low illuminance state and a wide dynamic range in a high illuminance state.
Since these two signals acquire optical signals at the same time by the same photoelectric conversion unit, they are excellent in moving image imaging characteristics and resolution characteristics.
It should be noted that a plurality of pixel output circuits and signal output lines are provided, and one column signal processing circuit can be associated with each output line, so that a decrease in the maximum frame frequency can be suppressed.
The effects of the invention described above can be similarly achieved by the driving method of the image pickup device of the present invention.

The equivalent circuit diagram of the unit pixel which concerns on Example 1 is shown. It shows the system block diagram of the solid-state image sensor which has the pixel array of the unit pixel which concerns on Example 1. FIG. It is a time chart of the input signal to the pixel circuit when the signal is read out using the pixel circuit of Example 1 shown in FIG. An example of a schematic plan view of a unit pixel according to the first embodiment is shown. Regarding the first embodiment, (A) shows a potential diagram at the time of exposure in low illuminance, and (B) shows a potential diagram at the time of movement of signal charge in low illuminance. Regarding the first embodiment, (A) shows a potential diagram at the time of exposure at high illuminance, and (B) shows a potential diagram at the time of movement of signal charge at high illuminance. Regarding the first embodiment, (A) is a signal output from the pixel circuit via the first stray diffusion capacitance (FD1) having a high conversion gain and a second stray diffusion capacitance (FD2) having a low conversion gain from the pixel circuit. It is a figure which shows the relationship with the incident light intensity with the output signal, (B) is the figure which shows the relationship with respect to the incident light intensity of the post-synthesis output signal after synthesis by the signal processing part of the latter stage. It is a top view which shows the result by the potential simulation of a unit pixel which concerns on Example 1. FIG. FIG. 8 is a cross-sectional view taken along the line BB'of FIG. FIG. 8 is a cross-sectional view taken along the line CC ′ of FIG. The equivalent circuit diagram of the unit pixel which concerns on Example 2 is shown. It shows the system block diagram of the solid-state image sensor which has the pixel array of the unit pixel which concerns on Example 2. FIG. It is a time chart of the input signal to a pixel circuit in the case where the signal is read out using Example 2 shown in FIG. An example of a schematic plan view of a unit pixel according to the second embodiment is shown. Regarding the second embodiment, (A) shows a potential diagram when the signal charge moves in low illuminance, and (B) shows a potential diagram when the signal charge moves in high illuminance. It is a top view which shows the result by the potential simulation of a unit pixel which concerns on Example 2. FIG. FIG. 16 is a cross-sectional view taken along the line BB'of FIG. FIG. 16 is a cross-sectional view taken along the line CC ′ of FIG. The equivalent circuit diagram of the unit pixel which concerns on Example 3 is shown. 6 is a time chart of an input signal to a pixel circuit when a signal is read out using the third embodiment shown in FIG. An example of a schematic plan view and a schematic cross-sectional view of a unit pixel according to the third embodiment is shown. It shows the equivalent circuit diagram of a single pixel of the solid-state image sensor according to the prior art.

Hereinafter, embodiments of the present invention will be described with reference to the above drawings.
<Example 1>
FIG. 2 is a system configuration diagram of a solid-state image sensor having a pixel array of unit pixels, specifically, a CMOS image sensor. The CMOS image sensor 200 has a pixel array 201 in which unit pixels 202 including a photoelectric conversion element are two-dimensionally arranged in an array and connected to a pixel drive wiring 203 and a vertical signal line 204, and a column signal as a peripheral circuit. It is composed of a processing circuit 205, an output circuit 206, a control circuit 207, a horizontal scanning circuit 208, and a vertical scanning circuit 209.
Here, the reason why the column signal processing circuit 205 and the horizontal scanning circuit 208 are arranged above and below in the drawing is that the frame frequency can be doubled as compared with the case where they are arranged on one side. Because.

Further, FIG. 1 shows an equivalent circuit diagram of a pixel circuit (reading control circuit) used in the CMOS image sensor according to the first embodiment.
As shown in FIG. 1, the read control circuit in this embodiment includes two signal paths, a first signal path and a second signal path.

As shown in FIG. 1, the photodiode (PD) 111, which is a photoelectric conversion element, is connected to the first floating diffusion capacitance (FD1) 113 via the transfer transistor (TX) 112. The first floating diffusion capacitance (FD1) 113 is connected to the second floating diffusion capacitance (FD2) 123 via the overflow gate (OFG) 122.

The pixel output circuit of the first stray diffusion capacitance (FD1) 113, which is the first signal path, is composed of a reset transistor 1 (RT1) 114, a source follower transistor 1 (SF1) 115, and a selection transistor 1 (SL1) 116. The pixel output 1 (OUT1) 117 is connected to the vertical signal line 204A.

On the other hand, the pixel output circuit of the second stray diffusion capacitance (FD2) 123, which is the second signal path, includes the reset transistor 2 (RT2) 124 and the source follower transistor 2 (SF2).
It is composed of 125 and the selection transistor 2 (SL2) 126, and the pixel output 2 (OUT2) 127 is connected to a vertical signal line 204B different from the above.

The drain electrodes of the reset transistor 1 (RT1) 114, the source follower transistor 1 (SF1) 115, the reset transistor 2 (RT2) 124, and the source follower transistor 2 (SF2) 125 are connected to the pixel power supply (VDD) 118. ..

Further, each gate of the transfer transistor (TX) 112, the overflow gate (OFG) 122, the reset transistor 1 (RT1) 114, the reset transistor 2 (RT2) 124, the selection transistor 1 (SL1) 116, and the selection transistor 2 (SL2) 126. The electrodes are connected to the respective pixel drive wiring 203.

In the pixel circuit (reading control circuit) of the unit pixel 202 shown in FIG. 1, the photodiode (PD) 111 accumulates a negative charge in an amount corresponding to the intensity of the incident light. The anode of the photodiode (PD) 111 is grounded, and the cathode is connected to the gate of the source follower transistor 1 (SF1) 115 via the transfer transistor (TX) 112 and the first stray diffusion capacitance (FD1) 113. .. The gate of the transfer transistor (TX) 112 is connected to the pixel drive wiring 203 (TX) from the vertical operation circuit 209, and a transfer signal is input.

In the first signal path, the source follower transistor 1 (SF1) 115 and the selection transistor 1 (SL1) 116 are connected in series between the pixel power supply (VDD) 118 and the pixel output 1 (OUT1) 117. The gate of the selection transistor 1 (SL1) 116 is connected to the pixel drive wiring 203 (SL1) from the vertical operation circuit 209, and the selection signal is input. The reset transistor 1 (RT1) 114 is connected between the pixel power supply (VDD) 118 and the gate of the source follower transistor 1 (SF1) 115. The gate of the reset transistor 1 (RT1) 114 is connected to the pixel drive wiring 203 (RT1) from the vertical operation circuit 209, and a reset signal is input.

Further, the first stray diffusion capacitance (FD1) 113 is connected to the gate of the source follower transistor 1 (SF1) 115.
As described above, the second floating diffusion capacity (FD2) 123 is connected to the first floating diffusion capacity (FD1) 113 via the overflow gate (OFG) 122, and is connected to the first floating diffusion capacity (FD1) 113. When the electric charge accumulated in 113 overflows from the overflow gate (OFG) 122, it is input to the second floating diffusion capacitance (FD2) 123.

In the second signal path, the source follower transistor 2 (SF2) 125 and the selection transistor 2 (SL2) 126 are connected in series between the pixel power supply (VDD) 118 and the pixel output 2 (OUT2) 127. The gate of the selection transistor 2 (SL2) 126 is connected to the pixel drive wiring 203 (SL2) from the vertical operation circuit 209, and the selection signal is input. The reset transistor 2 (RT2) 124 is connected between the pixel power supply (VDD) 118 and the gate of the source follower transistor 2 (SF2) 125. The gate of the reset transistor 2 (RT2) 124 is connected to the pixel drive wiring 203 (RT2) from the vertical operation circuit 209, and a reset signal is input.

Further, the second floating diffusion capacitance (FD2) 123 is connected to the gate of the source follower transistor 2 (SF2) 125.
FIG. 3 is a time chart showing an input signal of each transistor when a signal is read out using the pixel circuit (reading control circuit) 202 shown in FIG.

In FIG. 3, each chart shows the selection transistors 1, 2 (SL1, 2) 116, 126.
The signal waveforms of the reset transistors 1, 2 (RT1, 2) 114, 124, the first transfer transistor (TX) 112, and the overflow gate (OFG) 122 are shown, and are placed after SL, RT, TX, and OFG. The numbers ((1) to (n)) in the written parentheses indicate that they are the unit pixels of the first to nth lines on the corresponding line (row).

As shown in FIG. 3, when the selection transistors 1, 2 (SL1, 2) 116, 126 are in the ON state (SL1 and SL2 are at the “H” level), the reset transistors 1, 2 (RT1, 2) 114, 124 are set. By turning it on (RT1 and RT2 are at "H" level), the first and second stray diffusion capacitances (FD1, 2) 113 and 123 are reset. This is the same for all lines.
By setting the transfer transistor (TX) 112 to the ON state (TX (1) is at the “H” level), the signal charge of the photodiode (PD) 111 passes through the transfer transistor (TX) 112 and the first stray diffusion capacitance ( It moves to FD1) 113 and is converted into a signal voltage by the first stray diffusion capacitance (FD1) 113. When a signal charge exceeding the saturation capacity of the first floating diffusion capacitance (FD1) 113 flows in, it moves to the second floating diffusion capacitance (FD2) 123 via the overflow gate (OFG) 122, and this second floating diffusion capacitance (FD2) 123. It is converted into a signal voltage by the stray diffusion capacitance (FD2) 123 of.

Here, the capacitance of the first floating diffusion capacitance (FD1) 113 is reduced to set the conversion gain high, and the capacitance of the second floating diffusion capacitance (FD2) 123 is increased to set the conversion gain low.
The gate voltage (threshold value) of the overflow gate (OFG) 122 is fixed to a predetermined constant value after adjusting the voltage value in order to set the saturation capacity of the first stray diffusion capacitance (FD1) 113 to a predetermined value. .. The signal voltages of the first stray diffusion capacitance (FD1) 113 and the second stray diffusion capacitance (FD2) 123 are applied to the gate electrodes of the source follower transistor 1 (SF1) 115 and the source follower transistor 2 (SF2) 125, respectively. The output currents from the source follower transistor 1 (SF1) 115 and the source follower transistor 2 (SF2) 125 are output from the pixel output 1 (OUT1) and the pixel output 2 (OUT2) to separate vertical signal lines 204A and B.

FIG. 4 shows an example of a schematic plan view of the unit pixel according to the first embodiment, and corresponds to the equivalent circuit diagram of the unit pixel of FIG.
That is, in this schematic plan view, the photodiode (PD) 111 is via the transfer transistor (TX) 112, the first stray diffusion capacitance (FD1) 113, the reset transistor 1 (RT1) 114, and the pixel power supply (VDD) 118. It is shown that it is connected to the gate of the source follower transistor 1 (SF1) 115. The source follower transistor 1 (SF1) 115 is connected to the pixel output 1 (OUT1) 117 via the selection transistor 1 (SL1) 116.

On the other hand, in this schematic plan view, the photodiode (PD) 111 includes a transfer transistor (TX) 112, an overflow gate (OFG) 122, a second stray diffusion capacitance (FD2) 123, a reset transistor 2 (RT2) 124, and a pixel. It has been shown to be connected to the gate of the source follower transistor 2 (SF2) 125 via the power supply (VDD) 118. The source follower transistor 2 (SF2) 125 is connected to the pixel output 2 (OUT2) 127 via the selection transistor 2 (SL2) 126.

5A and 5B show a cross section taken along the line AA'in the schematic plan view of FIG. 4 in the case of low illuminance, in which FIG. 5A is for exposure and FIG. 5B is for signal charge transfer. It shows.
The name of the part where each potential is shown is indicated by a symbol above the part (same in FIG. 6).
Further, the portion indicated by cross-hatching in the figure indicates the amount of electrons existing in the first floating diffusion capacitance (FD1) 113 and the second floating diffusion capacitance (FD2) 123 from the beginning, and is shown in satin finish. The portion indicates the amount of photoelectrons flowing into the photodiode (PD) 111 or from the photodiode (PD) 111 (same in FIG. 6).
As is clear from these figures, the amount of photoelectrons in the photodiode (PD) 111 is small when the illuminance is low, so that when the transfer transistor (TX) 112 is in the ON state, the photoelectrons are first suspended and diffused. It only moves to the capacitance (FD1) 113, not to the second floating diffusion capacitance (FD2) 123. Therefore, the second stray diffusion capacitance (FD2) 123 remains the original voltage VDD.

On the other hand, FIG. 6 shows a cross section taken along the line AA'in the schematic plan view of FIG. 4 in the case of high illuminance, (A) is for exposure, and (B) is for movement of signal charge. , Each is shown.
As is clear from these figures, the amount of photoelectrons in the photodiode (PD) 111 is large when the illuminance is high, so that when the transfer transistor (TX) 112 is in the ON state, the photoelectrons are first suspended and diffused. At the same time as moving to the capacity (FD1) 113, it overflows from the first floating diffusion capacity (FD1) 113 and moves to the second floating diffusion capacity (FD2) 123. Therefore, in the second floating diffusion capacitance (FD2) 123, the amount of photoelectrons is increased from the original voltage VDD.

FIG. 7A shows a high conversion gain signal output from the pixel output circuit via the first stray diffusion capacitance FD1 (113) and an output from the pixel output circuit via the second stray diffusion capacitance FD2 (123). It is a figure which shows the relationship with respect to the incident light intensity of the signal of the low conversion gain to be made.
Further, in FIG. 7B, a signal having a high conversion gain (FD1) and a signal having a low conversion gain (FD2) are signal-synthesized in a signal processing unit (not shown) in a subsequent stage outside the solid-state image sensor. It is a figure which shows the signal (output signal after synthesis) in relation to the incident light intensity.
As can be seen from FIG. 7A, the high conversion gain (FD1) signal is saturated at a constant output value (saturation point), and at this incident light intensity, the low conversion gain (FD2) is just right. Since the signal of (FD2) rises, both signals may be combined so as to be connected at the rising point of the signal of this low conversion gain (FD2).
As shown in the figure, the combined signal has a large slope at low illuminance and a high S / N, while it has a small slope at high illuminance and has a wide dynamic range. Therefore, one signal can exert two contradictory characteristics. Therefore, matching with a low-brightness subject may saturate the signal of a high-brightness subject, or matching with a high-brightness subject may cause the signal of a low-brightness subject to be buried in noise. It can be avoided.
Further, in this embodiment, the resolution characteristics can be improved without dividing the photoelectric conversion unit, the moving image imaging characteristics can be improved without dividing the exposure time, and the sensitivity and high sensitivity can be further improved. The trade-off between S / N and wide dynamic range can be eliminated.

Next, FIG. 8 is a plan view showing the result of the potential simulation of the unit pixel. 2.5V for the gate electrode of the transfer transistor (TX) 112, 1.9V for the gate electrode of the overflow gate (OFG) 122, reset transistor 1 (RT1) 114, reset transistor 2 (RT2) 124, source follower transistor 1 0V is applied to the gate electrodes of (SF1) 115, the source follower transistor 2 (SF2) 125, the selection transistor 1 (SL1) 116, and the selection transistor 2 (SL2) 126.
In FIG. 8, the numbers of the respective parts in FIG. 8 are omitted in order to prevent the lines and the like representing the respective parts from becoming difficult to see due to the complexity caused by inserting the characters.

Further, FIG. 9 is a cross-sectional view taken along the line BB'in FIG. In the example of FIG. 9, a state in which photoelectrons are empty in the photodiode (PD) 111 is shown.
That is, in this BB'line cross section, it is shown that the photodiode (PD) 111 is in a state where electrons are not accumulated at the bottom of the conduction band and is in an empty state. On the other hand, a state in which a predetermined amount of electrons are contained in the first floating diffusion capacitance (FD1) 113 and the lower portion of the transfer transistor (TX) 112 is shown.

On the other hand, FIG. 10 is a cross-sectional view taken along the line CC'in FIG. In the example of FIG. 10, a state in which electrons are saturated is shown in the first floating diffusion capacitance (FD1) 113.
That is, the first floating diffusion capacitance (FD1) 113 is saturated with photoelectrons (the overflow gate (OFG) 122 is full), and the first floating diffusion capacitance (FD1) 113 is further filled with photoelectrons. When it comes, the photoelectrons flow into the second floating diffusion capacitance (FD2) 123. In the state shown in FIG. 10, the second floating diffusion capacitance (FD2) 123 is in the state of VDD = 3.3V and is the original state of electrons, and is from the first floating diffusion capacitance (FD1) 113. It is said that photoelectrons have not yet flowed in.
<Example 2>

Hereinafter, Example 2 of the present invention will be described with reference to the above drawings.
In addition, since the thing of Example 2 has many parts in common with the thing of Example 1, in the following description, the number given to each part of Example 1 plus 200 corresponds to each part of Example 1. It is attached to each part of the second embodiment, and the detailed description thereof may be omitted.
FIG. 12 shows a system configuration of a solid-state image sensor having a pixel array of unit pixels according to the second embodiment, specifically, a CMOS image sensor, and corresponds to FIG. 2 shown in the first embodiment. .. The CMOS image sensor 400 has a pixel array 401 in which unit pixels 402 including a photoelectric conversion element are two-dimensionally arranged in an array and connected to a pixel drive wiring 403 and a vertical signal line 404, and a column signal as a peripheral circuit. It is composed of a processing circuit 405, an output circuit 406 connected to a digital CDS circuit 410 outside the sensor, a control circuit 407, a horizontal scanning circuit 408, and a vertical scanning circuit 409.
Here, the reason why the column signal processing circuit 405 and the horizontal scanning circuit 408 are arranged above and below in the figure is that the frame frequency can be doubled as compared with the case where they are arranged on one side. Because.

Further, FIG. 11 shows an equivalent circuit diagram of a pixel circuit (reading control circuit) used in the CMOS image sensor according to the second embodiment. In this equivalent circuit, the pixel circuit that reads the signal charge from the photoelectric conversion unit is the first floating diffusion capacitance means, and since no transfer transistor is arranged, the pixel circuit is from three transistors, and the second floating diffusion capacitance means. It is composed of four transistors including an overflow gate, and is configured to generate a signal that is in a high S / N state in a low illuminance state and in a wide dynamic range state in a high illuminance state.
As shown in FIG. 11, the read control circuit according to the second embodiment includes two signal paths, a first signal path and a second signal path.

As shown in FIG. 11, the photodiode (PD) 311 which is a photoelectric conversion element is connected to the first floating diffusion capacitance (FD1) 313. The first floating diffusion capacitance (FD1) 313 is connected to the second floating diffusion capacitance (FD2) 323 via an overflow gate (OFG) 322.

The pixel output circuit of the first stray diffusion capacitance (FD1) 313, which is the first signal path, is composed of a reset transistor 1 (RT1) 314, a source follower transistor 1 (SF1) 315, and a selection transistor 1 (SL1) 316. The pixel output 1 (OUT1) 317 is connected to the vertical signal line 404A.

On the other hand, the pixel output circuit of the second stray diffusion capacitance (FD2) 323, which is the second signal path, includes the reset transistor 2 (RT2) 324, the source follower transistor 2 (SF2) 325, and the selection transistor 2 (SL2) 326. The pixel output 2 (OUT2) 327 is connected to a vertical signal line 404B different from the above.

Each drain electrode of the reset transistor 1 (RT1) 314, the source follower transistor 1 (SF1) 315, the reset transistor 2 (RT2) 324, and the source follower transistor 2 (SF2) 325 is connected to the pixel power supply (VDD) 318. ..

Further, each gate electrode of the overflow gate (OFG) 322, the reset transistor 1 (RT1) 314, the reset transistor 2 (RT2) 324, the selection transistor 1 (SL1) 316, and the selection transistor 2 (SL2) 326 is pixel-driven. It is connected to the wiring 403.

In the pixel circuit (reading control circuit) of the unit pixel 402 shown in FIG. 11, the photodiode (PD) 311 generates a negative charge in an amount corresponding to the intensity of the incident light. The anode of the photodiode (PD) 311 is grounded and the cathode is connected to the gate of the source follower transistor 1 (SF1) 315 via a first stray diffusion capacitance (FD1) 313.

In the first signal path, the source follower transistor 1 (SF1) 315 and the selection transistor 1 (SL1) 316 are connected in series between the pixel power supply (VDD) 318 and the pixel output 1 (OUT1) 317. The gate of the selection transistor 1 (SL1) 316 is connected to the pixel drive wiring 403 (SL1) from the vertical operation circuit 409, and the selection signal is input. The reset transistor 1 (RT1) 314 is connected between the pixel power supply (VDD) 318 and the gate of the source follower transistor 1 (SF1) 315. The gate of the reset transistor 1 (RT1) 314 is connected to the pixel drive wiring 403 (RT1) from the vertical operation circuit 409, and a reset signal is input.

Further, the first stray diffusion capacitance (FD1) 313 is connected to the gate of the source follower transistor 1 (SF1) 315.
As described above, the second floating diffusion capacity (FD2) 323 is connected to the first floating diffusion capacity (FD1) 313 via the overflow gate (OFG) 322, and the first floating diffusion capacity (FD1). When the electric charge accumulated in the 313 overflows from the overflow gate (OFG) 322, it is input to the second floating diffusion capacitance (FD2) 323.

In the second signal path, the source follower transistor 2 (SF2) 325 and the selection transistor 2 (SL2) 326 are connected in series between the pixel power supply (whether) 318 and the pixel output 2 (OUT2) 327. The gate of the selection transistor 2 (SL2) 326 is connected to the pixel drive wiring 403 (SL2) from the vertical operation circuit (numbered 409 in FIG. 12: the same applies hereinafter), and the selection signal is input. The reset transistor 2 (RT2) 324 is connected between the pixel power supply (VDD) 318 and the gate of the source follower transistor 2 (SF2) 325. The gate of the reset transistor 2 (RT2) 324 is connected to the pixel drive wiring 403 (RT2) from the vertical operation circuit 409, and a reset signal is input.

Further, the second floating diffusion capacitance (FD2) 323 is connected to the gate of the source follower transistor 2 (SF2) 325.
FIG. 13 is a time chart showing an input signal of each transistor when a signal is read out using the pixel circuit (reading control circuit) 402 shown in FIG.

In FIG. 13, each chart shows the signal waveforms of the selection transistors 1, 2 (SL1, 2) 316, 326, the reset transistors 1, 2 (RT1, 2) 314, 324, and the overflow gate (OFG) 322. , SL, RT and OFG, the numbers ((1) to (n)) in the parentheses indicate that they are the unit pixels of the 1st to nth lines on the corresponding line (line). There is. The ADC indicates the sampling timing of the AD converter. In the prior art, when the pixel circuit is composed of three transistors, the drive waveform is reset noise removed by a post-reset digital correlated double sampling (digital CDS). Since this method is an improvement from the case where the pixel circuit is composed of three transistors, the reset noise of the drive waveform is removed by the digital CDS of the post-reset method.

As shown in FIG. 13, when the selection transistors 1, 2 (SL1, 2) 316 and 326 are on (SL1 and SL2 are at "H" level), the reset transistors 1, 2 (RT1, 2) 314 and 324 are set. By turning it on (RT1 and RT2 are at "H" level), the first and second stray diffusion capacitances (FD1, 2) 313 and 323 are reset. This is the same for all lines.
The signal charge of the photodiode (PD) 311 moves to the first stray diffusion capacitance (FD1) 313 and is converted into a signal voltage by the first stray diffusion capacitance (FD1) 313. When a signal charge exceeding the saturation capacity of the first floating diffusion capacitance (FD1) 113 flows in, it moves to the second floating diffusion capacitance (FD2) 323 via the overflow gate (OFG) 322, and this second floating diffusion capacitance (FD2) It is converted into a signal voltage by the stray diffusion capacitance (FD2) 323 of.

Here, the capacitance of the first floating diffusion capacitance (FD1) 313 is reduced to set the conversion gain high, and the capacitance of the second floating diffusion capacitance (FD2) 323 is increased to set the conversion gain low.
The gate voltage (threshold value) of the overflow gate (OFG) 322 is fixed to a predetermined constant value after adjusting the voltage value in order to set the saturation capacitance of the first stray diffusion capacitance (FD1) 313 to a predetermined value. .. The signal voltages of the first stray diffusion capacitance (FD1) 313 and the second stray diffusion capacitance (FD2) 323 are applied to the gate electrodes of the source follower transistor 1 (SF1) 315 and the source follower transistor 2 (SF2) 325, respectively. The output currents from the source follower transistor 1 (SF1) 315 and the source follower transistor 2 (SF2) 325 are output from the pixel output 1 (OUT1) and the pixel output 2 (OUT2) to separate vertical signal lines 404A and B.

FIG. 14 shows an example of a schematic plan view of the unit pixel according to the second embodiment, and corresponds to the equivalent circuit diagram of the unit pixel of FIG.
That is, in this schematic plan view, the photodiode (PD) 311 is the source follower transistor 1 (SF1) via the first stray diffusion capacitance (FD1) 313, the reset transistor 1 (RT1) 314, and the pixel power supply (VDD) 318. ) It is shown to be connected to the gate of 315. The source follower transistor 1 (SF1) 315 is connected to the pixel output 1 (OUT1) 317 via the selection transistor 1 (SL1) 316.

On the other hand, in this schematic plan view, the photodiode (PD) 311 is via an overflow gate (OFG) 322, a second stray diffusion capacitance (FD2) 323, a reset transistor 2 (RT2) 324, and a pixel power supply (VDD) 318. It is shown that it is connected to the gate of the source follower transistor 2 (SF2) 325. The source follower transistor 2 (SF2) 325 is connected to the pixel output 2 (OUT2) 327 via the selection transistor 2 (SL2) 326.

FIG. 15A shows a cross section taken along the line AA'of FIG. 14 which is a schematic plan view in the case of low illuminance, and shows the time when the signal charge moves.
The name of the part where each potential is shown is indicated by a symbol above the part.
Further, the portion indicated by cross-hatching in the figure indicates the amount of electrons existing in the first floating diffusion capacitance (FD1) 313 and the second floating diffusion capacitance (FD2) 323, and the portion indicated by satin finish is It shows the amount of photoelectrons flowing in from the photodiode (PD) 311.
As is clear from these figures, when the illuminance is low, the amount of photoelectrons generated by the photodiode (PD) 311 is small, so that the photoelectrons only move to the first floating diffusion capacitance (FD1) 313. It does not move to the second floating diffusion capacitance (FD2) 323. Therefore, the second stray diffusion capacitance (FD2) 323 remains at the original voltage VDD.

On the other hand, FIG. 15B shows the AA'line cross section of the potential diagram in FIG. 14 in the case of high illuminance, and shows the time when the signal charge moves.
As is clear from these figures, when the illuminance is high, the amount of photoelectrons generated by the photodiode (PD) 311 is large, so that the photoelectrons move to the first floating diffusion capacitance (FD1) 313 at the same time. , It overflows from the first floating diffusion capacity (FD1) 313 and moves to the second floating diffusion capacity (FD2) 323. Therefore, in the second floating diffusion capacitance (FD2) 323, the amount of photoelectrons is increased from the original voltage VDD.

In this embodiment, a high conversion gain signal output from the pixel output circuit via the first floating diffusion capacitance FD1 (313) and an output from the pixel output circuit via the second floating diffusion capacitance FD2 (323). Since the relationship of the low conversion gain signal to the incident light intensity is the same as that described with reference to FIG. 7 in Example 1, the description thereof will be omitted here.

Next, FIG. 16 is a plan view showing the result of the potential simulation of a unit pixel. 1.9V, reset transistor 1 (RT1) 314, reset transistor 2 (RT2) 324, source follower transistor 1 (SF1) 315, source follower transistor 2 (SF2) 325, selected for the gate electrode of the overflow gate (OFG) 322. 0V is applied to the gate electrodes of the transistor 1 (SL1) 316 and the selection transistor 2 (SL2) 326.
Compared with FIG. 8 which is a similar diagram in the first embodiment, the difference is that the transfer transistor (TX) 112 is not provided between the photodiode (PD) 311 and the first stray diffusion capacitance (FD1) 313. (Same for FIG. 17).

Further, FIG. 17 is a cross-sectional view taken along the line BB'in FIG. In the example of FIG. 17, a state in which photoelectrons are empty is shown in the photodiode (PD) 311.
That is, in this BB'line cross section, the photodiode (PD) 311 is in a state where electrons are not accumulated at the bottom of the conduction band, and it is shown that the photodiode (PD) 311 is in an empty state. On the other hand, a state in which a predetermined amount of electrons are contained is shown in the lower part of the first floating diffusion capacitance (FD1) 313.

On the other hand, FIG. 18, which is a cross-sectional view taken along the line CC'in FIG. 16, is the same as the cross-sectional view taken along the line CC'of FIG. 8 in the first embodiment, and thus the description of FIG. 18 will be omitted.
In the second embodiment formed as described above, there are many configurations common to those of the first embodiment, but there are also parts different from each other. Hereinafter, this difference will be mainly described in an enumerated format.

<Differences between Example 1 and Example 2>
In the first embodiment, a wide dynamic range function is provided on the premise of a 4-transistor pixel circuit, whereas in the second embodiment, a wide dynamic range function is provided on the premise of a 3-transistor pixel circuit. .. Therefore, Example 1 and Example 2 differ from each other in that the premise is a 4-transistor pixel circuit and a 3-transistor pixel circuit (difference 1 below).
Further, in the first embodiment, the pixel circuit of four transistors is provided with a wide dynamic range function, and in the second embodiment, the pixel circuit of three transistors is provided with a wide dynamic range function. There is a difference in the difference in action and effect due to having a wide dynamic range function in different pixel circuits (difference 2 below).

[1] Difference 1
(1) Equivalent circuit and layout In the first embodiment, the transfer transistor (TX), the reset transistor 1 (RT1), the source follower transistor 1 (SF1), and the selection transistor 1 (SL1) are used for the first stray diffusion capacitance. It is composed of four transistors (4-transistor system) of ) Is composed of four transistors.
On the other hand, in the second embodiment, the transfer transistor (TX) is not provided, and the reset transistor 1 (RT1), the source follower transistor 1 (SF1), and the selection transistor 1 have the first stray diffusion capacitance. It is composed of three transistors (3-transistor system) of (SL1), and has an overflow gate (OFG), a reset transistor 2 (RT2), a source follower transistor 2 (SF2), and a selection transistor for the second stray diffusion capacitance. It is composed of four transistors of 2 (SL2).
However, in the first embodiment, by holding the transfer transistor (TX) in the ON state, the driving method for three transistors as in the second embodiment can be applied.
(2) Drive waveform In Example 1 of the 4-transistor method, a pre-reset method is adopted in which the signal is read after resetting. Therefore, an analog CDS is placed between the pixel and the AD converter to reset. Noise can be removed.
On the other hand, in the second embodiment of the three-transistor method, a post-reset method is adopted in which the signal is read and then reset. Therefore, even if the analog CDS is placed between the pixel and the AD converter, the reset is performed. Noise cannot be removed. Since there is a correlation regarding reset noise between the reset noise and the signal after one frame (signal + reset noise) (the reset noise is at substantially the same level), the digital CDS can be applied to remove the reset noise. The digital CDS (see the digital CDS 410 in FIG. 12) can be configured by arranging a frame memory outside the sensor chip.
(3) Maximum frame frequency In Example 2 of the 3-transistor system, when digital CDS is adopted, the reset noise and the signal (signal + reset noise) after one frame are read out by the AD converter, and both are read. Since the difference is obtained and the reset noise is offset to obtain an image signal for one frame (see FIG. 13), if the circuit configuration other than the pixels is the same, the 4-transistor method is used when the 3-transistor method is adopted. The maximum frame frequency is halved as compared with the case of adopting.
(4) Noise The correlation between the 4-transistor reset noise and the reset noise between the signal (signal + reset noise) is based on the correlation between the 3-transistor reset noise and the signal (signal + reset noise). The 4-transistor method has a greater effect of canceling reset noise in CDS.
(5) Saturation signal amount The saturation signal amount of the 4-transistor system is defined by the saturated electron amount of the photodiode (PD). The electrons overflowing from the photodiode (PD) during exposure move to the stray diffusion capacitance (FD) and are emitted to the pixel power supply (VDD) at reset. The electrons overflowing from the photodiode (PD) during the storage period of each frame are not used.
On the other hand, the saturation signal amount of the three-transistor system is defined by the saturated electron amount of the stray diffusion capacitance (FD). Since the photodiode (PD) is n-type and the impurity concentration is low, the floating diffusion capacitance (FD) is n + type and the impurity concentration is high, so that the floating diffusion capacitance (FD) has a high density of states and a small area. However, the amount of saturated electrons is larger than that of the photodiode (PD). The electrons overflowing from the floating diffusion capacitance (FD) during the accumulation period of each frame are not used.
(6) Sensitivity of the photodiode (PD) When a microlens is not attached to each pixel, the sensitivity of the photodiode (PD) is defined by the area of the photodiode (PD). On the other hand, when a microlens is attached to each pixel, the incident light is focused on the pixel, so the sensitivity of the photodiode (PD) is higher than the area of the photodiode (PD). Is greatly influenced by. The sensitivity of the photodiode (PD) is not significantly affected by whether it is a 4-transistor system or a 3-transistor system.

[2] Difference 2
(1) A circuit having a wide dynamic range function on the premise of the 4-transistor pixel circuit according to the first embodiment (hereinafter, may be referred to as a 4Tr. Method with a wide DR function) and a three-transistor pixel according to the second embodiment. Before comparing with a circuit having a wide dynamic range function (hereinafter, may be referred to as a 3Tr. Method with a wide DR function), the effect of adding the wide DR function will be mentioned.
The effects are that (A) the photoelectric conversion unit is not divided and the resolution characteristics are excellent, (B) the exposure time is not divided and the moving image imaging characteristics are excellent, and (C) the pixel output signal. The trade-off between high sensitivity and high S / N and wide dynamic range can be eliminated, and (D) high frame frequency can be achieved with ultra-multi-pixels.
(2) Specific Configuration and Effect of Wide DR Function The first floating diffusion capacity (FD1) and the second floating diffusion capacity (FD2) are connected by an overflow gate (OFG), and the first floating diffusion capacity is configured. The saturated electron amount of the capacitance (FD1) is adjusted by the gate voltage of the overflow gate (OFG), and the electrons overflowing from the first floating diffusion capacitance (FD1) are moved to the second floating diffusion capacitance (FD2). The first floating diffusion capacitance (FD1) and the second floating diffusion capacitance (FD2) output signals different from each other from the output units OUT1 and OUT2 via their respective pixel circuits. The area of the first floating diffusion capacitance (FD1) is small and the charge-voltage conversion coefficient is high, while the area of the second floating diffusion capacitance (FD2) is large and the charge-voltage conversion coefficient is low. On the low-light side, only the first floating diffusion capacitance (FD1) is used to obtain a high-sensitivity, high S / N signal, while on the high-illuminance side, the first floating diffusion capacitance (FD1) and the second floating diffusion capacitance (FD1) are used. The diffusion capacitance (FD2) is used to obtain a high-sensitivity, wide DR signal, and the above two signals are combined outside the sensor chip to obtain a wide DR signal.
In addition, 4Tr. Method and 3Tr. With wide DR function. The wide DR function itself of the method is the same.
(3) Maximum frame frequency Since two types of pixel outputs are provided, by arranging an AD converter for each, a decrease in the maximum frame frequency can be suppressed and a frame equivalent to the conventional technology can be suppressed. It can be a frequency.
(4) Noise, Semaphore Signal Amount, and Photodiode (PD) Sensitivity The noise, saturation signal amount, and photodiode (PD) sensitivity are the same as in Difference 1 above.
(5) 3Tr. With wide DR function. When using a photoelectric conversion film as the method 3Tr. With wide DR function. The method has the following advantages by laminating the photoelectric conversion film (see Example 3 below). In this case, the film material of the photoelectric conversion film is not particularly limited.
3Tr. With wide DR function in which a photoelectric conversion film is laminated. In the method, since the n + type Si having a floating diffusion capacitance (FD) and the metal of VIA are connected without a barrier, the reset operation time and the signal reading time can be shortened (in the prior art). It can be the same as the case of the 3Tr. Method).
In addition, 4Tr. With a wide DR function in which a photoelectric conversion film is laminated. In the method, a photoelectric conversion film can be laminated as a structure, but the n-type Si of the photodiode (PD) and the metal of VIA are connected, and the n + type Si of the stray diffusion capacitance (FD) and the metal of VIA are connected. In between, the photodiode (P
Since the n-type Si of D) enters and functions as a barrier, there is a problem because the reset operation time and the signal reading time become long.
Further, as shown in Example 2, 3 Tr. With a wide DR function using a general photodiode (PD). In the method, there are seven transistors in the pixel, the area ratio occupied by these transistors is large, and the aperture ratio of the photodiode (PD) is low. Therefore, it is necessary to collect light with a microlens. As shown in Example 3 described later, a 3Tr. With a wide DR function in which a photoelectric conversion film is laminated. In the method, the aperture ratio can be set to about 100% without a microlens.

<Example 3>
In the second embodiment, since the photodiode (PD) 311 can be replaced with the photoelectric conversion film (PF) 511, only the portion of the photodiode (PD) 311 is replaced with the photoelectric conversion film (PF) 511 in this way. This will be described below with reference to Example 3.

As shown in FIG. 19, it shows an equivalent circuit diagram of a pixel circuit (reading control circuit) used in a solid-state image sensor having a pixel array of unit pixels 602 according to the third embodiment, specifically, a CMOS image sensor. be. Since the thing of Example 3 has many parts in common with that of Example 2, in the following description, the number given to each part of Example 2 plus 200 corresponds to each part of Example 2. The detailed description of each part of the third embodiment may be omitted.

As shown in FIG. 19, the photoelectric conversion unit in Example 3 is a photoelectric conversion film (PF) 511. The photoelectric conversion film (PF) 511 is laminated on each unit pixel 602 and is connected to the first floating diffusion capacitance (FD1) 513.
By stacking the photoelectric conversion film on each unit pixel 602 in this way, the space for arranging each unit pixel 602 can be effectively used, and the density of the pixels can be increased.

In the pixel circuit (reading control circuit) of the unit pixel 602 shown in FIG. 19, the photoelectric conversion film (PF) 511 generates a negative charge in an amount corresponding to the intensity of the incident light. The upper electrode (UE) 511A of the photoelectric conversion film (PF) 511 is connected to the pixel drive wiring (UE) 603, and the lower electrode (LE) 511B is a source follower transistor via the first stray diffusion capacitance (FD1) 513. It is connected to the gate of 1 (SF1) 515.

FIG. 20 shows a time chart showing an input signal of each transistor when a signal is read out using the pixel circuit (reading control circuit) shown in FIG.

Since each chart in FIG. 20 is the same as each chart in FIG. 13 (other than the chart of the uppermost upper electrode (UE)) described in the second embodiment, the description of each chart will be omitted.
The upper electrode (UE) is configured so that the photoelectric conversion film is maintained in the ON state by constantly inputting an L signal.

FIG. 21 shows an example of a schematic plan view and a schematic cross-sectional view of a unit pixel, and corresponds to the equivalent circuit diagram of the unit pixel 602 of FIG.
That is, in the schematic plan view and the schematic cross-sectional view, the photoelectric conversion film (PF) 511 has a structure sandwiched between the upper electrode (UE) 511A and the lower electrode (LE) 511B, as shown in FIG. The upper electrode (UE) 511A is connected to the pixel drive wiring (UE) 603, and the lower electrode (LE) 511B is connected to the first stray diffusion capacitance (FD1) 513. Compared with FIG. 14 of the second embodiment, since there is no photodiode (PD) 311 that occupies a large area, the pixel size can be reduced.

Further, in the schematic plan view and the schematic cross-sectional view, the lower electrode (LE) 511B is connected to the first floating diffusion capacitance (FD1) 513, and the first floating diffusion capacitance (FD1) 513 is an overflow gate (OFG) 522. It is shown that it is connected to the second floating diffusion capacitance (FD2) 523 via.

Here, the case where the carrier of the photoelectric conversion film (PF) 511 is an electron and a negative voltage is applied to the upper electrode (UE) 511A has been described, but the carrier is a hole and a positive voltage is applied to the upper electrode (UE). The same effect can be obtained when is applied.

The image pickup apparatus, drive method, and readout control circuit of the present embodiment are configured as described above, so that linear and high S / N signal acquisition can be performed in a low illuminance state without narrowing the saturation level. This can be done, and in a high illuminance state, the dynamic range can be expanded while ensuring a good S / N in the linear region.
In particular, since each of the low-light state and the high-light state is equipped with a pixel output circuit and a signal output line, the optical signal obtained by the same photoelectric conversion unit at the same time is read out at a high frame frequency. It is possible to support an imaging device that reads out ultra-multipixels at a high frame frequency while having excellent moving image imaging characteristics and resolution characteristics.
Such an action effect is obtained, for example, in the case of reading an ultra-multi-pixel at a high frame frequency as in Super Hi-Vision, etc., as compared with the one described in Patent Document 2 (Patent No. 50666704) described in the prior art. It is extremely advantageous.

Further, the readout control circuit, the solid-state image pickup device, and the drive method of the image pickup device of the present invention are not limited to those of the above-described embodiment, and various other aspects may be adopted. For example, in the above embodiment, two sets of image output circuit units and two sets of output signal lines are provided, but instead of these, three or more sets of image output circuit units and three or more sets of output signal lines are provided. You may. When there are three sets of image output circuit units and three output signal lines, it is possible to correspond to each exposure of high illuminance, medium illuminance, and low illuminance.

Further, the equivalent circuit configuration of each unit pixel is not limited to the circuit shown in FIGS. 1, 11 and 19, but can be changed to various other modes, and each pixel output can be changed. It is also possible to increase the number of transistors in the circuit section.
Further, the saturated voltage of each stray diffusion capacitance (FD1, 2) 113, 123, 313, 323, 513, 523 (gate setting value of overflow gate (OFG)) and the gate voltage of various transistors can also be used as the gate voltage of the above embodiment. It is not limited to the one, and can be set to an appropriate value.

111, 311 photodiode (PD)
112 Transfer Transistor (TX)
113, 313, 513 First floating diffusion capacity (FD1)
114, 314, 514 Reset Transistor 1 (RT1)
115, 315, 515 Source follower transistor 1 (SF1)
116, 316, 516 Selective transistor 1 (SL1)
117, 317, 517 Pixel output 1 (OUT1)
118, 318, 518 pixel power supply (VDD)
122, 322, 522 Overflow Gate (OFG)
123, 323, 523 Second floating diffusion capacity (FD2)
124, 324, 524 Reset Transistor 2 (RT2)
125, 325, 525 Source follower transistor 2 (SF2)
126, 326, 526 Selective transistor 2 (SL2)
127, 327, 527 Pixel output 2 (OUT2)
200, 400 CMOS image sensor 201, 401 pixel array 202, 402, 602 unit pixel 203, 403, 603 pixel drive wiring 204, 204A, B, 404A, B, 604A, B vertical signal line 205, 405 column signal processing circuit 206 , 406 Output circuit 207, 407 Control circuit 208, 408 Horizontal scanning circuit 209, 409 Vertical scanning circuit 410 Digital CDS
511 Photoelectric conversion film (PF)
511A Upper electrode (UE)
511B lower electrode (LE)

Claims (6)

In the read-out control circuit of the solid-state image sensor, the first floating diffusion capacitance means in which the signal from the photoelectric conversion unit is accumulated, the capacitance value is relatively small, and the conversion gain is large,
A second floating diffusion capacitance means having a relatively large capacitance value and a small conversion gain, in which a signal from the first floating diffusion capacitance means is input and accumulated via an overflow gate, is provided.
Both the first stray diffusion capacitance means and the second stray diffusion capacitance means include a unique pixel output circuit, and the pixel output circuits according to each of the first and second stray diffusion capacitance means are parallel to each other. It is configured so that each of the pixel output circuits outputs a pixel output signal at the same time for each horizontal scanning (H) line.
For light incident on the photoelectric conversion portion, the inclination of the first and second floating diffusion capacitance means respectively synthesized post-synthetic output signal of each said pixel output signal from the pixel output circuit according to the, the incident light is It is configured to change from large to small in the region from the low strength side to the high strength side .
A read control circuit characterized by the fact that. The first stray diffusion capacitance means is configured by using four transistors including a transfer transistor, and the second stray diffusion capacitance means is configured by using four transistors including an overflow gate. The read control circuit according to claim 1. The first stray diffusion capacitance means is configured by using three transistors that do not include a transfer transistor, and the second stray diffusion capacitance means is configured by using four transistors that include an overflow gate. The read control circuit according to claim 1, wherein the read control circuit is provided. The read-out control circuit according to claim 3, wherein the photoelectric conversion unit is composed of a photoelectric conversion film. The read control circuit according to any one of claims 1 to 4,
A solid-state image pickup device including an output unit provided according to each of the pixel output circuits, which outputs a signal output from each of the unique pixel output circuits to a corresponding output signal line. The driving method for driving the solid-state image sensor according to claim 5.
When the first floating diffusion capacitance means and the second floating diffusion capacitance means are reset and photoelectrons move from the photoelectric conversion unit to the first floating diffusion capacitance means during the signal storage period,
The saturation capacity of the first stray diffusion capacitance means is set with the gate voltage of the overflow gate as a predetermined value, and when photoelectrons overflow from the first stray diffusion capacitance means, the overflowing electrons are referred to the first. It is moved to the floating diffusion capacitance means 2, and each signal voltage determined by the amount of photoelectrons and the conversion gain for the first floating diffusion capacitance means and the second floating diffusion capacitance means is set to each pixel output signal by the corresponding source follower element. A driving method for driving a solid-state image sensor, which comprises converting the voltage into the above and then outputting the two pixel output signals to the corresponding output signal lines.

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