JP2016010050A - Pixel circuit and imaging device mounting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pixel circuit in which the aperture ratio of the light-receiving portion can be increased furthermore, and the pixels can be miniaturized furthermore compared with a pixel circuit known in the art, and to provide an imaging device mounting the same.SOLUTION: Each signal storage section 110, 120 includes a charge generating part 11 generating charges depending on the light irradiation, intermediate charge storage means 23 for temporarily storing the signal charges thus generated, a transistor 22 for global shutter transferring the signal charges generated in the charge generating part 11 to the intermediate charge storage means 23, and a transistor 12 for read selection transferring the signal charges from the intermediate charge storage means 23 to a signal read section 130. The signal read section 130 includes charge storage means 13 for storing the signal charges from the intermediate charge storage means 23, a transistor 14 for reset which resets the charge storage means 13, a transistor 15 for amplification outputting a signal depending on the charges of the charge storage means 13, and a pixel selection transistor 16 performing pixel selection (signs of A, B are omitted).

Description

  The present invention relates to a pixel circuit that accumulates and reads out signal charges in each pixel of a CMOS type image sensor and an image pickup apparatus equipped with the same, and particularly under illumination where the power supply frequency is 50 Hz and the intensity change is 100 Hz. The present invention relates to a pixel circuit used in a CMOS type imaging device in which flicker generated when imaging with a frame frequency of 120 Hz is reduced, and an imaging device equipped with the pixel circuit.

  In recent years, video cameras, electronic still cameras, and the like using CMOS solid-state imaging devices have been widely used.

  In such a CMOS type solid-state imaging device (hereinafter, also referred to as “solid-state imaging device”), a method of sequentially reading out signal charges generated and accumulated in each pixel arranged in a two-dimensional matrix for each row is adopted. Has been. In this readout method, the exposure period in the photoelectric conversion unit of each pixel circuit is determined by the start and end of signal charge readout, and the exposure timing differs for each row. This readout method is called “rolling shutter”. For this reason, if a fast-moving subject is imaged using such a CMOS solid-state imaging device, the subject may be distorted and imaged.

  As an imaging method for eliminating the distortion of the subject image, a simultaneous imaging function (hereinafter referred to as “global shutter function”) that simultaneously generates and accumulates signal charges for all the pixels by exposing all the pixels at the same timing. Is known).

  By the way, in such a CMOS type solid-state imaging device having a global shutter function, the signal charge generated in each pixel is transferred to each storage capacitor unit at the same time in all the pixels and temporarily stored. The signal charges accumulated in the signal are sequentially converted into pixel signals at a predetermined readout timing.

  As a pixel circuit (equivalent circuit) having such a global shutter function, a type in which a storage capacitor portion is disposed between two stages of amplifier portions is known. That is, for example, as shown in FIG. 7, the first source follower amplifier unit SF1 and the second source follower amplifier unit SF2 are temporarily provided with a capacitor for holding a voltage (the type shown in FIG. 7). The detailed description of the circuit is described in, for example, Patent Document 1 and Non-Patent Document 1 below, and the detailed description thereof is omitted here).

  Further, it is also known that a pixel sharing type is used, such as the pixel circuit shown in FIG. 7, so that the aperture area ratio of the light receiving portion is increased and the pixel is miniaturized to some extent ( See the following Patent Document 1 and Non-Patent Document 1 below).

JP 2013-98858

3.5 μm global shutter pixel with transistor sharing and correlated double sampling Fig.1 (www.panorama-project.eu/docs/Bogaerts-IISW2013.pdf B. Wolfs, J. Bogaerts, G. Meynants)

However, in the type in which the voltage holding capacitor is arranged between the two-stage amplifier units, it is difficult to further increase the aperture ratio of the light receiving unit because of the circuit configuration. That is, as shown in FIG. 7, transistors of this type include two charge transfer transistors (TX) that transfer charges from two photodiodes (PD) to each floating diffusion capacitor (FD), and FD. A floating diffusion capacitance reset transistor (RFD) for resetting, a source follower amplifier 1 (SF1) for setting the voltage to the next stage according to the charge amount of FD, and a current source (CS) for setting a bias current to SF1 , Two memory reset transistors (RM) that reset the memory (MEM), two sample transistors (SAM) that set the output voltage of SF1 to MEM, and two source followers that output a voltage according to the voltage of MEM An amplifier 2 (SF) and two selection transistors (SEL) for selecting pixels are required. As a result, the total number of transistors is a transistor per two pixels. A minimum of 13 registers is required.
As described above, when the number of transistors is excessively large, the aperture ratio of the light receiving portion is significantly reduced depending on the area of the transistor, and there is a problem that it is difficult to miniaturize the pixel.

  The present invention has been made in view of the above circumstances, and a pixel capable of further increasing the aperture ratio of the light receiving unit and further miniaturizing the pixel as compared with a conventionally known pixel circuit. An object of the present invention is to provide a circuit and an image pickup apparatus equipped with the circuit.

The pixel circuit of the present invention is
In a pixel array in which a plurality of pixels are arranged in an XY matrix and each pixel is read and scanned by an image frame reading unit, a signal storage unit that stores charges related to the pixels, and storage in the signal storage unit A pixel circuit including a signal reading unit for reading the generated charge,
The pixel readout scanning is performed by a non-progressive method,
The signal storage unit includes a charge generation unit that generates charges in response to light irradiation, intermediate charge storage unit that temporarily stores signal charges generated by the charge generation unit, and signal charges generated by the charge generation unit. A global shutter transistor for transferring to the intermediate charge storage means at the end of the charge storage time for storing the signal charge, and a read selection for transferring the signal charge stored in the intermediate charge storage means to the signal reading section. With a transistor,
The signal readout unit includes a signal readout charge storage unit that accumulates a signal charge amount transferred from the intermediate charge storage unit, and a signal charge from the intermediate charge storage unit before being transferred at each charge storage time. A reset transistor that discharges the charge accumulated in the signal readout charge storage means, and an amplification transistor that outputs a signal corresponding to the charge accumulated in the signal readout charge storage means,
For each of the pixel circuits, the signal storage unit is provided for each pixel, and the signal readout unit is configured to share pixels,
The timing of ending the charge accumulation time by the operation of the global shutter transistor is simultaneously performed for each group of interlaced scanning in the non-progressive method.

  Here, the “XY matrix shape” means a state in which two axes intersecting on the element surface of the image sensor are arranged in both directions when one of the two axes is the X axis and the other is the Y axis.

  The “non-progressive method” refers to a so-called interlaced scanning method, which is different from the progressive method, which is a method of sequentially scanning from one direction of the image sensor. It is assumed that a method of performing interlaced scanning for each of the above lines and a scanning method in which scanning is apparently performed in the column direction (Y direction) and the scanning is interlaced scanning. That is, conceptually, the plurality of pixels are selected for every N rows or M columns, and the signal accumulation operation and the signal readout are sequentially performed for each group of N rows or M columns. In this method, the operation is repeated.

Also, generally, in the “image frame”, a group of lines formed by interlaced scanning, for example, a frame consisting of only odd rows (odd frame: conceptually corresponding to the first field by NTSC) or even rows only. Frames (even frames: conceptually corresponding to the second field by NTSC), and not only between odd frames or even frames but also between odd frames and even frames may be referred to as image frame intervals. Many.
However, if this is done in the present specification, it may be confused in the essential part of the invention, so the interval between odd frames or even frames is called an image frame interval, but the interval between odd frames and even frames. Is referred to as a divided image frame interval for convenience.

In the pixel circuit,
The plurality of pixels are set to either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame reading unit uses a non-progressive method, sets the divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and sets the charge accumulation time of each pixel in the pixel array to 10 milliseconds. Preferably it is set to seconds.

  The signal storage unit preferably includes a charge generation unit reset transistor that discharges the charge generated by the charge generation unit.

The image frame reading unit is preferably configured to control the charge accumulation time of each pixel to be 6/10 with respect to the image frame interval.
The non-progressive method is preferably an interlace method.

The imaging device of the present invention is
Any one of the pixel circuits described above;
A pixel array in which a plurality of pixels corresponding to the pixel circuit are arranged in an XY matrix;
The pixel array includes: a row selection circuit unit that selects and drives an address of a Y row; and the image frame readout unit that includes a column parallel readout circuit unit that reads out a signal for each X column. Is.

  In the pixel circuit and the image pickup apparatus of the present invention, the pixel circuit configuration is configured to enable pixel sharing, and an intermediate charge holding capacitor is provided between the photodiode and the floating diffusion capacitor (signal reading charge storage unit). It is set as the structure which arranged. When such a circuit configuration is used, the number of transistors can be greatly reduced as compared with a conventionally known circuit configuration in which a voltage holding capacitor is arranged between two stages of amplifiers. Can be improved.

  For example, in the case of the prior art shown in FIG. 7 as an example (a circuit configuration in which a voltage holding capacitor is arranged between two amplifier stages), the number of transistors is 13 for 2 pixels, and 6.5 transistors per pixel. Will be used. That is, in this type of circuit configuration, two charge transfer transistors (TX) that transfer charges from the photodiode (PD) to the floating diffusion capacitor (FD), and a floating diffusion capacitance reset transistor for resetting the FD (RFD), source follower amplifier 1 (SF1) that sets the voltage to the next stage according to the charge amount of FD, current source (CS) that sets the bias current to SF1, and memory (MEM) 2 Two memory reset transistors (RM), two sample transistors (SAM) that set the output voltage of SF1 to MEM, two source follower amplifiers 2 (SF2) that output voltage according to the voltage of MEM, and pixels Two selection transistors (SEL) to be selected are at a minimum, and 6.5 transistors per pixel are required to be used.

  On the other hand, in the case of the pixel circuit of the embodiment of the present invention shown in FIG. 1 (a circuit configuration in which a charge retention capacitor is arranged between a photodiode and a floating diffusion capacitor), the number of transistors is nine for two pixels. This means that 4.5 transistors are used per pixel. That is, the circuit of the present invention includes two photodiode reset transistors (RPD21A, B) that reset the photodiodes (PD11A, B) and two global shutter transistors (GS22A) that transfer charges from PD to SD all at once. , B), two transfer transistors (TX12A, B) for sequentially transferring the charge of the selected pixel from the charge holding capacitor (SD23A, B) to the floating diffusion capacitor (FD13), and a floating diffusion capacitor reset transistor for resetting the FD (RFD14), a source follower amplifier (SF15) that converts the electric charge of FD into a voltage and outputs it, and a selection transistor (SEL16) that selects a pixel, and can be formed by 4.5 transistors per pixel. it can.

  As described above, in the pixel circuit of the present invention, the number of transistors can be greatly reduced as compared with the prior art, and the miniaturization of the pixel can be improved.

FIG. 3 is a circuit diagram showing an equivalent circuit of a pixel circuit of 4.5 pixels per pixel, which is a two-pixel sharing type according to an embodiment of the present invention and has a global shutter function. FIG. 2 is a block diagram showing an imaging apparatus including a pixel array in which the pixel circuits shown in FIG. 1 are arranged and an image frame readout circuit. 3 is a time chart of an input signal to the pixel circuit when signal readout is performed using the pixel circuit shown in FIG. 1. It is the schematic which shows the odd-numbered line (solid line) and the even-numbered line (broken line) at the time of performing signal read-out using an interlace system in an image sensor. It is a time chart which shows an example of the time-sequential relationship between the illumination intensity change of 100 Hz, and the accumulation time in the odd-numbered line and even-numbered line of 120 Hz interlace scanning. It is a time chart which shows the time-sequential relationship of the image | video from the odd-numbered line and the even-numbered line of 120Hz interlace scanning. It is a circuit diagram which shows the equivalent circuit of the pixel circuit which concerns on a prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment>
A main configuration of a pixel circuit according to an embodiment of the present invention will be described with reference to FIG. 1 which is an equivalent circuit diagram of a pixel circuit equipped with a global shutter function. This pixel circuit is a two-pixel shared type and uses 4.5 transistors per pixel. The pixel circuit 10 shown in this equivalent circuit diagram is provided corresponding to two pixels arranged in parallel in the column direction (Y direction).

  As shown in FIG. 1, this pixel circuit 10 is a two-pixel shared type, and includes two photodiodes (PD) 11A and B, two photodiode reset transistors (RPD) 21A and B, and two globals. Shutter transistors (GS) 22A, B, two intermediate charge retention capacitors (SD) 23A, B, two charge transfer transistors (TX) 12A, B, floating diffusion capacitance (FD) 13, and floating diffusion capacitance reset A transistor (RFD) 14, a source follower amplifier (SF) 15, a selection transistor (SEL) 16, a pixel power supply unit (VDD) 17, and a pixel output unit (OUT) 18 are included.

  PD11A, B, RPD21A, B, GS22A, B, SD23A, B, and TX12A, B are provided for every two pixels, and FD13, RFD14, SF15, and SEL16 are two pixels. A shared configuration is used. The PD 11A, the RPD 21A, the GS 22A, the SD 23A, and the TX 12A constitute the first accumulation unit 110, and the PD 11B, the RPD 21B, the GS 22B, the SD 23B, and the TX 12B constitute the second accumulation unit 120. Is done.

Further, a signal reading unit is configured by the FD 13, the RFD 14, the SF 15, and the SEL 16.
In this way, since two pixels are composed of nine transistors, it can be composed of 4.5 transistors per pixel, and while having a global shutter function described later, the number of transistors per pixel The number can be minimized.

  In this embodiment, since the global shutter transistors (GS) 22A and B are provided, the shutter operation is performed simultaneously for all pixels (actually, between odd frame pixels and simultaneously between even frame pixels). Can do. As a result, distortion of the image can be prevented particularly for a subject that moves at high speed.

A number of pixels corresponding to the pixel circuit 10 are arranged in the X direction (row direction) and the Y direction (column direction) to form a pixel array 501 (see FIG. 2).
As shown in FIG. 2, the pixel array 501 includes a Y-direction scanning unit (vertical scanning unit: hereinafter the same) 502, an X-direction scanning unit (horizontal direction scanning unit: the same hereinafter) 503, a timing generator 504, and an output circuit 505. An imaging device (image sensor) 550 is configured. In the imaging device 550, the Y direction scanning unit 502, the X direction scanning unit 503, the timing generator 504, and the output circuit 505 constitute an image frame reading unit. Since the first storage unit 110 and the second storage unit 120 have the same configuration, they will be described together for convenience of description.

In each pixel circuit 10, the PDs 11 </ b> A and B accumulate negative charges in an amount corresponding to the intensity of incident light. The anodes of the PDs 11A and B are grounded, and the cathodes are connected to the VDD 17 via the RPDs 21A and B, and are connected to one of the source / drain portions of the GSs 22A and B. Note that the gates of the RPDs 21A and B are connected to signal lines L _RP1 and L _RP2 from the Y-direction scanning unit 502, and a reset signal is input thereto. The gates of GS22A and B are connected to signal lines L _G1 and L _G2 from the Y-direction scanning unit 502, and transfer signals are respectively input thereto.

The other of the source / drain portions of the GS 22A, B is connected to one of the SD 23A, B and the source / drain portions of the TX 12A, B that hold charges in the middle. The other of the source / drain portions of TX12A and B is connected to the gate of SF15. The gates of TX12A and B are connected to signal lines L _T1 and L _T2 from the Y-direction scanning unit 502, and transfer signals are respectively input thereto.

SF 15 and SEL 16 are connected in series between VDD 17 and output unit 18. The gate of the SEL 16 is connected to the signal line L _S from the Y-direction scanning unit 502 and receives a selection signal for pixel selection. The RFD 14 is connected between the VDD 17 and the gate of the SF 15. The gate of the RFD 14 is connected to the signal line L _R from the Y-direction scanning unit 502 and receives a reset signal.
The FD 13 is connected to the other of the source / drain portions of the TXs 12A and 12B and the gate of the SF15.

In order to reset the PDs 11A and B, reset signals from the signal lines L _RP1 and L _RP2 are input to the gates of the RPDs 21A and B to turn on the RPDs 21A and B. As a result, the negative charge accumulated in the PDs 11A and B is released to the VDD 17 via the RPDs 21A and B, and the reset operation is completed.

  Charge accumulation by incident light starts from the end of the reset operation of the PDs 11A and 11B. That is, when the reset signal input to the gates of the RPDs 21A and B and the transfer signal input to the gates of the GSs 22A and B become “L” level and the RPDs 21A and B and the GSs 22A and B are turned off, the amount corresponding to the intensity of the incident light Are stored in the PDs 11A and 11B, and the charge accumulation time starts.

  On the other hand, the accumulation time is terminated as follows. That is, by setting the transfer signal to the gates of GS22A and B to “H” level for a predetermined time to turn on GS22A and B, the accumulated charges in PD11A and B are moved to SD23A and B, and the gates of GS22A and B The storage time of the PDs 11A and 11B ends when the transfer signal input to the "L" level becomes LOW and the GS 22A and B are turned off.

When reading signal charges, first, a reset signal from the signal line L _R is input to the gate of the RFD 14 in the “H” level state to turn on the RFD 14. As a result, the charges accumulated in the FD (floating diffusion part: the same applies hereinafter) 13 are discharged to the VDD 17 via the RFD 14 and the reset operation is completed. Next, by setting the transfer signal to the gates of TX12A and B to the “H” level state for a predetermined time and turning on TX12A and B, the charges once stored in SD23A and B are moved to FD13. The amount of charge will be detected.
That is, the FD 13 is connected to the gate of the SF 15, and the SF 15 functions as an input unit of a source follower that reads the charge amount of the FD 13.

2 sends a row selection address signal and a drive control signal to the Y-direction scanning unit 502, and sends a column selection address signal and a read control signal to the X-direction scanning unit 503. The Y-direction scanning unit 502 has a function of a Y-direction scanning circuit and a voltage level shift circuit, and sequentially selects a plurality of predetermined rows of the pixel array 501 in accordance with the input row selection address signal and drive control signal. (For each odd row group and even row group), the signal lines L _RP1 , L _RP2 , L _G1 , L _G2 , L _T1 , L _T2 , L _R , L _S of the selected row A transfer signal, a reset signal, and a selection signal are sent to the pixel circuit 10.

The X direction scanning unit 503 has functions of an X direction scanning circuit and a column circuit, and a plurality of Y direction signal lines L from a plurality of pixel circuits 10 in a predetermined row selected by the Y direction scanning unit 502. _The current output to _V is converted into a plurality of predetermined signals.
Further, the output circuit 505 outputs a plurality of pixel signals generated by the X-direction scanning unit 503 to the outside.

  FIG. 3 is a time chart showing the input signal of each transistor when signal readout is performed using the pixel circuit 10 shown in FIG. In the present embodiment, the image frame rate is 120 Hz and interlace scanning is employed. Further, in the input signal waveforms to SEL, RFD, and TX, the numbers in parentheses following SEL, RFD, and TX indicate pixel rows. When two numbers such as 1, 2, 3, and 4 are written, it indicates that pixels are shared. The accumulation time for each row is indicated by a black belt. In this embodiment, n is set to 4320 (row).

  In this pixel circuit 10, first, in order to reset the PD 11A for odd-numbered rows (1, 3,..., N−1), the RPD 21A is turned on (RPD (1, 3,..., N− in FIG. 3). 1) is set to “H” level, and thereafter, the OFF state (RPD (1, 3,..., N−1) in FIG. 3 is set to “L” level). As a result, charge accumulation is started in the PD 11A from the end of the reset (see arrow A in FIG. 3).

Thereafter, after a predetermined accumulation time has elapsed, the GS 22A is turned on (GS (1, 3,..., N-1) is set to the “H” level), whereby the charge moves from the PD 11A to the SD 23A. The storage time ends when the subsequent GS 22A is turned off (GS (1, 3,..., N-1) is at "L" level) (see arrow B in FIG. 3). Also, signal charges are accumulated in the same way for even-numbered rows (2, 4,..., N) with a shift of one divided image frame interval. That is, since the signals L _G1 and L _G2 are input to the GS 22A and B at the same time for each of the odd and even rows, the accumulation time of all the pixels in the odd row is completed at the same time and shifted by one image frame interval. As a result, the accumulation time of all the pixels in the even-numbered rows is completed simultaneously.

  On the other hand, in the odd-numbered rows (1, 3,..., N−1), when reading of the PD 11A is started, the SEL 16 is turned on (SEL (1, 2) is “H” level), and the pixel to be read is In the selected pixel, when the RFD 14 is turned on (RFD (1, 2) is “H” level), the FD 13 is reset. Thereafter, the RFD 14 is turned off (RFD (1, 2) is “L”. Since the level of TX12A is turned on (TX (1) is at “H” level), the charge accumulated in SD23A moves to FD13. Thereby, the signal charge accumulated in the PD 11A is read out through the SF 15 during the accumulation time. This accumulation time is set to (1/100) second (= 10 milliseconds). Note that signal charges are read out in the same manner for even-numbered rows (2, 4,..., N) with a shift of one divided image frame interval.

  The pixel circuit configured as described above has a circuit configuration in which SDs 23A and B are arranged between the PDs 11A and B and the FD13. When configured in this way, the number of transistors can be greatly reduced compared to the conventional circuit configuration in which a voltage holding capacitor is arranged between two amplifier stages, and the pixel can be miniaturized. Can be improved.

  In the pixel circuit and the imaging apparatus according to the present embodiment, since the reading operation is performed by interlace scanning, first, the first row, the third row,. All the odd-numbered rows of signals are read out, and the image signals accumulated in the pixels of the odd-numbered rows are output. Subsequently, the second row, the fourth row,..., The nth row are sequentially selected to read out all even rows of signals, and output the image signals accumulated in the pixels of the even rows. The time interval (divided image frame interval) between a frame composed of odd rows (odd frames) and a frame composed of even rows (even frames) is set to (1/120) seconds = 8.333 milliseconds.

  In addition, as described above, the interval between the divided image frames in the first row and the second row is 8.333 milliseconds, and when one side is accumulating charges, the other side reads out a signal. The same applies to the relationship between the third row and the fourth row, and the relationship between the n−1th row and the nth row. In addition, the accumulation time of the odd-numbered row and the subsequent even-numbered row is set to partially overlap each other, while setting each accumulation time to 10 milliseconds, This is because the interval (image frame interval) is set to 16.667 milliseconds (60 Hz).

Hereinafter, the switching timing in the above-described embodiment will be described with reference to FIGS.
As described above, in this embodiment, pixel readout scanning of the pixel array 501 is performed using the interlace method. That is, as shown in FIG. 4, for all the rows of the pixel array 501, only an odd-numbered row (represented by a solid line in FIG. 4) pixel readout operation and an even-numbered row (represented by a broken line in FIG. 4). The operations for performing the pixel readout are alternately performed. This interlace method is used in the NTSC method and is also called interlaced scanning.

  According to the present embodiment, as shown in FIGS. 5 and 6, the illumination device or the like adopts an interlace method under illumination of 100 Hz (power frequency is 50 Hz), so that the image sensor (imaging device) 550 is configured. The charge accumulation time of the pixel (photodiode) is set to 10 milliseconds, and the imaging frame frequency is set to 120 Hz to prevent the occurrence of flicker while adapting to Super Hi-Vision.

  That is, when the electronic shutter speed is set to 10 milliseconds in order to prevent the occurrence of flicker, the imaging frame interval (division image frame interval) is (1/120) seconds = 8.333 milliseconds. The electronic shutter period with respect to the imaging frame interval is set to 6/5, which is larger than 1.

  Therefore, in this embodiment, even if the electronic shutter speed is 10 milliseconds and the imaging frame interval is (1/120) seconds = 8.333 milliseconds, the image frame interval ( Since the electronic shutter period for odd frames or even frames can be set to a value smaller than 1 (6/10 because an interlace method is adopted in this embodiment), illumination of 100 Hz with a power frequency of 50 Hz is possible. It is possible to prevent the occurrence of flicker when imaging at 120 Hz under an intensity change.

  In the above-described embodiment, the image frame interval is 1/120 seconds = 8.333 milliseconds. Alternatively, 1/120 seconds × 1001/1000 = 8.342 milliseconds may be used instead. The same effects as those of the embodiment can be obtained. Moreover, in the said embodiment, although the frame frequency is 120 Hz, it can replace with this and can show an effect substantially the same as the thing of the said embodiment also by setting it as 120 * 1000/1001 = 119.88Hz.

  Note that the imaging apparatus according to the above-described embodiment may be a backside illumination type that irradiates light from the backside of the imaging unit.

  Furthermore, the pixel circuit and the imaging device of the present invention are not limited to those of the above-described embodiment, and other various modes can be adopted. For example, in the above-described embodiment, an example of a two-pixel sharing type element shared by two pixels arranged in the Y-axis direction is given. However, signal reading using various other elements shared by a plurality of pixels is performed. It can be performed. For example, it is possible to use a common type for three pixels (rows) aligned in the Y-axis direction or a common type for a plurality of pixels (columns) aligned in the X-axis direction.

  Also, the configuration of the pixel circuit itself can be changed to various types. In short, it is a pixel circuit that shares a plurality of pixels, and can be changed to various types in which the intermediate charge holding capacitor is arranged between the photodiode and the floating diffusion capacitor (signal reading holding capacitor). is there.

210 Pixel circuit 11A, B Photodiode (PD)
12A, B Charge transfer transistor (TX)
13 Floating diffusion capacitance (FD)
14 Floating diffusion capacitance reset transistor (RFD)
15 Source follower amplifier (SF)
16 Selection transistor (SEL)
17 Pixel power supply (VDD)
18 Pixel output section (OUT)
21A, B Photodiode reset transistor (RPD)
22A, B Global shutter transistor (GS)
23A, B Charge retention capacity (SD)
110 First accumulation unit 120 Second accumulation unit 130 Signal readout unit

Claims (6)

In a pixel array in which a plurality of pixels are arranged in an XY matrix and each pixel is read and scanned by an image frame reading unit, a signal storage unit that stores charges related to the pixels, and storage in the signal storage unit A pixel circuit including a signal reading unit for reading the generated charge,
The pixel readout scanning is performed by a non-progressive method,
The signal storage unit includes a charge generation unit that generates charges in response to light irradiation, intermediate charge storage unit that temporarily stores signal charges generated by the charge generation unit, and signal charges generated by the charge generation unit. A global shutter transistor for transferring to the intermediate charge storage means at the end of the charge storage time for storing the signal charge, and a read selection for transferring the signal charge stored in the intermediate charge storage means to the signal reading section. With a transistor,
The signal readout unit includes a signal readout charge storage unit that accumulates a signal charge amount transferred from the intermediate charge storage unit, and a signal charge from the intermediate charge storage unit before being transferred at each charge storage time. A reset transistor for discharging the charge accumulated in the signal readout charge accumulating means, an amplifying transistor for outputting a signal corresponding to the charge accumulated in the signal readout charge accumulating means, and pixel selection A pixel selection transistor for performing
For each of the pixel circuits, the signal storage unit is provided for each pixel, and the signal readout unit is configured to share pixels,
2. The pixel circuit according to claim 1, wherein the timing of ending the charge accumulation time by the operation of the global shutter transistor is simultaneously performed for each group of interlaced scanning in the non-progressive method. In the pixel circuit,
The plurality of pixels are set to either 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame reading unit uses a non-progressive method, sets the divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and sets the charge accumulation time of each pixel in the pixel array to 10 milliseconds. 2. The pixel circuit according to claim 1, wherein the pixel circuit is set to seconds.   3. The pixel circuit according to claim 1, wherein the signal storage unit includes a charge generation unit reset transistor that discharges the charge generated by the charge generation unit.   The image frame reading unit is configured to control the charge accumulation time of each pixel to be 6/10 with respect to each image frame interval. 2. A pixel circuit according to item 1.   The pixel circuit according to claim 1, wherein the non-progressive method is an interlace method. A pixel circuit according to any one of claims 1 to 5;
A pixel array in which a plurality of pixels corresponding to the pixel circuit are arranged in an XY matrix;
An image pickup apparatus comprising: a row selection circuit unit that selects and drives an address of a Y row for the pixel array; and an image frame reading unit including a column parallel reading circuit unit that reads a signal for each X column .

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