JP6913312B2 - Data processing device and data transfer method - Google Patents

Description

The present invention relates to a data processing apparatus and a data transfer method.

In recent years, virtualization has attracted attention in the field of networks. With virtualization, the devices that make up the network can be logically used regardless of the actual physical hardware configuration. For virtualization, a configuration is being studied in which a device that was conventionally made of dedicated hardware in an optical access system is configured with general-purpose hardware and the functions are implemented by software. By realizing the functions with software, the functions of the devices can be replaced, and the devices can be shared and resources can be shared, so that the reduction of CAPEX (Capital Expenditure) can be expected. In addition, it is thought that OPEX (Operating Expense) can be reduced by facilitating function updates and setting changes. Therefore, it is conceivable to expand the software area of the optical access system to include physical layer processing and implement physical layer processing on an accelerator such as a GPU (Graphics Processing Unit) included in a communication device constituting the optical access system.

However, since the physical calculation of communication processing has conventionally been performed using a dedicated chip, there are few conventional studies in which processing is performed using a GPU. On the other hand, there are a plurality of study examples of implementing error correction using hardware such as FPGA (see, for example, Non-Patent Documents 1 and 2). These studies are RTL (Register Transfer Level) designs, and are different from the design concept of this study that utilizes GPUs because they are proposals for task-level parallelism between registers and the overall architecture.

An example of performing error correction on a GPU is adaptation to a RAID (Redundant Arrays of Inexpensive Disks) system (see, for example, Non-Patent Document 3). In this method, the concrete implementation method is not described, and only the system is proposed. In addition, the throughput of the system is not high.

In addition, the GPU is mainly used for accelerating the processing of the CPU (central processing unit). Therefore, as a technique for transferring data to the GPU, as shown in FIG. 7, a configuration for transferring data from the CPU to the GPU is generally used. As a DMA (Direct Memory Access) transfer memory, a method using a high-speed DDP-DRAM (Dual-Data-Port Dynamic Random Access Memory) can be mentioned (see, for example, Non-Patent Document 4). However, as far as we have investigated, there is no way to directly transfer the external input of a non-generalized standard signal to the GPU without going through the CPU.

Hanho Lee, Chang-Seok Choi, Jongyoon Shin, Je-Soo Ko, "100-Gb / s Three-Parallel Reed-Solomon based Foward Error Correction Architecture for Optical Communications", International SoC Design Conference 2008 (ISOCC '08), p . I-265-I-268, November 2008 Hanho Lee, "A High-Speed Low-Complexity Reed-Solomon Decoder for Optical Communications", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.52, No.8, p.461-465, August 2005 Matthew L. Curry, Anthony Skjellum, H. Lee Ward, Ron Brightwell, "Accelerating Reed-Solomon Coding in RAID systems with GPUs", IEEE International Symposium on Parallel and Distributed Processing 2008 (IPDPS 2008), April 2008 Donghyuk Lee, Lavanya Subramanian, Rachata Ausavarungnirun, Jongmoo Choi, Onur Mutlu, "Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM", In Proceedings of the 2015 International Conference on Parallel Architecture and Compilation ( PACT), October 2015

When considering the application of these systems to communication, it is important to reduce the delay in data processing.

In view of the above circumstances, an object of the present invention is to provide a data processing apparatus and a data transfer method capable of performing data processing at high speed using a general-purpose device.

One aspect of the present invention includes an interface circuit that adds update information indicating data update to data received from the outside and outputs the data, and an accelerator that performs arithmetic processing using the data. The accelerator is the interface. The storage unit that stores the data output from the circuit and the update information added to the data stored in the storage unit are repeatedly monitored, and when the update information indicating the data update is detected, it is detected. Based on the control of the poll unit that rewrites the update information to update detected, the control unit that controls the execution of arithmetic processing using the data to which the update information detected by the poll unit is added, and the control of the control unit. The data processing apparatus includes an arithmetic unit that executes arithmetic processing using the data stored in the storage unit.

One aspect of the present invention is the above-mentioned data processing device, in which the interface circuit further adds length information indicating the length of the data to the data and outputs the data, and the control unit outputs the data. The arithmetic unit is made to execute arithmetic processing with a degree of parallelism based on information.

One aspect of the present invention is the above-mentioned data processing apparatus, in which the interface circuit further adds control information indicating a type of arithmetic processing to the data and outputs the data, and the control unit is indicated by the control information. The arithmetic unit is made to execute the arithmetic processing of the kind.

One aspect of the present invention is the above-mentioned data processing device, and the data processing device is a communication device.

One aspect of the present invention is an output step in which the interface circuit adds update information indicating data update to the data received from the outside and outputs the data, and the accelerator stores the data output from the interface circuit in the storage unit. The storage step to be stored, the monitoring step for repeatedly monitoring the update information added to the data stored in the storage unit, and the detected update information when the update information indicating data update is detected in the monitoring step. It is a data transfer method including a rewriting step of rewriting the update information to update detected, and a calculation step of executing a calculation process using the data to which the update information detected in the monitoring step is added.

INDUSTRIAL APPLICABILITY According to the present invention, data processing can be performed at high speed using a general-purpose device.

It is a figure which shows the data transfer between the device used for the communication apparatus by 1st Embodiment of this invention. It is a functional block diagram of the communication device by the same embodiment. It is a figure which shows the example of the data format by the same embodiment. It is a figure which shows the processing flow of the polling processing by the same embodiment. It is a figure which shows the processing flow of the parallel arithmetic processing in GPU by 2nd Embodiment. It is a figure which shows the processing flow which switches the type of arithmetic processing in GPU according to 3rd Embodiment. It is a figure which shows the data transfer to the GPU by the prior art. It is a figure which shows the data transfer to a GPU using an interrupt.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
When applying a device using general-purpose hardware to communication, it is important to reduce the delay. In order to transfer data and reduce the processing delay, it is necessary to receive short data and perform arithmetic processing on it.

In order to input data to the GPU, which is general-purpose hardware, it is necessary to use an interface such as PCIe (PCIe), and for that purpose, hardware such as FPGA (field-programmable gate array) is required. Further, when the GPU receives data, interrupts are often used. However, there is no GPU that supports interrupts from hardware such as FPGA. On the other hand, the CPU uses interrupt control to transfer data from the FPGA to the GPU and start the GPU kernel that executes the GPU program.

From the above, for example, it is conceivable to implement the communication device as shown in FIG. In this implementation example, when transferring an external input to the GPU, the FPGA executes an interrupt to the CPU, and the CPU specifies a data transfer destination address to the FPGA and issues a transfer instruction to the CPU. The CPU also issues a kernel execution instruction to the GPU to specify the degree of parallelism and the execution instruction.

In such an implementation, when the amount of data transferred at one time is small, the number of communications between the CPU and another processor increases, and the amount of delay increases. Therefore, a method of directly transferring an external signal to the GPU without going through a CPU is desired.

Further, when the amount of data to be transferred at one time (frame data amount) is small and data is continuously input, the number of interrupts per hour increases. As a result, communication between the CPU, GPU, and FPGA increases, and processing within the restricted time may not be in time.

The GPU has been conventionally used as an accelerator of a CPU, and the timing of data input is controlled and the function is changed by the CPU control. Therefore, the issue is how to perform timing control for data input from other devices such as FPGA and sequential function change for data without going through the CPU. Since accelerators such as GPUs do not support interrupts, a method of implementing timing control for data input using polling is required.

Further, in the arithmetic processing of the GPU, the degree of parallelism of the processing performed by the GPU is usually changed by the control of the CPU, and the intervention of the CPU occurs. Further, when changing the process executed by the GPU, it is necessary to perform it under the control of the CPU. Therefore, a transfer method that reduces communication between the CPU, GPU, and FPGA and a calculation processing method thereof are required.

Therefore, in the present embodiment, in order to reduce the communication between the CPU-GPU-FPGA, polling is implemented in the GPU. In order for the GPU to know the data input timing without going through the CPU, the FPGA adds a flag indicating data update to all the frames to be transferred. The GPU buffers the transferred data in the memory, reads the buffered data by polling, and starts arithmetic processing when it is determined that the flag has been updated. Further, the FPGA adds information on the degree of parallelism and the type of arithmetic processing to the frame to be transferred to the GPU. As a result, the degree of parallelism when the GPU executes the arithmetic processing is changed, and the type of the arithmetic processing executed by the GPU is changed.

[First Embodiment]
FIG. 1 is a diagram showing data transfer between devices used in the communication device 1 of the present embodiment. The communication device 1 is an example of a data transfer device. The communication device 1 can be used, for example, as an optical subscriber line terminal (OLT) or an optical network unit (ONU) in a PON (Passive Optical Network).

The communication device 1 includes an FPGA 2 used as an IF (interface) circuit and a GPU 3 which is an example of an accelerator. The FPGA 2 receives a signal from another device via a transmission line, and transfers the frame data included in the received signal to the GPU 3. The FPGA 2 realizes data transfer without CPU control by adding additional data such as a flag indicating data update to the frame data to be transferred to the GPU 3. The GPU 3 receives the frame data output by the FPGA 2 and performs an operation. The GPU 3 may output the calculation result data to the FPGA 2, and the FPGA 2 may transmit a signal in which the data received from the GPU 3 is set to another device via the transmission line.

By using the additional data, the communication device 1 can reduce the communication between the FPGA and the CPU and between the CPU and the GPU as compared with the case of FIG. Preprocessing is required before executing data transfer from FPGA 2. As a preprocessing, the FPGA 2 secures the transfer destination GPU memory, acquires the transfer destination GPU address, and sets the value of the additional data in advance. Furthermore, it is necessary to execute the kernel of GPU3 that performs polling processing.

FIG. 2 is a functional block diagram of the communication device 1. The figure shows the functional parts of each device of FPGA2 and GPU3.
The FPGA 2 includes an IF unit 21, a memory 22, a flagging unit 23, and a transfer unit 24. The IF unit 21 inputs an external signal transmitted through the transmission line. When the communication device 1 is, for example, an OLT or an ONU, the IF unit 21 converts an optical signal to an electric signal or an electric signal to an optical signal. The memory 22 stores (buffers) an external signal input via the IF unit 21.

The flag giving unit 23 gives a flag to the frame data having a certain length buffered in the memory 22. The flag-giving unit 23 includes an update flag-giving unit 231, a length flag-giving unit 232, and a control flag-giving unit 233. The update flag giving unit 231 adds an Update flag indicating data update to the frame data. The length flag adding unit 232 adds a Length flag indicating the length of the data to the frame data. The control flag assigning unit 233 assigns a Control flag indicating the type of arithmetic processing to the frame data. The transfer unit 24 transfers the frame data to which various flags are added to the memory 31 of the GPU 3.

The GPU 3 includes a memory 31, a polling unit 32, a control unit 33, and a calculation unit 34. The memory 31 is an example of a storage unit that stores data. The memory 31 buffers the data transferred from the transfer unit 24 of the FPGA 2. The polling unit 32 of the GPU 3 performs polling processing on the data buffered in the memory 31 to detect the input of the signal. The control unit 33 controls the execution of various processes by executing the kernel. Further, the control unit 33 changes the degree of parallelism at the time of calculation in the calculation unit 34 and switches the type of calculation processing performed by the calculation unit 34. The calculation unit 34 performs calculation processing on the input signal based on the control from the control unit 33.

FIG. 3 is a diagram showing an example of a data format generated by flagging in FPGA 2. As shown in the figure, the data includes the header name "Update", the 32-bit length Update flag, the header name "Length", the 32-bit length Length flag, the header name "Control", and the 448-bit length Control. Flagged.

The update flag assigning unit 231 always sets the Update flag to a value “1” indicating data update, and notifies the GPU 3 of the data update. When the polling unit 32 of the GPU 3 detects the Update flag of the value "1" in the data stored in the memory 31, the Polling unit 32 rewrites the Update flag to the value "0" indicating that the update has been detected. The Length flag indicates the length of the data. By setting the length of the data in the Length flag, the GPU 3 can be used for recognizing the range of data to be processed, determining the degree of parallelism when performing parallel calculation, and the like. The Control flag is used for processing control. The Control flag is used when changing the type of arithmetic processing performed on the GPU 3. The values of these flags are changed during program execution by rewriting the values of the registers of FPGA2.

FIG. 4 is a diagram showing a processing flow of polling processing executed by the GPU kernel. The GPU kernel is booted at pre-configuration. When the frame data of the signal input by the IF unit 21 is buffered in the memory 22, the flag adding unit 23 of the FPGA 2 adds the Update flag, the Length flag, and the Control flag to the frame data, and outputs the frame data to the transfer unit 24. do. The transfer unit 24 transfers the frame data to which various flags are added to the memory 31 of the GPU 3. The memory 31 of the GPU 3 buffers the data transferred from the FPGA 2.

The polling unit 32 of the GPU 3 constantly checks the Update flag of the data stored in the memory 31 by the polling process (step S110). For example, the polling unit 32 checks the Update flag at predetermined time intervals. When the polling unit 32 determines that the value of the Update flag is 0 (step S110: == 0), it considers that new frame data has not yet arrived from FPGA 2. The GPU 3 does not perform the calculation processing of the frame data, returns to step S110, and restarts the check of the Update flag again.

On the other hand, when the polling unit 32 determines that the value of the Update flag is 1 (step S110 :! = 0), it considers that new frame data has been input and resets the Update flag to 0 (step S120). After resetting the Update flag, the control unit 33 causes the calculation unit 34 to execute an arbitrary calculation process for the frame data (step S130). GPU3 repeats the process from step S110.

The memory 31 is, for example, a ring buffer. The control unit 33 of the GPU 3 sequentially changes the address value representing the buffer position for which the update is checked next each time the Update flag is reset.

[Second Embodiment]
The GPU has a plurality of cores and can perform parallel operations. In this embodiment, the GPU performs parallel arithmetic processing of frame data.

FIG. 5 is a diagram showing a processing flow in which the GPU 3 performs parallel arithmetic processing on the frame data. The method of changing the degree of parallelism in which the GPU 3 executes arithmetic processing during kernel execution will be described with reference to the figure. The Length flag assigned to the frame data is used to change the degree of parallelism. When the GPU 3 performs arithmetic processing in n-bit units, the parallelism of Length / n is specified and the kernel is started. Here, assuming Dynamic parallelism that can be used with NVIDIA GPUs, the kernel is dynamically booted from within the kernel that is already running. For example, since n is different between the 10G-EPON (Gigabit --Ethernet (registered trademark) Passive Optical Network) frame and the NG-PON2 (Next generation --Passive Optical Network 2) frame, the data to be sequentially transferred from the transfer unit 24 of the FPGA 2 to the GPU 3. It is necessary to change the length of (the value set for the Length flag) to a multiple of n.

The process of steps S210 to S220 of FIG. 5 is the same as the process of steps S110 to S120 shown in FIG. After the process of step S220, the control unit 33 reads the Length flag of the frame data stored in the memory 31 and divides the data length set in the read Length flag by a preset n to determine the degree of parallelism. Is calculated (step S230). The control unit 33 starts the kernel based on the calculated parallelism by starting the kernel of the calculated parallelism from the kernel that has already been executed, and each kernel performs arithmetic processing in n-bit units. The calculation unit 34 is made to execute in parallel (step S240). GPU3 repeats the process from step S210.

[Third Embodiment]
In the present embodiment, the type of arithmetic processing executed by the GPU 3 is switched.
FIG. 6 is a diagram showing a processing flow for switching the type of arithmetic processing executed by the GPU 3. The Control flag assigned to the frame data is used to switch the type of arithmetic processing.

The process of steps S310 to S320 of FIG. 6 is the same as the process of steps S110 to S120 shown in FIG. After the process of step S320, the control unit 33 refers to the value of the Control flag in the branch instruction (step S330). The control unit 33 switches the kernel to be booted according to the value of the Control flag. When a plurality of kernels are set to kernels 0 to k (k is an integer of 1 or more), the control unit 33 starts kernel i when the value i of the Control flag (i is an integer of 0 or more and k or less). (Steps S340-0 to S340-k). As a result, for example, the control unit 33 can switch functions such as Reed-Solomon (255,223) and Reed-Solomon (255,239) with respect to the input data without going through the CPU. The GPU 3 repeats the process from step S310 after executing any one of steps S340-0 to S340-k.

According to the embodiment described above, the data processing device includes an interface circuit such as an FPGA and an accelerator such as a GPU. The data processing device is, for example, a communication device. The interface circuit adds update information indicating data update to the input frame data and transfers it to the accelerator. The update information is, for example, the Update flag. The accelerator stores the received frame data in the storage unit, and repeatedly monitors the update information of the stored data. When the accelerator detects the update information indicating the data update, it determines that the frame data has been input, rewrites the detected update information to the update detected, and performs an operation using the frame data to which the update information is added. Start processing. As a result, the accelerator can detect the input timing of the frame data without going through the CPU, so that it is possible to reduce the delay of data transfer and arithmetic processing in the communication device.

Further, the interface circuit may further add length information indicating the length of the data and control information indicating the type of arithmetic processing to the data and transfer the data to the accelerator. The length information and control information are, for example, the Length flag and the Control flag. The accelerator executes arithmetic processing with a degree of parallelism based on length information. As a result, it is possible to further reduce the delay in arithmetic processing. In addition, the accelerator executes the kind of arithmetic processing indicated by the control information. As a result, the arithmetic processing executed by the accelerator can be switched from the interface circuit.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs and the like within a range that does not deviate from the gist of the present invention.

1 ... Communication device, 2 ... FPGA, 3 ... GPU, 21 ... IF section, 22 ... Memory, 23 ... Flagging section, 24 ... Transfer section, 31 ... Memory, 32 ... Polling section, 33 ... Control section, 34 ... Calculation Unit, 231 ... Update flag assignment unit, 232 ... Length flag assignment unit, 233 ... Control flag assignment unit

Claims (4)

An interface circuit that adds update information indicating data update and control information indicating the type of arithmetic processing to data received from the outside and outputs it.
It is equipped with an accelerator that performs arithmetic processing using the data.
The accelerator
A storage unit that stores the data output from the interface circuit,
A polling unit that repeatedly monitors the update information added to the data stored in the storage unit and rewrites the detected update information to update detected when the update information indicating data update is detected.
A control unit that controls execution of arithmetic processing using the data to which the update information detected by the polling unit is added, and a control unit.
A calculation unit that executes arithmetic processing using the data stored in the storage unit based on the control of the control unit, and a calculation unit.
With
The control unit causes the calculation unit to execute the type of calculation processing indicated by the control information.
Data processing device. The interface circuit further adds length information indicating the length of the data to the data and outputs the data.
The control unit causes the calculation unit to execute arithmetic processing at a degree of parallelism based on the length information.
The data processing device according to claim 1. The data processing device is a communication device.
The data processing device according to claim 1 or 2. The interface circuit is
An output step that adds update information indicating data update and control information indicating the type of arithmetic processing to data received from the outside and outputs it.
Accelerator,
A storage step for storing the data output from the interface circuit in the storage unit, and
A monitoring step of repeatedly monitoring the update information added to the data stored in the storage unit, and
When the update information indicating data update is detected in the monitoring step, a rewrite step of rewriting the detected update information to update detected, and a rewrite step.
A calculation step for executing a calculation process using the data to which the update information detected in the monitoring step is added, and a calculation step.
Have,
In the calculation step, the kind of calculation processing indicated by the control information is executed.
Data transfer method.

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