JP6907386B2 - Semiconductor integrated circuit equipment and wearable equipment - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device and a wearable device, and more particularly to a semiconductor integrated circuit device suitable for low power consumption.

As a wearable device, there is a portable terminal device that is worn on the wrist like a smart watch. In such a mobile terminal device, although it is driven by the electric power supplied from the battery, it is required to operate for a particularly long time. A semiconductor integrated circuit device with a built-in microprocessor (hereinafter referred to as CPU: Central Processing Unit, central processing unit), memory, etc. inside the portable terminal device in order to achieve the function as a terminal and the function as a watch. (Hereinafter, also simply referred to as a semiconductor device) is mounted.

In order to enable the mobile terminal device to operate for a long time, a semiconductor device having a built-in low-speed CPU that operates at a low speed and a semiconductor device having a built-in high-speed CPU that operates at a high speed are mounted inside the mobile terminal device. It is conceivable to do. In this case, for example, the function as a wristwatch is achieved by a low-speed CPU (sub CPU), and the function as a terminal is achieved by a high-speed CPU (main CPU). Since the low-speed CPU operates at a low speed, the power consumption is low, so that the operating time of the mobile terminal device can be extended.

DVFS (Dynamic Voltage and Frequency Scaling) is known as a technique for reducing the power consumption of a semiconductor device. By using the DVFS technology, it is possible to reduce the power consumption of the semiconductor device by lowering the power supply voltage of the semiconductor device and lowering the frequency for operating the semiconductor device. Since the power consumption of the semiconductor device can be reduced, the operating time of the mobile terminal device can be extended.

Further, as a technique for reducing the power consumption of a semiconductor device, for example, Patent Document 1 describes applying a substrate bias voltage to the substrate of the semiconductor device to make the frequency for operating the semiconductor device variable. ..

As the memory built in the semiconductor device, there is a static random access memory (hereinafter, referred to as SRAM). A technique for reducing the power consumption of an SRAM is described in, for example, Patent Document 2.

Japanese Unexamined Patent Publication No. 2004-282776 Japanese Unexamined Patent Publication No. 2003-132683

In a configuration using two semiconductor devices, that is, a semiconductor device having a built-in main CPU and a semiconductor device having a built-in sub CPU, there is a concern that the number of semiconductor devices to be mounted will increase and the price of the portable terminal device will rise. Further, in the configuration using the DVFS technology, even if the frequency is lowered and the operation is performed at a low speed, the standby current due to the leakage current or the like is not reduced, and a high effect on the reduction of power consumption cannot be expected. Further, the frequency range that can be changed by the DVFS technology is about 50%, and the frequency cannot be changed in units of digits. Therefore, even this cannot be expected to have a high effect on low power consumption.

In a configuration in which the substrate bias voltage supplied to the substrate of the semiconductor device is changed, it is difficult to operate the semiconductor device in a stable manner.

Patent Documents 1 and 2 do not describe semiconductor devices capable of stable operation while reducing power consumption.

An object of the present invention is to provide a semiconductor device capable of stable operation while reducing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.

A brief description of typical inventions disclosed in the present application is as follows.

That is, the semiconductor device includes a first circuit, a mode designation circuit that specifies the operating speed of the first circuit, a P-type SOTB transistor, and an N-type SOTB transistor, and a second circuit connected to the first circuit. , The board bias circuit which is connected to the mode designation circuit and can supply the 1st and 2nd board bias voltages to the P type SOTB transistor and the N type SOTB transistor is provided. Here, when the mode designation circuit specifies the first operation mode for operating the first circuit at the first speed, the board bias circuit sets the first and second board bias voltages to the P-type SOTB transistor and the N-type SOTB. Supply to the transistor. On the other hand, when the mode specification circuit specifies the second operation mode in which the first circuit is operated at the second speed higher than the first speed, the board bias circuit biases the board to the P-type SOTB transistor and the N-type SOTB transistor. Does not supply voltage.

Here, SOTB is an abbreviation for Silicon on Thin Burried Oxide, and SOTB transistor means a transistor using a substrate in which an ultrathin insulating film and a silicon thin film are formed on a silicon substrate. In the SOTB transistor, the impurity concentration in the channel region (region of the silicon thin film) where the channel through which the drain current flows is formed is lowered. Therefore, the SOTB transistor is also called a dopantless transistor. The P-type SOTB transistor means a SOTB transistor in which the channel through which the drain current flows is a P-type channel, and the N-type SOTB transistor means a SOTB transistor in which the channel through which the drain current flows is an N-type channel.

In the SOTB transistor, the impurity concentration in the channel region (region of the silicon thin film) in which the channel is formed is low. Therefore, the variation in the threshold voltage between the SOTB transistors is small. That is, the variation in the threshold voltage between the P-type SOTB transistors and the variation in the threshold voltage between the N-type SOTB transistors are small. This makes it possible to reduce P-type SOTB transistors and / or N-type SOTB transistors that are erroneously turned on or off due to variations in the threshold voltage when a substrate bias voltage is supplied. It is possible to provide a semiconductor device that operates stably even if a bias voltage is supplied.

Further, since an insulating film is interposed between the silicon substrate to which the substrate bias voltage is supplied and the silicon thin film region serving as the channel region, the silicon thin film and the silicon substrate are supplied even if the substrate bias voltage is supplied. It is possible to prevent a leak current from flowing between the two. As a result, it is possible to suppress an increase in power consumption even if a substrate bias voltage is supplied. That is, it is possible to provide a semiconductor device that operates stably while reducing power consumption.

Further, in the SOTB transistor, the threshold voltage changes in proportion to the value of the supplied substrate bias voltage. Therefore, it is possible to easily change each of the P-type SOTB transistor and the N-type SOTB transistor to a desired threshold voltage depending on the value of the substrate bias voltage.

A silicon substrate has been described as an example in which a substrate bias voltage is supplied. However, when the region facing the silicon thin film is, for example, a well region formed on a silicon substrate, a substrate bias voltage is supplied to this well region.

In this specification, the field effect transistor is simply referred to as a MOS transistor to distinguish it from a SOTB transistor. Also in the field effect transistor, the MOS transistor whose channel is the P channel is referred to as a P-type MOS transistor, and the MOS transistor whose channel is an N-type channel is referred to as an N-type MOS transistor.

A brief description of the effects obtained by representative of the inventions disclosed in the present application is as follows.

It is possible to provide a semiconductor device capable of stable operation while achieving low power consumption.

It is a block diagram which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. (A) and (B) are sectional views schematically showing the structure of a MOS transistor and a SOTB transistor. It is explanatory drawing which shows the operation concept of the semiconductor device which concerns on Embodiment 1. FIG. It is a characteristic diagram which shows the change of the threshold voltage of the P-type SOTB transistor and the N-type SOTB transistor which concerns on Embodiment 1. FIG. It is a schematic waveform diagram which shows the change of the substrate bias voltage generated by the substrate bias circuit. It is a characteristic diagram which shows the relationship between the threshold voltage and the power-source voltage in a high-speed mode obtained by simulation. It is a characteristic diagram which shows the relationship between the threshold voltage and the power supply voltage in a low speed mode obtained by a simulation. It is a characteristic figure which shows the characteristic of the P-type SOTB transistor and N-type SOTB transistor which concerns on Embodiment 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiment, in principle, the same reference numerals are given to the same parts, and the repeated description thereof will be omitted in principle.

(Embodiment 1)
<Overall configuration of semiconductor device>
FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to the first embodiment. In the figure, the block surrounded by the alternate long and short dash line shows a circuit and a bus formed on one semiconductor chip. The semiconductor device 10 includes a CPU (Central Processing Unit) 26, GPIO29, SRAM30, ADC31, ROM (Read Only Memory) 32, I / F33, S / C24, I / O22, IOP28, and VBB-GEN23. ing. Here, the I / O 22 indicates an input / output circuit, and is not particularly limited, but includes a circuit that converts a signal voltage level between the outside and the inside of the semiconductor device 10, a circuit that performs signal buffering, and the like. Have.

In FIG. 1, the GPIO 29 is a general supply input / output circuit, and the microprocessor (CPU) 26 accesses the GPIO 29 via the control circuit IOP28. Based on the access from the CPU 26, the GPIO 29 transmits / receives information to / from the outside of the semiconductor device 10 via the input / output circuit I / O 22, and transmits / receives information to / from the outside to / from the CPU 26. Send and receive.

In FIG. 1, the SRAM 30 shows a static random access memory as described above, and is connected to the bus 27. Further, the ADC 31 indicates an analog / digital conversion circuit (hereinafter, referred to as an AD conversion circuit), the ROM 32 indicates a non-volatile memory, and the I / F 33 indicates an interface circuit. The AD conversion circuit ADC31, the non-volatile memory ROM 32, and the interface circuit I / F 33 are each connected to the bus 27. The CPU 26 is also connected to the bus 27. The CPU 26 accesses the SRAM 30, the AD conversion circuit ADC31, the non-volatile memory ROM 32, and the interface circuit I / F33 via the bus 27, and transmits / receives signals to / from these.

For example, the CPU 26 reads a program from the non-volatile memory ROM 32 via the bus 27, and executes processing according to the read program. In the execution process of this process, the CPU 26 uses the SRAM 30, the AD conversion circuit ADC31, and the interface circuit I / F33. For example, the CPU 26 uses the interface circuit I / F 33 to transmit / receive information to / from a device provided outside the semiconductor device 10.

A plurality of devices are provided outside the semiconductor device 10, and FIG. 1 illustrates a wireless device 34 and a sensor 35. In the example shown in FIG. 1, the interface circuit I / F 33 is not particularly limited, but includes an interface circuit for the wireless device 34 and an interface circuit for the sensor 35. The CPU 26 accesses the wireless device 34 via the interface circuit for the wireless device, and transmits / receives information by a wireless signal using the wireless device 34. Further, the sensor 35 is accessed via the interface circuit for the sensor, and the information from the sensor 35 is converted by, for example, the AD conversion circuit ADC31 and used for processing.

The semiconductor device 10 of this embodiment is built in a wearable device, for example, a smart watch. The sensor 35 is used to measure the body temperature of a human body wearing a smart watch, and the wireless device 34 is used to transmit the measured body temperature or the like to a so-called smartphone. Of course, it is not limited to such applications. For example, the wireless device 34 can also be used to wirelessly connect to a so-called IoT (Internet of Things) device.

In this embodiment, the non-volatile memory ROM 32 is an electrically rewritable non-volatile memory such as a flash memory, although it is not particularly limited. The non-volatile memory ROM 32 can be connected to the outside of the semiconductor device 10 via the input / output circuit I / O 22. This makes it possible to rewrite the non-volatile memory ROM 32 from the outside.

The SRAM 30 is used, for example, to store primary information when the CPU 26 performs processing according to the program. Of course, it is not limited to this application.

Further, the circuit connected to the bus 27 is not limited to the above-mentioned circuit. For example, an interface circuit such as SPI (Serial Peripheral Interface), UART (Universal Asynchronous Transmit Transmitter), I2C (Inter-Integrated Circuit) may be connected to the bus.

The semiconductor device 10 according to the embodiment has two operating speed modes. That is, the semiconductor device 10 has a low-speed mode 2 (first operation mode) in which the semiconductor device 10 operates at a low speed, and a high-speed mode 1 (second operation mode) in which the semiconductor device 10 operates at a higher speed than the low-speed mode 2. .. In this embodiment, the clock signal for operating the semiconductor device 10 when the low-speed mode 2 is specified and the clock signal for operating the semiconductor device 10 when the high-speed mode 1 is specified are It is generated by two clock generators 36A and 36B outside the semiconductor device 10. The clock generator 36A generates the high-speed clock signal 20, and the clock generator 36B generates the low-speed clock signal 21. In this embodiment, the clock generators 36A and 36B are configured by a crystal oscillator circuit, the frequency of the low-speed clock signal 21 is, for example, 32 KHz, and the frequency of a high-speed clock signal (hereinafter, also referred to as a high-speed clock signal) 20. Is, for example, 40 MHz. That is, the high-speed clock signal 20 and the low-speed clock signal (hereinafter, also referred to as low-speed clock signal) 21 have different frequency digits.

Although FIG. 1 shows an example in which the clock generators 36A and 36B are provided outside the semiconductor device 10, the clock generators 36A and 36B may be provided inside the semiconductor device 10. That is, the clock generators 36A and 36B may be formed on the same semiconductor chip as the circuit of the CPU 26 or the like. Further, one clock generator, for example, a clock generator 36B for generating a low-speed clock signal 21, is provided outside the semiconductor device 10, a multiplication circuit is provided in the semiconductor device 10, and the multiplication circuit is used to start from the low-speed clock signal 21. A high-speed clock signal 20 may be formed.

In FIG. 1, S / C 24 shows a system controller (mode designation circuit). Clock signals 20 and 21 are supplied to the system controller S / C 24 via the instruction signal M_Cont from the CPU 26 and the input / output circuits I / O 22. The system controller S / C 24 selects a high-speed clock signal 20 or a low-speed clock signal 21 according to the instruction signal M_Cont from the CPU 26, and supplies the high-speed clock signal 20 or the low-speed clock signal 21 to the CPU 26 as an operation clock signal 25. In other words, the system controller S / C24 designates the high-speed mode 1 and the low-speed mode 2 by the instruction signal M_Cont. In the designation of the high-speed mode 1, the system controller S / C 24 supplies the high-speed clock signal 20 as the operation clock signal 25 to the CPU 26. On the other hand, in the designation of the low speed mode 2, the system controller S / C 24 supplies the low speed clock signal 21 as the operation clock signal 25 to the CPU 26.

The CPU 26 operates in synchronization with the supplied operation clock signal 25. Therefore, when the low-speed clock signal 21 is supplied as the operating clock signal 25, the operating speed of the CPU 26 becomes slow, and when the high-speed clock signal 20 is supplied as the operating clock signal 25, the operating speed of the CPU 26 becomes slow. Becomes faster.

When realizing the function of a wristwatch, for example, the CPU 26 supplies a designated signal M_Cont corresponding to the low speed mode 2 to the system controller S / C 24. Further, when the function as a terminal is realized, for example, when an application is executed, the CPU 26 supplies the designated signal M_Cont corresponding to the high-speed mode 1 to the system controller S / C24. If it is a wristwatch function, for example, it is only necessary to display the time, so that the amount of processing required for the CPU 26 is relatively small. Therefore, even if the operating speed of the CPU 26 is slow, the CPU 26 can realize the function of the wristwatch in a relatively short time. On the other hand, when the application is executed as a terminal, the amount of processing required for the CPU 26 is much larger than that of the wristwatch function. Therefore, in order to execute the application in a relatively short time, the operating speed of the CPU 26 is increased. By slowing down the operating speed of the CPU 26 in the low-speed mode 2 in this way, it is possible to reduce the power consumed by the CPU 26 and the like.

Further, in this embodiment, the system controller S / C24 forms a mode designation signal for controlling the board bias circuit (hereinafter, also referred to as a board bias generation circuit) according to the designated signal M_Cont. In FIG. 1, the substrate bias circuit is shown as VBB-GEN23 and is controlled by the mode designation signal Vb_Cont from the system controller S / C24. This mode designation signal Vb_Cont is formed in the system controller S / C24 based on the designation signal M_Cont.

The substrate bias circuit VBB-GEN23 outputs a substrate bias voltage (Vsp, Vsn) supplied to a SOTB (Silicon on Thin Oxide) transistor and a substrate bias voltage (Vmp, Vmn) supplied to a MOS transistor. The substrate bias voltage supplied to the SOTB transistor outputs two types of substrate bias voltages corresponding to the channel type of the SOTB transistor. That is, the substrate bias voltage Vsp (first substrate bias voltage) is output as the substrate bias voltage supplied to the P-type SOTB transistor, and the substrate bias voltage Vsn (second substrate bias) is output as the substrate bias voltage supplied to the N-type SOTB transistor. Voltage) is output.

Similarly, for the MOS transistor, the substrate bias generation circuit VBB-GEN23 outputs the substrate bias voltage corresponding to the channel type. That is, the substrate bias voltage Vmp (third substrate bias voltage) is output as the substrate bias voltage supplied to the P-type MOS transistor, and the substrate bias voltage Vmn (fourth substrate bias voltage) is output for the N-type MOS transistor. Is output.

As will be described later, the voltage values of the board bias voltages Vsp, Vsn, Vmp, and Vmn output from the board bias generation circuit VBB-GEN23 are determined by the mode designation signal Vb_Cont. Next, a circuit to which the substrate bias voltages Vsp, Vsn, Vmp, and Vmn are supplied will be described.

In FIG. 1, for example, the input / output circuits I / O 22 and CPU 26 are composed of N-type MOS transistors and P-type MOS transistors instead of SOTB transistors. On the other hand, the SRAM 30 is composed of a SOTB transistor and a MOS transistor. The substrate bias voltages Vmp and Vmn are not supplied to the circuit composed of the MOS transistors, for example, the input / output circuit I / O 22, and the substrate bias voltages Vmp and Vmn are supplied to the CPU 26. This is because when the substrate bias voltage is supplied to the MOS transistors constituting the input / output circuit I / O 22, the threshold voltage of the MOS transistor changes and the input logic threshold voltage of the input / output circuit I / O 22 changes. Is. On the other hand, in the CPU 26, it is possible to reduce the power consumption by supplying the substrate bias voltages Vmp and Vmn. Next, a circuit to which the substrate bias voltages Vsp, Vsn, Vmp, and Vmn are supplied will be described by taking the CPU 26 and the SRAM 30 as an example.

<Configuration of CPU 26 (first circuit) and SRAM 30 (second circuit)>
FIG. 2 is a circuit diagram showing the configuration of the semiconductor device 10 according to the first embodiment. In the figure, in the semiconductor device 10 shown in FIG. 1, the circuit of the CPU 26 and the circuit of the SRAM 30 are shown. FIG. 2 also shows the bus 27, the AD conversion circuit ADC31, and the interface circuit I / F33 shown in FIG. 1, but since they are the same as those in FIG. 1, the description thereof will be omitted. Further, FIG. 2 also shows the configuration of the substrate bias circuit VBB-GEN23. Here, for convenience of explanation, the substrate bias circuit VBB-GEN23 includes a substrate bias generation circuit 23-Vsp that forms a substrate bias voltage Vsp, a substrate bias generation circuit 23-Vsn that forms a substrate bias voltage Vsn, and a substrate bias. It is shown that the substrate bias generating circuit 23-Vmp forming the voltage Vmp and the substrate bias generating circuit 23-Vmn forming the substrate bias voltage Vmn are provided, but the number is not limited.

The CPU 26 (first circuit) is composed of a plurality of P-type MOS transistors and a plurality of N-type MOS transistors. FIG. 2 shows, as an example, one P-type MOS transistor MP1 and one N-type MOS transistor MN1 among such a plurality of P-type MOS transistors and a plurality of N-type MOS transistors. A power supply voltage Vd is supplied to the source of the P-type MOS transistor MP1, and the drain thereof is connected to the drain of the N-type MOS transistor MN1. Further, a ground voltage Vs is supplied to the source of the N-type MOS transistor MN1. The gate of the N-type MOS transistor MN1 and the gate of the P-type MOS transistor MP1 are commonly connected. That is, the inverter circuit is composed of the N-type MOS transistor MN1 and the P-type MOS transistor MP1. The CPU 26 is configured by combining a plurality of logic circuits such as an inverter circuit, a sequential circuit, a memory circuit, and the like.

Next, the configuration of the SRAM 30 (second circuit) will be described. The SRAM 30 includes a memory cell array (not shown) having a plurality of memory cells MC00 to MCnn arranged in a matrix, and a peripheral circuit PRK connected to the memory cell array. Word lines W0 to Wn are arranged in each row of the memory cell array, and complementary data line pairs D0, / D0 to Dn, / Dn are arranged in each column. Here, the data lines / D0 to / Dn indicate that they are data lines that transmit signals having opposite phases to the data lines D0 to Dn. Each of the memory cells MC00 to MCnn is connected to a word line arranged in the row in which it is arranged and a complementary data line pair arranged in the column in which it is arranged.

In FIG. 2, among the memory cells MC00 to MCnn arranged in the memory cell array, the memory cells MC00 to MC11 having 2 rows and 2 columns and the word lines W0 and W1 corresponding to these memory cells MC00 to MC11 are complemented. Data line pairs D0, / D0, D1, / D1 are illustrated. Since the configurations of the memory cells MC00 to MCnn are the same as each other, FIG. 2 shows the circuit configuration of the memory cells MC00 only.

Here, the configuration of the memory cell will be described using the memory cell MC00 that illustrates the circuit configuration. The memory cell MC00 is composed of SOTB transistors. That is, the memory cell MC00 includes P-type SOTB transistors SP1 and SP2 and N-type SOTB transistors SN1, SN2, SN3, and SN4.

A power supply voltage Vd is supplied to the source of the P-type SOTB transistor SP1, and the drain thereof is connected to the drain of the N-type SOTB transistor SN1. A ground voltage Vs is supplied to the source of the N-type SOTB transistor SN1. The gate of the P-type SOTB transistor SP1 and the gate of the N-type SOTB transistor SN1 are connected to each other. As a result, a first inverter circuit is configured in which the gate of the P-type SOTB transistor SP1 and the gate of the N-type SOTB transistor SN1 are input, and the drain of the P-type SOTB transistor SP1 and the drain of the N-type SOTB transistor SN1 are output. ..

Similarly, a power supply voltage Vd is supplied to the source of the P-type SOTB transistor SP2, and the drain thereof is connected to the drain of the N-type SOTB transistor SN2. A ground voltage Vs is supplied to the source of the N-type SOTB transistor SN2. The gate of the P-type SOTB transistor SP2 and the gate of the N-type SOTB transistor SN2 are connected to each other. As a result, a second inverter circuit is configured in which the gate of the P-type SOTB transistor SP2 and the gate of the N-type SOTB transistor SN2 are input, and the drain of the P-type SOTB transistor SP2 and the drain of the N-type SOTB transistor SN2 are output. ..

The input of the first inverter circuit is connected to the output of the second inverter circuit, and the input of the second inverter circuit is connected to the output of the first inverter circuit. That is, the inputs and outputs of the first inverter circuit and the outputs and inputs of the second inverter circuit are cross-connected to form a flip-flop circuit. A pair of input / output of the flip flop circuit, that is, the input of the first inverter circuit (output of the second inverter circuit) and the input of the second inverter circuit (output of the first inverter circuit) are N-type SOTB transistors for transfer. (Transfer SOTB transistor) It is connected to the corresponding complementary data line pairs D0 and / D0 via SN3 and SN4. Further, the gates of the transfer SOTB transistors SN3 and SN4 are connected to the corresponding word line W0.

The word lines W0 to Wn and complementary data line pairs D0, / D0 to Dn, / Dn of the memory cell array are connected to the peripheral circuit PRK. The peripheral circuit PRK is connected to the bus 27 and receives an address signal (not shown) and a read / write control signal (not shown) via the bus 27. The peripheral circuit PRK selects a word line designated by an address signal from a plurality of word lines W0 to Wn based on the supplied address signal, and sets the selected word line to a high level. Further, the peripheral circuit PRK selects a complementary data line pair specified by the address signal from a plurality of complementary data line pairs D0, / D0 to Dn, / Dn based on the supplied address signal.

The peripheral circuit PRK supplies the bus 27 with information from the selected complementary data line pair when the read / write control signal specifies read operation. In this case, the information from the memory cell connected to the selected complementary data line pair and the voltage of the connected word line is at a high level is supplied to the bus 27. On the other hand, when the read / write control signal specifies write operation, the peripheral circuit PRK supplies the information on the bus 27 to the selected complementary data line pair. In this case, the information in the bus 27 is supplied to the memory cell connected to the selected complementary data line pair and the voltage of the connected word line is at a high level, and writing is performed.

The write operation and the read operation will be described by taking as an example the case where the word line W0 is selected by the peripheral circuit PRK and the complementary data line pairs D0 and / D0 are selected. When the word line W0 becomes high level by selection, both the transfer SOTB transistors SN3 and SN4 in the selected memory cell MC00 are turned on.

In the write operation, the voltages of the complementary data line pairs D0 and / D0 are transmitted to the pair of inputs and outputs of the flip-flop circuit via the transfer SOTB transistors SN3 and SN4. That is, the voltage of the complementary data line D0 is supplied to the input of the second inverter circuit via the transfer SOTB transistor SN3, and the voltage of the complementary data line / D0 is supplied to the input of the second inverter circuit via the transfer SOTB transistor SN4. It is supplied to the input of the circuit. The voltage (signal) on the complementary data line / D0 is phase-inverted with respect to the voltage (signal) on the complementary data line D0. Therefore, for example, a high level is supplied to the input of the first inverter circuit via the transfer SOTB transistor SN3, and a low level is supplied to the input of the second inverter circuit via the transfer SOTB transistor SN4. Become. As a result, the state held by the flip-flop circuit is determined by the signals in the complementary data line pairs D0 and / D0, and writing to the memory cell MC00 is performed.

On the other hand, in the read operation, a pair of input / output of the flip-flop circuit is connected to the complementary data line pairs D0 and / D0 via the transfer SOTB transistors SN3 and SN4. That is, the output of the second inverter circuit is connected to the complementary data line / D0 via the transfer SOTB transistor SN4, and the output of the first inverter circuit is connected to the complementary data line D0 via the transfer SOTB transistor SN3. Be connected. For example, in the flip-flop circuit, when the output of the first inverter circuit is at the low level and the output of the second inverter circuit is held at the high level, the low level is set to the complementary data line D0 via the transfer SOTB transistor SN3. The high level is supplied to the complementary data line / D0 via the transfer SOTB transistor SN4.

It is the same as the memory cell MC00 when the word line and the complementary data line pair corresponding to the other memory cells MC01 and MC10 to MCnn are selected.

Further, when the peripheral circuit PRK does not select the word line W0, that is, sets the word line W0 to a low level, both the transfer SOTB transistors SN3 and SN4 are turned off. As a result, the complementary data line pair and the input / output of the flip-flop circuit in the memory cell MC00 are electrically separated. At this time, since the power supply voltage Vd and the ground voltage Vs are supplied to the flip-flop circuit, the holding state is continuously held. Similarly, other memory cells continue to hold the corresponding word line when the corresponding word line is not selected.

The peripheral circuit PRK is composed of a plurality of P-type MOS transistors and a plurality of N-type MOS transistors. For example, the peripheral circuit PRK has a decoder circuit that decodes an address signal, a drive circuit that transmits the output of the decoder circuit to a word line, and the like, and these circuits include a plurality of P-type MOS transistors and a plurality of Ns. It is composed of a type MOS transistor. In FIG. 2, among a plurality of P-type MOS transistors and a plurality of N-type MOS transistors constituting the peripheral circuit PRK, some P-type MOS transistors and N-type MOS transistors are depicted as representatives. That is, FIG. 2 shows a MOS transistor constituting an output unit of a drive circuit that supplies selected and non-selected voltages to word lines W0 and W1.

In the figure, the output unit of the drive circuit has the same configuration as each other, and has a P-type MOS transistor MP2 and an N-type MOS transistor MN2. Here, a power supply voltage Vd is supplied to the source of the P-type MOS transistor MP2, and its drain is connected to a corresponding word line (for example, W0). Further, a ground voltage Vs is supplied to the source of the N-type MOS transistor MN2, and its drain is connected to the corresponding word line (W0). The gate of the P-type MOS transistor MP2 and the gate of the N-type MOS transistor MN2 are connected in common, and the signal decoded by the decoder circuit is transmitted.

As a result, in the output unit of the drive circuit corresponding to the word line (for example, W0) designated by the address signal, the P-type MOS transistor MP2 is turned on and the N-type MOS transistor MN2 is turned off. As a result, the power supply voltage Vd (high level) is supplied to the selected word line (W0) via the P-type MOS transistor MP2. On the other hand, in the output unit of the drive circuit corresponding to the word line (for example, W1) not specified by the address signal, the P-type MOS transistor MP2 is turned off and the N-type MOS transistor MN2 is turned on. As a result, the ground voltage Vs (low level) is supplied to the non-selected word line (W1) via the N-type MOS transistor MN2.

Each of the P-type SOTB transistor, the N-type SOTB transistor, the P-type MOS transistor, and the N-type MOS transistor will be described later with reference to FIG. It has a gate electrode (corresponding to the gate) and a back gate region (corresponding to the back gate).

In this embodiment, the substrate bias voltage Vsp (first substrate bias voltage) is supplied to the back gates of the P-type SOTB transistors SP1 and SP2 in the memory cells MC00 to MCnn included in the memory cell array in the SRAM 30. ing. Further, a substrate bias voltage Vsn (second substrate bias voltage) is supplied to the back gates of the N-type SOTB transistors SN1 to SN4 in each of the memory cells MC00 to MCnn. On the other hand, a substrate bias voltage Vmp (third substrate bias voltage) is supplied to each back gate of a plurality of P-type MOS transistors (MP2) constituting the peripheral circuit PRK in the SRAM 30, and the peripheral circuit PRK in the SRAM 30 is used. A substrate bias voltage Vmn (fourth substrate bias voltage) is supplied to each of the back gates of the plurality of N-type MOS transistors (MN2) that constitute the system. A substrate bias voltage Vmp (third substrate bias voltage) is also supplied to each back gate of the plurality of P-type MOS transistors (MP1) constituting the CPU 26, and the plurality of N-type MOS transistors (MN1) constituting the CPU 26 are supplied. ), A substrate bias voltage Vmn (fourth substrate bias voltage) is supplied to each back gate.

That is, in this embodiment, the substrate bias of the same voltage value is applied to the back gates of the P-type MOS transistor (MP1) constituting the CPU 26 and the P-type MOS transistor (MP2) constituting the peripheral circuit PRK in the SRAM 30. A substrate bias voltage Vmn of the same voltage value is supplied to the back gates of the N-type MOS transistor (MN1) constituting the CPU 26 and the N-type MOS transistor (MN2) constituting the peripheral circuit PRK in the SRAM 30. Is supplied.

Further, a substrate vise voltage Vsp, which is the same P channel type but different from the substrate bias voltage Vmp, is supplied to the back gates of the P type SOTB transistors SP1 and SP2 constituting each memory cell. Similarly, a substrate vise voltage Vsn, which is the same N-channel type but different from the substrate bias voltage Vmn, is supplied to the back gates of the N-type SOTB transistors SN1 and SN2 constituting each memory cell. Further, the substrate bias voltage Vsp and the substrate bias voltage Vsn are generated by the substrate bias generation circuit 23-Vsp and 23-Vsn so that their polarities are different from each other, and the substrate vise voltage Vmp and the substrate bias voltage Vmn are mutually polar. Is generated by the substrate bias generating circuit 23-Vmp, 23-Vmn so as to be different. The substrate bias voltage Vsp and the substrate bias voltage Vmp have the same polarity, and the substrate bias voltage Vsn and the substrate bias voltage Vmn have the same polarity.

<Structure of MOS transistor and SOTB transistor>
Next, the structures of the MOS transistor and the SOTB transistor will be described with reference to FIG. FIG. 3A is a cross-sectional view schematically showing the structures of a P-type MOS transistor and an N-type MOS transistor. Further, FIG. 3B is a cross-sectional view schematically showing the structures of a P-type SOTB transistor and an N-type SOTB transistor.

In a plurality of P-type MOS transistors, their structures are the same as each other, and in a plurality of N-type MOS transistors, their structures are also the same. Therefore, the P-type MOS transistor described in FIG. 3A corresponds to the P-type MOS transistor MP1 shown in FIG. 2, and the N-type MOSFET transistor corresponds to the N-type MOS transistor MN1 shown in FIG. Explain as if it were. Further, in a plurality of P-type SOTB transistors, their structures are the same as each other, and in a plurality of N-type SOTB transistors, their structures are also the same. Therefore, the P-type SOTB transistor described in FIG. 3B corresponds to the P-type SOTB transistor SP1 shown in FIG. 2, and the N-type SOTB transistor corresponds to the N-type SOTB transistor SN1 shown in FIG. Explain as if it were.

These MOS transistors and SOTB transistors are formed on one semiconductor chip. In FIG. 3, the substrate 40 is common to the MOS transistor and the SOTB transistor. Here, the substrate 40 will be described as being a P-channel type (hereinafter referred to as P-type) silicon substrate.

In FIG. 3A, 41 is an N-channel type (hereinafter referred to as N-type) well region formed on the P-type silicon substrate 40. An N-type well region 42 and a P-type well region 43 are formed in the N-type well region 41. The N-type well region 42 includes a P ^{+ type region 45 which is a source region of the P-type MOS transistor (MP1), a P +} type region 46 which is a drain region of the P-type MOS transistor (MP1), ^{and an N +} type region. 44 and are formed. In the figure, 50 indicates a gate electrode of a P-type MOS transistor (MP1). The gate electrode 50 is formed on the N-shaped well region 42 via an insulating film (gate insulating film) (not shown). In FIG. 3A, the gate electrode 50 is drawn so as to be separated from the source region 45 and the drain region 46 for the sake of easy viewing of the drawing, but in reality, the gate electrode 50 and the source region 45 And the drain region 46 is formed so as to overlap. Further, the N ⁺ type region 44 is a region for supplying the substrate bias voltage Vmp to the N type well region 42.

In FIG. 3A, 52 shows an electrode for supplying the substrate bias voltage Vmp to the N ⁺ type region 44, and 53 is an electrode for supplying the power supply voltage Vd to the P ⁺ type region 45. Is shown. Further, in FIG. 3A, 56 ^{shows an electrode for connecting the P +} type region 46 to the output out, and 54 shows an electrode for connecting the gate electrode 50 to the input in.

The P-type well region 43 described above includes an N ^{+ type region 48 which is a source region of the N-type MOS transistor (MN1), an N +} type region 47 which is a drain region of the N-type MOS transistor (MN1), ^{and a P +.} A mold region 49 is formed. In the figure, 51 indicates a gate electrode of an N-type MOS transistor (MN1). The gate electrode 51 is formed on the P-shaped well region 43 via an insulating film (gate insulating film) (not shown). In FIG. 3A, the gate electrode 51 is also drawn so as to be separated from the source region 48 and the drain region 47 in order to make the drawing easier to see, but in reality, the gate electrode 51 and the source region 48 are drawn. And the drain region 47 is formed so as to overlap. Further, the P ⁺ type region 49 is a region for supplying the substrate bias voltage Vmn to the P type well region 43.

In FIG. 3A, 59 shows an electrode for supplying the substrate bias voltage Vmn to the P ⁺ type region 49, and 58 is an electrode for supplying the ground voltage Vs to the N ⁺ type region 48. Is shown. Further, in FIG. 3A, 57 ^{indicates an electrode for connecting the N +} type region 47 to the output out, and 55 indicates an electrode for connecting the gate electrode 51 to the input in.

Each of the above-mentioned substrates 40, N-type well regions 41, 42, P-type well regions 43, P ⁺ type regions 45, 46, 49 and N ⁺ type regions 44, 47, 48 is silicon containing impurities. Each channel type is determined by the impurities contained.

The portion of the N-type well region 42 (P-type well region 43) below the gate electrode 50 (51), which is sandwiched between the source region 45 (48) and the drain region 46 (47). By supplying a voltage to the gate electrode 50 (51), a channel is formed. Further, in FIG. 3A, reference numeral 60 denotes an insulating region for separating the elements.

Similar to FIG. 3 (A), in FIG. 3 (B), 40 indicates a common P-type silicon substrate, 41 indicates an N-type well region formed on the P-type silicon substrate 40, and 42 indicates an N-type well region. The N-type well region formed in the N-type well region 41 is shown, and 43 indicates the P-type well region formed in the N-type well region 41.

A thin insulating film 80 is formed on the N-shaped well region 42. ^{A P +} type region 62, which ^{is a source region of the P-type SOTB transistor (SP1), and a P +} type region 64, which is a drain region, are formed on the N-type well region 42 so as to sandwich the thin insulating film 80. ing. Further, a silicon region (region of a silicon thin film) 63 containing substantially no impurities is formed between the ^{P +} type region 62 and the P ^{+ type region 64.} A gate electrode 69 is formed on the silicon region 63 via an insulating film (gate insulating film) (not shown). Here, the silicon region 63 is in contact with the P ⁺ type region 62 and the P ⁺ type region 64, and a channel is formed in the silicon region 63 by supplying a voltage to the gate electrode 69. Also in FIG. 3B, the gate electrode 69 is drawn so as to be separated from the source region 62 and the drain region 64 in order to make the drawing easier to see, but in reality, the gate electrode 69 and the source region The 62 and the drain region 64 are formed so as to overlap each other.

^{Further, an N +} type region 61 for supplying the substrate vise voltage Vsp to the N type well region 42 is formed on the N type well region 42. In FIG. 3B, 71 shows an electrode for supplying the substrate bias voltage Vsp to the N ⁺ type region 61, and 72 shows an electrode for supplying the power supply voltage Vd to the source region 62. Further, 74 indicates an electrode for connecting the drain region 64 to the output out, and 73 indicates an electrode for connecting the gate electrode 69 to the input in.

A thin insulating film 81 is formed on the P-shaped well region 43. ^{An N +} type region 67, which ^{is a source region of the N-type SOTB transistor (SN1), and an N +} type region 65, which is a drain region, are formed on the P-type well region 43 so as to sandwich the thin insulating film 81. ing. Further, a silicon region (a region of a silicon thin film) 66 containing substantially no impurities is formed between the ^{N +} type region 65 and the N ^{+ type region 67.} A gate electrode 70 is formed on the silicon region 66 via an insulating film (gate insulating film) (not shown). Here, the silicon region 66 is in contact with the N ⁺ type region 65 and the N ⁺ type region 67, and a channel is formed in the silicon region 66 by supplying a voltage to the gate electrode 70. Again, for the sake of clarity in the drawing, the gate electrode 70 is drawn to be separated from the source region 67 and the drain region 65, but in reality, the gate electrode 70, the source region 67 and the drain region 65 Are formed to overlap.

^{Further, a P +} type region 68 for supplying the substrate vise voltage Vsn to the P type well region 43 is formed on the P type well region 43. In FIG. 3B, 78 shows an electrode for supplying the substrate bias voltage Vsn to the P ⁺ type region 68, and 77 shows an electrode for supplying the ground voltage Vs to the source region 67. Further, 75 indicates an electrode for connecting the drain region 65 to the output out, and 77 indicates an electrode for connecting the gate electrode 70 to the input in. In addition, in FIG. 3B, 60 shows an insulating region for element separation as in FIG. 3A.

The thickness of each of the thin silicon region (region of the silicon thin film) 63, 66 and the thin insulating films 80, 81 is, for example, about 10 nm. The channel type of the SOTB transistor is determined by, for example, the composition of an insulating film provided between the gate electrodes 69 and 70 and the thin silicon regions 63 and 66, that is, the gate insulating film. For example, the channel type of the SOTB transistor is determined by using aluminum or hafnium as the composition of the gate insulating film. The threshold voltage of the SOTB transistor is determined by the amount of aluminum or hafnium and / or the amount of impurities contained in the thin insulating films 80 and 81.

As shown in FIG. 3A, in the P-type MOS transistor and the N-type MOS transistor, channels are formed in the N-type well region 42 and the P-type well region 43 containing impurities. Therefore, if the concentration of impurities contained varies between the N-type well regions 42 (and / or the P-type well regions 43) formed on the same semiconductor chip, the P-type MOS transistor (and / or the N-type MOS transistor) The threshold voltage will vary between them. Further, there is a PN junction between the N-type well region 42 (P-type well region 43) and the source region and drain region of the P-type MOS transistor (N-type MOS transistor). Therefore, when the substrate bias voltage Vmp (Vmn) is supplied to the N-type well region 42 (P-type well region 43), a leakage current due to the PN junction is generated.

On the other hand, in the P-type SOTB transistor and the N-type SOTB transistor, the regions 63 and 66 in which the channels are formed are substantially free of impurities. Therefore, it is possible to reduce the variation in the threshold voltage of the P-type SOTB transistor and the N-type SOTB transistor due to the variation in the amount of impurities. Further, since it contains substantially no impurities, the threshold voltages of the P-type SOTB transistor and the N-type SOTB transistor change in proportion to the substrate bias voltages Vsp and Vsn. Further, the N-type well region 42 (P-type well region 43) to which the substrate bias voltage Vsp (Vsn) is supplied and the source region and drain region of the P-type SOTB transistor (N-type SOTB transistor) are the insulating film 80 (81). ), So there is no PN junction. This makes it possible to prevent the leakage current from being generated by the PN junction.

The back gate of the P-type MOS transistor (MP1) corresponds to the N-type well region 42 of FIG. 3 (A), and the back gate of the N-type MOS transistor (MN1) corresponds to the P-type well region 43 of FIG. 3 (A). Applies to. The back gate of the P-type SOTB transistor (SP1) corresponds to the N-type well region 42 of FIG. 3 (B), and the back gate of the N-type SOTB transistor (SN1) corresponds to the P-type well of FIG. 3 (B). Region 43 is applicable.

<Operation of semiconductor device 10>
FIG. 4 is an explanatory diagram showing an operation concept of the semiconductor device 10 according to the first embodiment. In the figure, the horizontal axis represents time, and the vertical axis represents the operating frequency in a predetermined circuit block of the semiconductor device 10. The predetermined circuit here is, for example, a CPU 26.

In FIG. 4, 1 indicates an operating frequency in the high-speed mode, and 2 indicates an operating frequency in the low-speed mode. Further, 3 indicates a standby mode. In high-speed mode 1, as described with reference to FIG. 1, the CPU 26 operates in synchronization with the high-speed clock signal 20. Therefore, it operates at a high frequency (High f). Further, in the low speed mode 2, the CPU 26 operates in synchronization with the low speed clock signal 21. Therefore, it operates at a low frequency (Low f). On the other hand, in the standby mode, the clock signal is cut off.

The board bias circuit 23 generates board bias voltages Vmp, Vmn, Vsp and Vsn in the low speed mode 2 and the standby mode 3 and supplies them to the CPU 26, SRAM 30 and the like. The substrate bias voltages Vmp, Vmn, Vsp and Vsn are supplied to the back gates of the P-type MOS transistor, the N-type MOS transistor, the P-type SOTB transistor and the N-type SOTB transistor constituting the CPU 26, SRAM 30 and the like. The threshold voltage of each transistor becomes high. By increasing the threshold voltage of each transistor, it is possible to significantly reduce the leakage current. On the other hand, the substrate bias generation circuit 23 does not supply the substrate bias voltages Vmp, Vmn, Vsp and Vsn to the respective transistors in the high-speed mode 1. As a result, the threshold voltage of each transistor does not increase, so that the CPU 26, SRAM 30, and the like can operate at high speed.

In this embodiment, the voltage values of the power supply voltage Vd and the ground voltage Vs are not changed and are constant in any of the high-speed mode 1, the low-speed mode 2, and the standby mode 3.

In the standby mode 3, since the supply of the clock signal is cut off, the specific circuit block in the CPU 26 goes into a sleep state.

Such standby mode 3 and low speed mode 2 are switched at certain time intervals. This makes it possible to create an ultra-standby state that can reduce power consumption while performing processing at a low speed. In this super standby state or low speed mode 2, the semiconductor device 10 performs possible processing at a predetermined low speed. For example, in the super standby state or the low speed mode 2, the semiconductor device 10 executes a process for realizing the function of the clock. At this time, since the substrate bias voltage is supplied to the back gates of the MOS transistor and the SOTB transistor, the threshold voltage of each is increased, and the leakage current can be reduced. Moreover, since the operating frequency is low, the operating current is also reduced. This makes it possible to further reduce power consumption.

On the other hand, the function of the mobile terminal device, for example, an application such as a game is executed in the high-speed mode 1. In high-speed mode 1, the substrate bias voltages Vmp, Vmn, Vsp and Vsn are not supplied to the back gates of the P-type MOS transistor, N-type MOS transistor, P-type SOTB transistor and N-type SOTB transistor. The value voltage does not increase. As a result, the leak current increases, but at this time, since the operating frequency is high, the operating current becomes large, and the increase in power consumption due to the increase in the leak current is negligible.

In both the standby mode 3 and the low speed mode 2, the substrate bias voltages Vmp, Vmn, Vsp and Vsn constitute a CPU 26, SRAM 30, etc. P-type MOS transistor, N-type MOS transistor, P-type SOTB transistor and N-type SOTB. It should be supplied to each back gate of the transistor. Therefore, in the system controller S / C24, only when the designated signal M_Cont supplied from the CPU 26 corresponds to the second mode, the board bias generation circuit 23-Vmp, 23-Vmn, 23- Vsp, 23-Vsn (FIG. 2) is operated so that the substrate bias voltages Vmp, Vmn, Vsp and Vsn are supplied to the backgate. On the other hand, when the designated signal M_Cont supplied from the CPU 26 corresponds to the first mode, the system controller S / C24 uses the board bias generating circuit 23-Vmp, 23-Vmn, 23-Vsp, 23-Vsn (FIG. 2) is put into a non-operating state.

<Threshold control of SOTB transistor>
In order to operate the semiconductor device 10 stably, it is important to ensure that the SRAM 30 operates stably. In order to highly integrate the semiconductor device 10, the transistor constituting the memory cells MC00 to MCnn included in the SRAM 30 is the transistor having the smallest size among the transistors included in the semiconductor device 10. Since the size is the smallest, the size of the gate electrode of the transistor (width W and length L) is also small. In the P-type MOS transistor and the N-type MOS transistor, for example, impurities are injected into the semiconductor region directly below the gate electrode (in FIG. 3A, a part of the N-type well region 42 and the P-type well region 43). , Determines the threshold voltage of P-type MOS transistor and N-type MOSFET.

Since the size of the gate electrode is small, the semiconductor region directly under the gate electrode is also small, and the amount of impurities injected is also small. Therefore, if the amount of impurities to be injected varies, the characteristics of the P-type MOS transistor and the N-type MOS transistor will vary greatly. For example, in a 65 nm SRAM, when the MOS transistors constituting the memory cell are examined, the threshold voltage of the MOS transistor varies by, for example, 0.6 V. For example, when the threshold voltage of the MOS transistor of the memory cell is set to 0.2V, it is conceivable that a MOS transistor having a threshold voltage of 0.8V (0.2V + 0.6V) is generated due to the variation. .. This indicates that when the power supply voltage Vd drops to 0.8 V or less, memory cells that do not operate normally occur. That is, the lower limit voltage of operation of the memory cell of the SRAM determines the lower limit voltage of operation of the semiconductor device 10. It is conceivable to increase the power supply voltage Vd so that the memory cells of the SRAM operate stably, but increasing the power supply voltage Vd leads to an increase in power consumption.

In the embodiment, each of the memory cells MC00 to MCnn is composed of P-type SOTB transistors SP1 and SP2 and N-type SOTB transistors SN1 to SN4. Channels are formed in regions that are substantially free of impurities (63, 66 in FIG. 3B). Therefore, even if the size of these SOTB transistors is reduced, it is possible to suppress the variation in the threshold voltage due to the variation in impurities. For example, it is possible to suppress the variation of the threshold voltage to about 0.2V. As a result, even if the power supply voltage Vd is low, the SRAM 30 can be operated stably, and the semiconductor device 10 can be operated stably.

Further, in this embodiment, the threshold voltage of the P-type SOTB transistor is controlled by the substrate bias circuit 23 so that the SRAM 30 operates stably.

FIG. 5 is a characteristic diagram showing changes in the threshold voltages of the P-type SOTB transistors SP1 and SP2 and the N-type SOTB transistors SN1 to SN4 when the substrate bias voltages Vsp and Vsn are changed. In the figure, the horizontal axis shows the change in the threshold voltage (Vth) of the N-type SOTB transistor when the absolute value of the substrate bias voltage Vsn is increased, and the vertical axis shows the absolute value of the substrate bias voltage Vsp. It shows the change in the threshold voltage (Vth) of the P-type SOTB transistor when the value is increased.

In the high-speed mode 1, the substrate bias voltage is not supplied to the back gates of the P-type SOTB transistors SP1 and SP2 and the N-type SOTB transistors SN1 to SN4. In the high-speed mode 1, the CPU 26, SRAM 30, and the like operate in synchronization with the high-speed clock signal 20, so that the SRAM 30 uses the threshold voltages of the P-type SOTB transistors SP1 and SP2 so as to maximize the operation margin. The threshold voltages of the N-type SOTB transistors SN1 to SN4 are set to the same values Vth1 (P) and Vth1 (N). That is, the thresholds of these P-type SOTB transistors are set in a state where the substrate bias voltage Vsp is not supplied to the P-type SOTB transistors SP1 and SP2 and the substrate bias voltage Vsn is not supplied to the N-type SOTB transistors SN1 to SN4. It is manufactured so that the absolute value Vth1 (p) of the value voltage and the absolute value Vth1 (n) of the threshold voltage of these N-type SOTB transistors become the threshold voltage Vth1. In FIG. 5, the threshold voltages of the P-type SOTB transistor and the N-type SOTB transistor in the high-speed mode 1 are indicated by ◯.

When the low-speed mode 2 is specified, the back gate voltage of the P-type SOTB transistors SP1 and SP2 and the N-type SOTB transistors SN1 to are according to the board bias voltages Vsp and Vsn from the board bias generating circuits 23-Vsp and 23-Vsn. The voltage of the back gate of SN4 becomes higher in absolute value. As a result, the absolute value of the threshold voltage of the N-type SOTB transistors SN1 to SN4 changes to a large value as shown by the broken line in FIG. As already described, in the SOTB transistor, the threshold voltage changes in proportion to the voltage supplied to the back gate.

As will be described later with reference to FIGS. 7 and 8, in order for the SRAM 30 to operate stably, the absolute value of the threshold voltage of the P-type SOTB transistors SP1 and SP2 is set to that of the N-type SOTB transistors SN1 to SN4. It is desirable that it is at least twice the absolute value of the threshold voltage. Therefore, the substrate bias generating circuit 23-Vsp generates a substrate bias voltage Vsp having a voltage value that is more than twice as large as the absolute value of the substrate bias voltage Vsn generated by the substrate bias generating circuit 23-Vsn. As a result, the absolute value of the threshold voltage of the N-type SOTB transistors SN1 to SN4 increases along the broken line, but the threshold voltage of the P-type SOTB transistors SP1 and SP2 increases along the solid line 6. As a result, in the low speed mode 2, the absolute value of the threshold voltage of the P-type SOTB transistor becomes the threshold voltage Vth2, 3 (P) indicated by □. On the other hand, since the absolute value of the threshold voltage of the N-type SOTB increases along the broken line, the threshold voltage Vth2, 3 (N) is obtained in the low speed mode 2, and the absolute value is the P-type. It becomes smaller than the threshold voltage Vth2, 3 (P) of the SOTB transistor.

Also in the standby mode 3, the substrate bias voltages Vsp and Vsn having the same values as those in the low speed mode 2 are supplied to the back gates of the P-type SOTB transistor and the N-type SOTB transistor. Therefore, even in the standby mode 3, the threshold voltages of the P-type SOTB transistors SP1 and SP2 are Vth2, 3 (P), and the threshold voltages of the N-type SOTB transistors SN1 to SN4 are Vth2, 3 (N). It becomes.

In the low-speed mode 2 and the standby mode 3, P-type MOS transistors (for example, MP1 and MP2 in FIG. 2) and N-type MOS transistors (for example, MN1 and MN2 in FIG. 2) constituting peripheral circuits PRK and the like in the CPU 26 and SRAM 30 are used. ), The substrate bias generation circuits 23-Vmp and 23-Vmn supply the substrate bias voltages Vmp and Vmn to each back gate. Also in these P-type MOS transistors and N-type MOS transistors, the same threshold voltage is set in absolute value so that the operation margin is maximized in the high-speed mode 1. That is, when the substrate bias voltage is not supplied to the back gates of the P-type MOS transistor and the N-type MOS transistor, the absolute values of the threshold voltages of the P-type MOS transistor and the N-type MOS transistor are the same. To manufacture.

By supplying the substrate bias voltages Vmp and Vmn in the low speed mode 2 and the standby mode 3, the absolute values of the threshold voltages of the P-type MOS transistor and the N-type MOS transistor are increased. In order to increase the absolute values of the threshold voltages of the P-type MOS transistor and the N-type MOS transistor while maintaining the operation margin, in this embodiment, the substrate bias voltage Vmp and the same absolute value are used. Vmn is formed and supplied by the substrate vise generation circuits 23-Vmp and 23-Vmn. In this way, by supplying the substrate bias voltages Vmp and Vmn of the same absolute value to the back gates of the P-type MOS transistor and the N-type MOS transistor, the threshold voltage of the P-type MOS transistor and the threshold voltage of the N-type MOS transistor can be obtained. The threshold voltage reaches a high value in the low speed mode 2 and the standby mode 3 while maintaining equal values in absolute values.

By making the value of the substrate bias voltage Vmn supplied to the back gate of the N-type MOS transistor the same as the value of the substrate bias voltage Vsn supplied to the back gate of the N-type SOTB transistor, the substrate shown in FIG. 2 is shown. It is not necessary to provide the bias generation circuit 23-Vmn or 23-Vsn. In this case, both the substrate bias voltage Vmn and Vsn are formed by the remaining substrate bias generation circuit 23-Vsn or Vmn. Similarly, by making the value of the substrate bias voltage Vmp supplied to the back gate of the P-type MOS transistor the same as the value of the substrate bias voltage Vsp supplied to the back gate of the P-type SOTB transistor, FIG. It is not necessary to provide the indicated substrate bias generation circuit 23-Vmp or 23-Vsp. In this case, both the substrate bias voltage Vmp and Vsp are formed by the remaining substrate bias generation circuit 23-Vsp or Vmp.

By setting the substrate bias voltages Vmn and Vsn (or Vmp and Vsp) to the same voltage value in this way, it is possible to reduce the number of substrate bias generating circuits provided in the substrate bias generating circuit 23 to three. , It becomes possible to reduce the size of the semiconductor device 10.

FIG. 6 is a schematic waveform diagram showing a change in the substrate bias voltage generated by the substrate bias generation circuit 23. In the figure, the horizontal axis represents time, and the vertical axis represents the voltage value of the substrate bias voltage as an absolute value. In FIG. 6, the period indicated by 1 indicates the period during which the semiconductor device 10 is operating in the high-speed mode 1, and 2 and 3 indicate the period during which the semiconductor device 10 is operating in the low-speed mode 2 and the standby mode 3. There is. For example, the periods 2 and 3 indicate the period during which the semiconductor device 10 is operating in the above-mentioned super standby state.

The substrate bias generating circuits 23-Vsp and 23-Vsn do not supply the substrate bias voltages Vsp and Vsn to the back gate of the SOTB transistor in the high speed mode 1. On the other hand, in the low speed mode 2 and the standby mode 3, the board bias generation circuit 23-Vsn supplies the board bias voltage Vsn having the low bias voltage 4 to the back gate of the N-type SOTB transistor, and the board bias generation circuit The 23-Vsp supplies a substrate bias voltage Vsp having a high bias voltage 5 to the back gate of the P-type SOTB transistor. In this embodiment, in order to stabilize the SRAM 30, the threshold voltage of the P-type SOTB transistor is set to be at least twice the threshold voltage of the N-type SOTB transistor in absolute value. Therefore, the value of the high bias voltage 5 has a voltage that is twice or more the absolute value of the low bias voltage 4.

The substrate bias generating circuits 23-Vmn and 23-Vmp also do not supply the substrate bias voltages Vmp and Vmn to the back gates of the P-type MOS transistor and the N-type MOS transistor during the period 1 of the high-speed mode 1. On the other hand, in the low speed mode 2 and the standby mode 3, the substrate bias generating circuits 23-Vmn and 23-Vmp form the substrate bias voltages Vmp and Vmn having a voltage equal to the low bias voltage 4 or the high bias voltage 5 in absolute value. do. In this case, since the board bias voltage Vsp can be used as the board bias voltage Vmp or the board bias voltage Vsn can be used as the board bias voltage Vmn, the number of board bias generating circuits provided in the board bias generating circuit 23 is 3. It can be reduced to pieces.

<Stable operation of semiconductor devices>
As described above, in order to operate the semiconductor device 10 stably, the power supply voltage Vd is determined by the power supply voltage of the memory cells MC00 to MCnn included in the SRAM 30. That is, when the power supply voltage Vd of the semiconductor device 10 is lowered, the operation of the SRAM 30 becomes unstable first.

When the memory cells MC00 to MCnn are composed of P-type SOTB transistors SP1 and SP2 and N-type SOTB transistors SN1 to SN4 as shown in FIG. 2, the present inventors have a threshold voltage of the P-type SOTB transistor. It was determined by simulation whether the power supply voltage at which the SRAM 30 operates stably changes depending on the threshold voltage of the N-type SOTB transistor. 7 and 8 are characteristic diagrams showing the relationship between the threshold voltage and the power supply voltage obtained by simulation. In FIGS. 7 and 8, the horizontal axis is the ratio of the threshold voltage (Vth (P-type SOTB)) of the P-type SOTB transistor to the threshold voltage (Vth (N-type SOTB)) of the N-type SOTB transistor. Vth (P-type SOTB) / Vth (N-type SOTB)) is shown, and the vertical axis shows the power supply voltage Vd (voltage with respect to the ground voltage Vs) in which the SRAM operates stably. Here, FIG. 7 shows the state in the high-speed mode 1 in which the substrate bias voltage is not supplied, and FIG. 8 shows the state in the low-speed mode 2 in which the substrate bias voltage is supplied. .. In FIGS. 7 and 8, the smaller the operating voltage Vdmin shown on the vertical axis, the wider the operating range. That is, the smaller the operating voltage Vdmin, the larger the operating margin.

In FIG. 7, the broken line indicated by A indicates a case where the ratio of the threshold voltage of the P-type SOTB transistor and the N-type SOTB transistor is 1. That is, the case where the threshold voltage of the P-type SOTB transistor and the threshold voltage of the N-type SOTB transistor are equal is shown.

The minimum operating voltage at which the SRAM can operate is high when the threshold voltage Vth (P-type SOTB) of the N-type SOTB transistor is larger than the threshold voltage Vth (N-type SOTB) of the P-type SOTB transistor. As the value-voltage ratio approaches 1, it decreases. That is, the operating margin increases when the threshold voltage Vth (P-type SOTB) and the threshold voltage Vth (N-type SOTB) become equal. As the threshold voltage Vth (P-type SOTB) of the P-type SOTB increases and the ratio increases, the minimum operating voltage gradually increases. Therefore, even if the ratio is doubled (broken line B) or more, the minimum operating voltage is relatively low and the operating margin is relatively large.

When the substrate bias voltage is supplied, the minimum operating voltage of the SRAM changes as shown in FIG. That is, the minimum operating voltage Vdmin becomes low from the area where the ratio is less than 1 time, and becomes the lowest when the ratio is 2 times or more. That is, the operating margin is large when the ratio of the threshold voltage of the P-type SOTB transistor and the N-type SOTB transistor is twice or more. On the contrary, in the vicinity of 1 times the ratio, the operation margin deteriorates.

As described above, when the substrate bias voltage is not supplied, the ratio of the threshold voltage of the P-type SOTB transistor and the N-type SOTB transistor is about 1 times (equal to), and the operation margin of the SRAM becomes large. On the other hand, when the substrate bias voltage is supplied, increasing the ratio of the threshold voltage between the P-type SOTB transistor and the N-type SOTB transistor improves the operating margin, and doubling or more increases the operating margin. .. Therefore, when the substrate bias voltage is supplied, the ratio of the threshold voltage of the P-type SOTB transistor and the N-type SOTB transistor is preferably larger than 1 time, preferably 2 times or more.

(Embodiment 2)
In the semiconductor device according to the second embodiment, the voltage value of the substrate bias voltage generated by the substrate bias generating circuit 23 is changed with respect to the first embodiment. The configuration of the semiconductor device is the same as that of the first embodiment except that the number of substrate bias generating circuits is changed. Since the operation of the board bias circuit 23 and the like are the same as those in the first embodiment, the description thereof will be omitted.

FIG. 9 is a characteristic diagram showing the characteristics of the P-type SOTB transistor and the N-type SOTB transistor according to the second embodiment. Similar to FIG. 5, FIG. 9 shows the characteristics showing the changes in the threshold voltages of the P-type SOTB transistors SP1 and SP2 and the N-type SOTB transistors SN1 to SN4 when the substrate bias voltages Vsp and Vsn are changed. It is shown.

In the figure, the broken line shows the change in the threshold voltage of the N-type SOTB transistor, and the solid line 7 shows the change in the threshold voltage of the P-type SOTB transistor. In the second embodiment, the threshold voltages of the P-type SOTB transistors SP1 and SP2 are set to be larger in absolute value with respect to the N-type SOTB transistors SN1 to SN4. For example, the threshold voltages of the P-type SOTB transistors SP1 and SP2 are more than twice as large as the N-type SOTB transistors SN1 to SN4 in absolute value. This threshold voltage setting is, for example, the amount of aluminum or hafunium contained in the gate insulating film and / or the thin insulating film 80 for each of the P-type SOTB transistors SP1 and SP2 and the N-type SOTB transistors SN1 to SN4. , 81 (FIG. 3) is determined when manufacturing a semiconductor device by changing the amount of impurities contained in the device.

In the high-speed mode 1, the substrate bias circuit 23 does not supply the substrate bias voltages Vsp and Vsn to the back gates of the P-type SOTB transistors SP1 and SP2 and the N-type SOTB transistors SN1 to SN4, respectively. Further, the substrate bias voltages Vmp and Vmn are not supplied to the back gates of the P-type MOS transistor and the N-type MOS transistor constituting the peripheral circuit PRK (FIG. 2) of the CPU 26 and the SRAM 30. The threshold voltage (N-type MOSTB_Vth) of the N-type SOTB transistors SN1 to SN4 changes as shown by the broken line in FIG. 9 according to the change of the substrate bias voltage Vmn. Since the substrate bias voltage is not supplied to each of the type SOTB transistors SN1 to SN4, the threshold voltage at that time is Vth1 (N). On the other hand, when the substrate bias voltage Vsn is supplied to each of the N-type SOTB transistors SN1 to SN4, the absolute value of the threshold voltage of the N-type SOTB transistor increases, and in the low-speed mode 2 and the standby mode 3, the value is increased. The absolute values of the threshold voltage are Vth2 and Vth3 (N).

On the other hand, when the P-type SOTB transistors SP1 and SP2 are in high-speed mode 1, the absolute value of their threshold voltage (P-type SOTB_Vth) is Vth1 (P). At this time, the absolute value Vth (P) of the threshold voltages of the P-type SOTB transistors SP1 and SP2 is at least twice the threshold voltage Vth (N) of the N-type SOTB transistors SN1 to SN4.

In the low speed mode 2 or the standby mode 3, the substrate bias circuits 23 supply the substrate bias voltages Vsp and Vsn to the back gates of the P-type SOTB transistor and the N-type SOTB transistor. In the second embodiment, in the low speed mode 2 or the standby mode 3, the absolute values of the substrate vise voltages Vsp and Vsn formed by the substrate bias circuit 23 are set to be the same as each other. In other words, the substrate bias generating circuits 23-Vsp and 23-Vsn form the substrate bias voltages Vsp and Vsn having the same absolute value.

As a result, the absolute values of the threshold voltages of the P-type SOTB transistors SP1 and SP2 and the absolute values of the threshold voltages of the N-type transistors SN1 to SN4 are more than double the threshold voltage. While maintaining the state of difference (voltage difference between threshold voltages), it changes and transitions from high-speed mode 1 to low-speed mode 2 and / or standby mode 3. In FIG. 9, the absolute value of the threshold voltage of the P-type SOTB transistor in the low-speed mode 2 and the standby mode 3 is shown as Vth2, 3 (P), and this value is the threshold value of the N-type SOTB transistor. It has a value more than twice that of the absolute value Vth2, 3 (N) of the voltage.

As a result, the SRAM 30 can be stably operated even in the low speed mode 2 or the standby mode 3 as in the first embodiment.

In the second embodiment, the threshold values of the P-type MOS transistors MP1 and MP2 and the N-type MOS transistors MN1 and MN2 are manufactured so as to be equal in absolute value. In the high-speed mode 1, the substrate bias voltage is not supplied from the substrate bias circuit 23 to the back gates of the P-type MOS transistors MP1 and MP2 and the N-type MOS transistors MN1 and MN2, respectively, and the low-speed mode 2 and the standby mode In 3, the board bias voltage is supplied from the board bias circuit 23. As a result, in the high-speed mode 1, the threshold voltage of the P-type MOS transistor and the threshold voltage of the N-type MOS transistor become equal to each other in absolute value, and the operating margin can be increased.

On the other hand, in the low speed mode 2 and the standby mode 3, the substrate vise voltage Vsp generated by the substrate bias generation circuit 23-Vsp is supplied as the substrate bias voltage Vmp to the back gates of these P-type MOS transistors MP1 and MP2. The substrate bias voltage Vsn generated by the substrate vise generation circuit 23-Vsn is supplied to the back gates of the N-type MOSTB transistors MN1 and MN2 as the substrate vise voltage Vmn.

As a result, in the low-speed mode 2 and / or the standby mode 3, the back gates of the P-type MOS transistor and the N-type MOS transistor constituting the peripheral circuit PRK of the CPU 26 and the SRAM 30 have a substrate having equal absolute values. Bias voltages Vmp and Vmn will be supplied. By supplying the substrate bias voltages Vmp and Vmn, the P-type MOS transistor and the N-type MOS transistor increase in absolute value while maintaining equal values. As a result, in the low-speed mode 2 and the standby mode 3, each of the P-type MOS transistor and the N-type MOS transistor constituting the peripheral circuit PRK of the CPU 26 and the SRAM 30 becomes high while maintaining equal values with each other in absolute value. It is possible to reduce power consumption in the low speed mode 2 and the standby mode 3.

In the second embodiment, the substrate bias voltage generated by the substrate bias generating circuit 23-Vsp is used as the substrate bias voltage Vsp and Vmp, and the substrate bias voltage generated by the substrate bias generating circuit 23-Vsn is the substrate bias. Used as voltages Vsn and Vmn. Therefore, the substrate bias circuit 23 can be configured by the two substrate vise generation circuits 23-Vsp and 23-Vsn, and it is possible to suppress an increase in the size of the semiconductor device 10. In the high-speed mode 1, the absolute value of the threshold voltage of the P-type SOTB transistor becomes high, but there is substantially no problem with the operating margin.

As described above, in the low speed mode 2 and the standby mode 3, the substrate bias voltage is supplied to the back gates of the P-type SOTB transistor, the N-type SOTB transistor, the P-type MOS transistor, and the N-type MOS transistor. It is possible to increase the threshold voltage (absolute value) of each transistor, and it is possible to reduce the power consumption of the semiconductor device 10. Further, in the low speed mode 2 and the standby mode 3, it is possible to stabilize the operation.

In the first and second embodiments, in the high-speed mode 1, the substrate bias circuit 23 does not supply the substrate bias voltage to the back gates of the P-type SOTB transistor, the N-type SOTB transistor, the P-type MOS transistor, and the N-type MOS transistor. However, this means that the substrate bias voltage for raising the threshold voltage of each transistor is not supplied. Therefore, in the high-speed mode 1, the substrate bias circuit 23 may supply the same voltage as the source of each transistor to the back gate of each transistor. That is, in the high-speed mode 1, the substrate bias circuit 23 supplies a voltage having the same value as the voltage at the source of the P-type SOTB transistor to the back gate of the P-type SOTB transistor, and supplies the voltage to the back gate of the N-type SOTB transistor. A voltage having the same value as the voltage at the source of the N-type SOTB transistor may be supplied. Further, in the high-speed mode 1, the substrate bias circuit 23 supplies a voltage having the same value as the voltage at the source of the P-type MOS transistor to the back gate of the P-type MOS transistor, and supplies the N to the back gate of the N-type MOS transistor. A voltage having the same value as the voltage at the source of the type MOS transistor may be supplied.

Alternatively, the substrate bias circuit 23 may make the back gate of each transistor float in the high-speed mode 1.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

For example, the substrate bias voltage formed by the substrate bias circuit is the all P-type SOTB transistors, N-type SOTB transistors, P-type MOS transistors, and N-type MOS transistors that make up the semiconductor device 10 in the low-speed mode 2 and the standby mode 3. It may be supplied to the back gate of. However, when the semiconductor device 10 has an analog circuit, it is desirable that the substrate vise voltage is not supplied to the back gate of the transistors constituting the analog circuit.

Further, although the case of having three modes of high-speed mode 1, low-speed mode 2 and standby mode 3 has been described, the number is not limited to this. For example, it may have only high-speed mode 1 and low-speed mode 2 (or standby mode 3). Also in this case, in the high-speed mode 1, the substrate bias circuit 23 does not supply the substrate bias to the back gate of the transistor, but in the low-speed mode 2 (or standby mode 3), the substrate vise voltage is supplied. good.

1 High-speed mode 2 Low-speed mode 3 Standby mode 10 Semiconductor device 23 Board bias circuit 23-Vsp, 23-Vsn, 23-Vmp, 23-Vmn Board bias generation circuit 24 System controller 26 CPU
12 Analog circuit 30 SRAM
36A, 36B Clock generator SP1, SP2 P-type SOTB transistor SN1 to SN4 N-type SOTB transistor MP1, MP2 P-type MOS transistor MN1, MN2 N-type MOS transistor MC00 to MC11 Memory cell

Claims (6)

A first circuit having a P-type transistor and an N-type transistor,
A second circuit having a P-type SOTB transistor and an N-type SOTB transistor,
A voltage supply circuit for supplying a voltage to the first circuit and the second circuit, and
It is a semiconductor integrated circuit device having
The P-type SOTB transistor is a first channel in which a channel is formed between a first gate electrode, a first source region, a first drain region, and the first source region and the first drain region. It has a region, a first insulating film, and a first region facing the first channel region via the first insulating film.
The N-type SOTB transistor is a second channel in which a channel is formed between a second gate electrode, a second source region, a second drain region, and the second source region and the second drain region. It has a region, a second insulating film, and a second region facing the second channel region via the second insulating film.
The first circuit includes an input / output circuit.
The second circuit includes a memory cell.
The semiconductor integrated circuit device has a first operation mode and a second operation mode.
The voltage supply circuit outputs a first voltage and a second voltage.
In the first operation mode, the first voltage is supplied to the first region of the P-type SOTB transistor, and the second voltage is supplied to the second region of the N-type SOTB transistor. Integrated circuit device. The P-type transistor has a third channel region in which a channel is formed between a third gate electrode, a third source region, a third drain region, and the third source region and the third drain region. And a third region formed below the third channel region.
The semiconductor integrated circuit device according to claim 1, wherein the concentration of impurities in the first channel region is lower than the concentration of impurities in the third channel region. The N-type transistor has a fourth channel region in which a channel is formed between a fourth gate electrode, a fourth source region, a fourth drain region, and the fourth source region and the fourth drain region. And a fourth region formed below the fourth channel region.
The semiconductor integrated circuit device according to claim 2, wherein the concentration of impurities in the second channel region is lower than the concentration of impurities in the fourth channel region. The semiconductor integrated circuit device according to claim 1, wherein the first voltage is different from the second voltage. The semiconductor integrated circuit device further includes an SRAM.
The semiconductor integrated circuit device according to claim 3, wherein the SRAM includes the memory cell and a peripheral circuit connected to the memory cell. The semiconductor integrated circuit device according to claim 5, wherein the operating frequency of the first operating mode is lower than the operating frequency of the second operating mode.

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